JP2002270428A - Laminated chip inductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated chip inductor for eliminating the need for blocking the magnetic field that is generated by a coil and at the same time reducing floating capacitance that is generated by each conductive section. SOLUTION: The inductor has a coil 4 where each conductive pattern is successively connected and is formed spirally in a laminate 2 that is formed by alternately laminating an electric insulating layer and the conductive pattern in the crosswise direction. A pair of external electrode terminals 12 is provided on the lower surface of the laminate 2, and lead conductive sections 14 and 16 for connecting each external electrode terminal 12 to both end sections of the coil 4 are provided in the laminate 2. The first leading conductive section 14 is formed while being connected to a via hole, and the second leading conductive section 16 is pattern-formed between the layers of the laminate 2 so that it does not cross both end faces of the winding core section of the coil 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spiral coil in which an electrically insulating layer made of a magnetic material or a non-magnetic material and a conductor pattern are alternately laminated, and each of the conductor patterns is sequentially electrically connected. In particular, the present invention relates to a technique for improving the performance of a multilayer chip inductor.

[0002]

2. Description of the Related Art FIGS. 27 and 28 show an example of a conventional multilayer chip inductor. The multilayer chip inductor is formed in a rectangular parallelepiped shape that is long in the lateral direction, and includes therein a coil 4 that is spirally formed in the longitudinal direction of the chip. This laminated chip inductor is formed by alternately laminating an electric insulating layer and a conductor pattern along the longitudinal direction of the chip. Here, the laminated conductor patterns are sequentially connected along the lamination direction, and a spiral coil is formed inside the chip. The electric insulating layer is formed from an electric insulating material such as magnetic ceramics such as ferrite and dielectric ceramics.

[0003] This multilayer chip inductor is called a longitudinal type, and since the self-resonant frequency can be set higher than that of a conventional type in which the center axis of the coil 4 is not parallel to the longitudinal direction of the chip, the laminated chip inductor has recently been gradually spotlighted. Device.

[0004] External electrode terminals 6 are provided at both ends in the longitudinal direction of the chip. This external electrode terminal 6
Is formed over the entire end face of the chip and the peripheral edge thereof. These external electrode terminals 6 are terminals that are connected to connection terminals provided when the multilayer chip inductor is placed on an electronic circuit board or the like.

Further, between each external electrode terminal 6 and both ends 5 of the coil 4, there are provided lead conductors 8, 10 for electrically connecting them. Each of the lead conductors 8 and 10 includes a first lead conductor 8 extending from the coil end toward the center of the coil 4, and a first lead conductor 8 extending from the first lead conductor 8 along the center axis of the coil 4. And a second lead conductor portion 10 extending toward the external electrode terminal 6. The first lead conductor 8 is formed between layers of the chip, and the second lead conductor 10 is formed by connecting via holes.

[0006]

This multilayer chip inductor has the following problems. That is,
Since the external electrode terminals 6 are formed on the plane where the center axis of the coil 4 is orthogonal to the center of the coil, that is, on both end faces of the chip, the magnetic field generated by the coil 4 is cut off by the external electrode terminals 6 and the magnetic field decreases to lower the Q value And coil 4
In some cases, an eddy current is generated in the external electrode terminal 6 by the magnetic field generated in the step (1), thereby causing a loss. In addition, a stray capacitance is generated between the lead conductors 8 and 10 connecting both ends of the coil 4 and the respective external electrode terminals 6 and between the external electrode terminals 6,
This causes a decrease in the resonance frequency, and there is also a problem that it is difficult to use at a high frequency.

In order to solve these problems, the surface on which the external electrode terminals 6 are provided must be set not on the chip end surface but on another surface where the center axis of the coil 4 does not intersect. Also, the external electrode terminals 6 and the lead conductors 8, 10 are connected between the lead conductors 8, 10 connecting both ends of the coil 4 and the external electrode terminals 6 and between the external electrode terminals 6 so that stray capacitance is not generated as much as possible. It is necessary to provide. Moreover, these external electrode terminals 6 and the lead conductor portions 8 and 10 need to be provided as inexpensively as possible. That is, these external electrode terminals 6
The key is how to arrange and form the lead conductors 8 and 10 inside the chip.

The present invention has been made in view of such circumstances, and an object of the present invention is to prevent a magnetic field generated by a coil from being interrupted and to reduce a stray capacitance generated by each conductor. An object of the present invention is to provide a multilayer chip inductor.

[0009]

In order to achieve the above object, in a first multilayer chip inductor according to the present invention, an electrically insulating layer and a conductor pattern are alternately laminated to form a laminate. In addition, in the multilayer chip inductor provided with a spiral coil formed by sequentially connecting each end of each of the conductor patterns inside the laminate,
A pair of external electrode terminals formed on side surfaces of the laminate,
A lead conductor portion provided between the layers of the laminate to connect these external electrode terminals and both ends of the coil, and patterned so as not to cross both end surfaces of the core portion of the coil; It is characterized by comprising (claim 1).

In this laminated chip inductor, external electrode terminals are provided on the side surfaces thereof, and both end surfaces of the core portion of the coil are connected to connect these external electrode terminals to both end portions of the internal coil. By patterning the lead conductor part between the layers so that it does not cross,
With these external electrode terminals and internal lead conductors,
It is not necessary to block the magnetic field generated by the coil. by this,
It is possible to prevent the Q value from decreasing due to the decrease in the magnetic field, and to prevent eddy current from being generated at the external electrode terminals, and to improve the performance of the multilayer chip inductor.

Further, in this multilayer chip inductor, the lead conductor portions are arranged so as not to be opposed to each other with the coil interposed therebetween. With this arrangement, the stray capacitance generated between these lead conductors can be reduced as much as possible.

Further, in this multilayer chip inductor, the lead conductor portion extends radially from the frame portion toward each side surface of the multilayer body from the frame portion. And an extension portion exposed on the side surface (claim 3). By forming the lead conductor portion in this manner, when providing the external electrode terminal, it is not necessary to specify the side surface of the laminate where the lead conductor portion is exposed, and the external electrode is provided on one of the side surfaces of the laminate. The external electrode terminal can be easily connected to the coil end simply by providing the terminal.

In a second multilayer chip inductor according to the present invention, an electrical insulating layer and a conductor pattern are alternately laminated to form a laminate, and each of the conductor patterns is provided inside the laminate. In a multilayer chip inductor provided with a spiral coil formed by connecting each end sequentially, a pair of external electrode terminals formed on a side surface of the multilayer body and a center of the coil from both ends of the coil. A pair of first lead conductors formed by connecting via holes in parallel with an axis; and a pair of first lead conductors provided between the layers of the laminate to connect the ends of the first lead conductors to the external electrode terminals. And a pair of second lead-out conductor portions patterned so as not to cross both end surfaces of the core portion of the coil (claim 4).

In this laminated chip inductor, external electrode terminals are provided on the side surfaces thereof, and the external electrode terminals are connected to both ends of the internal coil. A pair of first lead conductors formed in parallel with the axis, and second lead conductors connecting the ends of the first lead conductors and the external electrode terminals so as not to cross both end faces of the core of the coil; With such a configuration, it is not necessary to block the magnetic field generated in the coil by the external electrode terminal or the internal lead conductor. As a result, the magnetic field decreases and the Q value decreases,
Further, generation of eddy current at the external electrode terminals can be prevented, and the performance of the multilayer chip inductor can be improved.

Further, in the multilayer chip inductor, the first lead conductors are arranged so as not to face each other with the coil interposed therebetween. The second lead conductors are arranged so as not to face each other with the coil interposed therebetween. With such an arrangement, stray capacitance generated between the first lead conductor portions or between the second lead conductor portions can be reduced as much as possible.

Further, the second lead conductor portion is formed in an annular frame connected to the first lead conductor portion, and extends radially from the frame portion toward each side surface of the laminate. And extending portions exposed on the respective side surfaces (claim 7). Thus the second
By forming the lead-out conductor portion, when providing the external electrode terminal, it is not necessary to specify the side surface of the laminate where the second lead-out conductor portion is exposed, and the external electrode terminal is provided on one of the side surfaces of the laminate. Is provided, the external electrode terminal can be easily connected to the coil end.

Further, the frame portion is formed in a rectangular shape, and the first lead-out conductor portions are arranged at diagonal positions of the frame portion, respectively. With such an arrangement, the stray capacitance generated between the first lead conductors can be reduced as much as possible.

In the third multilayer chip inductor according to the present invention, the electrical insulating layers and the conductor patterns are alternately laminated to form a laminate, and the conductor patterns of the conductor patterns are formed inside the laminate. In a multilayer chip inductor provided with a helical coil formed by sequentially connecting each end, a pair of external electrode terminals provided on a side surface of the multilayer body, and a pattern formed between layers of the multilayer body; A pair of internal lead conductors extending toward the side surfaces of the laminated body provided with the external electrode terminals so as not to cross both end surfaces of the core portion of the coil from each end of the coil, And a pair of external lead conductors formed on the side surface of the laminate to connect the internal lead conductors to the external electrode terminals (Claim 9).

In this laminated chip inductor, external electrode terminals are provided on the side surfaces thereof, and the coil is wound from both ends of the coil in order to connect these external electrode terminals to both ends of the internal coil. Internal lead conductor portions extending to the side surface on which the external electrode terminals are provided so as not to cross both end surfaces of the core portion, and formed on the side surfaces for connecting these internal lead conductor portions and the external electrode terminals. With the external drawer conductor
The magnetic field generated by the coil does not need to be interrupted by the external electrode terminal and the internal lead conductor. As a result, it is possible to prevent a decrease in the magnetic field and a decrease in the Q value, and to prevent an eddy current from being generated at the external electrode terminals, and to improve the performance of the multilayer chip inductor.

In the multilayer chip inductor, it is preferable that the internal lead-out conductor portion or the external lead-out conductor portion is arranged so as not to face each other with the coil interposed therebetween. . By such an arrangement, the stray capacitance generated between the internal lead-out conductor portions or between the external lead-out conductor portions can be reduced as much as possible.

In the multilayer chip inductor, it is preferable that a protective layer is provided on a side surface of the multilayer body to cover the external lead conductor from outside.
2). With this configuration, the external lead conductor can be protected from the outside. Further, it is preferable that the protective layer is formed of ceramic or resin.
3). Thereby, the external lead conductor can be sufficiently protected from the outside. Further, it is preferable that the external lead conductor portion contains a glass component. The glass component can enhance the adhesion between the external lead conductor portion and the protective layer.

Further, in this multilayer chip inductor, the external lead-out conductor portion extends along a lamination direction at a boundary between the multilayer chip inductor and another multilayer chip inductor formed adjacent thereto. It is characterized in that the via holes are formed in such a manner that the via holes are divided in half when the two laminated chip inductors are separated from each other (claim 15). Thus, the external lead conductor portion can be easily provided on the outer surface of the laminate without requiring a separate new process.

In the first to third multilayer chip inductors, it is preferable that a marker for determining the position of the external electrode terminal is provided on the outer surface of the multilayer body. Thus, the position of the external electrode terminal can be easily determined, and the position can be easily confirmed at the time of alignment and mounting of the multilayer chip inductor.

In each of the first to third multilayer chip inductors, it is preferable that a reinforcing layer made of ceramics or resin is provided on a longitudinal side surface of the multilayer body. Thereby, the bending strength can be improved by reinforcing the longitudinal side surface of the laminate. The multilayer chip inductor can be protected from damage and the like.

In each of the first to third multilayer chip inductors, the pair of external electrode terminals are provided on one of the side surfaces of the multilayer body, and the center axis of the coil is set at the end face of the multilayer body. It is preferable that the center electrode is shifted from the center in a direction away from the external electrode terminal. Since the center axis of the coil is shifted in a direction away from the external electrode terminal, stray capacitance generated between the coil and the external electrode terminal or the substrate can be reduced as much as possible, and the resonance frequency can be reduced. Can be increased.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multilayer chip inductor according to the present invention will be described below. 1 to 3
1 shows a first embodiment (corresponding to a second multilayer chip inductor) of a multilayer chip inductor according to the present invention. FIG. 1 is a perspective view showing the internal conductor structure,
FIG. 2 is a side view showing the internal conductor structure, and FIG. 3 is a transparent front view showing the internal conductor structure. The same components as those in the conventional example are denoted by the same reference numerals.

The laminated chip inductor is formed in a rectangular parallelepiped shape, and is formed by alternately laminating an electric insulating layer made of a magnetic ceramic or a non-magnetic ceramic or the like and a conductor pattern. The ends of the conductor patterns are sequentially connected along the laminating direction, and a spiral coil 4 is formed inside the laminate 2. On the outer surface thereof, a pair of external electrode terminals 12 are provided in a thin layer shape at intervals on the four side surfaces (here, the lower surface of the laminate 2) of the laminate 2 parallel to the central axis of the coil 4. I have.
The external electrode terminals 12 are connected to connection terminals provided when the multilayer chip inductor is mounted on an electronic circuit board or the like.

Inside the laminate 2, there are provided lead-out conductors 14 and 16 for connecting the pair of external electrode terminals 12 and both ends of the coil 4, respectively. The first and second lead conductors 14 and 16 extend linearly from both ends of the coil 4 along the stacking direction so as not to cross both end surfaces of the core portion of the coil 4 in parallel with the center axis of the coil 4. A predetermined pattern is formed between the lead-out conductor portion 14 and the layers of the laminate 2 outside the core portion so as to be connected to the end portion of each first lead-out portion 14 and not to cross both end surfaces of the core portion of the coil 4. And the second lead conductor 16 connected to each of the external electrode terminals 12. Here, the both end surfaces of the core include the surfaces extending in the axial direction from both ends of the coil 4.

The second lead conductor portion 16 has a rectangular frame portion 18 formed in an annular shape equal to or larger than the inner diameter of the coil 4, and four extending portions radially extending from the frame portion 18. And a unit 20. Frame part 18
Are arranged coaxially with the coil 4. The extending portion 20 extends straight from the center of each side of the frame 18 toward the four longitudinal side surfaces of the laminate 2. Each extension 2
0 is exposed at the outer surface of the laminate 2, and in the present embodiment, one of these four extensions 20 extends from the lower side of the frame toward the lower surface of the laminate. Extended) are connected to the external electrode terminals 12. Extending the second lead conductor portion 16 to each of the four side surfaces of the laminate 2 in this manner does not require specifying the surface where the second lead conductor portion 16 is exposed when the external terminal electrode 12 is provided. That's why. That is, when the laminated body 2 is formed into chips, the laminated body 2 is very small.
It is extremely difficult to align them and identify a given side. If the second lead conductor portion 16 extends on all four side surfaces, the external electrode terminals 12 may be provided on any of the four side surfaces, and the external electrode terminals 12 may be connected to the coil 4.
Can be easily connected to both ends.

On the other hand, the first lead conductor portion 14 is formed so as to penetrate the electric insulating layer, and is formed by connecting via holes. The two first lead conductors 14 are
The second lead-out conductors 16 are arranged at diagonally opposite corners of the frame 18 in this embodiment. The reason why the first lead-out conductor portions 14 are arranged at diagonal positions of the coil 4 in this manner is that these first lead-out conductor portions 14
This is to reduce the stray capacitance generated therebetween as much as possible. As the size of the laminate 2 becomes smaller, the volume of the first lead conductor portion 14 occupying the entire laminate 2 relatively increases, whereby the stray capacitance generated between the first lead conductor portions 14 cannot be ignored. Because. It is preferable that the first lead conductors 14 be separated from each other as much as possible to reduce the stray capacitance generated therebetween.

FIGS. 4 (a) to 4 (k) show various electric insulating sheets 22a, 22b, 22c, 22d, 2 used when the laminated chip inductor is manufactured by a sheet laminating method.
2e. In the sheet lamination method, magnetic ceramics and dielectric ceramics are formed into a sheet shape,
In this method, a conductor pattern is screen-printed thereon, and the ceramic sheets are sequentially laminated and integrated by pressure bonding.

FIGS. 4A and 4K show a dummy sheet 22a having no conductor pattern laminated on the upper end and the lower end of the laminate, respectively. This dummy sheet 22 a is mainly used for adjusting the size of the laminate 2. FIGS. 4D to 4H show the sheets 22b and 22c on which the conductor patterns forming the coil 4 are formed. 4D, 4F, and 4H are sheets 22b on which a U-shaped conductor pattern 4a is formed, and FIGS. 4E and 4F are U-shaped sheets. Sheet 22c on which via holes 4b for interconnecting conductor patterns are formed
It is. The sheet 22c shown in FIGS. 4E and 4G is arranged between the sheets shown in FIGS. 4D, 4F and 4H. The U-shaped conductor pattern 4a is a via hole 4
The spiral coils 4 are sequentially connected in a spiral through the “b” to form a spiral coil 4. These sheets 22b, 22b are stacked in the center of the stack 2 by a predetermined number according to the number of turns of the coil 4.

On the other hand, FIGS. 4 (c), (b), (i),
(J) shows sheets 22d and 22e in which lead conductors 14 and 16 for connecting both ends of the coil 4 and the external electrode terminals 12 are formed as conductor patterns. FIGS. 4C and 4I show the first lead conductor 14.
FIG. 4 shows a sheet 22d having via holes formed therein.
(B) and (j) show the sheet 22e on which the frame portion 18 and the four extending portions 20 are formed as the second lead conductor portion 16. The sheet 22d shown in FIGS. 4C and 4I having the first lead-out conductor portion 14 has both ends of the coil 4 and the second portion.
An appropriate number of sheets are laminated according to the distance from the lead conductor 16. 4 (c), (b), (i), (j)
Sheets 22d and 22e are dummy sheets 22a disposed at the upper end and lower end of the laminate 2 and sheets 22b and 22 disposed at the center of the laminate 2 forming the coil 4.
c.

Normally, such a multilayer chip inductor is not manufactured by laminating ceramic sheets individually for each chip, but is a multi-cavity method in which a large number is manufactured collectively for mass production. Is adopted. That is, a large number of the same patterns are arrayed and printed on one ceramic sheet in a matrix, and the chips are individually cut after lamination.

After sequentially laminating the ceramic sheets shown in FIGS. 4A to 4K, they are integrated by applying pressure from both sides, cut into a predetermined shape into chips, and further subjected to a firing treatment. Perform a finishing process such as barrel polishing. The finished chips are arranged, and external electrode terminals 12 are printed on the outer surface thereof. In the present embodiment, since the extending portions 20 of the second lead conductor portion 16 are exposed on the four side surfaces of the multilayer body 2, the external electrode terminal 12 is located anywhere on any of the four side surfaces. It may be formed. Thus, the external electrode terminals 12 can be easily formed without placing a concern on the location of the chip by inserting the chip formed by vibration or the like into a jig having an accommodation hole formed in accordance with the shape of the chip.

In addition, the multilayer chip inductor according to the present invention may be manufactured by a printing lamination method in which ceramic patterns and conductor patterns are alternately screen-printed and laminated.

As described above, in this laminated chip inductor, external electrode terminals 12 are provided on the side surfaces, respectively. In order to connect these external electrode terminals 12 to both ends of the internal coil 4, the coil 4 A pair of first lead conductors 14 formed from both ends in parallel with the central axis of the coil 4, and the ends of the first lead conductors 14 and the external electrode terminals 12 are connected to both end surfaces of the core part of the coil 4. Is provided so as not to traverse the magnetic field, the external electrode terminal 12 and the internal lead conductors 14 and 16 do not block the magnetic field generated in the coil 4, and the magnetic field can be reduced. It is possible to prevent the Q value from decreasing and the eddy current from being generated at the external electrode terminal 12, and to improve the performance of the multilayer chip inductor.

5 to 8 show the appearance of the outer surface of the multilayer chip inductor. FIG.
A black marker 24 is provided on the surface opposite to the surface on which the external electrode terminals 12 are provided, that is, on the entire surface of the laminate 2 so that the positions of the external electrode terminals 12 can be recognized. By attaching the marker 24 in this manner, the direction alignment and the mounting position of the laminate 2 can be easily confirmed.

The marker 24 is not limited to the surface on the side opposite to the surface on which the external electrode terminals 12 are provided, but is attached to the side surface of the other laminate 2 if the surface on which the external electrode terminals 12 are formed can be confirmed. It does not matter. In addition, the color is not limited to black, but may be any other color as long as the formation surface of the external electrode terminal 12 can be confirmed.

Further, if the marker 24 is also formed as a reinforcing layer by coloring low-temperature sintered ceramics or resin and applying it in a thin layer form and baking it simultaneously with the external electrode terminals 12, the bending strength is low. The laminated body 2 can be reinforced from the side surface, and breakage of the chip can be prevented.

This reinforcing layer may be provided on a surface other than the surface on which the marker 24 is provided as a mere reinforcing layer 26 without having a marker function as shown in FIG. If these reinforcing layers 26 are formed of an electrically insulating material, the second lead conductor 16 exposed on the side surface of the laminate 2
Can be electrically insulated from the outside.

The marker 24 and the reinforcing layer 26
Need not be provided over the entire side surface of the laminate 2, and as shown in FIG.
6 may be partially provided only where the extension 20 is exposed. The marker 24 and the reinforcing layer 26 are attached at the same time when the external electrode terminals 12 are formed by printing.

FIG. 8 is a side view of the pair of laminated bodies 2 facing the external electrode terminals 12 (here, the upper and lower surfaces of the laminated body 2).
1 shows the appearance of the laminate 2 in the case where a pair is provided. The external electrode terminals 12 are not necessarily
The present invention is not limited to the case where it is provided on one side surface, and may be provided over a plurality of side surfaces. Thus, the external electrode terminal 1
If 2 is provided over a plurality of side surfaces, the mounting operation can be easily performed. For example, if the external electrode terminals 12 are provided on all side surfaces (here, four side surfaces), mounting can be performed on any surface, and the mounting surface does not need to be selected.

FIG. 9 shows the internal conductor structure of the multilayer chip inductor when the number of turns of the coil 4 is large (corresponding to a first multilayer chip inductor). When the number of turns of the coil 4 is large and both ends of the coil 4 reach the vicinity of the external electrode terminals 12 as described above, the first lead conductor portion 14 is omitted, and only the second lead conductor 16 is used. And the external electrode terminal 12 are connected.

FIGS. 10 to 12 show a second embodiment of the multilayer chip inductor according to the present invention. Figure 1
0 is a perspective view showing the internal conductor structure, FIG. 11 is a side view showing the internal conductor structure, and FIG. 12 is a front view showing the appearance. In this multilayer chip inductor, the second lead conductor portion 16 does not extend to all four side surfaces of the multilayer body 2 parallel to the central axis of the coil 4 but extends only to one side surface on which the external electrode terminals 12 are provided. Let me. The second lead conductor 16 is formed in a band shape,
It extends straight from the end of the lead-out conductor portion 14 directly to the surface on which the external electrode terminals 12 are provided (in this case, the lower surface of the laminate 2) so as not to cross both end surfaces of the core portion of the coil 4. I have. If the surface on which the external electrode terminals 12 are formed can be specified in this way, the second lead conductor portion 16 does not need to extend to all the side surfaces of the laminate 2.

If the surface on which the external electrode terminals 12 are formed can be specified in this manner, the center axis M of the coil 4 is shifted from the center L of the end face of the laminated body 2 as shown in FIG.
Can be shifted in the direction away from (in this case, upward). Thus, the center axis M of the coil 4 is
The distance between the coil 4 and the external electrode terminal 12 or the substrate is increased by shifting the end surface center L away from the external electrode terminal 12 to further reduce the stray capacitance generated therebetween. And the resonance frequency can be increased.

FIGS. 13 to 15 show a third embodiment of the multilayer chip inductor according to the present invention, in which the external electrode terminals 12 are opposed to each other (here, the upper and lower surfaces of the multilayer 2). 2) shows the state of the internal conductor when a pair is provided. 13 is a perspective view, FIG. 14 is a side view, and FIG. 15 is a front view.
When the external electrode terminals 12 are provided on the opposing surfaces of the multilayer body 2 in this manner, the second lead conductor 16
To form a single linear strip pattern connecting these external electrode terminals 12.

FIG. 16 shows a case where the number of turns of the coil 4 is large and both ends of the coil 4 reach the vicinity of the external electrode terminal 12 (corresponding to a first multilayer chip inductor). Again, the first lead-out conductor portion 14 is omitted and the second
Only the lead conductor 16 corresponds.

FIGS. 17 and 18 show a fourth embodiment (corresponding to a third multilayer chip inductor) of a multilayer chip inductor according to the present invention. FIG. 17 is a perspective view showing the internal conductor structure, and FIG. 18 is a side view showing the internal conductor structure.

In this multilayer chip inductor, the multilayer body 2
Lead-out conductor portions 30 and 32 for connecting both end portions of the internal coil 4 and the pair of external electrode terminals 12 respectively extend from both end portions of the coil 4 toward the side surfaces of the laminate 2 provided with the external electrode terminals 12. The strip-shaped internal lead-out conductor portion 30 and the band-shaped external lead-out conductor portion 3 provided on the side surface of the laminated body 2 provided with the external electrode terminal 12 and connecting the internal lead-out conductor portion 30 and the external electrode terminal 12 respectively.
And 2.

The internal lead conductor 30 is formed so as not to cross both end faces of the core of the coil 4.
The coils 4 are arranged so as not to oppose each other with the coil 4 interposed therebetween. The end is exposed on the side surface of the laminate 2 on which the external electrode terminals 12 are provided. The internal lead conductor 30 is formed by screen printing or the like on the same ceramic sheet together with conductor patterns forming both ends of the coil 4.

Each of the external lead conductors 32 extends in opposite directions along the side surface of the laminate 2 from the exposed end of the internal lead conductor 30 and is connected to each external electrode terminal 12. The external lead conductor 32 is formed together with the external electrode terminals 12 and the like after chip formation.

On the surface on which the external lead conductor 32 and the external electrode terminals 12 are provided, the external lead conductor 3
2 is provided with a protective layer 34 for covering the same. The protective layer 34 is formed of an electrically insulating material such as ceramic or resin, and also serves as an insulating layer that insulates the external lead conductor 32 from the outside. In addition, it is preferable to add a glass component to the material for forming the external lead conductor 32 in order to improve the bonding property between the external lead conductor 32 and the ceramic forming the protective layer 34.

In this embodiment, the external electrode terminal 1
Since the surface forming the second layer 2 is specified, the center axis M of the coil 4 is shifted from the center L of the end surface of the multilayer body 2 in a direction away from the external electrode terminal 12 (here, upward) as shown in FIG. Can be done. Thereby, the stray capacitance generated between the coil 4 and the external electrode terminal 12, the substrate, or the like can be reduced, and the resonance frequency can be increased.

The external lead conductor 32 and the protective layer 3
The method of forming No. 4 will be described. FIG. 19 shows a procedure for forming the external lead conductor 32 and the protective layer 34. FIG. 19A shows a state in which the end of the internal lead conductor 30 is exposed on the side surface of the multilayer body 2 as shown in FIG.
A strip-shaped external lead conductor 32 is formed at the end of the exposed internal lead conductor 30 so as to cover the end from the outside. The situation at that time is shown in FIG. Further, a protective layer 34 made of ceramic, resin, or the like is formed on the surface of the formed external lead conductor 32 so as to cover the surface. Here, the protective layer 34 is formed at the center portion except for the portion where the external electrode terminals 12 are provided. The state at that time is shown in FIG. Then, as shown in FIG. 19D, the external electrode terminals 12 are provided on both sides of the protective layer.

In order to further reduce the stray capacitance generated between the internal lead-out conductor portions 30, the internal lead-out conductor portions 30 are directed outward in a direction away from both ends of the coil 4 as shown in FIG. It is more preferable that the inner lead conductors 30 are formed so as to extend from each other so as to increase the interval between the internal lead conductors 30.

FIGS. 21 (a) and 21 (b) show an example of a case where the external lead conductor 32 is formed thick to improve the connection with the internal lead conductor 30. FIG. Here, in order to form the external lead conductor 32 thick,
A via hole is formed along the outer edge of the laminate 12 to form a thick portion 36. The thick portion 36 is formed wider than the end of the internal lead conductor 30 and is provided along the position where the external lead conductor 32 is formed.

This via hole can be applied to the formation of the external lead conductor 32. In other words, a via hole is continuously provided at the outer edge of the multilayer body 2, and the conductor formed by the via hole is defined as the external lead conductor 32. FIG.
(A) to (c) show the procedure for forming the protective layer 34 at that time. Here, as in the case described above, first, the protection layer 34 is formed of ceramic or resin so as to cover the external lead conductor 32 exposed on the side surface of the multilayer body 2 in FIG. At this time, FIG.
As shown in (2), the end of the external lead conductor 32 connected to the external electrode terminal 12 is removed from the area where the protective layer 34 is formed. Then, as shown in FIG. 22C, the external lead-out conductor portion 3 where the protective layer 34 is not formed
An external electrode terminal 12 is provided to cover the end of the second electrode.

Here, as for the thick portion 36 and the external lead conductor portion 32, as shown in FIG. 23, a common via hole is provided at the boundary of another laminated body formed adjacent to each other to form a chip. If the via holes are cut so as to be cut into half just so as to be exposed on the outer surface of the laminated body, the work can be completed very easily, and the via holes can be formed without waste.

FIG. 24 shows a case where the number of turns of the coil 4 is large and both ends of the coil 4 reach the vicinity of the external electrode terminal 12, and the external lead conductor 32 is omitted and the internal lead conductor 30 alone is used. An example in the case of configuring is shown.

FIGS. 25 and 26 show a laminated chip inductor according to a fifth embodiment of the present invention. For the above-described external lead conductor 32, FIG.
As shown in FIG. 5 and FIG. 26, they may be arranged on the same straight line so as to face each other. In the fifth embodiment as well, since the surface on which the external electrode terminal 12 is formed is specified, as shown in FIG.
In the direction away from the external electrode terminal 12 from the center L of the end face of the multilayer body 2, the stray capacitance generated between the coil 4 and the external electrode terminal 12, the substrate, or the like can be reduced.
Thereby, it is preferable to increase the resonance frequency.

[0062]

According to the first multilayer chip inductor according to the present invention, the external electrode terminals are provided on the side surfaces thereof, and the external electrode terminals are connected to both ends of the internal coil. By patterning the lead conductors between the layers so as not to cross both end surfaces of the core, the external electrode terminals and the internal lead conductors do not have to block the magnetic field generated by the coil.
As a result, it is possible to prevent a decrease in the magnetic field and a decrease in the Q value, and to prevent an eddy current from being generated at the external electrode terminal, and to improve the performance of the multilayer chip inductor. 1).

Further, since the lead conductors are arranged so as not to face each other with the coil interposed therebetween, stray capacitance generated between these lead conductors can be reduced as much as possible. 2).

Further, the lead conductor portion is formed in a ring-shaped frame portion, and an extension portion radially extended from the frame portion toward each side surface of the laminated body and exposed on each side surface. By providing the external electrode terminal, it is not necessary to specify the side surface of the laminate where the lead conductor portion is exposed, and the external terminal can be easily provided simply by providing the external electrode terminal on one of the side surfaces of the laminate. The electrode terminal can be connected to the coil end (claim 3).

According to the second multilayer chip inductor of the present invention, the external electrode terminals are provided on the side surfaces thereof, and the external electrode terminals are connected to both ends of the internal coil. And a pair of first lead conductors formed in parallel with the center axis of the coil from both ends of the coil, and the ends of the first lead conductors and the external electrode terminals so as not to cross both end faces of the core of the coil. And the second extraction conductor portion connected to the external electrode terminal and the internal extraction conductor portion do not need to block the magnetic field generated by the coil. As a result, it is possible to prevent a decrease in the magnetic field and a decrease in the Q value, and to prevent an eddy current from being generated at the external electrode terminal, and to improve the performance of the multilayer chip inductor. 4).

Further, the first or second lead-out conductor portion is arranged so as not to be opposed to each other with the coil interposed therebetween, so that the first lead-out conductor portion or the second lead-out conductor portion is disposed between the first and second lead-out conductor portions. The stray capacitance generated therebetween can be reduced as much as possible (claims 5 and 6).

Further, the second lead-out conductor part has an annular frame connected to the first lead-out part, and radially extends from the frame toward each side of the laminate. And extending portions exposed on the respective side surfaces (claim 7). Thus the second
By forming the lead-out conductor portion, when providing the external electrode terminal, it is not necessary to specify the side surface of the laminate where the second lead-out conductor portion is exposed, and the external electrode terminal is provided on one of the side surfaces of the laminate. Is provided, the external electrode terminal can be easily connected to the coil end.

Further, the frame portion is formed in a rectangular shape, and the first lead-out conductor portions are arranged at diagonal positions of the frame portion, respectively. With such an arrangement, the stray capacitance generated between the first lead conductors can be reduced as much as possible.

According to the third multilayer chip inductor of the present invention, the external electrode terminals are provided on the side surfaces thereof, and the external electrode terminals are connected to both ends of the internal coil. Internal lead-out conductor portions extending from both ends of the coil to the side surfaces on which the external electrode terminals are provided so as not to cross both end surfaces of the core portion of the coil, and connect these internal lead-out conductor portions to the external electrode terminals. Therefore, by providing the external lead conductor portion formed on the side surface, the external electrode terminal and the internal lead conductor portion do not need to block the magnetic field generated in the coil.
As a result, it is possible to prevent a decrease in the magnetic field and a decrease in the Q value, and to prevent an eddy current from being generated at the external electrode terminal, and to improve the performance of the multilayer chip inductor. 9).

Further, since the internal lead-out conductor portion or the external lead-out conductor portion is arranged so as not to face each other with the coil interposed therebetween, a stray capacitance generated between these internal lead-out conductor portions or between the external lead-out conductor portions is provided. Can be reduced as much as possible (claims 10 and 11).

Further, by providing a protective layer for covering the external lead-out conductor portion from the outside on the side surface of the laminate, the external lead-out conductor portion can be protected from the outside (claim 12). Further, since the protective layer is formed of ceramic or resin, the external lead conductor can be sufficiently protected from the outside (claim 13). Further, since the glass component is contained in the external lead-out conductor, the adhesion between the external lead-out conductor and the protective layer can be enhanced (claim 14).

Further, the external lead-out conductor portion is provided with a via hole along the laminating direction at the boundary between the laminated chip inductor and another laminated chip inductor formed adjacent to the laminated chip inductor. When the multilayer chip inductor is separated, the via hole is formed by dividing the via hole in half, so that an external lead conductor can be easily provided on the outer surface of the multilayer body without requiring a separate new process. (Claim 15).

In each of the first to third multilayer chip inductors, a marker for determining the position of the external electrode terminal is attached to the outer surface of the multilayer body to simplify the position of the external electrode terminal. And the position can be easily confirmed at the time of alignment and mounting of the multilayer chip inductor (claim 16).

In each of the first to third multilayer chip inductors, a reinforcing layer made of ceramics or resin is provided on the longitudinal side surface of the laminate to reinforce the longitudinal side surface of the laminate. The bending strength can be improved, and the multilayer chip inductor can be protected from damage or the like (claim 17).

In each of the first to third multilayer chip inductors, the pair of external electrode terminals is provided on one of the side surfaces of the multilayer body, and the center axis of the coil is set at the end face of the multilayer body. By being shifted from the center in a direction away from the external electrode terminal, stray capacitance generated between the coil and the external electrode terminal or the substrate can be reduced as much as possible,
The resonance frequency can be increased (claim 18).

[Brief description of the drawings]

FIG. 1 is an internal perspective view showing a state of a conductor formed inside a first embodiment of a multilayer chip inductor according to the present invention.

2 is an internal perspective side view showing a state of a conductor formed inside the multilayer chip inductor shown in FIG. 1;

FIG. 3 is an internal perspective front view showing a state of a conductor portion formed inside the multilayer chip inductor shown in FIG. 1;

FIG. 4 is a plan view showing a sheet used when the multilayer chip inductor shown in FIG. 1 is manufactured by a sheet laminating method.

FIG. 5 is a perspective view showing an example of an outer surface portion of the multilayer chip inductor shown in FIG.

FIG. 6 is a perspective view showing another example of the outer surface of the multilayer chip inductor shown in FIG. 1;

FIG. 7 is a perspective view showing another example of the outer surface of the multilayer chip inductor shown in FIG. 1;

8 is a perspective view showing another example of the outer surface portion of the multilayer chip inductor shown in FIG.

FIG. 9 is an internal perspective view showing the structure of the internal conductor when the number of turns of the coil is large in the first embodiment of the multilayer chip inductor according to the present invention.

FIG. 10 is an internal perspective view showing a structure of an internal conductor of a second embodiment of the multilayer chip inductor according to the present invention.

11 is an internal perspective side view showing a state of a conductor portion formed inside the multilayer chip inductor shown in FIG. 10;

12 is an internal perspective front view showing a state of a conductor formed inside the multilayer chip inductor shown in FIG. 10;

FIG. 13 is an internal perspective view showing the structure of an internal conductor of a multilayer chip inductor according to a third embodiment of the present invention.

FIG. 14 is an internal perspective side view showing a state of a conductor formed inside the multilayer chip inductor shown in FIG. 13;

FIG. 15 is an internal perspective front view showing a state of a conductor formed inside the multilayer chip inductor shown in FIG. 13;

FIG. 16 is an internal perspective view showing the structure of the internal conductor when the number of turns of the coil is large in the third embodiment of the multilayer chip inductor according to the present invention.

FIG. 17 is an internal perspective view showing the structure of the internal conductor of the fourth embodiment of the multilayer chip inductor according to the present invention.

FIG. 18 is an internal perspective side view showing a state of a conductor formed inside the multilayer chip inductor shown in FIG. 17;

19 is an explanatory diagram showing a procedure for forming an external lead conductor in the multilayer chip inductor shown in FIG. 17;

FIG. 20 is an internal transparent front view showing another embodiment of the internal lead-out conductor part of the fourth embodiment of the multilayer chip inductor according to the present invention.

FIG. 21 is an internal perspective side view and an internal transparent front view showing another embodiment of the fourth embodiment of the multilayer chip inductor according to the present invention.

FIG. 22 is an explanatory view showing another procedure for forming the external lead conductor portion in the multilayer chip inductor shown in FIG. 17;

FIG. 23 is an explanatory diagram illustrating another procedure for forming the external lead conductor portion in the multilayer chip inductor illustrated in FIG. 17;

FIG. 24 is an internal perspective view showing the structure of the internal conductor when the number of turns of the coil is large in the fourth embodiment of the multilayer chip inductor according to the present invention.

FIG. 25 is an internal perspective view showing an internal conductor structure of a multilayer chip inductor according to a fifth embodiment of the present invention.

26 is an internal perspective side view showing the internal conductor structure of the multilayer chip inductor shown in FIG. 25.

FIG. 27 is an internal perspective view showing an example of the internal conductor structure of a conventional multilayer chip inductor.

FIG. 28 is an internal perspective front view showing the internal conductor structure of the multilayer chip inductor shown in FIG. 27;

[Explanation of symbols]

 2 Laminated body 4 Coil 12 External electrode terminal 14 First lead conductor part 16 Second lead conductor part 22 Ceramic sheet 24 Marker 30 Internal lead conductor part 32 External lead conductor part 34 Protective layer 36 Thick part

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E043 AA08 EA01 EA05 EA06 EB01 EB02 EB05 5E062 FF01 FF03 FG07 FG12 5E070 AA01 AB01 CB03 CB13 CB17 CB18 EA01 EA02

Claims (18)

[Claims] 1. A helical coil formed by alternately laminating an electric insulating layer and a conductor pattern to form a laminate and connecting each end of each conductor pattern in the laminate sequentially. A multilayer chip inductor comprising: a pair of external electrode terminals formed on side surfaces of the multilayer body;
A lead conductor portion provided between the layers of the laminate to connect these external electrode terminals and both ends of the coil, and patterned so as not to cross both end surfaces of the core portion of the coil; A multilayer chip inductor, comprising: 2. The multilayer chip inductor according to claim 1, wherein the lead conductors are arranged so as not to face each other with the coil interposed therebetween. 3. The frame according to claim 2, wherein the lead conductor portion is formed in a ring-shaped frame portion, and an extension portion radially extends from the frame portion toward each side surface of the laminate to be exposed on each side surface. The multilayer chip inductor according to claim 1, comprising: 4. A helical coil formed by alternately laminating an electric insulating layer and a conductor pattern to form a laminate and connecting each end of each conductor pattern in the laminate sequentially. A multilayer chip inductor comprising: a pair of external electrode terminals formed on side surfaces of the multilayer body;
A pair of first lead conductors formed by connecting via holes from both ends of the coil in parallel with the center axis of the coil, and ends of the first lead conductors are connected to the external electrode terminals. A multilayer chip inductor, comprising: a pair of second lead-out conductor portions provided between the layers of the multilayer body and patterned so as not to cross both end surfaces of the core portion of the coil. 5. The multilayer chip inductor according to claim 4, wherein the first lead conductors are arranged so as not to face each other with the coil interposed therebetween. 6. The multilayer chip inductor according to claim 4, wherein the second lead conductors are arranged so as not to face each other with the coil interposed therebetween. 7. The second lead conductor portion is formed in an annular frame connected to the first lead conductor portion, and is radially extended from the frame portion toward each side surface of the laminate. The multilayer chip inductor according to claim 4, further comprising an extension portion exposed on each of the side surfaces. 8. The first frame is formed in a rectangular shape, and
8. The multilayer chip inductor according to claim 7, wherein the lead conductors are arranged at diagonal positions of the frame. 9. A helical coil formed by alternately laminating an electric insulating layer and a conductor pattern to form a laminate and connecting each end of each conductor pattern in the laminate sequentially. A multilayer chip inductor comprising: a pair of external electrode terminals provided on a side surface of the multilayer body;
The pattern is formed between the layers of the laminate and extends from each end of the coil toward the side surface of the laminate on which the external electrode terminals are provided so as not to cross both end surfaces of the core portion of the coil. A pair of extracted internal conductors, and a pair of external conductors formed on the side surface of the laminated body to connect the internal conductors and the external electrode terminals. Chip inductor. 10. The multilayer chip inductor according to claim 9, wherein the internal lead conductors are arranged so as not to face each other with the coil interposed therebetween. 11. The multilayer chip inductor according to claim 9, wherein the external lead conductors are arranged so as not to face each other with the coil interposed therebetween. 12. The multilayer chip inductor according to claim 9, wherein a protective layer is provided on a side surface of the multilayer body to cover the external lead conductor from outside. 13. The multilayer chip inductor according to claim 12, wherein the protection layer is formed of ceramic or resin. 14. The multilayer chip inductor according to claim 13, wherein the external lead conductor portion contains a glass component. 15. The external lead-out conductor portion is provided with a via hole along a lamination direction at a boundary between the multilayer chip inductor and another multilayer chip inductor formed adjacent to the multilayer chip inductor. The multilayer chip inductor according to any one of claims 9 to 14, wherein the via hole is formed by dividing the via hole in half when the two multilayer chip inductors are separated. 16. The multilayer chip inductor according to claim 1, wherein a marker for determining a position of the external electrode terminal is provided on an outer surface of the multilayer body. . 17. The multilayer chip inductor according to claim 1, wherein a reinforcing layer made of ceramics or resin is provided on a side surface of the multilayer body in a longitudinal direction. 18. The semiconductor device according to claim 18, wherein the pair of external electrode terminals are provided on one of the side surfaces of the laminate, and a center axis of the coil is shifted from a center of an end surface of the laminate in a direction away from the external electrode terminals. Claims 1, 2, 4, 6 and 9
18. The multilayer chip inductor according to any one of items 17 to 17, wherein