JP2002259327A - Bus control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus control circuit which controls a buss width corresponding to a data traffic quantity on a microcomputer bus, has low power consumption suited to the needs of portable equipment, etc., and is provided with high performance. SOLUTION: The bus control circuit is provided with a counter 8 for counting the number of reading/writing times of a bus within a managing period by an internal timer 7, and has a circuit means for hardware-switching the bus width to 8 bits, 16 bits, 24 bits or 32 bits with the counted value of the counter 8 as the data traffic quantity of the bus and corresponding to the data traffic quantity. When the counted value of the counter 8 is small, an operation clock equivalent to the high-order bit of the bus is stopped to attain low power consumption. When the counted value of the counter is large, the bit number of the buss width is increased corresponding to the size to increase its data transfer capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control circuit for a microcomputer and, more particularly, to low power consumption for prolonging battery consumption of portable equipment and the like, and high data processing when necessary. The present invention relates to a bus circuit with a data traffic monitoring function that meets the half-conflicting needs of securing capacity.

[0002]

2. Description of the Related Art Generally, as a means for switching a bus width of a microcomputer, for example, a bus width of 8 bits or 16 bits, an SH70 issued by Hitachi, Ltd. is used.
32, SH7034 Hardware Manual ADJ-6
As described in Japanese Patent Application No. 02-077E, March 1993, 1st edition, and September 1998, 6th edition, switching means for switching by an access address, an external control pin or the like is known.

In addition, various means, for example, Japanese Patent Laid-Open Publication No. Sho 59-55525, disclose a microprocessor in which a required bus width is designated by inputting an external select signal. The microprocessor according to this disclosure does not have a data traffic monitoring function on the bus.

Japanese Patent Application Laid-Open No. 6-83765 discloses that
A microcomputer has been disclosed in which a bus sizing control function is realized by using a bus width designation terminal. However, the microprocessor according to this disclosure does not have a data traffic monitoring function on the bus.

Further, Japanese Patent Application Laid-Open No. 4-359335 discloses a memory in which bus width information is taken into a memory access method selection section in accordance with the bit width of a device connected to a bus, and the bus width is changed based on the bus width information. An access method is disclosed, and JP-A-7-93245 discloses an information processing device that changes a bus width by transmitting a bus width setting signal from a central control device (CPU). However, none of those disclosed therein performs bus width control based on data traffic information on the bus.

On the other hand, Japanese Patent Application Laid-Open No. 4-186443 discloses a method of measuring the amount of data traffic, which measures the amount of traffic for each line in a communication network and switches the connection between the central processing unit and the communication control unit. A load distribution control method for realizing line load distribution is disclosed in JP-A-3-226045.
Discloses a packet collision control method based on a packet queuing operation of a gateway, which measures traffic at a transfer destination and controls a packet queuing based on a result of the measurement, which is disclosed in Japanese Patent Application Laid-Open No. 7-47661. Is
There is disclosed a master terminal device and a data communication system which detect the traffic amount of two communication channels and switch to a channel having a small traffic amount.
However, none of these disclosures aims at securing and improving line performance in a communication network system, and does not focus on hardware circuit implementation on a microcomputer bus.

[0007]

The above-mentioned various technical means are initially set even though the amount of data traffic on the bus of the microcomputer changes greatly in accordance with the contents of data processing. Since the full operation is performed while maintaining the bus width, the power corresponding to the extra bus width is wasted.

The present invention has been made in view of such a technical background, and an object of the present invention is to control a bus width according to a data traffic amount on a microcomputer bus,
With low power consumption that meets the needs of mobile devices, etc.
Another object of the present invention is to provide a bus control circuit having high performance.

[0009]

In order to achieve the above object, the present invention comprises a counter for counting the number of times of reading and writing of a bus within a management period by an interval timer, and counts the count value of the counter to the data of the bus. A bus control circuit having circuit means for hardware-switching the bus width to any one of 8-bit, 16-bit, 24-bit, and 32-bit corresponding to the data traffic amount as the traffic amount, wherein the count value of the counter is When the count is small, the operation clock corresponding to the upper bits of the bus is stopped to reduce the power consumption.On the other hand, when the count value of the counter is large, the number of bits of the bus width is increased corresponding to the size. Means for increasing the data transfer capacity.

According to the above means, the number of times of reading and writing of the bus within a predetermined period is counted, and the counted number is regarded as the amount of data traffic on the bus, and when the counted number exceeds a certain value, the counted number is counted. In order to maximize the control functions of microcomputers and other control devices by securing the data flow capacity, the bus width is narrowed and the data transfer is performed by narrowing the bus width when the count is less than a certain value. The power consumption is suppressed by stopping the operation clocks of the buses other than the transfer data and the bus control system, thereby reducing the power consumption and the efficiency of the data transfer function as a whole. This is in accordance with the needs of the user when the control device such as described above is used for a mobile phone.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a bus control circuit according to the present invention, and is a block diagram showing a main part of the bus control circuit. An example in which this bus control circuit is used in a microcomputer of a portable telephone is shown. It shows.

As shown in FIG. 1, the bus control circuit includes a bus width selection control circuit 1, a bus controller 2, a central processing unit (CPU) 3, a first peripheral circuit 4, and a second peripheral circuit 5. , A third peripheral circuit 6 and the like.

The bus width selection control circuit 1 includes an interval timer (IntervalTimer) 7, an up counter (UP Counter) 8, a comparator (Comp-LH) 9, and a comparator (Comp).
-HL) 11 and a comparator (Comp-HH) 13
Register (Reg LH) 10 and register (Re
g HL) 12, a register (Reg HH) 14, a delay circuit (Delay) 15, and a flip-flop (FF)
1 to FF6) 16, 17, 18, 19, 20, 21;
An OR circuit (OR) 22 is provided. The bus controller 2 is a bus state controller (BSC-LL)
23 and a bus state controller (BSC-LH) 2
4 and bus state controller (BSC-HL) 25
And a bus state controller (BSC-HH) 26. The first peripheral circuit 4 includes a peripheral interface circuit (PIF-LL) 33, a peripheral interface circuit (PIF-LH) 34, a peripheral interface circuit (PIF-HL) 35, and a peripheral interface circuit (PIF-HH) 36. Is provided.

Further, a bus state controller (BS)
C-LL) 23 and peripheral interface circuit (PIF-
LL) 33, a bit 0-7 bus 29 is coupled,
Bits 8 to 15 bus 30 are coupled between bus state controller (BSC-LH) 24 and peripheral interface circuit (PIF-LH) 34, and bus state controller (BSC-HL) 25 and peripheral interface circuit (PIF-HL) ) 35 and a bus 16 to bit 23 are connected, and a bus state controller (BSC-
HH) 26 and peripheral interface circuit (PIF-H)
H) 36, a bit 24 to 31 bus 32 is connected.

The components 7 to 22 in the bus width selection control circuit 1 are interconnected as shown in FIG. Bus width selection control circuit 1 and bus controller 2
Are connected as shown in FIG. 1, and the bus width selection control circuit 1 and the first peripheral circuit 4 are also connected as shown in FIG. A write (write) control signal line 27 is provided between the bus controller 2 and the first peripheral circuit 4.
And a read (read) control signal line 28 are connected. Note that the second peripheral circuit 5 and the third peripheral circuit 6
It has almost the same configuration as the peripheral circuit 4.

The bus control circuit having the above configuration operates as follows.

When a signal is transmitted to the write control signal line 27 or a signal is transmitted to the read control signal line 28, those signals are added in the OR circuit 22, and the addition result is output as the number of pulses, and It is supplied to the counter 8. The up counter 8 counts this pulse number and counts up. At this time, different values are set in advance in the respective registers 10, 12, and 14 by the central controller 3, and the count value of the up counter 8 is compared with the set value of the register 10 by the comparator 9, and similarly, , Is compared with the set value of the register 12 by the comparator 11, and is compared with the set value of the register 14 by the comparator 13. As a result of these comparisons, when the count value matches the set value of the register 10, “1” is set in the flip-flop 16. Similarly, when the count value matches the set value of the register 12, The flip-flop 17 is set to "1", and when the count value matches the set value of the register 14, "1" is set to the flip-flop 18.

On the other hand, the interval timer 7 generates a pulse every time a predetermined period (management period) is reached.
This pulse is supplied to the up counter 8 as a reset signal. At the same time, this pulse
Flip-flop 1 corresponding to the held values of 6, 17, 18
The load signal to be transferred to 9, 20, 21 is supplied to a transmission gate (not shown). Further, this pulse is supplied as a clear signal to flip-flops 16, 17, and 18 after being delayed for a predetermined time through a delay circuit 15,
The values held in the flip-flops 16, 17, and 18 are cleared.

In the bus controller 2, when the enable (Enable LH) signal is output from the flip-flop 19, the bus state controller 24
Is turned on, and when the enable signal is not output from the flip-flop 19, that is, when the disable signal is output, the bus state controller 24 is turned off. Similarly, when the enable (Enable HL) signal is output from the flip-flop 20, the bus state controller 25 is set to the operating state, and when the enable signal is not output from the flip-flop 20, the bus state controller 25 is set to the non-operating state. To Further, when the enable (Enable HH) signal is output from the flip-flop 21, the bus state controller 26 is set to the operating state, and when the enable signal is not output from the flip-flop 21, the bus state controller 26 is set to the non-operating state. .

FIG. 2 is an explanatory diagram showing an example of an operation state of the bus control circuit shown in FIG.

In FIG. 2, the characteristics shown at the top are:
The register 10, the register 12, the register 14, and the count value of the up-counter 8 immediately before the interval timer 7 is reset, that is, an example of a change in the amount of data traffic on the bus.
Each set value of the register 12 and the register 14 is set in advance by the central controller 3 as described above. The characteristics shown in the intermediate stage are the flip-flops 19, 20, which are set by comparing the count value with the respective set values of the registers 10, 12, and 14 by the comparators 9, 11, and 13. 21 shows the held value and the change state of the bus width at that time, that is, the bus bit width. Further, the characteristic shown in the lower part indicates a reduction in power consumption in the bus controller 2 and the first peripheral circuit 4 (the same applies to the second and third peripheral circuits 5 and 6) in accordance with the change state of the bus width. It shows the status.

As shown in FIG. 2, the up counter 8
When the count value (data traffic amount of the bus) exceeds the set value of the register 10 and does not exceed the set value of the register 12, the flip-flop 19 is set to "1" and the flip-flops 20 and 21 are set to "0". , The bit 0-7 bus 29 and the bit 8-15 bus 30 are activated by the bus state controller 23 which is always in operation and the bus state controller 24 which is now activated. Bus bit width is 1
It becomes 6 bits. At this time, since the operation clock corresponding to the upper 16 bits of the bus stops, the amount of reduction in power consumption in the bus controller 2 and the first peripheral circuit 4 is:
It has an intermediate size as shown by the diagonal lines.

Next, when the count value of the up counter 8 (data traffic amount of the bus) exceeds the set value of the registers 10 and 12 and does not exceed the set value of the register 14, the flip-flops 19 and 20 are set to "1". ”And the flip-flop 21 is set to“ 0 ”, so that the bus state controller 2
3 and the bus state controller 2 that has been activated this time
4 and 25, bits 0 to 7 bus 29, bits 8 to
The 15 bus 30 and the bits 16 to 23 bus 31 are activated, and the bus bit width becomes 24 bits. At this time, since the operation clock corresponding to the upper 8 bits of the bus is stopped, the amount of reduction in power consumption in the bus controller 2 and the first peripheral circuit 4 is relatively small, as indicated by hatching.

Further, the count value of the up counter 8 (data traffic amount of the bus) is stored in the registers 10 and 1.
If it exceeds the set value of 2, 14, the flip-flop 1
Since 9, 20, and 21 are each set to “1”,
The bus state controller 23 which is always in operation and the bus state controllers 24, 2 which are now in operation
5 and 26, bits 0 to 7 bus 29, bits 8 to
15 bus 30, bit 16 to 23 bus 31, and bit 2
All of the 4 to 31 buses 32 are in operation, and the bus bit width becomes the maximum of 32 bits. At this time, since the operation clock corresponding to the upper bits of the bus does not stop, the amount of reduction in power consumption in the bus controller 2 and the first peripheral circuit 4 is almost eliminated.

On the other hand, the count value (the amount of data traffic of the bus) of the up counter 8 is stored in the registers 10, 12, 1.
4 does not exceed the set value, the flip-flop 19,
20 and 21 are respectively set to “0”, so that the bus state controller 23 which is always in the operating state,
Only the bits 0 to 7 bus 29 are active, and the bus bit width is a minimum of 8 bits. At this time, since the operation clock corresponding to the upper 24 bits of the bus stops,
The amount of reduction in power consumption in the bus controller 2 and the first peripheral circuit 4 is maximized as shown by hatching.

As described above, according to this embodiment, the set values of the flip-flops 19, 20, and 21 correspond to the operation of the bit buses 29 to 32 for coupling between the bus controller 2 and the first peripheral circuit 4. When the set value is "000", only the bits 0 to 7 bus 29 are activated, the bus width becomes 8 bits, and the data transfer is executed by 8 bits. When the value is “001”, bits 0 to 7 bus and bits 8 to 1
5 bus 30 is activated, has a bus width of 16 bits, performs data transfer with 16 bits, and has a set value of “0”.
11 ", bits 0-7 bus 29, bits 8-15
The bus 30 and the bits 16 to 23 are in the operating state, the data transfer is executed by 32 bits with a bus width of 24 bits, and when the set value is “111”, the bits 0 to 23 are set.
7 bus 29, bit 8-15 bus 30, bit 16-2
All of the 3 buses 31 and the bits 24 to 31 bus 32 are in the operating state, the bus width is 32 bits, and the data transfer is performed with 32 bits. At this time, the amount of reduction in power consumption in the bus controller 2 and the first peripheral circuit 4 is substantially inversely proportional to the bit width in the operating state, as indicated by the diagonal lines in FIG. A power consumption characteristic as shown by a certain white portion is obtained.

In this case, the bus control circuit may be formed as a single unit as a whole, or may be formed by combining various parts.

In the above embodiment, an example has been described in which the bus control circuit is used in a microcomputer of a portable telephone. However, the bus control circuit according to the present invention is limited to such a use state. Instead, the present invention may be used for a control device having a function equivalent to that of a microcomputer, and may be used for a portable device other than a mobile phone.

[0030]

As described above, according to the present invention,
Counting the number of times of reading and writing of the bus within a predetermined period, catching the counted number as the data traffic volume of the bus, and when the counted number becomes a certain value or more, expands the bus width corresponding to the counted number, Securing the data flow capacity and maximizing the control functions of microcomputers and other control devices.When the count is less than a certain value, narrow the bus width to continue data transfer, and The operation clocks of the bus and the bus control system are stopped to suppress power consumption, thereby achieving an effect of reducing power consumption and improving the efficiency of the data transfer function as a whole.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a bus control circuit according to the present invention and showing a main part configuration thereof.

FIG. 2 is an explanatory diagram illustrating an example of an operation state of the bus control circuit illustrated in FIG. 1;

[Description of Signs] 1 Bus width selection control circuit 2 Bus controller 3 Central processing unit (CPU) 4 First peripheral circuit 5 Second peripheral circuit 6 Third peripheral circuit 7 Interval timer (Interval Tim)
er) 8 Up counter (UP Counter) 9 Comparator (Comp-LH) 10 Register (Reg LH) 11 Comparator (Comp-HL) 12 Register (Reg HL) 13 Comparator (Comp-HH) 14 Register (Reg HH) 15 Delay Circuit (Delay) 16 Flip-flop (FF1) 17 Flip-flop (FF2) 18 Flip-flop (FF3) 19 Flip-flop (FF4) 20 Flip-flop (FF5) 21 Flip-flop (FF6) 22 OR circuit (OR) 23 Bus state controller (BSC-LL) 24 Bus state controller (BSC-LH) 25 Bus state controller (BSC-HL) 26 Bus state controller (BSC-HH) 27 Write control Signal line 28 Read control signal line 29 Bit 0 to 7 bus 30 Bit 8 to 15 bus 31 Bit 16 to 23 bus 32 Bit 24 to 31 bus 33 Peripheral interface circuit (PIF-LL) 34 Peripheral interface circuit (PIF-LH) 35 Peripheral interface circuit (PIF-HL) 36 Peripheral interface circuit (PIF-HH)

Claims (4)

[Claims] 1. A counter for counting the number of read / write operations of a bus during a management period by an interval timer, wherein the count value of the counter is defined as the data traffic volume of the bus, and the bus width is set to 8 bits corresponding to the data traffic volume. , A 16-bit, 24-bit, or 32-bit bus control circuit having a circuit means for hardware switching. When the count value of the counter is small, an operation clock corresponding to an upper bit of the bus is set to In order to reduce power consumption by stopping operation, on the other hand, when the count value of the counter is large, the number of bits of the bus width is increased in accordance with the count value to increase the data transfer capacity. Bus control circuit characterized. 2. The bus control circuit according to claim 1, wherein the data traffic monitoring function part of the bus control circuit is configured as a single device. 3. The bus control circuit according to claim 1, wherein said bus is a microcomputer bus. 4. The bus control circuit according to claim 3, wherein said bus is a bus connecting a central control unit of a microcomputer and a memory cell.