JP2002250934A - Method for manufacturing matrix substrate for liquid crystal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a matrix substrate for liquid crystal which has a high aperture ratio by using few photomasks. SOLUTION: A main portion as a TFT(thin film transistor) active matrix substrate is formed, a photosensitive acrylic resin film 10 is applied on its surface to flatten the surface. A resist layer 11 patterned by two or more steps of thickness is deposited on the film 10 by a half-tone exposure. The photosensitive acrylic resin film 10 is exposed by using the resist layer as a mask, and then the resist in other than a pixel forming area is removed by ashing. Then, a through hole which reaches the matrix circuit in a contact hole area is formed by performing a plasma water-repellent finish and developing the photosensitive acrylic resin 10. Water-repellent finish areas 12a to 12e remain only in the areas other than the pixel area. The coating type electrically conductive material is coated on the areas, patterned without using a mask, and a pixel electrode which overlaps a gate electrode in three dimensions is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a liquid crystal matrix substrate for forming a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device, Thin Fil has been used.
An active matrix liquid crystal display device using a thin film transistor, which is abbreviated as TFT from m Transistor, as a switching element is widely used. In an active matrix liquid crystal display device using a TFT as a switching element, a TFT array substrate having a TFT active matrix circuit formed on a transparent glass substrate is used. T
The FT array substrate is manufactured by repeating fine patterning by a photolithography process using a number of photomasks. From the viewpoint of improving the productivity and the manufacturing yield of the liquid crystal display device and reducing the cost, reduction in the number of photomasks used, that is, reduction in the photolithography process has been studied.

In order to reduce the power consumption and increase the luminance of a TFT active matrix type liquid crystal display device, it is necessary to improve the aperture ratio of a TFT array substrate in order to greatly improve the light transmittance of a liquid crystal cell. is there. As a technique for improving the aperture ratio, a method is known in which a pixel electrode for applying an electric field to a liquid crystal cell is formed on a flat protective film, and a gate electrode and a pixel electrode are three-dimensionally overlapped. In this method, a high aperture ratio exceeding 80% is realized. The manufacturing process of such an active matrix substrate having a high aperture ratio includes a G-S intersection where a scanning gate electrode wiring and a data source electrode wiring intersect, a TFT element part as a switching element, a pixel part, and a peripheral circuit. 8 (a) to 13 (p) are performed on a schematic cross-sectional configuration portion in which the terminal portions provided in FIG.

FIG. 8A shows a state in which a gate electrode film 22 is formed on the entire surface of a glass substrate 21.
The gate electrode film 22 is formed by a sputtering method or the like.
It is formed as a metal film of chromium (Cr), aluminum (Al), tantalum (Ta), or the like. Next, a photoresist is uniformly applied on the gate electrode film 22, and a resist pattern 23 as shown in FIG. 8B is formed using the first photomask. Next, etching is performed using the resist pattern 23, and the gate electrode film 22 is patterned as shown in FIG.

[0007] Next, as shown in FIG. 9 D, three layers of a gate insulating film 24, a first semiconductor layer 25, and a second semiconductor layer 26 are successively formed by a plasma CVD method or a sputtering method. Gate insulating film 24 is formed of, for example, a silicon nitride (SiNx) film. First semiconductor layer 25
Is formed of an amorphous-silicon (a-Si) film. The second semiconductor layer 26 is formed of a silicon (n ⁺ -Si) film doped with an n-type impurity at a high concentration.

Next, a photoresist is applied to the entire surface, and a resist pattern 27 shown in FIG. 9E is formed using a second photomask. The resist pattern 27 is formed in the TFT element portion, and is not formed in the GS intersection, the pixel portion, and the terminal portion. When etching is performed using the resist pattern 27, as shown in FIG.
Two layers of the first semiconductor layer 25 and the second semiconductor layer 26 are patterned in an island shape.

Next, the resist pattern 27 is removed, and FIG.
As shown in FIG. 1G, a source / drain electrode film 28 is formed on the entire surface. As the source / drain electrode film 28, a metal film such as chromium, aluminum, and tantalum is formed by a sputtering method or the like. Thereafter, a photoresist is once applied to the entire surface, and a resist pattern 29 as shown in FIG. 10H is formed using a third photomask. Although the resist pattern 29 is formed at the GS intersection and the TFT element, it is not formed at the channel in the TFT element. Next, etching is performed to remove the source / drain electrode film 28 and the second semiconductor layer 26 since the resist pattern 29 is not formed in the channel portion as shown in FIG.
Source / drain electrode separation patterning is performed. Further, the first semiconductor layer 25 is also partially etched, and channel etching for adjusting the thickness of the channel portion is performed.

FIG. 11 (j) is a diagram showing the source
This shows a state where the resist pattern 29 has been removed after the drain electrode separation patterning and the channel etching process have been performed. Next, as shown in FIG. 11K, a passivation film 30 is formed on the entire surface by a sputtering method, a CVD method, or the like. The passivation film 30 is a protective film made of, for example, silicon nitride (SiNx).
Further, as shown in FIG. 11 (l), a photosensitive acrylic resin film 31 is applied for flattening.

Next, using a fourth photomask, as shown in FIG. 12 (m), a photosensitive acrylic resin film 31 is formed.
Is patterned. In this patterning, the passivation film 30 is partially formed on the photosensitive acrylic resin film 31.
Is formed. When the passivation film 30 is etched using the patterned photosensitive acrylic resin film 31 as a mask as shown in FIG. 12 (n), the source electrode of the source / drain electrode film 28 starts from the surface of the photosensitive acrylic resin film 31. Then, a contact hole reaching the drain electrode separated from the drain electrode is formed. In the patterning and etching steps using the fourth photomask, a contact hole reaching the gate electrode from the surface of the photosensitive acrylic resin film 31 is similarly formed in the terminal portion. Although not shown in the drawing, a contact hole reaching the source electrode from the surface of the photosensitive acrylic resin film 31 is similarly formed in the source terminal portion.

Next, when a coating type transparent conductive film 32 is formed on the entire surface by a sputtering method or the like, the result is as shown in FIG. The coating type transparent conductive film 32 uses indium tin oxide (ITO) or tin oxide (SnO ₂ ). FIG.
(P) shows the photosensitive acrylic resin film 31 in FIG.
This shows a state in which the pixel electrode 33 is formed by patterning the coating type transparent conductive film 32 formed on the entire surface using a fifth photomask. In the TFT element portion, the pixel electrode 33 is formed of a photosensitive acrylic resin film 31 and a wiring pattern or T
The active matrix substrate 34 having a high aperture ratio is formed because the active matrix substrate 34 can be formed so as to be three-dimensionally overlapped with the FT element.

In the manufacturing process of the active matrix substrate 34 having a high aperture ratio described above, (b), (e), (h),
In each of the steps (m) and (p), a total of five photomasks are used. For this reason, it causes a prolonged process time and a reduction in manufacturing yield. Prior art relating to reducing the number of photomasks used in the manufacturing process of an active matrix substrate includes, for example,
-303111 can be mentioned. In this prior art, a coating type transparent conductive film is first formed on a substrate.
The coating type transparent conductive film is not only used as a pixel electrode,
It is also used as a base layer of a gate electrode. The gate electrode is
It is formed by applying electrolytic plating on the coating type transparent conductive film.
Japanese Patent Application Laid-Open No. 2000-206571 discloses a method in which resist patterns having different thicknesses are formed, and FIG.
The idea of performing the step shown in (i) using one photomask is shown. As shown in JP-A-61-181130, the resist patterns having different thicknesses are formed by changing the exposure amount. JP-A-61-181
In Japanese Patent Publication No. 130, a resist film pattern is formed by changing the exposure amount in order to form a highly accurate pattern even in a portion having a step. In Japanese Patent Application Laid-Open No. 2000-206571, it is possible to perform two-stage etching using portions having different thicknesses, thereby reducing the number of photomasks used by one. A similar concept is described by CW Kim et al. In Sid 2000 Digest, pp. 1006-11009, "A Nov.
el Four-Mask-Count Process Architecture for TFT-LC
Ds ”and“ Sangoku Denshi IPS TFT-LCD ”described on pages 31 to 35 of the May 1995 issue of the monthly FPD intelligence.
A process for manufacturing a TFT channel with 2 PEP-halftone exposure of the TFT channel portion "is also shown in a technical report.

[0012]

As described above, in the conventional manufacturing process of the high aperture ratio active matrix substrate 34, a total of five photomasks are required, which results in a prolonged process time and a reduction in manufacturing yield. Has become a factor. In the prior art disclosed in JP-A-5-303111, a gate electrode is formed by electrolytic plating using an ITO transparent electrode film formed simultaneously with a pixel electrode as a base,
By patterning the gate electrode film without using a photo process, the number of photo masks used in a TFT array manufacturing process is reduced. However, still five photomasks are required, which causes a prolonged process time and a reduction in manufacturing yield. Further, since the ITO transparent electrode film is used as a base film for forming the gate electrode by electrolytic plating on the TFT array substrate, the gate electrode and the pixel electrode cannot be overlapped, and the aperture ratio decreases. . In addition, when a gate electrode is manufactured by electrolytic plating, the nonuniformity of the film thickness due to the potential drop tends to be extremely large, and it is difficult to maintain the uniformity of the film thickness particularly in a large substrate.

In the method using a resist pattern having a changed thickness as disclosed in Japanese Patent Application Laid-Open No. 2000-206571, it is possible to reduce the number of photomasks when forming a TFT element portion. Only, and I
Only the TFT active matrix type liquid crystal display device of the PS (In Plane Switching) mode is mainly described. There is no indication that the possibility of further reducing the number of photomasks used in a TFT substrate in which the gate electrode and the pixel electrode are three-dimensionally overlapped and the aperture ratio is increased is not described.

It is an object of the present invention to provide a method of manufacturing a liquid crystal matrix substrate which can reduce the number of photomasks used in a manufacturing process of a TFT active matrix substrate or the like.

[0015]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a liquid crystal matrix substrate, wherein a matrix circuit for forming a plurality of liquid crystal cells is formed on an electrically insulating substrate. An electrically insulating synthetic resin material having photosensitivity is applied, an electric insulating film having a flat surface is formed, a resist layer is formed on the surface of the electric insulating film, and the resist layer is formed in a predetermined pixel electrode forming region. Halftone with a mask whose exposure is adjusted in multiple steps for each region so that it remains thick, so that the predetermined contact hole region does not remain, and the non-formed region other than the pixel electrode formation region and the contact hole region remains thin. Exposure and patterning, using the patterned resist layer as a mask, exposing the electrical insulating film in the contact hole region to the non-forming region The resist layer is etched to such a thickness that the thin remaining resist layer is removed, the electric insulating film in the contact hole region and the non-formed region is subjected to a water-repellent treatment, and the resist remaining in the pixel electrode formation region is peeled off. Develop the insulating film and pattern it so that a through hole reaching the matrix circuit is formed in the electric insulating film in the contact hole area, and apply a coating type conductive material on the patterned electric insulating film to form pixel electrodes A method of manufacturing a liquid crystal matrix substrate.

According to the present invention, a liquid crystal matrix substrate in which a matrix circuit for forming a plurality of liquid crystal cells is formed on an electrically insulating substrate has a multi-step thickness by forming an electric insulating film and halftone exposure. The resist layer patterned as described above is manufactured through patterning of an electric insulating film, water-repellent treatment, and formation of a pixel electrode. The formation of the electric insulating film is performed by applying a photosensitive electric insulating synthetic resin material on the electric insulating substrate on which the matrix circuit is formed so that the surface becomes flat. A resist layer is formed on the surface of the electrical insulating film, and the resist layer is formed in a region other than the contact hole region and the pixel electrode formation region so that a predetermined pixel electrode formation region remains thick and a predetermined contact hole region does not remain. The pattern is formed by halftone exposure using a mask in which the exposure amount is adjusted in a plurality of steps for each region so that the non-formed region remains thin. When exposure is performed using the patterned resist layer as a mask, only the electrical insulating film in the contact hole region is exposed. When the resist layer is etched to such a thickness that the thin remaining resist layer in the non-formation region is removed, the resist remains only in the pixel electrode formation region. In this state, by performing plasma treatment using a fluorine-based gas, water repellency is imparted to the electrical insulating film in the contact hole region and the non-formation region. After the resist remaining in the pixel electrode formation region is peeled off and the electric insulating film is developed, a through hole reaching the matrix circuit is formed in the electric insulating film in the contact hole region. At this time, since the electrical insulating film in the contact hole portion has already been exposed, the entire surface subjected to the water-repellent treatment is removed by the developing treatment. When the coating type conductive material is applied, the electric insulating film in the non-formed area has a property of repelling the coating type conductive material by water repellency, so that the coating type conductive material is applied to the pixel electrode formation area and filled in the contact hole area. Thus, a pixel electrode and a conductive portion of a contact hole can be formed. Since one photomask may be used to form the pixel electrode formation region and the through hole in the electrical insulating film, the number of photomasks used can be reduced.

Further, in the present invention, the matrix circuit is a TFT active matrix circuit including a plurality of thin film transistors, and the manufacturing process of the TFT active matrix circuit includes forming a film with a gate electrode material on the electrically insulating substrate; A gate electrode film patterning step of patterning, and a stacking step of sequentially stacking a gate insulating film, a first semiconductor layer serving as a channel region, a second semiconductor layer serving as an ohmic contact layer, and a metal layer serving as source / drain electrodes Then, the first semiconductor layer and the second semiconductor layer are formed in an island shape by halftone exposure using a mask in which the exposure amount is adjusted in a plurality of steps for each region, and patterning of the source / drain electrodes and channel etching are performed. After the separation etching step and the separation etching step,
And a passivation step of forming a passivation film.

According to the present invention, when forming a TFT active matrix circuit including a plurality of thin film transistors, the TFT active matrix circuit is formed by a manufacturing process including a gate electrode film patterning process, a lamination process, a separation etching process, and a passivation process. To manufacture. In the gate electrode film patterning step, a film is formed of a gate electrode material on an electrically insulating substrate and patterned. In the laminating step, a gate insulating film, a first semiconductor layer to be a channel region, a second semiconductor layer to be an ohmic contact layer, and a metal layer to be a source / drain electrode are sequentially laminated. In the separation etching step, the first semiconductor layer and the second semiconductor layer are formed in an island shape by halftone exposure with an adjusted amount of exposure, and patterning of source / drain electrodes and channel etching are performed. In the passivation step, a passivation film is formed and covered after the separation etching step. In manufacturing a TFT active matrix circuit, a photomask is used in each of a gate electrode film patterning process and a separation etching process,
Further, since one photomask is used when forming a pixel electrode overlapping with a wiring pattern or a TFT element, a TFT active matrix can obtain a high aperture ratio by using only three photomasks in total. A substrate can be manufactured.

Further, according to the present invention, after the formation of the pixel electrode,
The method is characterized in that the water repellency of the electric insulating film in the non-forming region is removed.

According to the present invention, since the water repellency of the electric insulating film is removed after the formation of the pixel electrode, the in-plane uniformity can be improved in the alignment treatment performed when forming the liquid crystal display device. .

In the present invention, a photosensitive acrylic resin is used as the electrically insulating synthetic resin material, and the water-repellent treatment is performed by irradiating a plasma using a fluorine-based gas,
According to the present invention, the pixel electrode is formed of a coating type transparent conductive material. The surface of the matrix substrate is flattened using a photosensitive acrylic resin, and the pixel electrode is repelled by plasma irradiation using a fluorine-based gas. The pixel electrode can be formed without using a photomask by applying water treatment to apply the coating type conductive material to the pixel electrode formation region and fill the contact hole.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 6A to 6P show a schematic structure of a high aperture ratio active matrix substrate as an embodiment of the present invention and an outline of a manufacturing method thereof. Also in the present embodiment, similarly to FIGS. 8 to 13, the GS intersection portion where the gate electrode and the source electrode intersect, and T
A schematic sectional configuration in which an FT element portion, a pixel portion, and a terminal portion are arranged will be described.

FIG. 1A shows a state in which a gate electrode film 2 is formed on a glass substrate 1. As the gate electrode film 2, a metal film such as chromium, aluminum, and tantalum is formed by a sputtering method or the like. On the gate electrode film 2, a resist layer is applied, and a first photomask is used to apply a resist layer as shown in FIG.
A resist pattern 3 as shown in FIG. Further, by etching using the resist pattern 3, the gate electrode film 2 is patterned as shown in FIG.

FIG. 2 (d) shows a gate insulating film 4, a first semiconductor layer 5 and a second semiconductor layer 6 which are successively laminated in three layers, and a source / drain electrode film 7 is formed by a plasma CVD method or a sputtering method. To form a continuous film formation. Gate insulating film 4 is formed of, for example, a silicon nitride (SiNx) film. The first semiconductor layer 5 is formed of an amorphous-silicon (a-Si) film. The second semiconductor layer 6 is formed of an n ⁺ -Si film heavily doped with n-type impurities. The source / drain electrode film 7 is formed of a metal such as chromium, aluminum, and tantalum. Further, after the resist is applied to the whole, the exposure amount is adjusted using a mask 15 such as a slit mask capable of halftone exposure, and the resist pattern 8 having a multi-step thickness is formed by one application, exposure, and development. Is formed as shown in FIG. The resist pattern 8 is not formed on the pixel portion and the terminal portion, and a portion corresponding to the channel portion 5a of the TFT element portion is formed as a thin portion 8a. Other portions are formed thick. Next, as shown in FIG. 2F, the three layers of the source / drain electrode 7, the second semiconductor layer 6, and the first semiconductor layer 5, which are not covered with the resist pattern 8, are all removed by etching. .

FIG. 3 (g) shows that the entire remaining resist pattern 8 shown in FIG. 2 (f) is reduced in thickness by ashing, and the source / drain electrode is formed at the position of the channel portion 5a corresponding to the thin portion 8a. This shows a state where the surface of the film 7 is exposed. Next, using the remaining resist pattern 8, source / drain electrode separation and channel etching are performed as shown in FIG. In the channel portion 5a, the second semiconductor layer 6 and the source / drain electrode film 7 are removed, and the thickness of the first semiconductor layer 5 is adjusted. Here, when the resist pattern 8 is removed, the state shown in FIG.

Next, as shown in FIG. 4J, a passivation film 9 is formed on the entire surface of the substrate. The passivation film 9 is a protective film made of silicon nitride or the like, and is formed by a sputtering method, a CVD method, or the like. When an electrically insulating synthetic resin material having photosensitivity, for example, a photosensitive acrylic resin is applied on the passivation film 9, FIG.
As shown in (k), a photosensitive acrylic resin film 10 which is an electric insulating film whose surface is flattened is obtained. After pre-baking the photosensitive acrylic resin film 10 at a temperature of 80 to 100 ° C. and further applying a resist thereon, the resist surface is partially exposed using a mask 15 capable of halftone exposure such as a slit mask. By adjusting the amount of exposure to light, a single resist application, exposure, and development
A resist layer 11 patterned to a plurality of thicknesses as shown in FIG. Specifically, the resist layer 1
1 is not formed in a pixel portion or a terminal portion in which the contact hole 10a is formed, the pixel portion region 11a is formed thick,
Other portions where the contact holes 10a and the pixel electrodes are not formed are formed thin. Subsequently, using the patterned resist layer 11 as a mask, the photosensitive acrylic resin film 10
Is exposed, only the portion to be the contact hole 10a shown in FIG.

Subsequently, an ashing process is performed on the entire surface of the resist layer 11 to uniformly reduce the resist thickness, thereby removing the resist other than the pixel region 11a as shown in FIG. The acrylic resin film 10 is exposed. Next, by performing a plasma process using a fluorine-based gas, the plasma water-repellent regions 12a, 12b, and 12b of the exposed photosensitive acrylic resin film shown in FIG.
Water repellency occurs in 12c, 12d, and 12e. After that, the resist remaining in the pixel portion region 11a is peeled off to obtain a state shown in FIG. Next, by performing a developing process, the portion of the photosensitive acrylic resin 10 which is to be exposed as the contact hole 10 a is removed, and a through hole reaching the passivation film 9 is formed. When etching is performed using the photosensitive acrylic resin 10 as a mask, FIG.
As shown in (o), a contact hole 10a reaching the source / drain electrode film 7 is formed. The plasma water-repellent regions 12d and 12e that have been subjected to the water-repellent treatment are removed at the same time that the portions of the photosensitive acrylic resin film 10 that become the contact holes 10a are removed by the development process.

Finally, when the application type transparent conductive film 13 is applied by spin coating or the like, as shown in FIG. 6 (p), the surface of the photosensitive acrylic resin film 10 to which water repellency is not provided and the contact hole The inside of 10 a is covered with the coating type transparent conductive film 13. As the coating type transparent conductive film 13, indium tin oxide (ITO) or the like can be used to form a pixel electrode. Thereafter, the substrate surface is baked at 200 ° C. to form a pixel electrode made of the coating type transparent conductive film 13.

As described above, the high aperture ratio active matrix substrate 14 is formed. In the manufacture of the high aperture ratio active matrix substrate 14 of the present embodiment, (b),
Since a photomask is used in the three steps (e) and (l), it is possible to manufacture a TFT array using a total of three photomasks. That is, a TFT array having a structure in which the gate electrode film 2 and the coating type transparent conductive film 13 serving as a pixel electrode are three-dimensionally overlapped and capable of realizing high luminance with a high aperture ratio is manufactured by a conventional manufacturing process. It is possible to manufacture with three photomasks, which is a smaller number of masks than in the case of FIG.

FIG. 7 is a diagram showing a simplified cross-sectional shape of the mask 15 for halftone exposure used in the embodiment of the present invention, a corresponding transmitted light amount, and a generated resist pattern shape. FIG. 7 shows an example in which a positive resist is used. The mask 15 is a mask capable of halftone exposure used as the second and third photomasks in the method of manufacturing the high aperture ratio active matrix substrate 14 according to the above-described embodiment. Mask 15
Are the transmission part 15A, the light shielding part 15B and the mesh part 15
C is provided. In a general photomask, a portion where the light transmission amount is formed to be 100%, such as the transmission portion 15A,
A portion formed such that the light transmission amount is targeted at 0%, such as the light-shielding portion 15B. Mask 1 used in the above-described manufacturing method
5, the amount of transmitted light is further reduced by the transmission portion 15A and the light shielding portion 15B.
And a mesh part 15 </ b> C which is intermediate between the two. The mesh portion 15C is formed of, for example, a mesh pattern or a slit pattern whose interval is smaller than the resolution of the light used.

When a positive resist is used as shown in FIG. 7 due to the difference in the amount of transmitted light in each part of the mask 15, the resist thickness is zero at the part corresponding to the transmission part 15A and the part corresponding to the light shielding part 15B. A resist pattern 16 having a maximum resist thickness at the portion and a resist thickness corresponding to the amount of transmitted light at a portion corresponding to the mesh portion 15C is obtained. That is, by providing portions having different transmitted light amounts, it is possible to form a resist pattern 16 having a resist thickness in inverse proportion to the transmitted light amount in each portion. In the case where a negative resist is used, a resist pattern having a larger resist thickness can be formed in a portion where the amount of transmitted light is larger.

According to the method of manufacturing the active matrix substrate 14 having a high aperture ratio according to the embodiment of the present invention by utilizing such halftone exposure, the number of masks is smaller than that of the conventional manufacturing process. It is possible to manufacture with a single photomask. As described above, the high aperture ratio active matrix substrate 1 according to the present embodiment
In the manufacturing process of No. 4, a photomask similar to the conventional one is used for patterning the first gate film, but a mask capable of halftone exposure is used for the second and third substrates. In the second mask, the conventional island patterning of the second TFT element portion and the third conventional source / drain separation and channel etching can be performed by a single photomask using halftone exposure. Do. In the third photomask, the conventional patterning of the photosensitive acrylic resin film for forming the fourth contact hole and the conventional patterning of the fifth ITO pixel electrode film are performed using halftone exposure. Performed collectively with one photomask.

In the high aperture ratio active matrix substrate 14 of the present embodiment, since the ITO film as the pixel electrode is formed by coating, the pixel electrode can be formed without using a vacuum film forming method such as plasma CVD or sputtering. The manufacturing cost can be reduced.

[0034]

As described above, according to the present invention, the surface of the electric insulating film other than the pixel electrode forming region is subjected to the water-repellent treatment, and the exposed and water-repellent surface is subjected to the development treatment to develop the electric-repellent surface. Since a conductive material is applied to the contact hole portion and the pixel electrode formation region from which the insulating film has been removed, it is not necessary to use a photomask for forming the contact hole and the pixel electrode. The number of photomasks required for the above can be reduced.

Further, according to the present invention, a resist layer is formed on the electric insulating film, and the resist layer is formed so that a predetermined pixel electrode formation region remains thick, a predetermined contact hole region does not remain, and the like. The non-formed area is left thin, so that halftone exposure is performed with a mask whose exposure is adjusted in multiple steps for each area, patterning is performed, and the electrical insulating film in the contact hole area is exposed using the patterned resist layer as a mask, The resist is etched until the thin resist layer in the non-formation area is removed, the electric insulation film other than the pixel electrode formation area is subjected to a water-repellent treatment to remove the resist, and then the electric insulation film is developed and the contact hole area is developed. It is patterned so that a through hole reaching the matrix circuit is formed in the electric insulating film, and is applied on the patterned electric insulating film. By forming the pixel electrode conductive material is applied, it is possible to form the pixel electrode conducting with the matrix through the contact hole and the contact hole in one photomask.

According to the present invention, an active matrix substrate having a high aperture ratio which allows the overlap of pixel electrodes can be formed only by using three photomasks. Since the water repellency of the electrical insulating film is removed after the formation, the liquid crystal display device can be formed even if the plasma water repellent region remains on the surface of the photosensitive acrylic resin film. The in-plane uniformity can be improved in the alignment treatment performed when forming the liquid crystal display device by removing the water-repellent region by etching or the like.

Further, according to the present invention, the surface of the matrix substrate is flattened by using a photosensitive acrylic resin as an electrically insulating synthetic resin material, and subjected to a water-repellent treatment by plasma irradiation using a fluorine-based gas. After removing the resist, the coating type transparent conductive material is limited to the region surrounded by the water-repellent treatment region, that is, the coating type conductive material is applied to the pixel electrode formation region and filled into the contact hole, and the photomask is formed. A pixel electrode can be formed without using it.

[Brief description of the drawings]

FIG. 1 is a simplified cross-sectional view showing a manufacturing process of a high aperture ratio active matrix substrate 14 according to an embodiment of the present invention.

FIG. 2 is a simplified cross-sectional view showing a manufacturing process of a high aperture ratio active matrix substrate 14 according to one embodiment of the present invention.

FIG. 3 is a simplified cross-sectional view showing a manufacturing process of the high aperture ratio active matrix substrate 14 according to one embodiment of the present invention.

FIG. 4 is a simplified cross-sectional view showing a manufacturing process of the high aperture ratio active matrix substrate 14 according to one embodiment of the present invention.

FIG. 5 is a simplified cross-sectional view showing a manufacturing process of the high aperture ratio active matrix substrate 14 according to one embodiment of the present invention.

FIG. 6 is a simplified cross-sectional view showing a manufacturing process of the high aperture ratio active matrix substrate 14 according to one embodiment of the present invention.

FIG. 7 is a diagram showing a simplified cross-sectional shape of a mask 15 for halftone exposure used in an embodiment of the present invention, a corresponding transmitted light amount, and a generated resist pattern shape.

FIG. 8 shows a conventional high aperture ratio active matrix substrate 34.
FIG. 4 is a simplified cross-sectional view showing an outline of a manufacturing process of FIG.

FIG. 9 shows a conventional high aperture ratio active matrix substrate 34.
FIG. 4 is a simplified cross-sectional view showing an outline of a manufacturing process of FIG.

FIG. 10 shows a conventional high aperture ratio active matrix substrate 3.
FIG. 4 is a simplified cross-sectional view illustrating an outline of a manufacturing process of No. 4;

FIG. 11 shows a conventional high aperture ratio active matrix substrate 3.
FIG. 4 is a simplified cross-sectional view illustrating an outline of a manufacturing process of No. 4;

FIG. 12 shows a conventional high aperture ratio active matrix substrate 3.
FIG. 4 is a simplified cross-sectional view illustrating an outline of a manufacturing process of No. 4;

FIG. 13 shows a conventional high aperture ratio active matrix substrate 3.
FIG. 4 is a simplified cross-sectional view illustrating an outline of a manufacturing process of No. 4;

[Explanation of symbols]

1,21 glass substrate 2,22 gate electrode film 3,8,16,23,27,29 resist pattern 4,24 gate insulating film 5,25 first semiconductor layer 5a channel section 6,26 second semiconductor layer 7,28 Source / drain electrode film 8a Thin portion 9,30 Passivation film 10,31 Photosensitive acrylic resin film 10a Contact hole 11 Resist layer 11a Pixel region 12a, 12b, 12c, 12d, 12e Plasma water-repellent region 13,32 Coating Type transparent conductive film 14, 34 High aperture ratio active matrix substrate 15 Mask 15A Transmission part 15B Light shielding part 15C Mesh part 33 Pixel electrode

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 21/336 H01L 29/78 612D 627C (72) Inventor Tatsushi Yamamoto 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka (72) Inventor Toru Kira 22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka F-term (reference) 2H092 GA29 JA24 JA34 JA37 JA41 JA46 JB57 KB24 MA05 MA08 MA13 MA15 MA17 NA07 NA27 PA01 5C094 AA10 AA43 BA03 BA43 CA19 DA14 DA15 DB01 DB04 EA04 EA07 EB02 ED15 FB12 FB14 FB15 5F033 GG04 HH38 JJ38 KK04 KK08 KK17 KK21 MM05 PP26 QQ00 QQ01 QQ26 QQ73 RR21 RR27 SS21 XX33 FF33 FF33 FF33 HK04 HK09 HK16 HK21 HK33 HK35 HL07 HL14 HL21 HL26 HL27 NN03 NN24 NN27 NN34 NN35 NN36 NN72 QQ02 QQ19 QQ30

Claims (4)

[Claims] 1. A method of manufacturing a matrix substrate for a liquid crystal in which a matrix circuit for forming a plurality of liquid crystal cells is formed on an electrically insulating substrate. A resin material is applied to form an electric insulating film having a flat surface, a resist layer is formed on the surface of the electric insulating film, and the resist layer is contacted with a predetermined contact so that a predetermined pixel electrode formation region remains thick. Half-tone exposure is performed using a mask with the exposure adjusted in multiple stages for each area so that the hole area does not remain, and the non-formation area other than the pixel electrode formation area and the contact hole area remains thin. Using the resist layer as a mask, exposing the electrical insulating film in the contact hole region to a resist remaining thin in the non-formed region. The resist layer is etched to a thickness at which the layer is removed, the electric insulating film in the contact hole area and the non-formed area is subjected to a water-repellent treatment to remove the resist remaining in the pixel electrode forming area, and the electric insulating film is developed. Patterning so that a through hole reaching the matrix circuit is formed in the electric insulating film in the contact hole region, and applying a coating type conductive material on the patterned electric insulating film to form a pixel electrode. Of manufacturing a liquid crystal matrix substrate. 2. The method according to claim 1, wherein the matrix circuit is a TFT active matrix circuit including a plurality of thin film transistors, and the manufacturing process of the TFT active matrix circuit includes: forming a gate electrode material on the electrically insulating substrate; An electrode film patterning step, a laminating step of sequentially laminating a gate insulating film, a first semiconductor layer serving as a channel region, a second semiconductor layer serving as an ohmic contact layer, and a metal layer serving as source / drain electrodes. The first semiconductor layer and the second semiconductor layer by halftone exposure using a mask in which the exposure amount is adjusted in a plurality of stages for each
2. The method according to claim 1, further comprising: a separation etching step of forming the semiconductor layer in an island shape, patterning a source / drain electrode and channel etching, and a passivation step of forming a passivation film after the separation etching step. The manufacturing method of the matrix substrate for liquid crystal of the description. 3. The method for manufacturing a liquid crystal matrix substrate according to claim 1, wherein the water repellency of the electric insulating film in the non-formation region is removed after the formation of the pixel electrode. 4. A photosensitive acrylic resin is used as the electrically insulating synthetic resin material, and the water-repellent treatment is performed by irradiating a plasma using a fluorine-based gas. The method for manufacturing a liquid crystal matrix substrate according to claim 1, wherein the method is formed of a conductive material.