JP2002244993A - Dma transfer control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manage the priority order of a memory access on the DMA(Direct Memory Access) controller side, optimize the memory access, and enhance the throughput of the data transfer of the whole system. SOLUTION: Using a DMA controller 320, the DMA transfer is controlled between a DRAM 204, a plurality of CPU1 and CPU2 (201 and 202), and a plurality of DMA channels (310, 311, 312) corresponding to the respective peripheral circuits as specified. The DMA controller 320 is equipped with a priority order deciding circuit 133, which decides the priority order concerning the data input/output for not only the DMA channels of the peripheral circuits but also a plurality of CPU memories in accordance with the conditions of the control lines between the DMA channels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory and a DMA transfer control device for performing a DMA transfer between a plurality of DMA channels respectively corresponding to predetermined peripheral circuits.

[0002]

2. Description of the Related Art Hitherto, a so-called DMA transfer technique for performing data transfer using a DMA controller has been known in various information processing apparatuses such as printers, copiers, and computers. In the DMA transfer, the DMA controller performs arbitration (arbitration) of the bus without the control of the CPU. Therefore, generally, high-speed data transfer can be performed regardless of the capacity and load of the CPU.

A conventional DMA controller only controls the multi-channels controlled by the DMA controller itself.
As for the access, the user did not have a means for freely determining the priority. Normally, CPU access is prioritized, and during periods when the CPU is not using DMA access,
The controller occupies the bus. At this time, among the plurality of DMA channels managed by the DMA controller, the DMA channel having the highest priority acquires the right to access.

[0004]

However, in a system using a plurality of CPUs in the above-mentioned conventional example, it is necessary to always increase the priority of memory access with respect to the CPU as described above. The result was a limit to improvement.

For example, in a case where a memory access by a DMA controller is used for data transfer to a print head in an ink jet printer, the data transfer by the DMA controller is not allowed to be delayed in order to form an accurate image. On the other hand, for cost reduction, a structure in which the memory used by a plurality of CPUs is shared with the DMA controller is conceivable. The worst case may occur where the controller gains access rights less often, delaying data transfer to the printhead.

However, simply lowering the priority of the CPU by the DMA controller may increase the wait state of the CPU and reduce the throughput.

An object of the present invention is to manage the priority of memory access on the DMA controller side, optimize memory access, and improve the data transfer throughput of the entire system.

[0008]

According to the present invention, there is provided a DMA transfer control apparatus for performing a DMA transfer between a plurality of DMA channels each corresponding to a predetermined peripheral circuit. A plurality of CPUs for inputting / outputting data to / from the memory; and detecting input / output requests to / from the memory of the plurality of CPUs as DMA transfer requests of DMA channels corresponding to the respective CPUs. A plurality of DMA channels, and a DM of a DMA channel corresponding to the CPU.
If any one of the A transfer requests occurs at the same time, the generated D
A configuration having a DMA controller that performs a DMA transfer corresponding to an MA transfer request is employed.

[0009]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

(First Embodiment) FIG. 2 shows a device employing the present invention, in particular, a plurality of CPUs (CPU1 and CPU2).
Alternatively, the overall configuration of a system including peripheral circuits for performing memory access by DMA transfer via a plurality of DMA channels (CH1, CH2,...) May be shown. Such a configuration is common to various information processing apparatuses such as a printer (for example, an ink jet printer described in the related art), a copying machine, and a computer.

FIG. 2 shows how a custom IC (hereinafter referred to as an ASIC) incorporating the DMA controller is arranged in the entire system.

In FIG. 2, reference numeral 201 denotes CPUs 1 and 20.
2 is CPU2, 203 is ASIC, 204 is DRAM,
205 is a ROM. The DRAM of 204 has an address bus, a data bus and a control bus,
ASIC 203 is connected via DR
The configuration is such that control of the AM 204 is completely delegated to an internal DMA controller.

FIG. 3 mainly shows the structure of the ASIC 203 of FIG. In FIG. 3, reference numeral 310 denotes a channel 1 (CH1) which is a peripheral circuit block for requesting memory access to the DMA controller, 311 denotes a channel 2 (CH2) which is a peripheral circuit block for requesting memory access to the DMA controller, and 312 Channel 3 (CH3), which is a peripheral circuit block that requests a memory access to the DMA controller.

The above peripheral circuits include a network I / F.
And various data input / output circuits (printer I
/ F and control circuit of printing hardware)
Various various input / output circuits that need to input / output to / from M204 are included.

CPU1 (201) and CPU2 (20)
2) is connected to the DMA controller 320 in a completely parallel relationship with the peripheral circuit blocks 310 to 312.
Therefore, the DMA controller 320 only uses the D channel based on the priority of the internally set connected channel.
The access control for the RAM 204 is performed.

FIG. 1 shows the internal configuration of a DMA controller 320 employing the present invention. In FIG. 1, selectors 105 and 106 are provided for controlling addresses of a plurality of DMA channels (CH1, CH2,...) For controlling memory access of peripheral circuits.

That is, in FIG. 1, reference numeral 100 denotes
The address generation circuit for channel 1 (CH1) 101
The address generation circuit for channel 2 (CH1), 102
The address generation circuit for channel 3 (CH1) 103
An address bus 104 of the CPU 1 is an address bus of the CPU 2.

The address lines output from 101 to 104 are connected to a selector 105. The selector 105 selects and outputs the channel or CPU address determined by the DMA priority determination circuit 133 and inputs the selected address to the selector 106. Here, the selector 10
5 is DR using the row address enable signal 151.
Generate the row address and column address of AM204,
Output to the address bus 107.

A timing controller circuit 115 is provided for controlling memory access of the two CPUs 1 and 2.

That is, reference numeral 110 denotes the DR of the CPU 1.
A chip select signal for the AM 204, 111 is a read signal (RD), 112 is a write signal (WR), 113
Is a wait signal (WAIT) for extending the bus cycle of the CPU 1;
Acknowledgment signal (DACK4) output when access to is completed.

Reference numeral 115 denotes a chip select signal (C
S) 110 and acknowledge signal (DACK4) 11
4, a DMA request signal (DREQ4) 11
6 and an output enable signal (OE) 117.

Reference numeral 120 denotes a DRAM 204 of the CPU 2.
Select signal (CS), 121 is a read signal (RD), 122 is a write signal (WR), 123 is a wait signal (WAIT) for extending the bus cycle of the CPU 2, and 124 is an end of access from the CPU 2 to the DRAM 204. This is an acknowledge signal (DACK5) that is output when this is done.

Reference numeral 125 denotes a chip select signal (C
S) 120 and acknowledge signal (DACK4) 12
4, the DMA request signal (DREQ5) 12
6 and a timing generation circuit for generating an output enable signal (OE) 127.

Reference numeral 130 denotes a DMA channel 1 (CH
1) DMA request signal (DREQ1), 131 is a DMA request signal (DREQ2) of DMA channel 2 (CH1), 132 is DMA channel 3 (CH1)
DMA request signal (DREQ3).

The priority determining circuit 133 receives the request signals (DREQ1 to DREQ3) 130 to 132 and outputs
Request signals (DREQ4, DREQ4) from PU1 and PU2
REQ5) 116, 117, and selects the request signal with the highest priority among these DMA requests.
Output as ESULT [5: 1]. This RESU
The LT signal 134 is a signal that outputs “1” only to the selected request signal.

The priority determining circuit 133 generates the generated DM.
The priority of the A request is determined as follows.

In the present embodiment, the CPU is simply used as in the prior art.
Of the peripheral circuit channel during the period when there is no access
Instead of performing MA transfer, CPU1 (201)
And the CPU 2 (202)
DMA controller 320 in a completely parallel relationship with 312
The priority order determination circuit 133 treats a CPU with a higher priority as a DMA channel with the highest priority, and sets a lower priority with a DMA controller for a CPU with a lower priority. Treated as one channel.

Such a priority setting is performed by a register provided inside the priority determining circuit 133, etc.
The priority setting of each channel including the CPU 2 is stored, and when a plurality of DMA requests occur at the same time, the DMA request of the higher priority channel is preferentially executed using the setting information of this register. You.

For example, CPU1, CPU2 (201,
202), if one of them is in charge of processing that requires real-time processing, such as inputting data to the print head of an ink jet printer as described in the conventional example, the CPU priority is determined. It is conceivable that the value is increased by the circuit 133. Thus, CPU1,
By increasing the priority of DMA channels that require real-time performance, including the CPU 2, the throughput of the system is improved, and the processing that requires real-time performance is prevented from being delayed. Can be prevented beforehand.

Further, in FIG.
This is a timing generation circuit that generates an output signal to the RAM 204. Reference numeral 151 denotes a row address enable signal (RAE), which enables the output of the row address among the addresses finally selected by the selector 106. Then, a row address enable signal (RAE) 1
When 51 is disabled, a column address is output.

Reference numeral 152 denotes a RAS signal, 153 denotes a CAS signal, 154 denotes a write enable signal (WE),
Reference numeral 155 denotes an output enable signal (OE) for the DRAM 204, and reference numeral 156 denotes an ACK signal (ACK) for notifying that the access has been completed in response to a request from the DMA controller 320. 157 is a DRAM 204
This is an output buffer enable signal (OBE) for enabling data output to the output buffer.

Reference numeral 160 denotes a logic circuit, which distributes an ACK signal (ACK) 156 to any one of the acknowledgment signals 161 to 165 based on the RESULT [5: 1] signal 134 output from the priority determination circuit 133. The acknowledge signals denoted by reference numerals 161 to 165 are as follows.

Reference numeral 161 denotes a DACK1 signal connected to the channel 1 block circuit (310), and reference numeral 162 denotes a DACK signal connected to the channel 2 block circuit (311).
2 signals, 163 is a block circuit of channel 3 (312)
Is a DACK3 signal connected to. Reference numeral 164
Are the DACK4 signals connected to the CPU 1 (201),
65 is a DACK5 signal connected to the CPU2 (202).

The control of the data bus is performed by the following circuit.

Reference numeral 140 denotes write data from channel 1; 141, write data from channel 2;
Is a write data from channel 3, 144 is a data bus connected to CPU1, and 145 is a data bus connected to CPU2.

Reference numeral 146 denotes a selector for selecting write data based on the priority output from the priority determining circuit 133 based on the write data 140 to 142 described above. The write data selected by the selector 146 is based on an output buffer enable signal 157 output from the timing creation circuit 150,
Output to RAM 204.

Next, the operation of the above configuration will be described.

FIG. 4 is a state machine showing the operation of the control circuit of the present invention. The operation starts from the reset state of 501 after the power is turned on. Although not shown in FIG. 4, at this point, the address generation circuits 100 to 102 have completed the initial setting of what address to generate, and the priority determination circuit 133 determines which request Set priority (for example,
It is assumed that the above-described priority programming by the built-in register of the priority order determination circuit 133 has been completed.

Immediately after the reset, the operation shifts to the standby state denoted by reference numeral 502. This standby state is
The A controller 320 is in a state of waiting for a request from a peripheral circuit.

Here, when an access request is issued from the CPU 1 to the DRAM 204, the processing shifts to the CPU 1 access state 510. The condition for this transition is when the access of the CPU 1 is recognized by the priority order determination circuit 133. Similarly, when an access request is issued from the CPU 2 to the DRAM 204, the processing shifts to the CPU 2 access state 511. The condition for this transition is when the access of the CPU 2 is recognized by the priority order determination circuit 133 as described above.

The DMA channel 1 to the DRAM 20
When an access request is issued to the DMA channel No. 4, the state shifts to the DMA channel 1 access state 520. The condition for this transition is when the access to the DMA channel 1 is recognized by the priority order determination circuit 133. Similarly, when an access request is issued from the DMA channel 2 to the DRAM 204, the state shifts to the DMA channel 2 access state 521. The condition for this transition is when the access to the DMA channel 2 is recognized by the priority order determination circuit 133. Similarly, the DMA channel 3 to the DRAM 204
When an access request is issued to the DMA channel 3, the state shifts to the DMA channel 3 access state 522. The condition for this transition is when the access to the DMA channel 3 is recognized by the priority order determination circuit 133.

As described above, when a plurality of access requests occur simultaneously, the priority order determination circuit 133 determines which access request is to be given priority and permitted based on a predetermined priority order.

As described above, according to the present embodiment,
A plurality of CPUs, CPU1 (201) and CPU2 (20
2) is connected to the DMA controller 320 in a completely parallel relationship with the peripheral circuit blocks 310 to 312, and the DMA access priority including the DMA request of the CPU is unitarily managed by the DMA controller. It can be treated as a DMA channel with the highest priority, and a CPU with a lower priority can be treated as one channel with a lower priority set by the DMA controller. With this configuration, according to the present embodiment, it is possible to optimize the memory access by increasing the priority of the DMA channels that require real-time properties, and to improve the data transfer throughput of the entire system. it can.

(Second Embodiment) FIG. 5 shows a different embodiment obtained by expanding the first embodiment of FIG. FIG. 5 shows D in FIG.
This is a circuit example in which a part of the MA controller 320 is modified, and the other configuration is the same as that described above. FIG.
Reference numeral 600 denotes an address generation circuit for automatically setting an address when the CPU 2 accesses the DRAM 204. 620 is DRAM2 from CPU2
A FIFO for temporarily storing write data to the C.04,
610 is a chip select signal of the FIFO 620, 631
Is a busy signal indicating that the FIFO 620 is full, 632 is an empty signal indicating that the FIFO 620 is empty, and when there is data in the FIFO,
A DMA request signal 126 is generated for the priority determining circuit 133.

As described above, even in a configuration in which write data on the CPU 2 side is input via the FIFO 620 and a DMA request is detected using the DMA request signal 126, the same operation as described above is performed using the priority order determination circuit 133. , The priority of memory access can be controlled, the memory access can be optimized, and the data transfer throughput of the entire system can be improved.

[0046]

As is apparent from the above description, according to the present invention, in a memory and a DMA transfer control device for performing DMA transfer between a plurality of DMA channels respectively corresponding to predetermined peripheral circuits, A plurality of CPUs for inputting and outputting data to and from the memory, and detecting input / output requests to the memory of the plurality of CPUs as DMA transfer requests of DMA channels corresponding to the respective CPUs;
When any one of the DMA transfer requests of the plurality of DMA channels corresponding to the peripheral circuit and the DMA channel corresponding to the CPU occurs at the same time, the generated DMA transfer request is performed based on a predetermined priority order. Since a configuration having a DMA controller for performing the corresponding DMA transfer is employed, the priority order of the DMA access including the DMA request of the CPU is centrally managed by the DMA controller.
Is treated as the highest priority DMA channel, and
Optimize memory access by increasing the priority of DMA channels that require real-time processing by treating low priority CPUs as one channel with a low priority set by the DMA controller. And the data transfer throughput of the entire system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a DMA controller according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an entire system using the DMA controller of FIG. 1;

FIG. 3 is a block diagram of an ASIC portion including the DMA controller of FIG. 1;

FIG. 4 is a state transition diagram showing a state of DMA transfer control according to the first embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a DMA controller according to a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 100 address generation circuit (channel 1) 101 address generation circuit (channel 2) 102 address generation circuit (channel 3) 103 address bus of CPU1 104 address bus of CPU1 105 selector 106 selector (row address / column address) 107 DRAM address bus 110 DRAM chip select signal (CPU1) 111 Read signal (CPU1) 112 Write signal (CPU1) 113 Wait signal (CPU1) 114 DMA acknowledge signal 4 115 Timing controller 116 DMA request signal 4 117 Output enable signal (CPU1) 120 DRAM chip select Signal (CPU2) 121 Read signal (CPU2) 122 Write signal (CPU2) 123 Weight signal (CPU2) 124 DMA acknowledge signal 5 125 Timing controller 126 DMA request signal 4 127 Output enable signal (CPU2) 133 Priority determination circuit 134 RESULT signal 140 Write data (channel 1) 141 Write data (channel 2) 142 Write data (channel 3) 143 Data bus (CPU1) 144 Data bus (CPU2) 145 ASIC internal data bus 146 Selector 148 DRAM data bus 150 Timing generation circuit 151 Row address enable signal 152 RAS signal 153 CAS signal 154 Write enable signal 155 Output enable signal 156 DMA acknowledge Signal 157 Output buffer enable signal 160 Logic circuit 161 DA K1 signal 162 DACK2 signal 163 DACK3 signal 164 DACK4 signal 165 DACK5 signal 201 CPU1 202 CPU2 203 ASIC 204 DRAM 205 ROM ROM 310 DMA channel 1 circuit block 311 DMA channel 2 circuit block 312 DMA channel 3 circuit block 320 DMA controller 502 State 510 Access state (CPU1) 511 Access state (CPU2) 520 DMA channel 1 access state 521 DMA channel 2 access state 522 DMA channel 3 access state 600 CPU2 address generation circuit 610 FIFO chip select signal (CPU2) 620 FIFO 631 Busy signal 632 Empty signal

Claims (1)

[Claims] 1. A DMA transfer control device for performing a DMA transfer between a memory and a plurality of DMA channels respectively corresponding to predetermined peripheral circuits, comprising: a plurality of CPUs for inputting and outputting data to and from the memory;
And detecting input / output requests to the memory of the plurality of CPUs as DMA transfer requests of DMA channels corresponding to the respective CPUs, and detecting a plurality of DMs corresponding to the peripheral circuits.
When any one of the A channel and the DMA transfer request of the DMA channel corresponding to the CPU occurs at the same time, a DMA transfer corresponding to the generated DMA transfer request is performed based on a predetermined priority.
A DMA transfer control device comprising an MA controller.