JP2002237576A - Equipment for communication system and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an equipment for a communication system which is suitable for arrangement under severe conditions of use temperature and space constrains or the like. SOLUTION: Equipment for a communication system has a semiconductor device, which is formed by integrating Schottky diode 20, an MOSFETs 30, 40, a capacitor 50 and an inductor 60 on an SiC substrate 10. The SiC substrate 10 is provided with a first lamination part 12, wherein a δ-doped layer 12a containing high concentration n-type impurities (nitrogen) and an undoped layer 12b are laminated alternately, and a second lamination part 13, wherein a δ-doped layer 13a containing high concentration p-type impurities (aluminum) and an undoped layer 13b are laminated alternately one by one, starting from below. Carrier of the δ-doped layer extends to an undoped layer. Since the impurity concentration in an undoped layer is low, impurity ion scattering is small, thus low resistance and high break down voltage value are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a semiconductor power device used for a high withstand voltage and a large current is arranged, and equipment for a communication system such as a portable terminal and a radio base station using the same. About.

[0002]

2. Description of the Related Art Silicon carbide (silicon carbide, Si
C) is a semiconductor having a large band gap as compared with silicon (Si), and thus has a high withstand voltage, and is a semiconductor that is stable even at high temperatures. Is expected to be applied to next-generation power devices and high-temperature operating devices.

[0003] In general, a power device is a general term for a device that converts and controls a large amount of power, and is called a power diode, a power transistor, or the like. And
Applications of power devices include, for example, mobile terminals that function as mobile stations in communication systems, automobile telephones, transistors and diodes disposed in their base stations, and the like. it is conceivable that.

In general, for these uses, a configuration is adopted in which a plurality of semiconductor chips each having a built-in power device are connected by wiring according to the use and purpose, and are housed in one package to form a module. I have. For example, a wiring is formed on a substrate so as to form a circuit corresponding to a use, and each semiconductor chip is mounted on the substrate, whereby a desired circuit is formed by the semiconductor chip and the wiring. Here, a Schottky diode and an M
A wireless base station transmitting / receiving circuit using an ESFET will be described.

FIG. 20 shows a conventional base station described in the literature (“High-frequency / optical semiconductor device p124 opening up a new era of information and communication”, Daisuke Ueda et al., Published on December 1, 1999 by the Institute of Electronics, Information and Communication Engineers). (Base station of communication system)
FIG. 3 is a block circuit diagram showing the internal configuration of FIG. As shown in the figure, an antenna body, an antenna unit, a reception amplification unit,
It includes a transmission amplifier, a radio transceiver, a baseband signal processor, an interface, an exchange controller, a controller, and a power supply. The reception amplification unit is configured by arranging a filter and a low-noise amplifier (LNA) in two stages in series. A mixer for mixing the outputs of the local amplifier and the high-frequency transmitter to generate a high-frequency signal is disposed in the wireless transmitting and receiving unit. The transmission amplifier includes a driver amplifier, a filter, a middle amplifier, and a power distribution / combination circuit in which four main amplifiers are disposed. Further, a baseband signal processing unit for processing an audio signal, an interface unit, and an exchange control unit connected to an exchange network (network) are provided.

Here, in the conventional base station, the main amplifier includes an input matching circuit, a field effect transistor (MESFET) formed using a GaAs substrate, and a capacitor, an inductor and a resistance element on the input side and the output side. They are arranged so as to achieve impedance matching.

A control unit, a baseband signal processing unit,
A MOSFET, a diode, a capacitor, a resistance element, and the like formed on a silicon substrate are arranged in the interface unit and the exchange control unit. In particular, components such as a capacitor (capacitor) and an inductor that require a large area are formed as independent chips.

[0008]

However, the conventional communication system has the following disadvantages.

In the above-mentioned conventional base station, a signal amplifying element which is the most important part such as a transmission / reception circuit is generally formed using a GaAs substrate. Since GaAs has low heat resistance, a cooling device having a large cooling capacity is required to suppress a rise in temperature, and a large running cost is required to maintain the base station. Also,
In the case of application to portable terminals, it is necessary to reduce the size of the circuit. However, GaAs MESFETs and other devices with weak heat resistance are subject to strict positional restrictions such as keeping away from FETs and inductors that tend to rise to high temperatures due to high-frequency signals. is there. As a result, although the positional relationship between the components is devised in various ways, the transmission / reception circuit itself must be large.

A signal amplifying element, which is the most important part of a transmission / reception circuit or the like, is provided with a large number of MESFETs, particularly in a part where large power must be amplified. Is higher,
Since the influence of the reflected wave from the MESFET overlaps, it is difficult to achieve impedance matching. As a result, there has been a problem that the trouble of trimming for impedance adjustment becomes large.

An object of the present invention is to provide a communication system device using an active element which is suitable for being placed under severe conditions such as operating temperature and space restrictions.

[0012]

An apparatus for a communication system according to the present invention is an apparatus arranged in a communication system and having an active element formed using a compound semiconductor, wherein the active element is provided on a substrate. Compound semiconductor layer, at least one first semiconductor layer provided on the compound semiconductor layer and functioning as a carrier traveling region, and a film containing a high concentration of carrier impurities and a film thickness higher than that of the first semiconductor layer. An active region formed by providing at least one second semiconductor layer having a small thickness and capable of distributing carriers by a quantum effect so as to be in contact with each other.

According to this structure, the carriers in the second semiconductor layer spread to the first semiconductor layer, and the carriers are distributed over the entire active region. When the active element operates, the impurity concentration in the first semiconductor layer is low, so that impurity ion scattering in the first semiconductor layer is reduced. Therefore, the active element is
When a T or Schottky diode is used, a particularly high carrier traveling speed can be obtained, so that a large current can be obtained by utilizing low resistance. In addition, despite the fact that the average impurity concentration in the active region is relatively high, the entire active region is depleted in the off state and no carriers are present in the active region. Thus, the breakdown voltage is defined, and a high breakdown voltage value can be obtained in the entire compound semiconductor layer.

Therefore, by arranging active elements having high withstand voltage and low resistance (that is, high current driving force) in a communication system, the number of active elements in communication system equipment can be reduced. This makes it possible to reduce the size of the device and facilitate the impedance adjustment.

By laminating the first semiconductor layer and the second semiconductor layer in a plurality of layers, respectively, the above-described effects can be more reliably exerted.

Since the active element is a horizontal Schottky diode, the Schottky diode is
Since it can be integrated on one substrate together with the ESFET, etc., impedance matching becomes easy especially in a communication system device handling a high frequency signal.
As a result, a remarkable effect that the operating frequency can be improved can be exhibited.

The active element includes a gate insulating film provided on the first semiconductor layer, a gate electrode provided on the gate insulating film, and both sides of the gate electrode in the compound semiconductor layer. MISFET further provided with a source / drain region provided in the MISFET, the impurity concentration of the first semiconductor layer is low, so that the MISFET is trapped in the gate insulating film or near the interface between the gate insulating film and the compound semiconductor layer. The number of charges of the second conductivity type is also reduced, and the effect of the charges on the carrier traveling is reduced. Further, when the carriers spread due to the quantum effect, the first conductivity type charges are trapped by the impurities in the second semiconductor layer, so that the carriers are trapped in the gate insulating film or near the interface between the gate insulating film and the compound semiconductor layer. It is possible to compensate for the effect of the charge of the second conductivity type on the traveling of carriers. Therefore, it is possible to further increase the channel mobility.

By further providing a capacitor and an inductor provided on the compound semiconductor layer, it becomes possible to configure an MMIC using a compound semiconductor. Furthermore, since the capacitors and inductors are integrated on one substrate, it is possible to further facilitate the impedance matching.

By using the compound semiconductor layer as the SiC layer, it is possible to realize a high withstand voltage utilizing a large band gap of SiC and a high integration of an element utilizing a high heat resistance.

The above device may be either a base station or a mobile station of a communication system.

The communication system may be a mobile phone, a PHS,
It can be any one of a car phone and a PDA.

By arranging the active element in the transmission section of the communication system, it is possible to utilize a structure particularly suitable for high power.

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having an active element formed using a compound semiconductor, wherein the active element includes a compound semiconductor layer provided on a substrate, An active region provided on the semiconductor layer, the at least one first semiconductor layer functioning as a carrier traveling region; and a thinner than the first semiconductor layer containing a high-concentration carrier impurity. An active region configured to be provided in contact with at least one second semiconductor layer capable of distributing carriers by a quantum effect.

With this structure, the carriers in the second semiconductor layer spread to the first semiconductor layer, and the carriers are distributed over the entire active region. When the active element operates, the impurity concentration in the first semiconductor layer is low, so that impurity ion scattering in the first semiconductor layer is reduced. Therefore, the active element is
When a T or Schottky diode is used, a particularly high carrier traveling speed can be obtained, so that a large current can be obtained by utilizing low resistance. Moreover, in spite of the low average impurity concentration in the active region, the entire active region is depleted in the off state and no carriers are present in the active region. Is defined, and a high breakdown voltage can be obtained in the entire compound semiconductor layer.

The semiconductor integrated circuit device according to the present invention can also adopt the same preferred embodiment as the above-described communication system device.

[0026]

FIG. 1 is a block diagram schematically showing a configuration of a communication system according to an embodiment of the present invention. As shown in FIG.
It comprises a number of base stations 101 connected to each other via a switching network (network) 100, and a mobile phone terminal 102 for communicating with each other via each base station 101. Each base station 101 includes an antenna device 111 for receiving and transmitting a radio wave, and a reception amplification unit 1 having a function of amplifying a radio signal received by the antenna device 111.
12, a transmission amplification unit 113 for sending the amplified high-frequency signal to the antenna device 111, a radio transmission / reception unit 114 connected to the reception amplification unit 112 and the transmission amplification unit 113,
A control unit 115 for controlling the operation of each device and a wired connection unit 116 for connecting signals between the base station 101 and the switching network 100 are provided. In addition, the mobile phone terminal 102 has an antenna device 121 for receiving and transmitting radio waves, a reception amplifying unit 122 having a function of amplifying a radio signal received by the antenna device 121, and a signal amplified by the antenna device 121. A transmission amplification unit 123 for sending a high-frequency signal and a control unit 125 for controlling the operation of each device are provided.

FIG. 2 is a block circuit diagram showing the internal configuration of base station 101 in more detail. As shown in the drawing, the antenna device 111 includes an antenna body 111a and an antenna unit 111b for switching transmission and reception of the antenna body 111a. Further, the reception amplifying unit 112 includes a filter 131 and a low noise amplifier (LNA).
132 and two stages in series. A mixer 134 for mixing the outputs of the local amplifier and the high-frequency transmitter to generate a high-frequency signal
Is arranged. The transmission amplifier 113 includes a driver amplifier 135, a filter 136, and a middle amplifier 137.
And a main amplifier 138. The wired connection unit 116 includes a baseband signal processing unit 117 for processing an audio signal, an interface unit 118, and an exchange control unit 11 connected to an exchange network (network) 100.
9.

FIG. 3 is an electric circuit diagram showing a structural example of the main amplifier 138 arranged in the transmission / reception amplifier 113 shown in FIG. As shown in FIG.
Is a MESFE that receives an input signal Pin at a gate via an input side circuit and outputs an output signal Pout from a drain.
T is arranged. A gate bias Vg is applied to the gate of the MESFET via a resistor Rg, a power supply voltage Vd is applied to a drain of the MESFET via a choke inductor, and a source of the MESFET is connected to the ground. The input side circuit includes an input terminal Tin for supplying an input signal Pin to the MESFET, a signal source for supplying power to the input terminal Tin via a signal source resistor _RS , and an input side impedance matching circuit. , And capacitors C1 and Cin and a microstrip line. The output side circuit includes an output terminal Tout for sending an output signal to the outside via the output side circuit, capacitors C2 and Cout and a microstrip line constituting an output side impedance matching circuit,
A load resistor _RL interposed between the output terminal Tout and the ground is provided. When a bipolar transistor is used instead of the MESFET, a diode shown by a broken line may be arranged between the emitter of the bipolar transistor and the ground.

Power amplifiers used for communication are required to have characteristics such as high efficiency and low distortion. Generally, in a high-frequency power device, efficiency and distortion have a trade-off relationship. In power amplifiers, it is important how to increase the efficiency while ensuring low distortion. As shown in the figure, in the input-side impedance matching circuit, the capacitance value of the capacitor Cin connected in parallel and the length Lin of the microstrip line are set so that the reflection coefficient viewed from the input terminal Pin to the MESFET side is as small as possible. Length and have been adjusted. Here, the capacitors C1 and C2 are capacitors for blocking current, and have sufficiently low impedance in a high frequency region. The resistance Rg for supplying the gate bias is set to a value higher than the gate input impedance so that the high frequency power does not leak. The inductance of the choke inductor L for supplying the drain bias, the capacitance of the capacitors C1 and C2, and the resistance of the resistor Rg do not affect the impedance in the high frequency range.

-Example of Semiconductor Device- Here, active elements such as transistors and diodes and passive elements such as capacitors and inductors, which are characteristic parts of the present invention, which are arranged in each circuit of the base station 101, are integrated. Will be described.

FIG. 4 shows an embodiment of the SiC according to the present invention.
Schottky diode, MESFET, MO on substrate
1 is a cross-sectional view of a semiconductor device (semiconductor integrated circuit device) formed by integrating an SFET, a capacitor, and an inductor.

The SiC substrate 10 which is a 4H-SiC substrate includes a first lightly doped layer 15 containing a lightly doped n-type impurity (nitrogen) and a δ-doped layer containing a lightly doped n-type impurity (nitrogen). And an undoped layer are alternately laminated, an active region serving as a carrier traveling region, a second low-concentration doped layer 16 containing a low-concentration p-type impurity (aluminum), Concentration of p-type impurity (aluminum)
A second laminated portion 13 (an active region serving as a carrier traveling region) in which a δ-doped layer and an undoped layer are alternately laminated is provided in order from the bottom, and the second laminated portion 13 and the second One region of the second lightly doped layer 16 is removed, and a part of the first stacked unit 12 is exposed on the substrate. An element isolation region 11 in which a silicon oxide film is buried in a trench is provided for partitioning each of the laminated portions 12 and 13 and each of the low-concentration doped layers 15 and 16 for each element. The low-concentration doped layers 15 and 16 may both be undoped layers.

Here, as shown in an enlarged manner below FIG. 4, the first laminated portion 12 has a high concentration (for example, 1 × 10 ¹⁸ at).
oms · cm ^-3 ), an n-type doped layer 12a containing nitrogen of about 10 nm in thickness and an undoped layer 12b of about 50 nm in thickness made of undoped 4H—SiC single crystal,
Each is composed of five layers. On the other hand, the second stacked section 13 has a high concentration (for example, 1 × 10 ¹⁸ atoms · c).
m- ³ ) a p-type doped layer 13a containing aluminum of about 10 nm in thickness and an undoped layer 13b of about 50 nm in thickness made of undoped 4H-SiC single crystal are alternately formed.
Each is composed of five layers. Each of the n-type doped layer 12a and the p-type doped layer 13a is formed thin enough to allow carriers to seep into the undoped layers 12b and 13b by the quantum effect. As described later, the impurity concentration profile of the n-type doped layer or the p-type doped layer has a substantially δ-functional shape with respect to the base of the undoped layer. Therefore, in this specification, the n-type doped layer 1
The 2a and p-type doped layers 13a are called so-called δ-doped layers. A structure in which a plurality of high-concentration doped layers (δ-doped layers) exhibiting a steep concentration gradient are alternately stacked with low-concentration doped layers (undoped layers) is referred to as a multiple δ-doped layer.

On a portion of the SiC substrate 10 where the first laminated portion 12 is exposed, a Schottky diode 20 (rectifying element) and a MESFET 30 (power amplifier) are provided. The nMOSF is located on a portion of the semiconductor device 10 where the second laminated portion 13 is present at the uppermost portion.
An ET 40 (switching element), a capacitor 50 (capacitance element), and an inductor 60 (inductive element) are provided. That is, MESFETs, diodes (broken lines), capacitors, and inductors that constitute the main amplifier 138 of the transmission amplification unit 113 shown in FIG.
The FET is provided on one SiC substrate.

The Schottky diode 20 has a first
(Ni) in Schottky contact with the laminated portion 12 of
The electrode lead layer 22 formed by injecting high-concentration nitrogen (for example, about 1 × 10 ¹⁸ atoms · cm ⁻³ ) into the first laminated portion 12 and the Schottky electrode 21 made of Nickel (Ni) for ohmic contact
And an ohmic electrode 23 composed of

The MESFET 30 is provided in the first laminated portion 1
A Schottky gate electrode 32 made of a Ni alloy film in Schottky contact with the undoped layer 12a,
And a source electrode 34 and a drain electrode 35 that are provided on regions of the first stacked unit 12 located on both sides of the gate electrode 32 and that make ohmic contact with the first stacked unit 12. However, high-concentration nitrogen may be introduced into a region of the first stacked unit 12 that contacts the source electrode 34 and the drain electrode 35.

The nMOSFET 40 includes a gate insulating film 4 made of SiO ₂ formed on the second laminated portion 13.
1, a gate electrode 42 made of a Ni alloy film formed on the gate insulating film 41, and a concentration of 1 × 10 ¹⁸ c
n-type source region 43 formed by injecting m ⁻³ of nitrogen
a and a drain region 43b, and a source electrode 44 and a drain electrode 4 made of a Ni alloy film in ohmic contact with the source region 43a and the drain region 43b, respectively.
5 is provided. It is needless to say that a pMOSFET can be provided by forming an insulated gate electrode, a p-type source / drain region, and the like in a certain region in the first stacked unit 12.

The capacitor 50 is connected to the second laminated portion 13
A base insulating film 51 made of a SiN film provided on
A lower electrode 52 made of a platinum (Pt) film provided on the base insulating film 51;
A capacitor insulating film 53 made of a high dielectric film such as ST, and platinum (P) facing the lower electrode 52 with the capacitor insulating film 53 interposed therebetween.
t) an upper electrode 54 made of a film.

The inductor 60 is connected to the first laminated portion 13
A dielectric film 61 made of a SiN film and a conductor film 62 made of a spiral Cu film formed on the dielectric film 61. Here, the conductive film 62
Has a width of about 9 μm, a thickness of about 4 μm, and a gap between the conductive films 62 of about 4 μm. However, the SiC substrate 1
Since 0 is high in heat resistance and high in thermal conductivity, the conductive film 62 can be miniaturized depending on the amount of current, and a finer pattern, for example, a width of 1 to 2 μm and a gap of 1
Shapes of about 2 μm are also possible.

An interlayer insulating film 70 made of a silicon oxide film is formed on the substrate, and a wiring (not shown) made of an aluminum alloy film, a Cu alloy film, or the like is formed on the interlayer insulating film 70. Is provided. The conductors of the elements 20, 30, 40, 50, and 60 are connected to wiring via contacts 71 made of an aluminum alloy film or the like filling the contact holes formed in the interlayer insulating film 70, as shown in FIG. Each circuit in the base station shown is configured. However, it is not necessary that all the circuits shown in FIG. 2 are provided on one SiC substrate, and one of the elements may be provided on another substrate (silicon substrate). For example, the transmission amplification unit and the reception amplification unit require a power element, so they are provided on a SiC substrate. However, a baseband processing unit that does not require a power element may be provided on a silicon substrate.

In the present embodiment, as shown in FIG. 4, the main devices among the devices in the base station 101 are mounted on one SiC substrate, and the necessary circuits are miniaturized. Therefore, the base station 1 in the present embodiment
1 (for example, the entire circuit shown in FIG. 2) can be miniaturized, and the total thickness thereof is only the sum of the thickness of the SiC substrate plus the thickness of the laminated film or the interlayer insulating film. Therefore, the entire base station 101 has a very thin structure. That is, the size of the base station 101 itself can be reduced. In particular, as shown in FIG. 4, a Schottky diode has a horizontal structure, and MES is formed on one SiC substrate.
Since it is possible to provide an FET, a Schottky diode, a MOSFET, and the like, integration is facilitated. Further, since passive elements such as inductors and capacitors can be mounted on the common SiC substrate, further miniaturization can be achieved.

Further, MESF formed on a SiC substrate
The temperature at which the normal operation of the ET or the Schottky diode can be secured is about 400 ° C.
Various restrictions due to the severe upper limit of the temperature of ° C. are greatly relaxed. That is, in the present embodiment, since the heat resistance of the MESFET and the Schottky diode on the SiC substrate is high, even if all the elements are arranged close to each other, almost no trouble due to the heat resistance occurs. In addition, since the circuit can be significantly reduced in size, a high degree of freedom in arrangement within the base station can be secured, and since the SiC substrate has a high thermal conductivity and good heat dissipation, each element in the circuit can be used. Can easily be prevented from being adversely affected by the heat dissipation of the power amplifier.

Therefore, it is possible to provide a semiconductor device having high power and high withstand voltage characteristics and suitable for a base station or a mobile station in a communication system. Since the heat resistance of the SiC substrate is high, when this semiconductor device is arranged in a base station, it can withstand long-term use without providing a cooling device having a particularly large cooling capacity. Installation costs and running costs such as electric power can be reduced. When this semiconductor device is arranged in a mobile station, a heat-generating element such as an inductor and
Even if the SFETs are arranged close to each other, it is possible to suppress the deterioration of the characteristics due to the temperature rise as in the case of using a GaAs substrate. Therefore, restrictions on the arrangement relationship of the semiconductor devices in the mobile station are relaxed, and the size of the entire mobile station can be reduced.

Further, by integrating many elements in the base station and the mobile station on a common SiC substrate, the labor for assembling parts can be omitted, and the manufacturing cost of semiconductor devices can be reduced. Furthermore, it is known that the device having the laminated portion in which the δ-doped layer and the low-concentration doped layer are laminated can improve the yield of the device because the reliability of the device is improved. Can also be achieved.

In particular, when the semiconductor device is applied to a device that handles a high-frequency signal on the order of GHz, it is preferable that the dielectric film 61 of the inductor 60 be formed of a BCB film (benzocyclobutene film). The BCB film refers to a film containing BCB in a structure obtained by dissolving a BCB-DVS monomer in a solvent, applying the solution, and baking. The BCB film has a characteristic that the relative dielectric constant is as small as about 2.7 and a thick film of about 30 μm can be easily formed by one application. The tan δ of the BCB film is 60
The BCB film can exhibit excellent characteristics particularly as a dielectric film constituting an inductor or a microstrip line, since it is about 0.006 at GHz and about one digit smaller than SiO ₂ .

-Multiple δ-doped layers- As described above, the semiconductor device of the present embodiment has a stacked structure in which n-type or p-type doped layers 12a and 13a, which are δ-doped layers, and undoped layers 12b and 13b are alternately stacked. Part (multiple δ
(Doped layer). Such a structure in which a high-concentration doped layer (δ-doped layer) and a low-concentration doped layer (undoped layer) are alternately laminated is described in Japanese Patent Application No. 2000-58964 and 2000-0621 as described later.
It is obtained by using the crystal growth apparatus and the crystal growth method disclosed in the specification of No. 0 and the drawings. More specifically, the supply of dopant gas (referred to as pulse doping) and the supply of source gas using a pulse valve are performed simultaneously, and an epitaxial growth method using in-situ doping is used.

FIG. 5 is a diagram showing the dopant concentration distribution in the depth direction of the multiple δ-doped layers (corresponding to the laminated portions 12 and 13) which are the active regions formed in this embodiment. In addition, the period during which the pulse valve is open (pulse width) when forming the n-type doped layer is 102 μs, and the period during which the pulse valve is closed (interval between pulses) is 4 ms. The concentration profile shown in the figure is obtained as a result of measurement using a secondary ion mass spectrometer (SIMS). In the figure, the horizontal axis represents the depth (μm) from the uppermost surface of the substrate, and the vertical axis represents the concentration of nitrogen as a dopant (atoms · cm ⁻³ ). As shown in the figure,
The concentration of nitrogen (N) in each n-type doped layer 12a formed by the method of the present embodiment is substantially uniform (about 1 × 10
¹⁸ atoms · cm ^-3 ), and undoped layers 12a to n
Transition to n-type doped layer 12b, n-type doped layer 12b
In each of the regions where the transition from to the undoped layer 12a occurs, the impurity concentration shows a very steep change. Note that the data in FIG. 5 is data obtained for a doped layer formed while flowing a nitrogen gas as a dopant gas when the period (pulse width) during which the pulse valve is open is set to 102 μs. Although the peak concentration of nitrogen is about 1 × 10 ¹⁸ atoms · cm ⁻³ , the peak concentration of nitrogen is set to 1 × 10 ¹⁸ by setting the period (pulse width) during which the pulse valve is open to about 110 μs.
It can be increased to about ¹⁹ atoms · cm ^-3 . If a nitrogen gas as a carrier gas is supplied, it is easy to control the nitrogen concentration of the undoped layer to about 1 × 10 ¹⁶ atoms · cm ⁻³ . By supplying a certain amount of nitrogen to the undoped layer by flowing a carrier gas,
There is also an advantage that the nitrogen concentration of the undoped layer can be stably controlled to a constant concentration.

FIG. 5 shows data on the n-type doped layer 12a, but a similar impurity concentration profile can be obtained for a p-type doped layer containing aluminum or the like as a dopant. As shown in FIG. 5, it can be seen that the impurity concentration profile of the n-type doped layer or the p-type doped layer has a substantially δ-functional shape with respect to the base of the undoped layer.

FIGS. 6A and 6B show the relationship between the concentration profile of nitrogen as an n-type impurity and the carrier distribution in the depth direction of the first laminated portion 12 which is the multiple δ-doped layer in the present embodiment. And a partial band diagram showing the shape of the conduction band edge along the depth direction of the first stacked unit 12. 6A and 6B show that the nitrogen concentration in the undoped layer 12b (low-concentration doped layer) is 5 × 10 ¹⁵ atoms · without using nitrogen as a carrier gas.
cm ⁻³ , the pulse width of the pulse valve is controlled to about 102 μs, and the nitrogen concentration of the n-type doped layer 12 a (highly doped layer) is set to 1 × 10 ¹⁸ atoms · cm ^−3. is there. 6 (a) and 6 (b) show the structure of the multiple δ-doped layer and the distribution state of carriers, taking the first laminated portion 12 as an example, but the same structure is also applied to the second laminated portion 13. And carrier distribution. Therefore, the same operation as in the first laminated section 12 described below occurs in the second laminated section 13 as well.

As shown in FIGS. 6A and 6B, since the thickness of the n-type doped layer 12a is as thin as about 10 nm, n
A quantum level due to the quantum effect is generated in the n-type doped layer 12a, and the wave function of electrons localized in the n-type doped layer 12a has a certain extent. As a result, as shown by the broken line in the figure, the carrier is
The distribution state is such that not only a but also the undoped layer 12b exists at a higher concentration than the original concentration. Then, in a state where the potential of the first laminated portion 12 is increased and carriers travel, electrons are constantly supplied to the n-type doped layer 12a and the undoped layer 12b, so that the electrons are always supplied to the n-type doped layer 12a. In addition, the distribution state is such that a relatively high concentration exists in the undoped layer 12b as well. In this state, electrons travel not only in the n-type doped layer 12a but also in the undoped layer 12b.
The resistance value of the laminated portion 12 is reduced. At this time, since impurity ion scattering in the undoped layer 12b is reduced, particularly high electron mobility is obtained in the undoped layer 12b.

On the other hand, when the entire first laminated portion is depleted, the undoped layer 12b and the n-type doped layer 1
Since no carrier is present in 2a, the withstand voltage is regulated by the undoped layer 12b having a low impurity concentration.
Thus, a high breakdown voltage value can be obtained in the entire laminated portion 12.

The above-described basic effect can be exhibited not only when there are a plurality of δ-doped layers but also when there is a single δ-doped layer in the carrier traveling region. it can. That is, when at least one δ-doped layer exists in the carrier traveling region serving as a depletion layer when a voltage at which the device operates is applied, the δ-doped layer changes from the δ-doped layer to the adjacent undoped layer (low-concentration doped layer) Since the carrier oozes, the carrier travels in the region of the undoped layer where the carrier oozes, and low resistance is obtained by the above-described action. On the other hand, when the device is off, the δ-doped layer is also depleted, so that high withstand voltage can be obtained. Therefore, if at least one δ-doped layer exists in the carrier traveling region when a voltage at which the device operates (set ON voltage) is applied, low resistance and high withstand voltage can be exhibited simultaneously. .

Each of the above-described functions is also obtained when holes are used instead of electrons as carriers.

As shown in FIG. 6B, the conduction band edge of the entire first laminated portion 12 is connected to the conduction band edge of the n-type doped layer 12a (δ-doped layer) indicated by a broken line in the figure. 12
It becomes a shape connecting the conduction band end of b. The impurity concentration of the n-type doped layer 12a, the although the conduction band edge is common to thicken the extent that below the Fermi level E _f, may not necessarily be not so dense. Also in the second laminated portion 13, the relationship between the Fermi level and the valence band edge of the δ-doped layer is such that the conduction band edge is replaced with the valence band edge in FIG. Becomes

By using the first and second laminated portions 12 and 13 (multiple δ-doped layers) having such a structure as the carrier traveling region, as described in each embodiment described later, Device can be obtained. Here, in the multiple δ-doped layers, the fact that the δ-doped layer and the undoped layer function as a carrier traveling region will be described in the following embodiments.

In this embodiment, the n-type doped layer is formed using nitrogen, but other elements (for example, phosphorus (P), arsenic (A)
s) etc. may be used.

In this embodiment, the p-type doped layer is formed using aluminum, but other elements (for example, boron (B),
A doping gas containing gallium (Ga) or the like may be used.

In this embodiment, the δ-doped layer is formed on the undoped layer. Instead of the undoped layer, a low-concentration n-type or p-type
A mold doping layer may be used.

In the present embodiment, a laminated portion in which an undoped layer (low-concentration doped layer) and a δ-doped layer (high-concentration doped layer) are laminated on a silicon carbide substrate (SiC substrate) by an epitaxial growth method is provided. Although the structure described above has been described, the structure of the laminated portion of the present invention may be provided on a substrate made of a material other than SiC. In particular, a substrate such as GaAs or GaN has an advantage that a device with a high withstand voltage can be formed by applying the present invention since the band gap is so wide as to be called a so-called semi-insulating material.

In this embodiment, a CVD method using induction heating has been described as a method for growing a thin film on a substrate. However, if a thin film is grown on a substrate using a gas, a plasma CVD method, Light irradiation CVD method, electron irradiation C
It goes without saying that the thin film growth method of the present invention is also effective when a thin film is grown on the substrate by any of the operations of the VD method.

Further, according to the present invention, a low-concentration doped layer (including an undoped layer) is formed by using not only the CVD method but also other methods such as a sputtering method, a vapor deposition method, and an MBE method. The present invention can also be applied to a structure in which a high-concentration doped layer having a thickness small enough to allow carriers to ooze into the low-concentration doped layer due to the quantum effect is stacked.

-Experimental Data- Next, the present inventors filed a PCT application (PCT / JP00 / 0).
1855), the relationship between the thickness of the multiple δ-doped layer and the effect will be described.

FIGS. 7A and 7B show the conduction band edge of Sample A having a laminated portion in which a δ-doped layer having a thickness of 10 nm and an undoped layer having a thickness of 50 nm are alternately laminated by five layers. FIG. 9 is a diagram illustrating a result of simulating a band structure, and a diagram illustrating a result of simulating a carrier concentration distribution. 8A and 8B show that the thickness is 2
Diagram showing the result of simulating the band structure at the conduction band edge in sample B having a laminated portion formed by alternately laminating five δ-doped layers having a thickness of 0 nm and undoped layers having a thickness of 50 nm, and simulating the carrier concentration distribution. It is a figure which shows the result. FIG. 7 (a), FIG. 8 (a)
As shown in the figure, in a cross section orthogonal to the δ-doped layer, electrons are confined in a V-type Coulomb potential (quantum well) sandwiched by a positively charged donor layer, in which the quantum state is changed. It is formed. The effective mass of the electrons is 1.1, and the relative permittivity of the 6H-SiC layer is 9.66. 6H-Si used for undoped layer
The background carrier concentration of the C layer is 5 × 10 ¹⁵ c
m ⁻³ and the carrier concentration of the n-type δ-doped layer is 1 × 10
¹⁸ cm ^-3 .

As shown in FIG. 7B, the thickness is 10 nm.
In the δ-doped layer (sample A), two-dimensional electrons are widely distributed to the undoped layer sandwiched between the two δ-doped layers, and the region having an electron concentration of 2 × 10 ¹⁶ cm ⁻³ or more is located at the interface from the interface. The range is 25 nm. That is, FIG.
(A) is consistent with the distribution state of the carriers schematically depicted, and it can be seen that the carriers are seeping from the δ-doped layer to the undoped layer.

On the other hand, as shown in FIG.
In the 0 nm thick δ-doped layer (sample B), the region where the carrier existence probability defined by the electron wave function is high and the δ-doped layer having the ionization scattering center strongly overlap, and the electron concentration is low. 2 × 10 ¹⁶ c
The region of m ^-3 or more is 11 nm from the interface. That is, it can be seen that the seepage of carriers from the δ-doped layer into the undoped layer is relatively small. However, even in this case, if the minimum value of the carrier concentration in the region between the δ-doped layers is higher than the original carrier concentration of the undoped layer,
The basic effect of the multiple δ-doped layer of the present invention can be exhibited. The strength of such a carrier seeping effect can be appropriately adjusted by the impurity concentration and the film thickness of each of the δ-doped layer and the undoped layer.

In this embodiment, the SiC substrate 10
Since the first laminated portion 12 and the second laminated portion 13 having the structure shown in the lower part of FIG. 4 are provided, the following remarkable effects can be exhibited for each element.

First, in the Schottky diode 20, in the Schottky diode 20, the carriers in the n-type doped layer 12a are distributed so as to seep into the undoped layer 12b by the quantum effect. In this state,
When a forward bias is applied to the Schottky diode 20, the potential of the first stacked unit 12 is increased, and electrons are constantly supplied to the n-type doped layer 12a and the undoped layer 12b. The current easily flows through Schottky electrode 21 through both n-type doped layer 12a and undoped layer 12b. That is, not only the n-type doped layer 12a of the first stacked unit 12 but also the undoped layer 12b functions as a carrier traveling region. At this time, since the impurity concentration in the undoped layer 12b is low, impurity scattering in the undoped layer 12b is reduced. Therefore, the resistance value can be kept small, and low power consumption and large current can be realized. On the other hand, when a reverse bias is applied to the Schottky diode 20, the undoped layer 12b of the first stacked unit 12
From this, the depletion layer spreads to the n-type doped layer 12a, and the entire first laminated portion 12 is easily depleted, so that a large breakdown voltage value can be obtained. Therefore, it is possible to realize a power diode having a low on-resistance, a high power, and a high withstand voltage.

Hereinafter, the operation of the horizontal Schottky diode of the present embodiment will be described in detail in comparison with a conventional vertical Schottky diode.

FIGS. 9 (a1) to 9 (c3) are energy band diagrams showing a change in the shape of the conduction band edge due to a change in bias for the Schottky diode of the present embodiment and the conventional Schottky diode. Here, FIG.
1), (b1) and (c1) show the conduction band edge of the undoped layer 12b of the Schottky diode of the present embodiment, and FIG.
(A2), (b2) and (c2) show the conduction band edge of the n-type doped layer 12a of the Schottky diode of the present embodiment, and FIGS. 9 (a3), (b3) and (c3) show conventional Schottky diodes. Respectively show the conduction band edges of the SiC substrate. However, in a conventional Schottky diode, a uniform doping layer doped with a uniform concentration of nitrogen is in contact with the Schottky electrode, and an ohmic electrode is in ohmic contact with any part of the uniform doping layer. It has a structure. 9 (a1) to 9 (a3) show the case where no voltage is applied between the Schottky electrode and the ohmic electrode (0 bias), and FIGS. 9 (b1) to 9 (b3) show the case where the Schottky electrode and the ohmic electrode are not applied. 9 (c1) to 9 (c3), when the voltage is applied such that the Schottky electrode becomes higher between the Schottky electrode and the ohmic electrode, the ohmic electrode becomes closer between the Schottky electrode and the ohmic electrode. The shapes of the conduction band edges when a voltage is applied so as to increase (reverse bias) are shown. The contact state between the ohmic electrode and the first laminated portion 12 does not essentially change due to a change in the bias, and is not shown. Further, in the present embodiment, a case is described in which an n-type semiconductor layer in which electrons travel as carriers is provided, and therefore, the shape of a valence band edge is not shown.

As shown in FIGS. 9 (a1) to 9 (a3), in this embodiment and the conventional Schottky diode, the undoped layer of the active region or n
A high Schottky barrier (about 1 to 2 eV) is formed between the mold dope or the like and the Schottky electrode and between the uniformly doped layer and the Schottky electrode.

Then, as shown in FIGS. 9B1 and 9B2, when a forward bias is applied to the Schottky diode of the present embodiment, the potential of the first laminated portion 12 is increased, that is, the first Layer 1 of the laminated portion 12 of
The energy level at the conduction band edge in 2b and n-type doped layer 12a increases. At this time, the undoped layer 12b
6 (a), a current easily flows through the Schottky electrode 21 through both the n-type doped layer 12a and the undoped layer 12b of the first laminated portion 12. Flows. That is, not only the n-type doped layer 12a of the first stacked unit 12 but also the undoped layer 12b functions as a carrier traveling region. At this time,
Although the carrier distribution as shown in FIG. 6A occurs in the undoped layer 12b, the impurity concentration is low, so that the impurity scattering is reduced in the undoped layer 12b.
Therefore, the resistance value of the entire first stacked unit 12 can be kept small, and low power consumption and large current can be realized.

On the other hand, as shown in FIG. 9B3, when a forward bias is applied to the conventional Schottky diode,
Current flows from the uniformly doped layer to the Schottky electrode.

As shown in FIGS. 9C1 and 9C2, when a reverse bias is applied to the Schottky diode of the present embodiment, the undoped layer 12
The overall energy level at the conduction band edge in the b and n-type doped layers 12a is reduced. As described above, the breakdown voltage is defined by the electric field applied to the depletion layer at the time of reverse bias. In that case, the slope of the conduction band edge becomes gentler as the impurity concentration is lower, so that the width of the depletion layer is naturally wider as the impurity concentration is lower. Therefore, as shown in FIG. 9C1, a large breakdown voltage is obtained in the undoped layer 12b. On the other hand, when the heavily doped layer is simply in contact with the Schottky electrode, the conduction band edge of the heavily doped layer at the time of reverse bias is as shown by the broken line in FIG. The width of the depletion layer should be extremely narrow. However, in the present embodiment, since the thickness of the n-type doped layer 12a is extremely thin, that is, 10 nm, the depletion layer from the undoped layer 12b spreads as shown by the solid line in FIG. Since the depletion layer has expanded to this point, no electron transfer can occur.

When the entire first laminated portion 12 is depleted, carrier distribution does not occur in the undoped layer 12b, so that the resistance of the entire first laminated portion 12 is increased. When the depletion is incomplete, the Schottky electrode 2
Even if current flows from 1 to the extraction doping layer 22, since the thickness of the n-type doped layer 12a is extremely thin, 10 nm, the n-type doped layer 12a receives a large resistance. Not flowing. That is, there is substantially no ohmic contact between the n-type doped layer 12a and the Schottky electrode 21, and the Schottky contact is maintained. Moreover, the undoped layer 12
By adjusting the thickness and impurity concentration of the b and n-type doped layers 12a, the breakdown voltage can be defined by the depletion layer width between the undoped layer 12b having a large thickness and the Schottky electrode 21. Therefore, a high breakdown voltage can be obtained.

On the other hand, as shown in FIG. 9C3, in the conventional Schottky diode, the width of the depletion layer of the uniformly doped layer changes according to the impurity concentration of the uniformly doped layer. It is possible to control the resistance value and the withstand voltage value by adjusting. However, when the impurity concentration of the uniformly doped layer is increased in order to lower the resistance value, the width of the depletion layer is reduced and the withstand voltage value is reduced.
Since there is a trade-off that the resistance value increases when the impurity concentration of the uniformly doped layer is reduced, the conventional Schottky diode simultaneously achieves the low resistance (low power consumption) and the high withstand voltage desired for a power device. Is difficult to do. On the other hand, if a conventional Schottky diode has a horizontal structure, it is difficult to obtain a large withstand voltage while securing a large current, and only a vertical structure has been realized for power devices.

On the other hand, in the Schottky device of the present embodiment, the carrier is n
Distributed from the doped layer 12a (highly doped layer) to the undoped layer 12b (lowly doped layer), and the scattering of impurities in the undoped layer 12b is reduced. 2
1, carriers (electrons) can be easily moved. On the other hand, in the reverse bias state, since electrons do not exist in the undoped layer 12b due to depletion, almost no electrons flow from the Schottky electrode 21 to the extraction doped layer 22. That is, the MESFE of the present embodiment
By paying attention to the fact that the carrier distribution state is different between the forward bias state and the reverse bias state by T, it is possible to eliminate the trade-off between the low resistance and the high breakdown voltage that existed in the conventional Schottky diode. You can.

The power diode has a horizontal structure, so that the power diode is
It has become easy to integrate them on a common SiC substrate together with ET and the like. That is, conventionally, it is difficult to secure a high withstand voltage while securing a large current with a Schottky diode having a horizontal structure, so that a Schottky diode for high power has to be a vertical structure. . In contrast, the Schottky diode of the present embodiment can be used as a power device while eliminating the trade-off between low resistance and high withstand voltage, and securing a large amount of current. Therefore, the Schottky diode of the present embodiment can be replaced by a common Si
When the integrated circuit device is configured by integrating the components on the C substrate, the integrated circuit device can be used for communication system equipment. In this case, in communication system equipment that handles high-frequency signals, impedance matching is easier than in the case of a discrete type vertical Schottky diode, and as a result, the operating frequency can be improved. can do.

In the case of a vertical Schottky diode, since it has a capacitor structure, there is a problem that the operating frequency is reduced due to parasitic capacitance. On the other hand, the horizontal Schottky diode as in the present embodiment does not have a capacitor structure, and thus has an advantage that the operating frequency can be further improved.

Incidentally, in a communication system device such as a conventional base station, a diode is provided on a silicon substrate. In such a case, a pin diode or a pn diode is generally formed instead of a Schottky diode due to the characteristics of silicon. However, when an SiC substrate is used as in this embodiment, a Schottky diode can be easily formed. Since the Schottky diode has a characteristic that the carrier recovery time is shorter than that of the pin diode or the pn diode, a structure suitable for higher-speed operation can be obtained.

-MESFET- Next, in the MESFET 30, similarly to the case of the Schottky diode 20, the carriers in the n-type doped layer 12a are distributed so as to seep into the undoped layer 12b by the quantum effect. In this state, MESFET3
When a forward bias is applied to 0, the potential of the first stacked unit 12 is increased, and electrons are constantly supplied to the n-type doped layer 12a and the undoped layer 12b. Therefore,
A current easily flows between the source electrode and the drain electrode through both the n-type doped layer 12a and the undoped layer 12b of the first stacked unit 12. At this time, the undoped layer 12b
, The impurity concentration in the undoped layer 12b is reduced. Therefore, the resistance value can be kept small, and low power consumption and large current can be realized.

On the other hand, when the MESFET is off, the first
Layer 12 from the undoped layer 12b to the n-type doped layer 1
Since the depletion layer spreads to 2a and the entire first laminated portion 12 is easily depleted, a large withstand voltage value can be obtained. Therefore, a high power and high withstand voltage power amplifier device with low on-resistance can be obtained.

Here, regarding the evaluation results of the performance of the MESFET of the present embodiment and the comparison of the performance of the MESFET of the present embodiment with the performance of the conventional MESFET, the inventors of the present invention made a PCT application (PCT / JP00 / 01855). ) Will be described based on the matters disclosed in the above.

First, the gate-source withstand voltage was compared between the two. Undoped layer and n in this embodiment
Region with an active region (multiple δ-doped layer) formed by alternately laminating five-type doped layers by five layers each as a channel layer
In T, the withstand voltage becomes 120 V, and the conventional MESFE
It had a withstand voltage value four times that of T.

Next, for the MESFET of the present embodiment, the gate voltage dependence (IV characteristics) of the relationship between the drain current and the drain voltage was examined. A constant voltage is applied between the source electrode 34 and the drain electrode 35, and the gate electrode 3
By applying a voltage to 2, the current between the source and the drain was modulated according to the voltage applied to the gate electrode 32, and a switching operation was obtained. At this time, even if the drain voltage was 140 V or more, a stable drain current was obtained without breakdown.

FIG. 10 is a graph showing the results of measuring the gate voltage dependency (IV characteristics) of the relationship between the drain current and the drain voltage for the MESFET of this embodiment. In the figure, the horizontal axis represents the drain-to-drain voltage Vds (V).
The vertical axis represents the drain current Ids (A), and the gate voltage Vg is used as a parameter.

Further, the present embodiment and the conventional MESFET
, The transconductance near the threshold voltage was measured. As a result, the transconductance of the MESFET of the present embodiment using the first stacked portion 12 as a channel layer as described above is approximately twice as high as that of a conventional MESFET using a uniformly doped layer as a channel layer. I knew it was. This is the MESFE of the present embodiment.
This is because the electron mobility at T is increased as described above.

From the above results, the MESFE of the present embodiment
At T, the effects of low power consumption, high withstand voltage, and high gain can be exhibited.

When the power amplifier of the present embodiment and the conventional power amplifier are compared in correspondence with the above-described difference in function between the MESFET of the present embodiment and the conventional MESFET, the following differences are obtained.

As shown in FIG. 20, in a conventional base station, four main amplifiers having MESFETs are arranged in a transmission amplifier that requires large power amplification. However, as the number of MESFETs increases, each M
It is difficult to match the impedance between ESFETs, and the difficulty increases as the frequency of the high-frequency signal increases.

On the other hand, in the present embodiment, the transmission amplifier circuit includes one main amplifier 13 having a MESFET.
By simply arranging 8, it is possible to obtain desired power. And, by reducing the number of MESFETs,
Even in a circuit that handles a high-frequency signal in a high frequency region, the configuration of the impedance matching circuit can be simplified as compared with a circuit in a conventional base station. Moreover, as described above, the Schottky diode is also integrated on the same SiC substrate together with the MESFET, and the number of Schottky diodes is reduced, so that the configuration of the impedance matching circuit is further facilitated. Therefore, it is possible to incorporate the semiconductor integrated circuit device equipped with the MESFET of the present embodiment into a communication system that handles a high frequency of, for example, GHz order.

-MOSFET- In the nMOSFET 40, a driving voltage is applied to the gate electrode 42, and in the inversion state in which the carrier travels, the end of the conduction band end bent upward by the potential eV corresponding to the applied voltage V. Electrons gather in the portion, and the electrons travel through the portion of the second stacked portion 13 that will be the channel layer according to the potential difference between the source region 43a and the drain region 43b. At this time, the concentration of carriers (electrons in this case) is distributed immediately below the gate insulating film 41 so as to be higher and lower as the concentration goes down. 13b occupies almost all of the channel layer. However, since impurities are hardly doped in the undoped layer 13b, scattering of impurity ions on carriers traveling in the undoped layer 13b is reduced. That is, high channel mobility can be obtained by reducing impurity ion scattering that hinders the carrier from traveling in the second stacked unit 13.

Since the gate insulating film of the MOSFET is almost always an oxide film formed by heat treatment of the substrate, the negative electrode trapped in the gate insulating film 41 formed by thermally oxidizing the undoped layer 13b. Charge is small. Therefore, since the electrons flowing through the uppermost undoped layer 13b in the second stacked portion 13 are hardly affected by the traveling hindrance due to the interaction with the charges in the gate insulating film 41, the channel mobility is improved. I do. Further, when the driving voltage is not applied to the gate electrode 42, even when a high voltage is applied between the source region 43a and the drain region 43b, the depletion layer is changed from the undoped layer 13b to n similarly to the case of the MESFET 30. Mold dope layer 1
Since it easily spreads to 3a, a high withstand voltage can be exhibited.

That is, excellent characteristics such as high withstand voltage, low on-resistance, large current capacity and high mutual conductance can be exhibited. For example, if the drain voltage is 40
Even at 0 V or more, a stable drain current can be obtained without breakdown, and the breakdown voltage of the off-state MOSFET is 600 V or more.

When a pMOSFET is provided,
As in the case of the nMOSFET, holes traveling in the channel region are hardly affected by scattering by impurity ions in the channel region or obstruction by positive charges trapped by impurities in the gate insulating film. It can exhibit on-resistance, large current capacity, and high mutual conductance characteristics.

-Capacitor- The capacitor 50 (capacitor) has a relative dielectric constant of 10 when a BST film is formed with an area of, for example, 5 mm square.
Since the thickness is about 00 and the thickness can be reduced to about 10 nm, a capacitance of about 22 μF can be obtained. That is, a large-capacity capacitor can be formed with a small area.

If a spiral conductor film having a line width of 9 μm is provided at an interval of 4 μm in an area of about 5 mm square, the inductor 60 has about 160 turns and an inductance of 780 μH. That is, an inductor that satisfies desired specifications with a small area can be provided.

Here, the Schottky diode, M
The stacked part in the ESFET and the MOSFET may have only one high-concentration doped layer and one low-concentration doped layer. Either the heavily doped layer or the lightly doped layer may be formed first. One low-concentration doped layer (undoped layer) may be disposed above and below one high-concentration doped layer. That is, the number of the heavily doped layers and the number of the lightly doped layers may be different.

-Manufacturing Process- Next, the manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS. Here, FIGS. 11A to 11C are cross-sectional views showing steps from the formation of the first and second laminated portions to the formation of the element isolation region in the manufacturing process of the semiconductor device of the present embodiment. . FIGS. 12A to 12C are cross-sectional views showing steps from the formation of source / drain regions to the formation of electrodes or conductor films of each element in the manufacturing process of the semiconductor device of the present embodiment. FIGS. 13A and 13B are cross-sectional views showing steps from the formation of the upper electrode of the capacitor to the formation of the contact hole in the conductor of each element in the manufacturing process of the semiconductor device of the present embodiment. The crystal growth apparatus and the crystal growth method according to the present embodiment are described in Patent Application 2000
-58964 or Patent Application 2000-06210 based on the structure or method disclosed in the specification and drawings.

First, in the step shown in FIG. 11A, a p-type SiC substrate 10 is prepared. In the present embodiment, S
The main surface of the iC substrate 10 is a {11-200} surface (A surface)
A 4H-SiC substrate having an orientation corresponding to the above is used. However, a SiC substrate whose main surface has an orientation shifted from the (00001) plane (C plane) by several degrees may be used.

Then, the SiC substrate 1 was placed in a steam atmosphere bubbled with oxygen at a flow rate of 5 (l / min).
0 was thermally oxidized at 1100 ° C. for about 3 hours to form a thermal oxide film having a thickness of about 40 nm on the surface.
The thermal oxide film is removed. Then, the SiC substrate 10 is set in the chamber of the CVD apparatus, and
^The pressure is reduced until the degree of vacuum reaches about ^-6 Pa (≒ 10 ^-8 Torr). Next, a hydrogen gas at a flow rate of 2 (l / min) as a diluent gas (carrier gas) and a flow rate of 1 (l / m
in) with argon gas, the pressure in the chamber was 0.0933 MPa, and the substrate temperature was about 1600 ° C.
To control. While maintaining the flow rates of the hydrogen gas and the argon gas at the above-mentioned constant values, the flow rates of the raw material gas were 2 (ml).
/ Min) propane gas and a flow rate of 3 (ml / mi)
n) The silane gas is introduced into the chamber. The source gas is diluted with a hydrogen gas at a flow rate of 50 (ml / min). Then, while supplying the source gas and the diluent gas in the chamber, nitrogen (doping gas), which is an n-type impurity, is supplied in a pulsed manner, so that the SiC substrate 10 is supplied.
A first lightly doped layer 15 having a thickness of about 1200 nm is formed on the main surface of the first step. Here, as the doping gas, for example, nitrogen is stored in a high-pressure cylinder, and a pulse valve is provided between the high-pressure cylinder and the doping gas supply pipe. By repeatedly opening and closing the pulse valve while supplying the source gas and the diluent gas, the doping gas can be supplied in a pulse shape directly above the SiC substrate 10 in the chamber.

Next, on the lightly doped layer 15, an n-type doped layer 12a (highly doped layer) having a thickness of about 10 nm is formed. Here, when the lightly doped layer 15 is formed, the period (pulse width) during which the pulse valve is open is shortened, and when the n-type doped layer 12a is formed, the period during which the pulse valve is open ( By increasing the pulse width, the difference in the impurity concentration can be easily realized. Note that an undoped layer may be formed instead of the first lightly doped layer 15.

When the epitaxial growth of the n-type doped layer 12a is completed, the supply of the doping gas is stopped, that is, the propane gas and the silane gas are supplied onto the SiC substrate 10 with the pulse valve completely closed. By doing so, an undoped layer 12b (lightly doped layer) having a thickness of about 50 nm and made of undoped SiC single crystal is epitaxially grown on the main surface of SiC substrate 10.

In this way, the n-type doped layer 12a is formed by simultaneously opening and closing the pulse valve and introducing the doping gas while supplying the source gas, and the doping gas is not supplied while the pulse valve is closed. By repeating the formation of the undoped layer 12b only by supplying the source gas 5 times each, the n-type doped layer 12a
And an undoped layer 12b are alternately laminated to form a first laminated portion 12 composed of five layers. At this time, the undoped layer 12b is formed as the uppermost layer, and its thickness is set to be about 15 nm thicker than the other undoped layers 12b. The average nitrogen concentration in the first stacked unit 12 is about 1 × 10 ¹⁷ atoms
Cm ^-3 , and the total thickness of the first laminated portion 12 is about 300 nm.

Next, the source gas and the diluent gas are left as they are.
And doping gas is aluminum which is a p-type impurity.
By switching to a gas containing gas (doping gas)
And a thickness of about 1200 nm on the first laminated portion 12.
A lightly doped layer 16 is formed. Where the doping gas
For example, trimethyl aluminum (Al (CH
_Three )_Three Of hydrogen gas containing about 10% is used.

In the same manner as the procedure for forming the first laminated portion 12, the doping gas (hydrogen gas containing trimethylaluminum) is introduced by simultaneously opening and closing the pulse valve while supplying the source gas. To form a p-type doped layer 13a (highly doped layer) having a thickness of about 5 nm. The formation of the p-type doped layer 13a and the formation of the undoped layer 13b only by supplying the source gas without supplying the doping gas with the pulse valve closed are each performed in two steps.
By repeating 0 times each, a second p-type doped layer 13a and an undoped layer 13b are alternately stacked for 20 periods.
Is formed. At this time, an undoped layer 13b is formed on the uppermost layer, and the thickness of the undoped layer 13b is
It is made about 15 nm thicker than 3b. 2nd laminated part 1
3 has an average aluminum concentration of about 1 × 10 ¹⁷ at
oms · cm ⁻³ , and the total thickness of the second laminated portion 13 after the completion of the thermal oxidation is about 1100 nm.

Next, in the step shown in FIG. 11B, the Schottky diode 20 and the MESFET 30 of the second laminated portion 13 and the second lightly doped layer 16 are to be formed by selective etching. Remove the area,
The first stacked unit 12 is exposed in a region where the Schottky diode 20 and the MESFET 30 are to be formed.

Next, in a step shown in FIG. 11C, a trench for forming an element isolation region is formed in the substrate.
An element isolation region 11 is formed by burying a silicon oxide film in the trench.

Next, in the step shown in FIG.
Pure substance (for example, nitrogen ion N⁺ Shot by injection)
The electrode lead layer 22 of the key diode 20 is formed.
At this time, a region for implanting n-type impurity ions is formed on the substrate.
To cover the other regions and implant the n-type impurity ions.
Forming implantation mask consisting of open silicon oxide film etc.
After that, the substrate temperature is heated to between 500 and 800 ° C.
From above the implantation mask, nitrogen ions (N⁺ ) And other ions
Perform injection. Furthermore, annealing for impurity activation
The temperature at 1500 ° C for 10 minutes,
The impurity concentration is about 1 × 10¹⁸atoms · cm^-3Electrode extraction
A layer 22 is formed. At this time, nitrogen ions (N⁺ )
, For example, six ions having different implantation energies
It is implanted into the substrate in the implantation step. For example, the first
Ion implantation conditions are accelerating voltage 180 keV, dose amount
1.5 × 10¹⁴atoms · cm^-2Then, the second ion injection
The conditions of the input were an acceleration voltage of 130 keV and a dose of 1 × 10.¹⁴
atoms · cm^-2The conditions of the third ion implantation accelerated
Voltage 110 keV, dose 5 × 10¹³atoms · cm ^-2
Then, the condition of the fourth ion implantation is that the acceleration voltage is 100 ke.
V, dose 8 × 10 ¹³atoms · cm^-2And the fifth
The conditions of the ion implantation are an acceleration voltage of 60 keV and a dose of 6 ×.
10¹³atoms · cm^-2Then, the conditions for the sixth ion implantation
Has an acceleration voltage of 30 keV and a dose of 5 × 10¹³atoms · c
m^-2It is. The direction of ion implantation is in each case S
This is a direction inclined by 7 ° with respect to the normal line of the iC substrate 10.
The penetration depth is about 0.3 μm. At this time, MESF
Portion located directly below the source / drain electrodes of ET30
In addition, a thin high-concentration doped layer
Good.

Similarly, an n-type impurity (eg, nitrogen ion N
+), The source region 4 of the nMOSFET 40 is
3a and the drain region 43b are formed. At this time, after forming an implantation mask made of a silicon oxide film or the like on the substrate other than the region into which the n-type impurity ions are implanted and opening the region into which the n-type impurity ions are implanted, the substrate temperature is set to 500 to By heating at 800 ° C., ion implantation of nitrogen ions (N ⁺ ) or the like is performed from above the implantation mask. Further, annealing for activating impurities is performed at a temperature of 1 °.
By performing the treatment at 500 ° C. for 10 minutes, the implantation depth is about 0.8 μm and the n-type impurity concentration is about 1 × 10 ¹⁸ atoms · c.
An m ⁻³ source region 43a and a drain region 43b are formed. At this time, an n-type impurity (for example, nitrogen ion N +) may be implanted shallowly into a portion of the MESFET 30 located immediately below the source / drain electrodes.

Next, in the step shown in FIG. 12B, after removing the implantation mask from the substrate, an SiN film having a thickness of about 0.4 μm is formed by the plasma CVD method.
The film is patterned to form a base insulating film 51 and a dielectric film 61 on a region of the second stacked unit 13 where the capacitor 50 and the inductor 60 are to be formed.

Next, in the step shown in FIG.
In the FET formation region, the second
By thermally oxidizing the surface portion (about 15 nm thick) of the uppermost undoped layer 13b of the stacked portion 13, a gate insulating film 41 made of a thermal oxide film having a thickness of about 30 nm is formed. Next, the source region 43 of the gate insulating film 41 is formed.
An opening is provided by removing a portion located above the a and drain region 43b, and a source electrode 44 and a drain electrode 45 made of a Ni alloy film formed by a vacuum deposition method are formed in the opening. At this time, simultaneously, the electrode lead layer 22 of the Schottky diode 20 and the first laminated portion 12
Ohmic electrode 23 made of a Ni alloy film,
A source electrode 34 and a drain electrode 35 are formed. Further, in order to make ohmic contact between the source electrodes 34, 44, the drain electrodes 35, 45, and the ohmic electrode 23 and each of the laminated portions 12, 13 or the electrode lead layer 22, one step is taken.
Anneal at 000 ° C. for 3 minutes. Subsequently, a nickel (Ni) alloy film is deposited on the gate insulating film 41 to form a gate electrode 4 made of a nickel alloy film having a gate length of about 1 μm.
Form 2 In addition, nickel (Ni) is deposited on a region of the first laminated portion 12 where the Schottky diode 20 and the MESFET 30 are to be formed, so that the Schottky electrode 21 and the Schottky gate electrode 3 made of nickel are formed.
2 and the underlying insulating film 5 of the capacitor 50
The lower electrode 52 made of platinum is formed by performing platinum (Pt) vapor deposition on the first electrode 52.

Next, in a region where the inductor 60 is to be formed, a resist film having a spiral opening is formed, and then a Cu film having a thickness of about 4 μm is deposited thereon, and lift-off is performed. The spiral conductive film 62 is left on the film 61. Note that the conductor film may be formed of an aluminum alloy film instead of the Cu film. In that case, after depositing the aluminum alloy film, the aluminum alloy film is patterned by RIE dry etching using Cl ₂ gas and BCl ₃ gas to form a spiral conductive film 62.

Next, in the step shown in FIG. 13A, the BS is formed on the lower electrode of the capacitor 50 by sputtering.
After forming the T film, a platinum (Pt) film is formed on the BST film by an evaporation method. Then, the platinum film and the BST film are patterned into a predetermined shape to form the upper electrode 54 and the capacitance insulating film 53.

Next, in a step shown in FIG. 13B, an interlayer insulating film 70 made of a silicon oxide film is deposited on the substrate, and the Schottky electrode 21 of the Schottky diode 20 and the ohmic electrode 23 and MESFE
T30 Schottky gate electrode 32, source electrode 34
And the drain electrode 35, the gate electrode 42, the source electrode 44 and the drain electrode 45 of the nMOSFET 40, the upper electrode 54 and the lower electrode 52 of the capacitor 50, the center of the spiral of the conductor film 62 of the inductor 60 and the outer peripheral end. Are formed respectively.

Then, after forming an aluminum alloy film in each contact hole 74 and on the interlayer insulating film 70,
By patterning this, the structure of the semiconductor device shown in FIG. 3 is obtained.

As described above, according to the manufacturing method of this embodiment, the Schottky diode, the MESFET, and the MOSF
ET, resistance element, inductor, etc.
It can be provided on an iC substrate. In particular, as described above, the active elements such as the MESFET and the Schottky diode have a horizontal structure, and the MESFE is formed in a common SiC substrate.
Since the T and Schottky diodes can be provided, integration is facilitated. Further, since a passive element such as an inductor can be mounted on a common SiC substrate, further miniaturization can be achieved.

In the present embodiment, the SiC substrate is used. However, not only the semiconductor device provided on the SiC substrate but also, for example,
e, SiGeC, and other general semiconductor devices provided on a compound semiconductor substrate comprising a compound of a plurality of elements (active layers include GaAs, AlGaAs, GaN, AlGa
This embodiment can be applied to a layer made of N, InGaN, SiGe, SiGeC, or the like. Also in this case, by providing a laminated portion in which a δ-doped layer and a lightly doped layer (including an undoped layer) are laminated below the gate insulating film, impurity ion scattering is reduced, and the entire channel region in an off state is provided. Channel depletion and trapping of charges into impurities in the δ-doped layer (charge compensation) can be used to improve channel mobility and breakdown voltage.

Next, FIG. 14 is a diagram schematically showing an example of the mobile phone terminal (mobile station) 102 in the communication system shown in FIG.
Here, the PDC method is adopted. The high-frequency radio section shown in FIG. 14 includes the reception amplification section 122 and the transmission amplification section 123 shown in FIG. The control unit of the portable terminal 102 as the mobile station shown in FIG. 1 includes a CPU shown in FIG. 14, an encryption TDMA-CCT, an SP-CODEC, and a ROM / R.
AM, TERM-ADP, DPSK-MOD, and H
iSpeedSYNTH, IF-IC, CPSK-
DEMOD (EQL).

A linear PA in the high-frequency radio section shown in FIG.
The (power amplifier) is, for example, the MESFE shown in FIG.
It can be constituted by a circuit in which T is arranged. At this time, the MOSFET in each circuit for the control unit
It can be constituted by an OSFET (n-channel MOSFET or p-channel MOSFET).

FIG. 15 is an electric circuit diagram showing a circuit configuration example of the mixer 134 shown in FIG. 2 or the mixer shown in FIG. Here, an example of a mixer with a local amplifier is shown. That is, the local signal Alo is received at the gate, and a signal Sout1 obtained by amplifying the local signal Alo is output from the drain.
Mix 2 is received at the gate, and the signal Sou amplified by mixing
MESF for mixer signal amplification outputting t2 from drain
ET2 are arranged. MESFE in this circuit
For example, as shown in FIG. 4, the T, the diode, and the capacitor can be formed on one SiC substrate to form one MMIC. Although not shown in FIG. 4, since the resistance element can be regarded as a part of the conductor film of the inductor, it is extremely easy to form the resistance element on the SiC substrate.

FIG. 16 is an electric circuit diagram showing an example of the high output switch circuit including the SPDT switch shown in FIG. 14 or the high output switch circuit arranged in the antenna section shown in FIG. In this example, it is configured to receive the input signals Sin1 and Sin2 and output a signal Sout obtained by amplifying one of the input signals Sin1 and Sin2. Here, the output signals MESFET1-MESFET4, the capacitor C1
-C6, diode D1-D2, and resistance element R1-R
6 can be formed on one SiC substrate to form an MMIC.

(Modification) FIG. 17 is a diagram showing another configuration example (first modification) of the main amplifier shown in FIG. 3 in the above embodiment. In this modified example, a pre-stage MESFET and a post-stage MES which are two-stage amplification transistors
FET. On the input side of the previous-stage MESFET, an input-side impedance adjustment circuit having a capacitor C1, a resistance element R1, and an inductor I1 is provided. An intermediate impedance adjustment circuit having capacitors C2 and C3, a resistance element R2, and an inductor I2 is provided between the first-stage MESFET and the second-stage MESFET. A capacitor C4 is provided on the output side of the subsequent MESFET.
And an output-side impedance adjustment circuit including an inductor I3.

Each element in the first modification is shown in FIG.
The MESFET 30, the capacitor 50, and the inductor 60 as shown in FIG. Therefore, an MMIC in which the circuit shown in FIG. 17 is provided on one SiC substrate can be obtained.

FIG. 18 is a diagram showing another configuration example (second modification) of the main amplifier shown in FIG. 3 in the above embodiment. This modification has a structure in which four MESFETs A to D constituting a differential amplifier are arranged in parallel. And, on the input side of each MESFET A-D,
An input-side pre-matching having a capacitor, a resistance element (not shown) and the like and a bonding wire are provided, and each ME is provided.
On the output side of the SFETs A to D, an output side pre-matching having a capacitor, a resistance element (not shown) and the like and a bonding wire are provided.

Each element in the second modification is shown in FIG.
The MESFET 30, the capacitor 50, and the inductor 60 as shown in FIG. Therefore, an MMIC in which the circuit shown in FIG. 18 is provided on one SiC substrate can be obtained.

FIG. 19 is a block circuit diagram schematically showing a configuration of base station 101a according to a third modification in which two main amplifiers 138 are arranged in parallel. Also in this case, the two main amplifiers can be constituted by the circuit shown in FIG.

Comparing the amplifier circuits shown in FIGS. 3, 16 and 17, it is preferable to provide an amplifier circuit as shown in FIG. 16 or 17 in order to obtain the largest amplification factor. On the other hand, as the number of MESFETs increases, the configuration of the impedance matching circuit becomes more complicated.
When handling signals in a high frequency range on the order of GHz, M
As the number of ESFETs increases, the effort (such as trimming) for impedance matching becomes more complicated. Therefore, it is preferable to select the configuration of the base station according to the application and the scale.

The active element of the present invention, MESFE
T, Schottky diode and the like are arranged on the transmission side of the communication system equipment, so that the ME of the present invention
A structure suitable for high power, such as an SFET and a Schottky diode, can be used.

(Other Embodiments) In the above embodiment, an example in which the communication system device of the present invention is applied to a base station and a terminal (mobile station) of a mobile phone has been described. However, the present invention is not limited to this. As the communication system, for example, a car telephone system, PH
S, PDA, etc., and the devices arranged in these systems include MESFET, diode, MOS shown in FIG.
By providing an FET, a capacitor, an inductor, and the like, the same effects as in the above embodiment can be exerted.

In each of the above embodiments, the SiC
Although a substrate was used, a semi-insulating substrate other than a SiC substrate, for example, a GaAs or GaN substrate, was used to form a laminated portion composed of a δ-doped layer and an undoped layer shown in FIG. GaN, AlGaN,
Even if a layer made of InGaN, SiGe, SiGeC or the like is provided, large current characteristics and high withstand voltage can be exhibited.

[0131]

According to the communication system equipment of the present invention,
An active element having a stacked portion formed by alternately stacking a low-concentration first semiconductor layer and a second semiconductor layer containing a high-concentration impurity capable of distributing carriers by quantum effect is arranged. Therefore, it is possible to provide equipment for a communication system suitable for being arranged under severe conditions such as operating temperature and space restrictions by utilizing the high carrier running characteristics and pressure resistance.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of a communication system according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing in more detail an internal configuration of a base station in the communication system according to the embodiment of the present invention.

FIG. 3 is an electric circuit diagram showing a structural example of a main amplifier arranged in the transmission / reception amplifier shown in FIG. 1;

FIG. 4 is a cross-sectional view of a semiconductor device in which a Schottky diode, a MESFET, a MOSFET, a capacitor, and an inductor are integrated on a SiC substrate according to an embodiment of the present invention.

FIG. 5 is a diagram showing a dopant concentration distribution in a depth direction of an active region formed in an embodiment of the present invention.

FIGS. 6A and 6B are diagrams schematically showing a relationship between a nitrogen concentration profile and a carrier distribution in a depth direction of a first stacked portion in the embodiment of the present invention, and FIGS.
FIG. 4 is a partial band diagram showing a shape of a conduction band edge along a depth direction of a laminated portion of FIG.

FIGS. 7A and 7B are diagrams showing the results of simulating the band structure at the conduction band edge in sample A having a δ-doped layer having a thickness of 10 nm, and the diagrams showing the results of simulating the carrier concentration distribution. It is.

FIGS. 8A and 8B are diagrams showing a simulation result of a band structure at a conduction band edge in a sample B having a δ-doped layer having a thickness of 20 nm, and diagrams showing a simulation result of a carrier concentration distribution. It is.

FIGS. 9A to 9C are energy band diagrams showing a change in the shape of a conduction band edge due to a change in bias in the Schottky diode according to the embodiment of the present invention and a conventional Schottky diode.

FIG. 10 shows a MESFET according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a result of measuring a gate voltage dependency (IV characteristic) of a relationship between a drain current and a drain voltage.

FIGS. 11A to 11C are cross-sectional views illustrating steps from the formation of the first and second stacked units to the formation of the element isolation region in the manufacturing process of the semiconductor device according to the embodiment;

FIGS. 12A to 12C are cross-sectional views showing steps from the formation of source / drain regions to the formation of electrodes or conductor films of each element in the manufacturing steps of the semiconductor device of the embodiment.

FIGS. 13A and 13B are cross-sectional views showing steps from the formation of the upper electrode of the capacitor to the formation of the contact hole in the conductor of each element in the manufacturing steps of the semiconductor device of the embodiment. .

14 is a diagram schematically showing an example of a mobile phone terminal (mobile station) in the communication system shown in FIG.

FIG. 15 is an electric circuit diagram showing a circuit configuration example of the mixer shown in FIG. 2 or FIG. 14;

16 is an electric circuit diagram showing an example of a high-output switch circuit including the SPDT switch shown in FIG. 14 or a high-output switch circuit arranged in the antenna section shown in FIG. 2;

FIG. 17 is a diagram showing another configuration example (first modification) of the main amplifier shown in FIG. 3 in the embodiment.

FIG. 18 is a diagram illustrating another configuration example (a second modification) of the main amplifier illustrated in FIG. 3 in the embodiment.

FIG. 19 is a block circuit diagram schematically showing a configuration of a base station in a third modification in which two main amplifiers are arranged in parallel.

FIG. 20 is a block circuit diagram showing an internal configuration of a conventional base station (base station of a communication system).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 SiC substrate 11 Element isolation region 12 1st laminated part 12a n-type doped layer 12b undoped layer 13 2nd laminated part 13a p-type doped layer 13b undoped layer 20 Schottky diode 21 Schottky electrode 22 Electrode extraction layer 23 Ohmic electrode Reference Signs List 30 pMOSFET 32 Gate electrode 33a Source region 33b Drain region 34 Source electrode 35 Drain electrode 40 nMOSFET 41 Gate insulating film 42 Gate electrode 43a Source region 43b Drain region 44 Source electrode 45 Drain electrode 50 Capacitor 51 Base insulating film 52 Lower electrode 53 Capacitance insulating Film 54 Upper electrode 60 Inductor 61 Dielectric film 62 Conductive film 70 Interlayer insulating film 71 Contact 74 Contact hole 75 Pad 100 Exchange network (network) 10 Reference Signs List 1 base station 102 mobile terminal 111 antenna 112 reception amplification unit 113 transmission amplification unit 114 wireless transmission / reception unit 115 control unit 116 wired connection unit 117 baseband signal processing unit 118 interface unit 119 exchange control unit 120 power supply unit 121 antenna 122 reception amplification unit 123 Transmission amplifying unit 125 Control unit 131 Filter 132 Low noise amplifier (LNA) 134 Mixer 135 Driver amplifier 136 Filter 137 Middle amplifier 138 Main amplifier

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 27/06 29/872 (72) Inventor Masao Uchida 1006 Odakadoma, Kadoma City, Osaka Matsushita Electric Inside Sangyo Co., Ltd. (72) Inventor Makoto Kitabatake 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Osamu Kusumoto 1006 Okadoma Kazuma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. 4M104 AA03 BB05 CC03 DD26 GG03 GG09 GG12 GG13 5F038 AV01 AV04 AV06 AZ03 AZ04 DF02 EZ02 EZ20 5F048 AA05 AC10 BA03 BA05 BA14 BB05 5F102 FA01 FA02 GA05 GA14 GA15 GA16 GB01 GC01 GD01 GJ02 GL01 GM01 GM01 GM01 GM01

Claims (20)

[Claims] 1. An apparatus arranged in a communication system and having an active element formed using a compound semiconductor, wherein the active element includes: a compound semiconductor layer provided on a substrate; At least one first semiconductor layer functioning as a carrier traveling region, and a carrier containing a high-concentration carrier impurity and having a thickness smaller than that of the first semiconductor layer and having a quantum effect. And an active region formed by providing at least one second semiconductor layer capable of distributing the first and second semiconductor layers in contact with each other. 2. The communication system device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are each stacked in a plurality of layers. 3. The communication system device according to claim 1, wherein said active element is a MESFET in which said first semiconductor layer is disposed immediately below a gate electrode. Equipment. 4. The communication system device according to claim 1, wherein the active element is a Schottky diode in which the first semiconductor layer is disposed immediately below a Schottky electrode. Communication system equipment. 5. The communication system device according to claim 4, wherein said active element is a horizontal Schottky diode. 6. The communication system device according to claim 1, wherein the active element is provided on a gate insulating film provided on the first semiconductor layer and on the gate insulating film. MISFE further comprising: a gate electrode; and source / drain regions provided on both sides of the gate electrode in the compound semiconductor layer.
T. A communication system device. 7. The communication system device according to claim 1, further comprising: a capacitor and an inductor provided on the compound semiconductor layer. Equipment. 8. The communication device according to claim 1, wherein the compound semiconductor layer is a SiC layer. 9. The communication system device according to claim 1, wherein the device is a base station of a communication system. 10. The communication system device according to claim 1, wherein the device is a mobile station of a communication system. 11. The communication system device according to claim 1, wherein the communication system is one of a mobile phone, a PHS, a car phone, and a PDA. Communication system equipment. 12. The communication system device according to claim 1, wherein the active element is disposed in a transmission unit of the communication system. . 13. A semiconductor integrated circuit device having an active element formed using a compound semiconductor, wherein the active element is provided on a compound semiconductor layer provided on a substrate and on the compound semiconductor layer. At least one first semiconductor layer functioning as a carrier traveling region, and having a high concentration of carrier impurities and having a thickness smaller than that of the first semiconductor layer and distribution of carriers due to a quantum effect. An active area configured by providing at least one possible second semiconductor layer in contact with each other. 14. The semiconductor integrated circuit device according to claim 13, wherein the first semiconductor layer and the second semiconductor layer are each stacked in a plurality of layers. 15. The semiconductor integrated circuit device according to claim 13, wherein said active element is a MESFET in which said first semiconductor layer is disposed immediately below a gate electrode. Circuit device. 16. The semiconductor integrated circuit device according to claim 13, wherein said active element is a Schottky diode in which said first semiconductor layer is disposed immediately below a Schottky electrode. Semiconductor integrated circuit device. 17. The semiconductor integrated circuit device according to claim 16, wherein said active element is a horizontal Schottky diode. 18. The semiconductor integrated circuit device according to claim 13, wherein the active element is provided on a gate insulating film provided on the first semiconductor layer, and provided on the gate insulating film. MISFE further comprising: a gate electrode; and source / drain regions provided on both sides of the gate electrode in the compound semiconductor layer.
T is a semiconductor integrated circuit device. 19. The semiconductor integrated circuit device according to claim 13, further comprising a capacitor and an inductor provided on said compound semiconductor layer. Circuit device. 20. The semiconductor integrated circuit device according to claim 13, wherein said compound semiconductor layer is a SiC layer.