JP2002236659A - Electronic control device for vehicle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure real-time processing of control data by shortening processing time required for communication. SOLUTION: A first CPU 10 includes a SPI 11, DMAs 12, 23, and RAMs 14, 15. A second CPU 20 includes a CPI 21, DMAs 22, 23, and RAMs 24, 25. Various types of control data are renewed in the first and second CPUs 10, 20 in order, and the renewed control data are mutually communicated between the respective CPUs. At this time, the respective CPUs 10, 20 renew the various types of control data by an individually set renewed cycle to store data renewed information corresponding to the renewed cycle at every renewal time. The CPUs 10, 20 regard the control data judged to have been renewed based on the stored data renewal information, as effective data to be transmitted at the time of the transmission, thereby transmitting only the effective data to a CPU on a receiving side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic control unit for a vehicle having a plurality of CPUs.

[0002]

2. Description of the Related Art In a vehicular electronic control system composed of a plurality of CPUs, when communication between CPUs is performed using DMA (Direct Memory Access) or SPI (Synchronous Serial Communication Interface), the data is transferred to DMA. In some cases, the data size to be set is a fixed length, and the number of DMA transfers is a fixed number of times corresponding to this size.
In addition, in order to detect an abnormality in communication data, there is a communication method in which a check code value such as a checksum or a CRC is calculated by software when transmitting and receiving data.

FIG. 15 shows an example of the configuration of communication between CPUs in the above-mentioned conventional technology. FIG. 15 shows a configuration example of the first CPU 10 and the second CPU 20.
Reference numeral 20 denotes one-channel SPIs 11 and 21 for transmitting and receiving communication, and two-channel DMAs 12, 13, 22 and
23 are used for transmission and reception, respectively. SPI1
Reference numerals 1 and 21 each include a transmission data register and a reception data register. DMAs 12, 13, 22, 23
Have a source address register, a destination address register, and a transfer count register. Each SPI
A clock line and a serial communication line are connected between 11 and 21, and a communication clock is supplied from the first CPU 10 side.

[0004] Each of the CPUs 10 and 20 has a RAM 14, 15, 24, 2 for temporarily storing control data.
5, two of which have transmission intermediate buffers 15a and 25a and reception intermediate buffers 15b and 15b for storing data used in various controls.
5b. Also, the RAMs 14 and 24 respectively
Transmission buffers 14a, 14 for storing transmission / reception data
4a and reception buffers 14b and 24b. These DMA, SPI and RAM are connected to each other by a data bus. In this case, at the time of communication, the RAM 14,
The control data is transmitted and received via the DMA and the SPI by using the transmission / reception buffer in 24.

Next, the communication operation between the CPUs will be described. However, here, the first CPU 10 to the second CPU 20
A case in which data is transmitted to the server will be described. First, when there is a communication start request, the first CPU 10 copies the control data in the transmission intermediate buffer 15a to the transmission buffer 14a. Next, check code values such as a checksum are calculated for all areas in the transmission buffer 14a. The calculated value is stored in a predetermined area in the transmission buffer 14a.

Next, the first CPU 10 transmits the DMA 1
The transmission source, the transmission destination, and the number of transfers are set in the second register, and communication is started. However, the number of transfers set at this time is fixed to the transmission / reception buffer size determined at the time of design. When the communication is started, the transmission DMA 12 transmits the data in the transmission buffer 14a to the SP for the number of times set in the register.
The data is transmitted to the second CPU 20 through I11. For example, 100-byte data is sent as the number of transfers 100.

In the second CPU 20, a receiving DMA
Similarly, data is fetched from the SPI 21 by the number of transfers set in the register, and the reception buffer 24b
Transfer to When the reception DMA 23 completes the reception of the reception data, an interrupt is generated and the reception buffer 2
Check code values for all areas in 4b are calculated. Finally, the second CPU 20 detects an abnormality in the data based on whether or not the check code value received in the communication and the calculation result match.
Is copied to the reception intermediate buffer 25b. Thereafter, the data in the reception intermediate buffer 25b is used for various controls.

[0008]

In the prior art, the check code value calculation target area is fixed to the entire area of the transmission buffer and the reception buffer.
The check code value is calculated for data that has not changed since the previous communication. In addition, even if the transmission / reception data is not updated, the data is copied between the transmission / reception intermediate buffer and the transmission / reception buffer. Therefore, there is a problem that the processing time required for calculating the check code value and copying the data becomes long.

Therefore, it is conceivable to shorten the processing time by, for example, performing communication in a time-division manner and reducing the buffer size. However, in this case, a substantial communication cycle of the same data is lengthened by the time division of the communication, which causes a problem that the real-time property of the control data is deteriorated. That is, a delay of up to the communication cycle occurs at the maximum from when the control data is updated to when the control data is actually transmitted. However, this delay becomes longer due to time division of communication.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the processing time required for communication and to ensure real-time control data. It is to provide a control device.

[0011]

According to the present invention, various control data are sequentially updated by the CPU, and the updated control data is mutually communicated between the CPUs. In particular, the control data is divided into a plurality of data groups, and the CPU stores data update information for each data group. In the data communication, the CPU sets control data determined to be updated based on the stored data update information as valid data to be communicated, and transmits only the valid data to the receiving CPU.

According to the present invention, based on the data update information, various control data can be transferred to other CPs in units of each data group.
It is determined whether to communicate with U. In this case, the amount of communication data between the CPUs can be reduced as compared with the related art in which control data is uniquely communicated regardless of factors such as the presence or absence of updating. As a result, the processing time required for communication can be reduced, and the real-time control data can be secured.

Further, in the invention according to claim 2, the CPU
Updates various control data at individually set update cycles, and stores data update information corresponding to the update cycle at each update. In this case, the necessity of data communication is determined based on the data update information corresponding to the update cycle,
Only the control data determined to be updated is communicated. Therefore, the effects of shortening the communication processing time and securing the real-time property can be realized.

According to the third aspect of the present invention, the data update information is composed of data of several bits corresponding to the number of update cycles of each control data, and each bit of the data update information corresponds to each update cycle. This corresponds to 1. in this case,
The update history of the control data can be easily checked.

According to the present invention, updated control data is sequentially stored in the control memory unit, and the control data copied from the control memory unit is temporarily stored in the transmission memory unit as transmission data. It is provided with a configuration for storing the information. Then, at the time of data communication, the CPU copies only control data that is made valid data based on the data update information from the control memory unit to the transmission memory unit. In this case, since the control data is selectively copied based on the data update information, the amount of data copying between the control memory unit and the transmission memory unit can be reduced.

In the invention described in claim 5, the communication partner C
The system further includes a configuration for temporarily storing the control data received from the PU in the receiving memory unit. Then, the transmitting CPU among the plurality of CPUs transmits the data update information together with the control data to the receiving CPU. Also, the receiving CPU
Copies only the control data that is made valid data based on the received data update information from the receiving memory unit to the control memory unit. Also in this case, since the control data is selectively copied based on the data update information, the data copy amount between the control memory unit and the reception memory unit can be reduced.

According to the present invention, a check code value is calculated for control data before transmission, and a check code value is similarly calculated for control data after transmission, and the check code value calculated for each of them is calculated. Are collated to determine a communication abnormality. Here, in particular, the CPU calculates a check code value only for control data that is regarded as valid data based on the data update information. In this case, since the check code value is calculated only for the valid data, the calculation amount can be reduced.

As described above, even if the control data is selectively communicated based on the data update information, the communication time between the CPUs does not change if the number of data to be transmitted each time is uniquely fixed, for example, by the memory size. It is. Therefore, the following invention proposes setting the communication data amount each time to reduce the communication time to a minimum.

That is, according to the seventh aspect of the present invention, when communicating desired control data, the main communication for communicating the control data and the communication data amount to be performed prior to the main communication are used to determine the communication data amount in the main communication. And pre-communication for notifying the CPU. In this case, the CPUs on the transmitting side and the receiving side can know the amount of communication data in each case, and the communication time for each time can be reduced to a minimum.

More specifically, as described in claim 8, the transmitting CPU among the plurality of CPUs transmits only control data that is made valid data based on the data update information at the time of pre-communication. The data amount is calculated and notified to the receiving CPU, and the receiving CPU may receive the control data by the notified transmission data amount. As a result, desired control data can be reliably transmitted and received when the main communication is performed.

According to a ninth aspect of the present invention, the transmitting CPU among the plurality of CPUs determines the fixed data amount for transmitting the transmission data amount information in the next pre-communication in the main communication. , And the receiving CPU
It is preferable that control data is received for the notified transmission data amount. Thus, when performing the pre-communication, the transmission data amount information in the next main communication can be reliably transmitted and received.

Further, as described in claim 10, the CPU adds to the data update information communication identification information for identifying whether communication is pre-communication or main communication each time, and sends the data update information to the receiving CPU. Good to send. Thereby, it is possible to correctly identify whether the communication is the pre-communication or the main communication.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The present invention provides a plurality of C
The present invention is embodied as an electronic control unit for a vehicle including a PU, and a characteristic configuration and operation for suitably performing communication between CPUs will be described in detail below.

FIG. 1 is a diagram showing a configuration relating to communication between CPUs in the electronic control unit of the present embodiment.
The configuration of FIG. 1 substantially conforms to FIG. 15, which is a conventional technique, and includes SPIs in the first CPU 10 and the second CPU 20.
The configuration of each module such as DMA is the same as that of FIG. That is, each of the CPUs 10 and 20 is the first CPU
The bidirectional serial communication is performed via the SPI and the DMA in accordance with the communication clock from the CPU 10. Each CPU 10,
Reference numeral 20 updates various control data at individually set update intervals, and transmits the control data to the transmission partner CPU as necessary. Here, the control data includes data updated at a period of 8 ms and data updated at 64 ms, 128 ms, or the like. The difference from FIG. 1 is that RA
The buffer configuration in M14, 15, 24, 25 is different,
The details will be described with reference to FIGS.

In this embodiment, the RAMs 15, 25
Is the control memory unit, the transmission buffers 14a and 24a of the RAMs 14 and 24 are the transmission memory units, and the RAMs 14 and 24 are the transmission buffers 14a and 24a.
Of the receiving buffers 14b and 24b correspond to the receiving memory unit.

In FIG. 2, (a) shows the configuration of the transmission intermediate buffer (15a, 25a in FIG. 1), and (b) shows the configuration of the transmission buffer (14a, 24a in FIG. 1). FIG.
As shown in (a), the transmission intermediate buffer has update information IND indicating whether or not various control data has been updated (update history).
An EX storage area is newly added. The update information INDEX is composed of several bits of data corresponding to the number of update cycles of each control data, and each bit of the INDEX has a one-to-one correspondence with each update cycle. In this case, at the time of the update process in each update cycle, "1" is set to each corresponding bit. This update information INDEX is used to determine which data is to be transmitted. That is, in the present embodiment, various types of control data are divided into a plurality of data groups based on individual update periods.

The arrangement of data in the transmission intermediate buffer is divided for each control data update cycle, and the address and size are statically determined. In FIG.
An address of an update cycle n + 1 is provided. By doing so, transmission data can be selected for each update cycle and set in the transmission buffer. The arrangement of the data is not limited to the update cycle, but may be arbitrary.

As shown in FIG. 2B, the transmission buffer is provided with a transfer data area and a check code value storage area as in the existing conventional configuration. Further, a storage area for the update information INDEX is newly added to this configuration.
DEX informs the receiving side which data has been transmitted. Note that the transfer data area is set to a size corresponding to the assumed maximum communication amount.

On the other hand, in FIG. 3, (a) shows the configuration of the reception intermediate buffer (15b, 25b in FIG. 1), and (b)
Indicates the configuration of the reception buffer (14b, 24b in FIG. 1). As shown in FIG. 3A, the reception intermediate buffer is divided into areas for each update cycle, and the address and the size are statically determined, similarly to the transmission intermediate buffer. Thus, when data is received by the reception buffer, the reception data can be selectively stored in the update cycle area corresponding to each of the reception intermediate buffers.

As shown in FIG. 3B, the reception buffer has the same configuration as the transmission buffer.
In particular, a storage area for the update information INDEX is newly added, and it is possible to confirm which data has been received by the update information INDEX.

Next, the operation of communication between CPUs in this embodiment will be described with reference to FIG. Here, temporarily, the first C
A case where control data is transmitted from the PU 10 to the second CPU 20 will be described. FIG. 4 shows a case where the control data of the update cycle m is updated.

In FIG. 4, at the end of the update processing of the control data to be communicated, that is, at the time when the update of the control data is completed, the first CPU 10 Is set to "1" (FIG. 4A).

Thereafter, when a periodic communication start request occurs, the update information INDEX in the transmission intermediate buffer 15a is checked, and INDEX and control data corresponding to the bit whose INDEX value is "1" are read. Is copied to the transmission buffer 14a (FIG. 4B). Here, regularity corresponding to INDEX is provided in the order of copying. For example, data corresponding to the 0th bit of INDEX is placed at a lower address of the transmission buffer 14a,
The data corresponding to the first bit is after that, and so on. According to this rule, the receiving side can easily retrieve desired data for each update cycle from the reception buffer.

As described above, when data is copied from the transmission intermediate buffer 15a to the transmission buffer 14a, the data is selectively copied based on the update information INDEX. The processing load required for copying is reduced as compared with the case of.

Next, a check code value is calculated for the data in the transmission buffer 14a by a checksum or CRC. In this case, only the control data newly updated this time is stored in the transmission buffer 14a, and the check code value is calculated for the data. Therefore, the check code value is required to be calculated as compared with the related art. The processing load is reduced.
That is, in the related art, the check code value is calculated by the size of the transmission buffer, whereas in the present embodiment, it is possible to determine what data is stored by the update information INDEX and to determine the effective data size for communication. , The check code value is calculated only for that size.

Next, desired settings are made in the register of the transmission DMA 12, and the data in the transmission buffer 14a is stored in the SP.
It is transmitted to the second CPU 20 (receiving CPU) through I11 ((c) in FIG. 4). At this time, the update information INDE
X, the updated control data, and the check code value are transmitted.

In the second CPU 20, the reception buffer 24b
Of the data in the, how much is valid data,
A check is performed based on the received INDEX information, and check code values corresponding to the size are calculated ((d) in FIG. 4).
Further, the calculated check code value is compared with the check code value received from the first CPU 10 to check for a communication error. If the communication is normal, the reception buffer 24b
Is copied to the area corresponding to INDEX of the reception intermediate buffer 25b. Thus, data reception is completed. Similarly to the data transmission, the data copy amount between the reception buffer 24b and the reception intermediate buffer 25b and the processing load required to calculate the check code value are reduced at the time of data reception.

FIGS. 5 to 7 are flowcharts showing communication processing by each of the CPUs 10 and 20, and each flowchart will be described in detail. First, the process of setting the update information INDEX will be described with reference to the flowchart of FIG. The process of FIG. 5 is started in the process of updating each control data performed at a predetermined update cycle. Then, in the processing, after updating the corresponding control data, the first or second CPU 10 or 20 sets “1” to the bit corresponding to the current update cycle among the bits of the update information INDEX in the transmission intermediate buffer. (Step 10
1). The other bits of INDEX are not cleared.

Next, the communication start processing by the transmitting CPU will be described with reference to the flowchart of FIG. FIG. 6 is activated in response to a communication start request, and first, an initialization process is performed for each communication start request. That is, step 20
At 1, the size counter indicating the number of valid transmission data is cleared to "0". In step 202, a copy destination address is initialized when data is copied from the transmission intermediate buffer to the transmission buffer. Here, the start address of the communication data area of the transmission buffer is set as the copy destination address.

Thereafter, in step 203, the update information I
After all the bits of the NDEX have been referred to, it is determined whether or not all the control data to be transmitted has been checked for updates. This check is performed for the number of update cycles, and if the check has not been completed, the subsequent step 20 is executed.
Proceed to 4. In step 204, it is determined whether each bit of the update information INDEX stored in the transmission intermediate buffer is “1” in order. This allows
The presence or absence of the updated data is confirmed. If the bit is 1, the process proceeds to step 205.

Steps 205 to 207 are for extracting updated data from the transmission intermediate buffer and copying it to the transmission buffer. Specifically, in step 205, the data updated this time (data corresponding to INDEX bit = 1) is copied to a predetermined copy destination in the transmission buffer. In step 206, the data size copied this time is added to the size counter in order to count the number of valid transmission data (total amount of copy data). Thereafter, in step 207, the copy destination address of the transmission buffer is updated in preparation for the next data copy. That is, the data size copied this time is added to the start address of the current copy. By these steps 205 to 207, the copy data before and after are continuously stored in the transmission buffer.

On the other hand, if it is confirmed whether or not all the control data has been updated (if step 203 becomes YES), the routine proceeds to step 208, where check code values are calculated. However, in this case, the target of calculation is only the data previously copied from the transmission intermediate buffer, that is, only valid data for communication, and the check code value is calculated for the data of the size counter value calculated in step 206. . Thereafter, in step 209, the update information IND of the transmission intermediate buffer
EX is copied to a predetermined area of the transmission buffer. In the following step 210, the update information INDEX in the transmission intermediate buffer is cleared to “0” for the next communication. Then, the process proceeds to the DMA register setting process.

FIG. 7 is a flowchart showing the DMA register setting process. Referring to FIG.
303 are register setting processes of the DMA for transmission,
Steps 304 to 306 correspond to the setting processing of the receiving DMA register.

More specifically, in step 301, the transmission D
The head address of the transmission buffer which is the transmission source for the DMA is set in the transmission source address register of the MA. In step 302, the SPI address which is the transmission destination for the DMA is stored in the transmission destination address register of the transmission DMA.
Set the address of the transmission data register. Also,
In step 303, the number of data transfers by the DMA is set in the transfer count register of the DMA for transmission. However, the number of data transfers is the size of the transmission buffer. The register setting of the reception DMA is performed in the same manner as the transmission DMA (steps 304 to 306). If the settings are made up to this point and the DMA is started, communication is started.

Next, the data receiving process by the receiving CPU will be described. FIG. 8 is a flowchart showing a transfer end interrupt process synchronized with the end of the transfer in the receiving DMA.

In FIG. 8, in step 401, a size counter indicating the number of valid reception data is cleared to "0". In step 402, it is determined whether or not the update information INDEX has been checked for the number of update cycles.
If the check has not been completed, the following step 4
Go to 03. In step 403, a search is made for a bit set to "1" in the update information INDEX stored in the reception buffer. If bit = 1 is found, the process proceeds to step 404. In step 404, the data size copied this time is added to the size counter in order to count the number of valid reception data (total amount of transfer data).

The processing in steps 402 to 404 is as follows.
This is based on the process of obtaining the number of valid data in the transmitting CPU (steps 203, 204, and 206 in FIG. 6), and the number of valid data and the number of valid data actually match. Therefore, information on the number of valid transmission data may be transmitted from the transmitting CPU, and may be used as the number of valid reception data. However, if calculations are separately performed on the transmission side and the reception side, the number of communication data can be reduced by that amount.

When the number of valid reception data is known (step 4
The process proceeds to step 405 (when 02 becomes YES) to calculate a check code value for the reception valid data. Thereafter, in step 406, the calculated check code value and the transmission-side CP
Check with the check code value received from U. If they do not match, it is determined that a communication error has occurred, and the process ends without updating the reception intermediate buffer. If they match, it is determined that the communication is normal, and the process proceeds to the subsequent step 407.

Steps 407 to 412 are parts showing the update processing of the reception intermediate buffer. That is, step 40
At 7, the size counter is cleared to "0". next,
In step 408, the update information IND is updated by the number of update cycles.
It is determined whether or not the EX check has been performed, and if all the checks have been completed, the process ends. If the check is not completed, the process proceeds to the subsequent step 409. In step 409, the update information IND indicates what data has been received.
Search from EX. Then, if a bit that is "1" is found in the INDEX, step 410
To update the copy source address of the reception buffer.
That is, the size counter value indicating the total amount of data extracted so far is added to the head address of the reception buffer.

Thereafter, in step 411, data is taken out from the copy source address of the reception buffer obtained in step 410, and the data is copied to a predetermined area (data area corresponding to INDEX bit = 1) of the reception intermediate buffer. I do. In the following step 412, the data size extracted this time is added to the size counter in preparation for the next data extraction. The receiving operation is completed by the above processing.

According to the embodiment described above, the following effects can be obtained. Each of the CPUs 10 and 20 uses the control data determined to be updated as valid data for communication based on the update information INDEX corresponding to the update cycle of various control data, and transmits only the valid data to the receiving CPU. In this case, only the control data determined to be updated is communicated. Therefore, the amount of communication data between CPUs can be reduced as compared with the related art in which control data is uniquely communicated regardless of whether or not there is an update. As a result, the processing time required for communication can be reduced, and the real-time control data can be secured.

In this case, only the control data which is made valid data based on the update information INDEX is selectively copied between the buffers. Therefore, the data copy amount from the transmission intermediate buffer to the transmission buffer and the data copy amount from the reception buffer to the reception intermediate buffer can be reduced.

Further, since the check code value is calculated only for the control data which is made valid data based on the update information INDEX, the amount of calculation can be reduced. By thus reducing the amount of data copy and the amount of calculation of the check code value, the processing load on the CPU can be greatly reduced.

(Second Embodiment) Next, a second embodiment of the present invention will be described focusing on differences from the above-described first embodiment.

In the above-described embodiment, the copying time between buffers by the CPU and the calculation processing time of the check code value are shortened. Time is included. Therefore, in the present embodiment, a method for reducing the communication time of the SPI module will be described.

In short, in FIG. 1, the communication clock is supplied from the first CPU 10, and the number of output clocks is equal to the number of transmission data on the first CPU 10. In other words, the same number of clocks is used by the first CPU 10 for the transmission DMA.
, And the number of transfers is conventionally the same as the transmission buffer size of the first CPU 10. The second CPU 20 transmits its own data only by the number of communication clocks supplied from the first CPU 10 or
Since the data from the first CPU 10 cannot be fetched, the transmission / reception buffer of the second CPU 20 becomes the same as the transmission buffer size of the first CPU 10. 2nd CPU
Since the size of the transmission buffer 20 and the size of the reception buffer of the first CPU 10 are the same, all four buffer sizes are the same. The communication time is uniquely fixed by the transmission buffer size of the first CPU 10.

In this case, as described above, the update information INDEX
SP even if control data is selectively communicated based on
The communication time of I is unchanged. Therefore, in this embodiment,
By limiting the data communicated by the SPI to valid data, the communication time of the SPI is also reduced. That is, SPI
In order to reduce the communication time, the number of DMA transfers may be set to the number of valid data instead of the fixed buffer size as in the related art.

FIG. 9 shows a CPU according to the second embodiment.
FIG. 2 is a configuration diagram illustrating an outline of inter-communication. In the configuration of FIG. 1, the number of DMA transfers on the second CPU 20 side is the first CPU 1
The number of DMA transfers is dependent on the number of clocks supplied from 0, and the number of DMA transfers is fixed. On the other hand, in the configuration of FIG. 9, the number of DMA transfers is controlled according to the number of valid data transmitted by the second CPU 20 side. The configuration can be changed.

Hereinafter, the configuration of FIG. 9 will be described. FIG.
In this embodiment, the difference from FIG. 1 is that two SPI modules are provided. That is, the first CPU
10 is provided with an SPI 16 linked to the transmission DMA 12 and an SPI 17 linked to the reception DMA 13, and the second CPU 20 is provided with an SPI 16 linked to the transmission DMA 22.
26 and an SPI 27 linked to the receiving DMA 23 are provided. The communication clock is supplied from both CPUs 10 and 20, and does not depend on the transmission data amount of the other.

In data communication, each of the CPUs 10 and 20 makes the number of transfers by DMA variable according to the number of data, and transmits data indicating the amount of data to be transmitted in advance.
That is, the configuration is such that the next transmission amount is notified to the receiving CPU at the time of data transmission. The transmission buffers 14a and 24a and the reception buffers 14b and 24b are provided with storage areas for newly storing transmission data amount information.

Next, the operation of communication between CPUs in this embodiment will be described with reference to FIG. As shown in FIG. 10, in the present embodiment, communication is performed in two stages: main communication and pre-communication performed prior to the main communication.

That is, at the timing of t1 in the figure, a communication start request of the pre-communication is generated, and the communication start process of the pre-communication is performed accordingly. In this communication start process, control data that is valid this time is selected based on the update information INDEX, and the transmission data amount of the main communication is calculated. In the DMA communication, the transmission data amount of the main communication is transmitted to the receiving CPU. Thereafter, in the transfer end interrupt processing, the check code value is collated with respect to the current pre-communication.

Thereafter, at a timing t2 after a lapse of a predetermined time from the pre-communication start request (timing t1), a main communication start request is generated, and a communication start process of the main communication is performed accordingly. In the communication start process, the transmission data amount of the pre-communication is calculated in preparation for the subsequent pre-communication (pre-communication at t3). However, since no control data is transmitted in the pre-communication, the transmission data amount here is a known fixed size determined by the update information INDEX and the like. In the DMA communication, control data that becomes valid this time is transmitted to the receiving CPU based on the transmission data amount of the main communication notified by the pre-communication. At the same time, the transmission data amount of the pre-communication is transmitted to the receiving CPU. Thereafter, in the transfer end interrupt processing, the check code value is collated with respect to the current main communication.

The 0th bit of the update information INDEX is used as a communication identification bit in order to identify whether the type of communication is pre-communication or main communication each time. In this case, "0" is set to the communication identification bit in the communication start processing of the pre-communication, and "1" is set to the communication identification bit in the communication start processing of the main communication.

The pre-communication may be started in synchronization with the existing data communication cycle, and the main communication may be started after a fixed period. However, the time interval between the pre-communication and the main communication is not longer than the data communication cycle.

FIGS. 11 to 14 show flowcharts of various processes by the CPUs 10 and 20, and details thereof will be sequentially described. FIG. 11 is a flowchart showing a communication start process of the pre-communication. In this pre-communication, preparations are made for the subsequent main communication. Note that the processing in FIG. 11 is substantially similar to the processing in FIG. 6, and the processing in steps 501 to 510 is the same as that in steps 201 to 210 in FIG. That is, steps 501 to 5
At 10, the control data is selectively copied from the transmission intermediate buffer to the transmission buffer based on the update information INDEX, and the data size and the check code value are calculated for the corresponding data.

Steps 511 and 512 are different from those shown in FIG. 6. In step 511, the communication identification bit is set to "0". In step 512, the data size (the value calculated in step 506) calculated as the transmission data amount information is set in a predetermined transmission buffer area. Thereafter, the process proceeds to the DMA register setting process shown in FIG.

FIG. 12 is a flowchart showing the communication start processing of the main communication. In this communication start processing, preparation for the next pre-communication is performed. That is, in step 601, the transmission data size of the pre-communication is set in a predetermined transmission buffer area. The transmission data size here is a known fixed size determined by the update information INDEX and the like as described above. However, at this time, each value is separately stored in a different area of the transmission buffer so that the transmission data size of the pre-communication can be distinguished from the transmission data size of the main communication (the value of step 512 in FIG. 11). In step 602, a check code value is calculated for the pre-communication data. At step 603, the communication identification bit is set to "1".
Is set. Thereafter, the process proceeds to the DMA register setting process shown in FIG.

FIG. 13 is a flowchart showing the DMA register setting process. This is basically the same as FIG.
, But the setting of the number of times of DMA transfer for transmission and reception is different.

In steps 701 and 702, the transmission DM
A source address register and a destination address register are set for A. In the following step 703, it is determined whether the current communication is the pre-communication or the main communication based on the communication identification bit. If the communication is the pre-communication, the flow proceeds to step 704 to set the transmission data size of the pre-communication in the transfer count register of the transmission DMA. I do. If the communication is the main communication, the process proceeds to step 705, and the transmission data size of the main communication is set in the transfer count register of the transmission DMA.

Thereafter, in steps 706 and 707, the source address register and the destination address register are set for the receiving DMA. Next step 708
Then, the transmission data size received from the transmitting CPU is set in the transfer count register of the receiving DMA. If the settings are made up to this point and the DMA is started, communication is started.

FIG. 14 is a flowchart showing the transfer end interrupt processing of the receiving DMA. This processing is basically similar to the processing of FIG. 8 described above, and different parts will be described. In FIG. 8, the communication data size is calculated first (steps 401 to 40).
4) In FIG. 14, there is no need to calculate the data size because there is data size information already received as communication information from the transmitting CPU. Therefore, in FIG.
At 01, a check code value is calculated based on the data size information from the transmitting CPU. Also, the following step 80
In step 2, it is checked whether the calculated check code value matches the check code value received from the transmitting CPU.

In FIG. 14, a process for identifying whether or not the communication is the pre-communication is newly added as step 803. In this case, it is determined whether or not this time is the pre-communication based on the communication identification bit added to the update information INDEX. In the case of the pre-communication, the data copy processing to the reception intermediate buffer (steps 804 to 809) is skipped, and the present interrupt processing ends. If it is not the pre-communication, it is determined that this is the main communication, and in steps 804 to 809, data copy processing from the reception buffer to the reception intermediate buffer is performed. However, the processing in steps 804 to 809 is the same as the processing in steps 407 to 412 in FIG.

As described above, according to the second embodiment, the first
In addition to the effects of the embodiment, the following effects can be obtained. That is, each of the CPUs on the transmission side and the reception side can know the amount of transmission data (the number of valid data) in each case, and the communication time for each time can be reduced to a minimum. That is, the number of times of DMA transfer can be limited to the number of valid data, and the communication time by SPI can be reduced.

The present invention can be embodied in the following modes other than the above. In the above embodiment, the update information INDEX is stored in correspondence with the update cycle of each type of control data, but this is changed. That is, in a broad sense, it is sufficient if control data is divided into a plurality of data groups and the update information INDEX is stored for each data group. For example, the data group is divided according to the control content instead of the update cycle. Then, when any data in each data group is updated, the CPU also updates the INDEX information. In data communication, the CPU uses control data (data group) determined to be updated based on the update information INDEX as valid data to be communicated, and transmits only the valid data to the receiving CPU. Also in this case, effects such as shortening the communication processing time and securing the real-time property can be realized.

A priority is set for each bit of the update information INDEX, so that high-priority data is communicated preferentially, and low-priority data is made to wait. This makes it possible to reduce the size of the transmission and reception buffers in each CPU.

In the above embodiment, the update information INDEX is rewritten in synchronization with the control data update cycle. Instead, the update information INDEX is rewritten in synchronization with the communication start request in order to distribute the communication load. . In this case, time division communication can be easily handled. Also,
Regarding rewriting of the update information INDEX, it is possible to use both synchronization to the update cycle and synchronization to the start of communication. As described above, according to the present invention, reduction of communication load,
Dispersion can be realized flexibly.

In the second embodiment, the values are separately stored in different areas of the transmission buffer so that the transmission data sizes of the pre-communication and the main communication can be distinguished.
The transmission data size may be stored in the same area and overwritten each time. In short, any configuration may be used as long as the number of DMA transfers required for each of the pre-communication and the main communication can be appropriately set.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration for communication between CPUs in an electronic control unit.

FIG. 2 is a diagram illustrating a configuration of a transmission intermediate buffer and a transmission buffer.

FIG. 3 is a diagram showing a configuration of a reception intermediate buffer and a reception buffer.

FIG. 4 is a diagram illustrating an operation of communication between CPUs.

FIG. 5 is a flowchart showing an INDEX setting process.

FIG. 6 is a flowchart showing communication start processing.

FIG. 7 is a flowchart showing a DMA register setting process.

FIG. 8 is a flowchart showing a transfer end interrupt process.

FIG. 9 is a diagram showing a configuration for communication between CPUs in an electronic control unit in the second embodiment.

FIG. 10 is a diagram for explaining the operation of communication between CPUs.

FIG. 11 is a flowchart showing communication start processing of pre-communication.

FIG. 12 is a flowchart illustrating communication start processing of main communication.

FIG. 13 is a flowchart showing a DMA register setting process.

FIG. 14 is a flowchart illustrating a transfer end interrupt process.

FIG. 15 is a diagram showing a configuration for communication between CPUs in the related art.

[Explanation of symbols]

10 first CPU, 20 second CPU, 14, 15, 2
4, 25 ... RAM.

Claims (10)

[Claims] An electronic control unit for a vehicle in which a plurality of CPUs are provided, and various control data are sequentially updated in each of the CPUs, and the updated control data is mutually communicated between the CPUs. The CPU stores means for storing data update information for each data group, and, in data communication, the control data determined to be updated based on the stored data update information as an effective communication target. Means for transmitting only valid data to the receiving CPU as data. 2. The vehicle according to claim 1, wherein the CPU updates various control data at individually set update cycles, and stores data update information corresponding to each update cycle each time the control data is updated. For electronic control device. 3. The data update information comprises several bits of data corresponding to the number of update cycles of each control data, and each bit of the data update information corresponds to each update cycle on a one-to-one basis. The vehicle electronic control device according to claim 2. 4. The CPU has a control memory unit for storing updated control data, and a transmission memory unit for temporarily storing control data copied from the control memory unit as transmission data. Wherein the CPU copies only control data that is valid data based on the data update information from the control memory unit to the transmission memory unit during data communication.
An electronic control unit for a vehicle according to any one of the above. 5. The electronic control unit for a vehicle according to claim 4, wherein the CPU further includes a receiving memory unit for temporarily storing control data received from a CPU of a communication partner. The transmitting CPU transmits the data update information together with the control data to the receiving CPU, and the receiving CPU controls only the control data that is regarded as valid data based on the received data update information from the receiving memory unit. Electronic control unit for vehicles that copies to the memory unit for vehicles. 6. A check code value is calculated for control data before transmission, a check code value is similarly calculated for control data after transmission, and the calculated check code value is compared with each of them to determine a communication abnormality. The vehicle electronic control device according to any one of claims 1 to 5, wherein in the vehicle electronic control device, the CPU calculates a check code value only for control data that is valid data based on the data update information. 7. When communicating desired control data, a main communication for communicating the control data and a pre-communication executed prior to the communication and notifying a communication data amount in the main communication to a CPU of a communication partner side. Claim 1 that implements
The electronic control unit for a vehicle according to any one of claims 1 to 6. 8. The electronic control unit for a vehicle according to claim 7, wherein the transmitting CPU among the plurality of CPUs performs pre-communication.
Based on the data update information, the transmission data amount is calculated only for the control data that is regarded as valid data, and the transmission data amount is notified to the receiving CPU. Electronic control unit for a vehicle. 9. The electronic control unit for a vehicle according to claim 7, wherein the transmission-side CPU among the plurality of CPUs is configured to transmit the transmission data amount information in the next pre-communication in the main communication. Notify the receiving CPU of the data amount, and
The PU is an electronic control unit for a vehicle that receives control data by the notified transmission data amount. 10. The electronic control unit for a vehicle according to claim 7, wherein the CPU updates communication identification information for identifying whether communication is pre-communication or main communication each time the data is updated. An electronic control unit for a vehicle that transmits the information to the receiving CPU in addition to the information.