JP2002232403A - Timing generation device having automatic calibration function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing generation device which has comparatively high precision, which can be produced at a comparatively low cost and which has an automatic calibrating function. SOLUTION: A calibration module 22 receives a coarse timing pulse signal and a fine timing pulse signal, decides the phase difference between the coarse timing pulse signal and the fine timing pulse signal and generates a phase compensation signal corresponding to the difference between the phase difference and a prescribed phase difference. A slave timing module 211 includes a delay control unit 6 receiving the phase compensation signal and generating a delay voltage signal corresponding to the phase compensation signal and a delay unit 7 receiving the coarse timing pulse signal and the delay voltage signal and introducing phase delay corresponding to the delay voltage signal to the coarse timing pulse signal so that the fine timing pulse signal is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a timing generator, and more particularly to a timing generator having an automatic calibration function.

[0002]

2. Description of the Related Art A timing generator is generally used to supply a timing pulse signal to an IC automatic test equipment (ATE), and a module of the IC ATE operates according to the timing pulse signal. Since the IC ATE needs to test a variety of IC products, the timing generator must provide accurate timing pulses to accommodate a wide range of IC products. Recently, CMOS
The components are used for IC ATE. However, with changes in temperature, CMOS components experience timing variations that require compensation or calibration circuits.

FIG. 1 shows a master timing module 1
0 and a conventional timing generator including a plurality of slave timing modules 11 electrically connected to the master timing module 10, respectively. The master timing module 10 receives an external reference clock and generates a plurality of coarse timing pulse signals. The slave timing module 11 is operable to receive each of the coarse timing pulse signals and generate a fine timing pulse signal in response to the selected coarse timing pulse signal. For example, coarse timing pulse signals are 1.0 ns, 2.0 ns, 3.0 ns,
. . . Have different time lengths. The slave timing module is, for example, 0.05 ns, 0.1
It is possible to generate multiple timing pulse signals with different time adjustments, such as 0 ns, 0.15 ns. When a conventional timing generator needs to generate a timing pulse signal having a length of 6.12 ns,
A coarse timing pulse signal having a length of 6.0 ns is selected by one of the slave timing modules 11 that produces a phase delay of 0.12 ns.

FIG. 2 shows an embodiment of a conventional timing generator. The master timing module 10 is a closed-loop phase locked ring oscillator. The slave timing module 11 is configured by a programmable delay unit that is an open loop system, and the module 11 cannot maintain the accuracy of a fine timing pulse signal.

FIG. 3 shows another embodiment of the conventional timing generator. Unlike FIG. 2, the slave timing module 11 ′ in FIG.
11 is implemented as a phase locked delay line which generates a fine timing pulse signal from a coarse timing pulse signal. Slave timing module 11 '
Note that while the fine timing pulse signal is obtained from the phase select multiplexer 111 and the drive are outside the phase locked loop of the phase locked delay line. Therefore, the accuracy of the fine timing pulse signal is affected by the high temperature coefficient of the solid state device, and a temperature compensation mechanism is needed to maintain the fine timing pulse signal accuracy at different temperatures.

[0006]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a timing generator having an automatic calibration function which has relatively high accuracy and can be produced at relatively low cost. .

[0007]

SUMMARY OF THE INVENTION A timing generator according to the present invention includes a master timing module, a slave timing module, and a calibration module.

The master timing module is adapted to receive an external reference clock and generate a coarse timing pulse signal therefrom.

[0009] The slave timing module is electrically connected to the master timing module to receive the coarse timing pulse signal from the master timing module, and is capable of generating a fine timing pulse signal from the coarse timing pulse signal.

[0010] The calibration module is electrically connected to the master timing module and the slave timing module. The calibration module receives the coarse timing pulse signal and the fine timing pulse signal, determines a phase difference value between the coarse timing pulse signal and the fine timing pulse signal, and calculates a difference between the phase difference value and the predetermined phase difference value. Is generated.

The slave timing module receives the phase compensation signal from the calibration module, generates a delay voltage signal corresponding to the phase compensation signal, receives the coarse timing pulse signal and the delay voltage signal, A voltage controlled delay unit for introducing a phase delay corresponding to the signal into the coarse timing pulse signal and generating a fine timing pulse signal.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS Other features and advantages of the present invention will become apparent from the detailed description of an embodiment thereof, with reference to the accompanying drawings.

Referring to FIG. FIG. 4 shows a master timing module 20 and a plurality of slave timing modules 211, 212,. . . 2N and a timing generator according to an embodiment of the present invention including a calibration module 22.

The master timing module 20 is adapted to receive an external reference clock from which a plurality of coarse timing pulse signals are generated in a conventional manner.

Each slave timing module 211,
212,. . . , 2N are electrically connected to the master timing module 20 to receive the coarse timing pulse signal from the master timing module and are capable of generating a fine pulse signal from the selected coarse timing pulse signal.

The calibration module 22 includes a master module 20 and each slave timing module 211, 21.
2,. . . , 2N. The calibration module 22 receives the coarse timing pulse signal and the fine timing pulse signal, determines a phase difference value between the selected coarse timing pulse signal and the corresponding fine timing pulse signal, and determines the phase difference value described above and a predetermined value. A phase compensation signal corresponding to the difference between the phase difference values is generated.

Referring to FIG. The slave timing module 211 includes a delay control unit 6, a voltage controlled delay unit 7 electrically connected to the delay control unit 6 and further to the master timing module 20 via a multiplexer 71. The calibration module 22
Each slave timing module 211, 21
2,. . . A phase detection unit 3 electrically connected to the 2N voltage-controlled delay unit 7 and the master timing module 20, a phase measurement unit 4 electrically connected to the phase detection unit 3, and a phase measurement unit 4. Further, it includes a phase compensation unit 5 electrically connected to the delay control unit 6 of the slave timing module 211 via the demultiplexer 23.

As shown in FIG. 6, in the present embodiment, the phase detection unit 3 includes the master timing module 2
A first multiplexer 32 operable to receive a coarse timing pulse signal from 0 and to output a selected coarse timing pulse signal (TM _core ) (see FIG. 7A).
And the slave timing modules 211 and 21
2,. . . , 2N, and receives a fine timing pulse signal (TM _fin ) from the slave timing module 211 (see FIG. 7B).
A second multiplexer 33 operative to output
A first input 34 electrically connected to the first multiplexer 32 to receive the selected coarse timing pulse signal (TM _coa ) and a second multiplexer to receive the fine timing pulse signal (TM _fin ). 3
3 includes an exclusive OR gate 31 having a second input 35 electrically connected to the gate 3. The gate 31 receives the selected coarse timing pulse signal (T
M _core ) and a fine timing pulse signal (T
If M _fin ) is in a different logic state, gate 31
The phase difference pulse output 36 generates a phase difference pulse.

As shown in FIG. 8, in the present embodiment, the phase measuring unit 4 is electrically connected to the phase difference pulse output 36 of the exclusive OR gate 31 and receives the phase difference pulse. 43 and a digital counter 41 having an input 42 for receiving a frequency (F) counting clock. In the duty cycle (Dτ) of the phase difference pulse period (T), the digital counter 41 determines the phase difference value between the selected coarse timing pulse signal (TM _core ) and the fine timing pulse signal (TM _fin ). And output. The phase difference value is equal to Dτ ^* F. FIG. 9A
Indicates a phase difference pulse from the gate 31. FIG. 9B shows a first coefficient clock, and FIG. 9C shows a second counting clock, where the first counting clock has a higher frequency than the second counting clock. Using the first counting clock instead of the second counting clock results in a more accurate phase measurement.

As shown in FIG. 10, in this embodiment,
The phase compensation unit 5 includes a register 51 that stores a predetermined phase difference value, and a subtracter 50 that is electrically connected to the register 51 and the digital counter 41. The subtractor 50 receives the phase difference value from the digital counter 41 and the predetermined phase difference value from the register 51, and generates a phase compensation signal in digital form at an output 53.

As shown in FIG. 11, in this embodiment,
The delay control unit 6 includes a charge pump circuit 6 and a capacitor (C). The charge pump circuit 60 has an input 62 and an output 63 for receiving a phase compensation signal from the subtractor 50 of the phase compensation unit 5 via the demultiplexer 23. The capacitor (C) is connected across the output 63 of the charge pump circuit 60. The delay control unit 6 is obtained across the capacitor (C) and generates an analog delay voltage signal corresponding to the digital phase compensation signal.

As shown in FIG. 12, in this embodiment,
The voltage controlled delay unit 7 is electrically connected to the output 63 of the charge pump circuit 60 to receive the delayed voltage signal, receives the coarse timing pulse signal selected from the master timing module 20 via the multiplexer 71, a variable gain buffer (VCB) 70 which is a voltage controlled has an output 701, a capacitor connected across the output 701 of the variable gain buffer 70 which is voltage controlled (C _L), the variable gain buffer 70 which is voltage controlled It includes a fixed gain output buffer (BUF) electrically connected to output 701 and having output 74. The voltage controlled delay unit 7 introduces a phase delay corresponding to the delayed voltage signal into the selected coarse timing pulse signal (TM _core ) to generate a fine timing pulse signal available at output 74.

The following are some of the advantages of the present invention.

1. Since the timing generator of the present invention is a closed loop system and the phase of the fine timing pulse signal is detected from the output 74 of the slave timing module, the accuracy of the fine timing pulse signal is compensated.

2. The calibration module 22 of the present invention includes an automatic calibration and a coarse timing pulse signal (TM _core ).
Since a direct measurement of the phase angle between the fine timing pulse signal (TM _fin ) and the fine timing pulse signal is used, no additional calibration process is required.

3. Since the digital counter 41 is used,
No need to convert analog signals to digital signals,
Thus, relatively high accuracy and relatively low cost are obtained.

4. Because the phase difference value is a statistical value, the calibration module 22 can be flexibly adjusted to meet the requirements of a highly accurate or fast response system.

Although the present invention has been described with reference to the most practical embodiments, the present invention is not limited to the disclosed embodiments, but is intended to be within the broad scope and spirit of the invention. , And is therefore understood to include variations and equivalent arrangements.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a conventional timing generator.

FIG. 2 is an electric circuit diagram showing an embodiment of a conventional timing generator.

FIG. 3 is an electric circuit diagram showing another embodiment of the conventional timing generator.

FIG. 4 is a circuit block diagram showing an embodiment of the timing generator of the present invention.

FIG. 5 is a circuit block diagram showing a slave timing module and a calibration module of the embodiment.

FIG. 6 is an electric circuit diagram showing a phase detection unit of the calibration module.

FIG. 7A is a timing chart showing a coarse timing pulse signal.

FIG. 7B is a timing chart showing a fine timing pulse signal.

FIG. 7C is a timing chart showing a phase difference pulse.

FIG. 8 is an electric circuit diagram showing a phase measurement unit of the calibration module.

FIG. 9A is a timing chart showing a phase difference pulse.

FIG. 9B is a timing chart showing a first counting clock.

FIG. 9C is a timing chart showing a second counting clock.

FIG. 10 is an electric circuit diagram showing a phase compensation unit of the calibration module.

FIG. 11 is an electric circuit diagram showing a delay control unit of the slave timing module.

FIG. 12 is an electric circuit diagram showing a voltage-controlled delay unit of the slave timing module.

[Explanation of symbols]

10, 20 master timing modules 11, 11 ', 211, 212,. . . 2N slave timing module 111 phase selection multiplexer 22 calibration module 23 demultiplexer 3 phase detection unit 31 OR gate 32 first multiplexer 33 second multiplexer 34, 35 input 36 output 4 phase measurement unit 41 digital counter 42 input 43 rank Phase difference pulse input 5 Phase compensation unit 50 Subtractor 51 Register 53 Output 6 Delay control unit 60 Charge pump circuit 62 Input 63 Output 7 Voltage controlled delay unit 70 Voltage controlled variable gain buffer 701 Output 71 Multiplexer 74 Output TM _core Timing pulse signal TM _fin Fine timing pulse signal

Continuing from the front page (72) Inventor Lin Shi Hong 281-9, Guangfu Village, Lianyingang, Tainan County, Taiwan (72) Inventor Yang Jinmin 267 Kogang-ri, Kominato-ku, Kaohsiung, Taiwan F-term (reference) 2G132 AA01 AG08 AL15 AL16 5J106 AA03 BB05 CC21 CC59 DD10 DD17 DD32 DD38 DD46 GG14 JJ07 KK05 KK36 5K047 AA01 AA15 GG03 GG09 GG11 MM36 MM60 MM63

Claims (7)

[Claims] An external reference clock is received and said reference clock is received.
From the lock to the coarse timing pulse signal (TM_core)
Master timing module adapted to generate
From the master timing module (20).
Imming pulse signal (TM_coreAbove) to receive
Electrically connected to the master timing module
The coarse timing pulse signal (TM_core) From fine
Timing pulse signal (TM_finLike to generate
Operable slave timing module (211)
The master timing module (20) and the thread
Electrically connected to the slave timing module (211)
And the coarse timing pulse signal (TM_{c oa})When
The fine timing pulse signal (TM_fin) And received
The coarse timing pulse signal (TM_core)When
The fine timing pulse signal (TM _finBetween)
Is determined, and the phase difference value and a predetermined phase difference value are determined.
Calibration module that generates a phase compensation signal corresponding to the difference between
A slave timing module (211).
Receiving the phase compensation signal from the calibration module (22)
And generates a delay voltage signal corresponding to the phase compensation signal.
A delay control unit (6) for causing the coarse timing pulse signal (TM_core) And above late
And the fine timing pulse signal
No. (TM_fin) To the delayed voltage signal
The corresponding phase delay is set by the coarse timing pulse signal (T
M_core) To introduce a voltage controlled delay unit
(7) A timing generator comprising: 2. The phase detection module according to claim 1, wherein the calibration module is configured to generate a phase difference pulse when the coarse timing pulse signal (TM _core ) and the fine timing pulse signal (TM _fin ) are in different logic states. A further feature comprising: a unit (3); and a phase measurement unit (4) that is electrically connected to the phase detection unit (3) and generates a phase difference value that matches a width of the phase difference pulse. The timing generator according to claim 1, wherein 3. The timing generator according to claim 2, wherein said phase detection unit further comprises an exclusive OR gate. 4. The timing generator according to claim 2, wherein said phase measuring unit further comprises a digital counter. 5. The calibration module (22) is further electrically connected to a register (51) for storing the predetermined phase difference value, and to the register (51) and the phase measurement unit (4). A subtractor (50), the subtracter (50) receiving the phase difference value from the phase measurement unit (4), the predetermined phase difference value from the register (51), and The timing generator according to claim 4, further comprising a phase compensation unit (5) for generating a signal. 6. A charge pump circuit (60) having an input (62) for receiving the phase compensation signal from the phase compensation unit (5) and an output (63). The timing generator of claim 1, further comprising a capacitor (C) connected across said output (63) of said charge pump circuit (60) for providing said delayed voltage signal. 7. The voltage-controlled delay unit (7).
Is the delay voltage signal and the coarse timing pulse signal (T
_Mcoa ) and a voltage-controlled variable gain buffer (70) having an output (701), and a capacitor (70) connected across the output (701) of the voltage-controlled variable gain buffer (70). C _L ) and a fixed gain output electrically connected to the output (701) of the voltage controlled variable gain buffer (70) and having an output (74) from which the fine timing pulse signal (TM _fin ) is obtained. The timing generator of claim 1, further comprising a buffer (72).