JP2002232380A - Concatenation signal processing method and apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, when an SDH(synchronous digital hierarchy) frame includes virtual container (VC-3)constituting a virtual concatenation, the arrival time of the VC-3 differs, depending on its transfer route and, to solve this, a phase adjuster must be installed in every virtual concatenation to result in a large circuit scale for these signal processors. SOLUTION: The apparatus comprises a phase adjuster for receiving MFI information of an arrival VC-3 and a VC-3 arrival interval measuring unit which decides whether a specified arrival interval of a VC-3 agreeing with the MFI is exceeded and holds the now arrival VC-3 as a reference VC-3, if the arrival interval exceeds a specified value. This is repeated for one cycle of MFI to write or read a VC-3 following the reference VC-3 in or from a memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to concatenation transmission used in synchronous digital hierarchy (SDH), and more particularly to a method and apparatus for processing a concatenation signal.

[0002]

2. Description of the Related Art In recent years, a synchronous digital hierarchy (SDH) has been newly proposed for unification of the B-ISDN standard, and the ITU-T recommendation G.264. 707 and the like specify details. Among them, the configuration of a transmission signal in which various signals are multiplexed as an SDH frame is called a synchronous transmission module (STM). For example, when described as STM-48, the multiplicity is 48 and 90 bytes × 48 × 9. It becomes a line frame configuration. FIG. 5 shows a virtual container (VC-
3) shows the structure of an STM-48 frame format in which 48 channels are multiplexed. The STM-48 frame is a VC-3 multiplexed with a section overhead 600 for transferring data for signal monitoring control and maintenance operation.
601 (A) for storing pointer information indicating the head of
U pointer) and a payload (information area) 604. The payload 604 includes VC-3 (602-1
602 to 48) are multiplexed in 48 channels. Each V
C-3 has a configuration of 85 bytes (87 bytes when two fixed values are included) × 9 rows, and the first column has a path overhead 60 for transferring data for signal monitoring control and maintenance operation.
5 and the remaining area is a virtual container for transmitting information. A predetermined position (H in the path overhead 605)
4 bytes) 603 includes VC-3 in the payload 604.
Are stored. A multi-frame indicator (MFI) indicating the position and the order relation of is stored. The MFI includes a code indicating which SDH frame among the SDH frames to which the data is mapped, to which the VC-3 belongs.

Here, the amount of a signal to be transmitted is one VC-
3 is not enough, a technique of combining a plurality of VC-3s, preserving the bit order structure, and securing one band is called virtual concatenation. 707
Stipulated. The VC-3 can also be constituted by a VC-4.

When data is mapped to two VC-3s, these two VC-3s are independently processed in a network, and therefore, two VC-3s are processed due to a processing delay in a device or a difference in a transfer path. 3 has a delay difference. For example, at the time of transmission, two VC-3s constituting virtual concatenation in the same STM are detected in different STMs on the receiving side. Therefore, a mechanism for absorbing the delay difference is required at the end of the virtual concatenation.

FIG. 6 shows a method of performing phase adjustment in each virtual concatenation when a plurality of virtual concatenations exist. The configuration includes a frame synchronization processing unit 600 for detecting the beginning of an STM frame in received data,
A pointer position information generation unit 601 for detecting a position (AU pointer 501) at which pointer information indicating the head of -3 is stored. At the subsequent stage, a pointer processing unit 603 that obtains information from the pointer position information generation unit 601 and detects pointer information indicating the head of each of the multiplexed VC-3s in the AU pointer 501 of the received STM frame; Recognize the head of each VC-3 and
An MFI position information generation unit 602 for detecting the position of the H4 byte in the path overhead 505 of C-3 is arranged. Further, at the subsequent stage, there is an MFI detection unit 604 for detecting MFI information added in VC-3 units from the detected pointer information in the H4 byte. Furthermore, the number of phase adjustment units 6 is equal to the number of virtual concatenations.
06-1 to 606-n and timers 607-1 to 607-
n, and each phase adjustment unit is provided with an MFI detection unit 60.
4 receives the MFI information added in units of VC-3. Each of the phase adjustment units corresponds to a specific virtual concatenation, and receives information of a specific VC-3 forming the specific virtual concatenation from the virtual container setting units 605-1 to 605-n. I have.

[0006] The phase adjustment unit 606-1 includes an MFI detection unit 6
It monitors whether the MFI of the VC-3 received from the server 04 matches the set value. When the matched data is received, the timer 607-1 is started to determine whether to receive data within a certain time which is the MFI of the VC-3 channel constituting the virtual concatenation and which matches the set value. To monitor. Within the above-mentioned fixed time, VC-3
If all of the channels have been received, the memory 60 is referenced based on the VC-3 channel at the time the timer was started.
9 is started to be written. If all of the VC-3 channels constituting the virtual concatenation are not received within a certain time, another VC among the set MFI values is used.
-3 Start a timer from the time of receiving channel 3 and monitor. When all the VC-3 channels constituting the virtual concatenation have been written into the memory 609, the write management unit 611 changes the read control unit 610.
The umbilical information is sent, and reading is started. The information about the VC-3 that constitutes the virtual concatenation is stored in the virtual container setting units 605-1 to 605-1.
From 5-n, the data is sent to the pointer processing unit 603 and the MFI detection unit 604, so that the irrelevant VC-3 (that is, does not constitute the virtual concatenation) is not accessed. The write management unit 611 also obtains the same information from the virtual container setting units 605-1 to 605-n, and determines whether the necessary VC-3 channel write processing has been completed.

[0007]

However, in the above-described virtual concatenation processing, as the number of virtual concatenations increases, it is necessary to provide the same number of phase adjustment units and timers as the number of virtual concatenations. There is a problem that it increases in proportion to the number of nations. An object of the present invention is to provide a processing method and apparatus for solving this problem.

[0008]

According to the present invention, there is provided a concatenation signal processing method comprising the steps of:
When receiving the H signal, the arrival time intervals of the virtual containers belonging to the same SDH frame and constituting the concatenation are sequentially measured, and when it is determined that this arrival time interval is longer than the predetermined time interval, the virtual Let the container be the reference virtual container,
The data of the reference virtual container and the data of the virtual containers that subsequently arrive at a time interval equal to or shorter than the predetermined time interval are stored in the memory in this order.

Here, the arrival time of the virtual container is measured at least for the maximum frame that can be expressed by the MFI value. The predetermined time interval is a value larger than the maximum value of the difference between the delays generated between the virtual containers constituting the concatenation in the process of transmitting the SDH signal.

Next, the concatenation signal processing apparatus according to the present invention comprises means for receiving an SDH frame and detecting a multi-frame indicator for a virtual container constituting the SDH frame, and multi-frame indicator information output from the means. A phase adjustment unit that determines whether the arrival time interval of the corresponding virtual container is larger than a predetermined value and determines the currently arriving virtual container as the reference virtual container when the corresponding virtual container is longer than a predetermined value. An arrival interval measuring unit for measuring an arrival time interval of the virtual container according to an instruction of the phase adjusting unit; a memory for holding data of the virtual container; and a memory for writing data of the virtual container to the memory by a control signal from the phase adjusting unit. Read from memory Comprising a to write and read means.

[0011] The phase adjustment unit may include a multi-frame indicator comparison unit that determines whether the multi-frame indicator information output by the multi-frame indicator detection unit matches a preset value, and a virtual container of a concatenation. A reference virtual container determination unit that determines a virtual container that arrives at a time interval greater than a predetermined value as a reference, and a memory that holds multiframe indicator information of a virtual memory determined as the reference virtual container by the determination unit.

According to these inventions, the circuit configuration can be reduced in scale.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of a configuration for executing the present invention. The configuration and functions up to the detection of multi-frame indicator (MFI) information are basically the same as the configuration in FIG. That is, it includes a frame synchronization processing unit 100 for detecting the head of the STM frame in the received data, and a pointer position information generation unit 101 for detecting a position where pointer information indicating the head of each VC-3 is stored. Pointer processing unit 10 for detecting pointer information indicating the head of each of the multiplexed VC-3s in the AU pointer
3 and the beginning of each of the VC-3s.
MFI position information generation unit 102 that generates information indicating the position of the H4 byte in the path overhead of the MFI. Further, it has an MFI detection unit 104 for detecting MFI information added in VC-3 units from the information.

In the configuration shown in FIG. 1, a phase adjustment unit 107 is provided downstream of the MFI detection unit 104, and an arrival interval measurement unit 108 connected to the phase adjustment unit 107 is provided. The phase adjustment unit 107 determines a reference VC-3 from the VC-3s constituting the virtual concatenation, and determines the arrival interval measurement unit 10.
8 measures the arrival time interval of each VC-3. It also has virtual container setting units 105-1 to 105-n, and the setting units are VCs that constitute virtual concatenation.
-3 information, and V for which phase adjustment is necessary.
The C-3 information is generated by the effective channel setting generation unit 106, and is notified to the pointer processing unit 103, the MFI detection unit 104, and the phase adjustment unit 107 (actually, the reference VC-3 determination unit 202). A write control unit 109 and a write management unit 111 are arranged downstream of the phase adjustment unit 107. The write control unit 109 receives the write permission signal from the phase adjustment unit 107 and controls the writing of data to the memory 110 for each multiplexed VC-3 channel. The write management unit 111 determines a readable VC-3, and reads data from the memory 110.
Output the result to 2.

FIG. 2 shows a specific configuration example of the phase adjustment unit 107.
Is shown in The phase adjustment unit 107 is provided in the MFI detection unit 104
Of the detected VC-3 MFI information and the preset MF
An MFI comparison unit 200 that compares I values (here, numbers commonly assigned to VC-3s that constitute virtual concatenation in the same SDH frame, for example, “0”)
And a reference VC that determines an arrival time interval of the VC-3 having the MFI that matches the set value and determines the reference VC-3.
-3 determining unit 202, a reference VC-3 management memory 203 for managing the reference VC-3, and an error monitoring unit 201 for monitoring whether or not the phase is shifted after the completion of the phase adjustment.
Having. In addition, when the MFI information of the detected VC-3 matches the preset MFI value, the measuring unit 108 measures how much time has elapsed since the previous match.

The operation of the configuration shown in FIGS. 1 and 2 will be described below. The MFI detector is a phase adjuster 107
The process up to sending the MFI information to the server is as described above. In FIG. 1, when the frame synchronization processing unit 100 detects the head bit of an SDH frame (for example, STM-48), the pointer position information generation unit 101 determines the head of the multiplexed VC-3 at a fixed position from the frame head. The pointer processing unit 103 generates information indicating the position of the pointer information to be indicated.
Send to The information indicating the position of the pointer information can be determined, for example, by operating a counter and using a predetermined counter value. The pointer processing unit 103 detects pointer information based on information indicating the position of the pointer information from the pointer position information generation unit 101. MFI position information generator 10
2 receives the pointer position information and the head information of VC-3,
MFI stored at a fixed position from the top of each VC-3
Information indicating the position of the information is generated and sent to the MFI detection unit 104. The position information of the MFI can be generated by the counter similarly to the information indicating the position of the pointer information. MF
The I detection unit 104 detects MFI information based on the information sent from the MFI position information generation unit 102, and
Send to 07.

In the phase adjusting section 107, the MFI comparing section 20
0 receives this MFI information and compares it with a preset MFI set value (for example, the above-mentioned “0”). The phase adjusting unit 107 starts the phase adjusting operation and, at the same time, the arrival interval measuring unit 1
08 to start measurement. Upon receiving the match signal from MFI comparing section 200, reference VC-3 determining section 202 determines the arrival interval measured by arrival interval measuring section 108 (that is, VC-3 which has the same MFI as the currently arriving VC-3 and the immediately preceding VC-3). Is determined to be larger than the specified value. This specified value may be set to be larger than the maximum value of the delay difference of the VC-3 forming the virtual concatenation, for example. The maximum value of the delay difference of the VC-3 is the maximum value of the deviation between the VC-3s constituting the virtual concatenation that occurs in the transfer process on the network. If the arrival interval is larger than the specified value, the currently arrived VC-3 is used as a reference for writing to the memory.
MFI specifying the reference VC-3 in the management memory 203
At the same time, and notifies the arrival interval measuring unit 108 of the start of the next measurement. At this time, the VC-3 arriving earlier is stored in the memory 110 because it needs to be delayed.
If the arrival interval is less than or equal to the specified value, the arrival interval measuring unit 108 is notified only of the start of the next measurement.

After starting the phase adjustment, a series of these processes is performed for one cycle of MFI (SDH on which data is mapped).
By the number of frames) to obtain the reference VC-
3 is obtained. Note that these processes are performed a plurality of times, and the reference VC-3 is determined only when the reference VC-3 is the same in all the times. When the reference VC-3 is determined, the reference VC-3 and subsequently the MF
The write control unit 109 is given permission to write data to the memory 110 for the VC-3s constituting the virtual concatenation in the order in which I match. When the next reference VC-3 arrives, all the VC-3s received up to that point have been written to the memory 110.
This is notified to the write management unit 111. Read control unit 1
Reference numeral 12 reads data from the memory 110 in the order of the multiplexed VC-3. Whether the reading is valid is determined based on information managed by the writing management unit 111. That is, it is determined that reading is valid for the VC-3 for which writing has been completed. Error monitoring unit 201
Monitors the MFI for each VC-3 unit and detects a phase shift that may occur again after the phase adjustment is completed. When this phase shift is detected, the above-described phase adjustment processing is performed only on the VC-3s constituting the virtual concatenation to which the detected VC-3 belongs.

For a VC-3 that does not constitute a virtual concatenation, a write permission is issued immediately upon arrival of the data, and the data is written to the memory 110.

Next, the above operation will be described using a specific example.
FIG. 3 shows a state where 8-multiplexed VC-3 (STM-8) arrives. In FIG. 3, A to H indicate channels of the VC-3 multiplexed by 8, and A0 indicates that data whose MFI is “0” has arrived. The set value of the MFI comparison is “0”. The combination of the VC-3 channels constituting the virtual concatenation is A and C, B and D,
Assume that there are four, E and F, and G and H. Where the reception interval of the data whose MFI is “0” is equal to or greater than the specified value, the interval is D0-E0, F0-G0, and H0-A0. For example, when the phase adjustment is started at 300 in the figure, a counter (arrival interval measuring unit) is activated to measure an interval until data such that the MFI is “0” is received. First, when C0 is received, the counter (arrival interval measuring unit) is reset because the interval is equal to or less than the set specified value, and the next M
The reception of data whose FI is “0” is monitored. Next, D0 is received. Since the interval between C0 and D0 is equal to or smaller than a specified value, the same process as when C0 arrives is performed.
Next, when E0 is received, since the interval between D0 and E0 is equal to or greater than the specified value set in this case, the VC-3 channel E is stored as the reference VC-3. When the same processing is repeated every time data having an MFI of “0” is received, the reference VC-3 is detected to be E, G, and A by repeating the MFI cycle. In this specific example, writing to the memory is started from A0 of 301 in the figure, and when writing is completed at D0 of 302, reading of A to D becomes possible. At this time, A and C and B which constitute the virtual concatenation
And D are in a state where the phases from A to D are aligned with respect to A.

Next, another example of the present invention will be described with reference to the drawings. The write completion manager 111 of FIG. 1 includes a write channel manager 400 and a read permission flag generator 401 as shown in FIG. The write channel management unit 400
It receives and manages the channel information whose writing to the memory has been started from the phase adjustment unit 107. Read permission flag generator 4
No. 01 compares the channel information for which writing has started with the settings 105-1 to 105-n of the VC-3 channel constituting the virtual concatenation. If all of the VC-3 channels constituting a certain virtual concatenation have started writing, a read permission flag is generated and notified to the read control unit 112. In this example, the read control unit 11 does not recognize the set that constitutes the virtual concatenation until the phase is adjusted and the data is written to the memory.
2, when reading from the memory, reading can be started when writing of all VC-3 channels constituting a certain virtual concatenation is completed,
The time stored in the memory, that is, the delay time can be reduced. For example, in the above specific example, A to D
After the writing is completed, reading of A to D is started. The other embodiment utilizes the fact that A and C and B and D constitute a virtual concatenation, and starts reading when A and C are written to the memory, thereby waiting for writing of D. Since the reading can be performed without any delay, the delay time can be reduced.

In the above description, the example of the VC-3 is described, but the same can be applied to the VC-4.

[0023]

According to the present invention, a circuit for performing phase adjustment is required for each set of VC-3s constituting a virtual concatenation. In contrast, the present invention has an MFI that matches a preset value. The reception of data is monitored, and if the reception interval between the currently received VC-3 and the VC-3 received immediately before is longer than a predetermined value, the phase adjustment is performed based on the currently received VC-3. Therefore, the circuit scale of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a concatenation signal processing device according to the present invention.

FIG. 2 is a block diagram illustrating an example of a phase adjustment unit of the concatenation signal processing device.

FIG. 3 is a diagram showing an example of an arrival order and intervals of VC-3.

FIG. 4 is a block diagram illustrating an example of a write management unit.

FIG. 5 is a diagram showing a configuration of a synchronous transmission module (STM).

FIG. 6 is a block diagram showing a configuration example of a conventional concatenation signal processing device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 frame synchronization processing unit 101 pointer position information generation unit 102 MFI position information generation unit 103 pointer processing unit 104 MFI detection unit 106 effective channel setting generation unit 107 phase adjustment unit 108 arrival interval measurement unit 109 write control unit 110 memory 111 write Management unit 112 Read control unit 200 MFI comparison unit 202 Reference VC-3 determination unit

Claims (9)

[Claims] When receiving an SDH signal transmitted by the SDH transmission method, the arrival time intervals of virtual containers belonging to the same SDH frame and constituting a virtual concatenation are sequentially measured, and the arrival time interval is determined to be a predetermined value. When it is determined that the virtual container is longer than the time interval, the virtual container arriving at that time is set as a reference virtual container, and the data of the reference virtual container and the data of the virtual containers that subsequently arrive at a time interval equal to or less than the predetermined time interval are stored in this order. A concatenation signal processing method characterized by storing the information in a concatenation signal. 2. The concatenation signal processing method according to claim 1, wherein the measurement of the arrival time of the virtual container is performed for at least a maximum frame that can be represented by an MFI value. 3. The concatenation signal processing method according to claim 1, wherein the predetermined time interval is a value larger than a maximum value of a delay difference generated between virtual containers constituting the virtual concatenation in a process of transmitting the SDH signal. . 4. A means for receiving an SDH frame and detecting a multi-frame indicator for a virtual container constituting a virtual concatenation in the SDH frame, the multi-frame indicator information output from the means and a preset value A phase adjuster that determines the currently arrived virtual container as the reference virtual container when the interval of the arrival time of the corresponding virtual container is larger than a predetermined value; An arrival interval measuring unit for measuring an arrival time interval of a virtual container, a memory for holding data of the virtual container, and writing of data of the virtual container to and from the memory according to a control signal from the phase adjusting unit A concatenation signal processing device comprising a reading unit. 5. The concatenation signal processing device according to claim 4, further comprising: means for detecting the multi-frame indicator and notifying the phase adjustment unit of information about the virtual container constituting the concatenation. 6. A phase adjusting unit comprising: a multi-frame indicator comparing unit that determines whether the multi-frame indicator information output from the multi-frame indicator detecting unit matches a preset value; and a virtual container of a concatenation. A reference virtual container determining unit that determines a virtual container arriving at a time interval greater than a predetermined value as a reference, and a memory that retains multi-frame indicator information of a virtual memory determined as the reference virtual container by the determining unit. Item 5. The concatenation signal processing device according to Item 4. 7. The concatenation signal processing device according to claim 4, wherein the multi-frame indicator information determined to be coincident by the multi-frame indicator comparison unit is a display of an SDH frame to which the arriving virtual container belongs. 8. The writing / reading unit receives a signal from a phase adjustment unit, and writes a virtual container data to the memory in response to a signal from the phase adjustment unit, and notifies the writing control unit of a write of the virtual container data from the writing control unit. The concatenation signal processing device according to claim 4, further comprising: a write management unit that receives the data; and a read control unit that reads data from the memory based on information held by the write management unit. 9. The writing control unit, wherein writing to the memory is started and receiving channel information from the phase adjusting unit, and receiving the information about a virtual container forming a concatenation, the writing control unit receiving the information. 9. The concatenation signal processing device according to claim 8, further comprising: a read permission signal generation unit that sends a read permission signal to a read control unit based on the information held by the read channel management unit.