JP2002223076A - Multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board, with which an electric characteristic between an electronic component integrally included in a substrate and an IC chip or the like mounted on a first main surface, and the electronic component and the IC chip can be normally operated at high speed. SOLUTION: This multilayer wiring board 1 include a substrate 2 having insulating layers 3, 4, 5 and wiring layers 6, 7, which are alternately laminated, a front surface 4a and a rear surface 5a, a throughhole 8, which penetrates between the front surface 4a and the rear surface 5a of this substrate 2, a chip capacitor (electronic component) 10 filled in the throughhole 8 via an embedded resin 9, and built-up layers BU1, BU2, which are formed above the front and rear surfaces 4a, 5a of the substrate 2 and include resin insulating layers 18, 24, 19, 25 and wiring layers 22, 23. An electrode 11 of the chip capacitor 10 and the wiring layer 16 are connected in the front surface 4a (front surface 9c of the resin insulating layer 9). A solder bump (terminal) 28 protruded higher than a first main surface 26 is formed on the wiring layer 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board in which electronic components are embedded in through holes and the like of a board via an embedded resin.

[0002]

2. Description of the Related Art In order to cope with recent miniaturization of wiring boards and high-density wiring in the boards, not only electronic parts such as IC chips are mounted on a first main surface of the wiring board, but also the size of the board is reduced. There has been proposed a multilayer wiring board in which electronic components are built. For example, the multilayer wiring board 7 shown in FIG.
0 is the front and back surfaces 72 and 7 of the insulating substrate (core substrate) 71
A plurality of chip-shaped electronic components 78 are incorporated in a through hole 76 penetrating between the three through a buried resin 77. As shown in FIG. 8, such an electronic component 78 is
It has a plurality of electrodes 79a and 79b projecting downward symmetrically. The electrodes 79a and 79b are provided on the substrate 71.
Are individually connected to the wiring layers 80 and 81 formed on the front and back surfaces 72 and 73.

[0003] Further, as shown in FIG.
A through-hole conductor 75 and a filling resin 75a are provided in a plurality of through-holes 74 penetrating between the front and back surfaces 72 and 73.
Are individually formed, and the through-hole conductor 75 is individually connected to the wiring layers 80 and 81 at the upper and lower ends. On the surface 72 of the substrate 71 and the wiring layer 80, a resin insulating layer 82,
88, 94, wiring layers 86, 92, and via conductors 84,
90 are formed. In the uppermost insulating layer (solder resist) 94, a plurality of solder bumps 96 penetrating therethrough and protruding above the wiring layer 92 above the first main surface 94a are formed. Such bump 9
8, the IC chip (semiconductor element) 98 mounted on the first main surface 94a and terminals are individually connected as shown in FIG.

[0004] Further, as shown in FIG. 8, resin insulating layers 83, 8 are formed on the back surface 73 of the substrate 71 and under the wiring layer 81.
9, 95, wiring layers 87, 93, and via conductors 85, 9
1 is formed. The lowermost insulating layer (solder resist) 95 has a plurality of openings 97 formed on the second main surface 95a side, and the wirings 99 extending from the wiring layer 93 and exposed in the respective openings 97 are formed on the front surface. N
It is coated with i and Au plating and is used as a terminal for connection to a motherboard (not shown) on which the wiring board 70 itself is mounted.

[0005]

The multilayer wiring board 70
8, between the electrode 79a of the electronic component 78 incorporated in the substrate 71 and the IC chip 98 mounted on the first main surface 94a, wiring layers 80, 86, 92 and via conductors 84 are provided. , 90 and solder bumps 96 are interposed. For this reason, by increasing the loop inductance in such a conduction path, switching noise and crosstalk noise are likely to occur,
There is a problem that the electronic component 78 and the IC chip 98 may malfunction. The present invention solves the above-described problems in the conventional technology, improves the electrical characteristics between an electronic component incorporated in a substrate and an IC chip mounted on a first main surface, and improves such an electronic component. It is an object of the present invention to provide a multilayer wiring board capable of operating an IC chip or the like normally and at a high speed.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an electronic component mounted on a board and mounted on an electronic component.
The present invention has been made with an idea that a conduction path between the C chip and the like is made as short as possible. That is, the multilayer wiring board of the present invention has a structure in which insulating layers and wiring layers are alternately laminated and has a front surface and a back surface, and a region between the front surface and the back surface of the substrate (straddling a plurality of insulating layers). ) Through holes,
Alternatively, a concave portion that is opened on the front or back surface (to straddle a plurality of insulating layers), an electronic component incorporated through the embedded resin in the through hole or the concave portion, and at least the front and back surfaces of the substrate A build-up layer formed on one side and including a resin insulating layer and a wiring layer; and an electrode of the electronic component and a wiring layer of the build-up layer are connected on a surface of the substrate. It is characterized by the following. Further, the build-up layer above the surface of the substrate is provided with terminals for connecting a wiring layer and a semiconductor element such as an IC chip mounted on the first main surface of the build-up layer in the vicinity of the first main surface. The present invention also includes a multilayer wiring board having the above.

According to these, when the overall thickness is substantially the same and the number of internal wiring layers is the same, a single substrate
The conduction path between the electrodes of the electronic component and the IC chip mounted on the first main surface can be made as short as possible, as compared with the multilayer wiring board 70 shown in FIG. . As a result, the loop inductance in such a conduction path can be reduced, so that electrical characteristics such as switching noise and crosstalk noise can be reduced. Therefore, it is possible to provide a multilayer wiring board that can operate the built-in electronic components and the mounted IC chip normally and at a high speed. In this specification, the surface of the substrate refers to the surface of the insulating layer or the embedded resin, and the back surface of the substrate refers to the back surface of the insulating layer or the embedded resin.

[0008] In addition, an insulating layer and a wiring layer are alternately laminated, and a substrate having a front surface and a back surface, and penetrating (straddling a plurality of insulating layers) between the front surface and the back surface of the substrate. Through-holes, or recesses that open on the front or back surface (to straddle a plurality of insulating layers), electronic components built-in via the embedded resin in the through-holes or recesses, the surface of the substrate and A build-up layer formed above at least one of the back surfaces and including a resin insulating layer and a wiring layer, wherein the electrodes of the electronic component and the wiring layer of the build-up layer are formed of embedded resin in the substrate. It is also possible to include a multilayer wiring board connected at the surface in the present invention. In addition, the present invention can include a multilayer wiring board in which wiring layers and insulating layers are alternately laminated on the front and back surfaces of the insulating layer body. The insulating layer main body is a so-called core substrate, and by using such a multi-layer substrate, it is possible to increase the density of wiring and to perform normal operations of built-in electronic components and the like.

The through hole is formed by laser processing or drilling a substrate having a multilayer structure. on the other hand,
The concave portion may be formed by forming an insulating layer or a wiring layer forming a substrate having a multilayer structure by router processing using an end mill, or by laminating an insulating layer previously processed by router or laser processing with another insulating layer or wiring layer. Can be formed. The electronic components include passive components such as capacitors, inductors, resistors, and filters, and low-noise amplifiers (L
NA), transistors, semiconductor elements, active components such as FETs, SAW filters, LC filters, antenna switch modules, couplers, diplexers, and the like, or chips of these, but are not limited thereto. Further, among them, different kinds of electronic components may be incorporated in the same through-hole or recess. Further, the electronic component includes a form having an electrode only on one of the front surface and the back surface of the substrate.

[0010] In addition, the present invention can include a wiring board in which the through hole or the concave portion is substantially rectangular in plan view, and a round surface or a chamfer is formed in a corner between side walls thereof. is there. In this case, the adhesion between the substrate and the buried resin in the corner portion between the side walls of the through hole or the concave portion can be improved and stabilized, so that the generation of a gap or a crack near the corner can be reliably prevented. be able to. In addition, a round surface or a chamfer may be formed at a corner between the side wall and the bottom surface in the concave portion.

Further, the present invention can include a wiring substrate in which an organic compound (coupling agent) is applied in advance to the side wall of the through hole or the side wall and the bottom surface of the concave portion. Also in this case, it is possible to further improve the adhesion between the substrate and the embedded resin. The organic compound (coupling agent) includes a titanium-based, aluminum-based, or silane-based organic compound, or a mixture of these organic compounds. Thus, the adhesion between the substrate and the embedding resin at the interface between the substrate and the embedding resin can be further ensured. The above mixture includes titanium and aluminum, titanium and silane, aluminum and silane, titanium and aluminum and silane, titanium and another titanium, aluminum and another aluminum, and silane. And another silane system,
Alternatively, a type based on a combination of three or more of these is included.

[0012]

Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross section of a main part in a multilayer wiring board 1 according to one embodiment of the present invention. As shown in FIG. 1, the multilayer wiring board 1 includes a substrate 2 composed of insulating layers 3, 4, 5 and wiring layers 6, 7 located therebetween, and wirings formed on the front surface 4a and under the rear surface 5a. Layer 16,
22, 17, 23, and resin insulating layers 18, 24, 1
9 and 25, which are build-up layers BU1 and BU2. The thickness of the wiring layer 16 and the like is about 15 μm, and the thickness of the resin insulating layer 18 and the like is about 30 μm. The substrate 2 has a substantially square shape in plan view and an overall thickness of about 0.8 mm, and is laminated on an insulating layer (also referred to as a core substrate or an insulating layer body) 3 made of an epoxy resin containing glass cloth, and on the upper and lower sides thereof. It has a multilayer structure composed of insulating layers 4 and 5 made of epoxy resin containing inorganic filler such as silica filler and copper wiring layers 6 and 7 located between them.

Further, as shown in FIG. 1, a through hole 8 having a substantially square shape in plan view and a side of 12 mm is formed by drilling or laser processing the central portion of the substrate 2. The surface roughness of the side wall of the through hole 8 is in the range of 0.5 to 5.0 μm in center line average roughness Ra and in the range of 5.0 to 30.0 μm in ten point average roughness Rz. It is desirable to enter. Therefore, after drilling or the like, the through hole 8
If necessary, a chemical roughening treatment with potassium permanganate or chromic acid is performed on the side wall of the metal. Thereby, the adhesion between the substrate 2 and the embedding resin 9 described later can be improved.

Further, an organic compound (coupling agent: an organic compound composed of any of titanium, aluminum and silane, or a mixture of these organic compounds) is further applied to the side wall of the through hole 8. You may. The organic compound includes an organic compound made of any of titanium, aluminum, and silane, or a mixture of these organic compounds. Further, it is desirable that the thickness of the organic compound is about 0.5 μm or less (however, 0 is not included) and the organic compound is coated. The reason why the thickness is set to 0.5 μm or less is that if the thickness is more than 0.5 μm, a jelly-like lump is formed on the surface, and the adhesion and the waterproofing effect of the organic compound are reduced. More preferably, the organic compound has a thickness of about 0.2 μm.
It is desirable that the film be covered with a film of m or less (excluding 0). Thereby, jelly-like lump hardly occurs on the surface, and further adhesiveness can be obtained. Such an organic compound may be coated on the surface of the chip capacitor (electronic component) 10 built in the through hole 8 together with the side wall of the through hole 8 and the front and back surfaces 4a and 5a of the substrate 2.

Further, a chamfered or rounded surface may be formed at a corner between the side walls of the through hole 8. Accordingly, even if the embedded resin 9 in which the chip capacitor 10 is embedded is heated after the defoaming treatment, stress concentration is less likely to occur in the corner of the through hole 8, and the surface roughness of each side wall including the chamfer or the round surface is reduced. Together with this, the adhesion between the substrate 2 and the embedded resin 9 can be further enhanced.

A plurality of chip capacitors (electronic components) 10 are built in the through holes 8 of the substrate 2 via an epoxy-based embedded resin 9 containing an inorganic filler such as silica filler. The volume expansion coefficient of the embedded resin 9 is 4
It is 0 ppm / ° C. or lower, preferably 30 ppm / ° C. or lower, more preferably 15 ppm / ° C. or lower, and its lower limit is 10 ppm / ° C. or higher. As a result, it is possible to reduce the stress concentration caused by the difference in the coefficient of thermal expansion between the electronic component 10 built in the multilayer wiring board 1 and the IC chip (semiconductor element) mounted on the surface of the wiring board 1, Helps prevent cracks. Incidentally, the inorganic filler is not particularly limited, but crystalline silica, fused silica,
Alumina, silicon nitride, or the like is used.

The chip capacitor 10 has a plurality of electrodes 11 and 12 symmetrically protruding from the upper and lower ends on both sides and located on the front surface 4a or the back surface 5a of the substrate 2.
The chip capacitor 10 is a ceramic capacitor in which, for example, a dielectric layer containing barium titanate as a main component and a Ni layer serving as an internal electrode are alternately laminated, and is 3.2 m in length.
It has a size of mx 1.6 mm x 0.7 mm. As shown in FIG. 1, a plurality of through-holes 13 are formed around the through-holes 8 so as to penetrate between the front and rear surfaces 4a and 5a of the substrate 2 with a required space, and the inside is made of copper plating. A through-hole conductor 14 and a filling resin 15 containing silica filler are formed respectively. Each of the through-hole conductors 14 is connected to the wiring layers 6 and 7 of the substrate 2 in the middle. Instead of the filling resin 15, a conductive resin containing a large amount of metal powder or a non-conductive resin containing metal powder may be used.

As shown in FIG. 1, a wiring layer 16 made of copper plating and a resin insulating layer 18 made of epoxy resin containing silica filler are provided on the surface 4a of the substrate 2 and the surface 9c of the embedded resin 9. Are formed. The wiring layer 16 includes the electrode 11 of the chip capacitor 10 and the through-hole conductor 14.
Is connected to the upper end of As shown in FIG. 1, a plurality of filled via conductors 20 are provided at predetermined positions in the insulating layer 18.
Are formed, and the upper ends of the via conductors 20 and the insulating layer 18 are formed.
The wiring layer 22 is formed on the substrate. In the present embodiment, the surface of the substrate 2 refers to the surface 4a of the insulating layer 4 or the surface 9c of the embedded resin 9.

On the wiring layer 22, a solder resist layer
(Insulating layer) 24 and a plurality of solder bumps penetrating therethrough and projecting higher than the first main surface 26 (IC connection terminals (Pb−
Sn-based, Sn-Ag-based, Sn-Sb-based, Sn-Zn-based, etc.) 28 are formed. The wiring layers 16 and 22 and the resin insulating layers 18 and 24 form the build-up layer BU1. Further, the solder bumps 28 are connected to the first main surface 26.
It is individually connected to connection terminals (not shown) projecting from the bottom surface of an IC chip (semiconductor element) 29 mounted thereon. still,
Around the connection terminals of the IC chip 29 and the solder bumps 28, the IC chip 29 and the first
An underfill material (not shown) is filled between the main surface 26 and the main surface 26.

As shown in FIG. 1, a wiring layer 17 made of copper plating and a resin insulating layer 19 made of epoxy resin containing silica filler are also formed under the back surface 5a of the substrate 2 and the back surface 9b of the embedded resin 9. Have been. The wiring layer 17 includes the electrode 12 and the through-hole conductor 14 of the chip capacitor 10.
Is connected to the lower end. In this embodiment, the back surface of the substrate 2 refers to the back surface 5 a of the insulating layer 5 or the embedded resin 9.
Back 9b. Further, a plurality of filled via conductors 21 are formed at predetermined positions of the resin insulating layer 19, and a wiring layer 23 is formed below the lower end of the via conductor 21 and under the insulating layer 19. Under the wiring layer 23, a solder resist layer (insulating layer) 25 is formed, and the wiring 27 in the wiring layer 23 exposed in the opening 25b opened to the second main surface 25a side.
Is coated with Ni and Au plating on its surface, and serves as a connection terminal to a motherboard such as a printed board (not shown) on which the wiring board 1 itself is mounted. The above wiring layer 1
The layers 7, 23 and the resin insulating layers 19, 25 form a build-up layer BU2. The upper and lower wiring layers 16 and 17 sandwiching the substrate 2 conduct through the through-hole conductors 14 and also conduct through the electrodes 11 and 12 of each chip capacitor 10.

According to the multilayer wiring board 1 described above, a wiring is provided between the electrode 11 of the chip capacitor 10 built in the through hole 8 of the board 2 and the IC chip 29 mounted on the first main surface 26. A relatively short conduction path consisting of the layers 16,22, via conductors 20, and solder bumps 28 is interposed. For this reason, when the overall thickness is substantially the same and the number of wiring layers is the same, the multilayer wiring board 1 has more loops than the conventional multilayer wiring board 70 shown in FIG. The inductance is reduced. As a result, the electrical characteristics such as the occurrence of switching noise and crosstalk noise are reduced, so that the chip capacitor 10 and the IC chip 29 can operate normally and at high speed. Moreover, since the chip capacitor 10 is incorporated in the multilayered substrate 2, the core substrate 3
The wiring layers 6 and 7 are thinned to less than
, It is possible to easily cope with the demand for increasing the density of wiring and reducing the size of the whole.

The insulating layers 4 and 5 of the substrate 2 may be formed with via conductors for connecting between the wiring layers 6 and 16 or between the wiring layers 7 and 17. In the present embodiment, the via conductor is not limited to the filled via conductor 20 or the like, but may be a conformal via conductor that is not completely filled with the conductor. According to the structure of the substrate 2, as shown in FIG. 1, since the through-hole conductor 14 penetrates the insulating layers 4 and 5, the via conductors 20 and 21 are formed immediately above (upper / lower in FIG. 1). Since it becomes possible, the portion of the through-hole conductor 14
It is not necessary to form a filled via conductor in the (penetrating portions of the insulating layers 4 and 5) to form a stacked via (stacked via) structure. As a result, the filled via conductors are separated from the insulating layers 4 and 5.
It is not necessary to form the vias, and the cost of forming vias can be reduced.

Referring to FIG. 2 to FIG.
The main manufacturing steps will be described. As shown in FIG.
A core substrate made of glass-epoxy resin having a thickness of 0.45 mm and having copper foils 3 a and 3 b having a thickness of 16 μm on the front and back surfaces.
(Insulating layer) 3 is prepared. Next, after an etching resist (not shown) having a predetermined pattern is formed on the copper foils 3a and 3b, etching (a known subtractive method) is performed. As a result, wiring layers 6 and 7 having a predetermined pattern are formed on the front and back surfaces of the core substrate 3 as shown in FIG. Next, after the front and back surfaces of the core substrate 3 and the wiring layers 6 and 7 are roughened, an epoxy resin film having a thickness of 600 μm and containing silica filler is bonded thereon by thermocompression bonding. As a result, as shown in FIG.
The insulating layers 4 and 5 are formed above and below. Thereby, the substrate 2 having a multilayer structure is obtained.

Further, as shown in FIG. 2C, a predetermined position is irradiated with a laser Ls (CO ₂ laser in this embodiment) from the insulating layer 4 side of the substrate 2. As a result, as shown in FIG. 2D, a plurality of through holes 13 having a diameter of 350 μm were formed on the substrate 2.
Formed between the front and back surfaces 4a and 5a. next,
Electroless copper plating and electrolytic copper plating are applied to the inner wall of each through hole 13 and the front and back surfaces 4a and 5a of the insulating layers 4 and 5. Such plating is performed on a plurality of product units (multilayer wiring board 1) in a multi-panel panel including the board 2. As a result, as shown in FIG. 3A, a through-hole conductor 14 having a thickness of 18 μm is formed along the inner wall of each through-hole 13 and the insulating layers 4 and 4 are formed.
The copper plating layers 4b and 5b are formed on the front and back surfaces 4a and 5a of FIG. Further, as shown in FIG. 3B, a hollow resin inside the through-hole conductor 14 is filled with a filling resin 15.

Further, as shown in FIG. 3C, a central portion of the substrate 2 is drilled to form a through hole 8 of 12 mm long × 12 mm wide. At this time, a chamfer or a round surface may be formed at the corner between the side walls of the through hole 8 at the same time. By subjecting the side wall of the through-hole 8 to a chemical roughening treatment as necessary, the surface roughness is in the range of 0.5 to 5.0 μm in center line average roughness Ra, and the ten-point average. The roughness Rz may be in the range of 5.0 to 30.0 μm. Further, an organic compound is applied to the side wall of the through hole 8.
(Coupling agent) may be applied. Next, as shown in FIG. 3C, the substrate 2 is rotated by 180 °, and the front and back surfaces 4a,
5a is turned upside down, and on the surface 4a side of the through hole 8,
The tape T is attached across a plurality of product units (multilayer wiring board 1) in the multi-cavity panel including the board 2. The adhesive surface of the tape T faces the through hole 8 side.

Next, as shown in FIG. 4A, a plurality of chip capacitors 10 are inserted into the through holes 8 using a chip mounter (not shown),
The zero electrode 11 is adhered to a predetermined position on the adhesive surface of the tape T. As shown, the end surfaces of the electrodes 11 and 12 of each chip capacitor 10 are
a, 5a. In this state, FIG.
As shown in the figure, from the back surface 5a side of the substrate 2 into the through hole 8,
After filling the melted embedding resin 9 containing an epoxy resin as a main component, a defoaming treatment and a curing treatment of heating to about 100 ° C. and holding for about 60 minutes are performed. Next, the raised back surface 9a of the embedded resin 9 is flattened by, for example, buffing. As a result, as shown in FIG. 4C, a flat back surface 9b from which the electrode 12 of each chip capacitor 10 is exposed is formed. Also, as shown, when the tape T is peeled off,
The electrode 11 of each chip capacitor 10 is exposed on the surface 9c of the embedded resin 9. If the surface 9c is also leveled in the same manner as described above, each electrode 11 can be reliably exposed.

Further, as shown in FIG. 5A, copper plating layers 16a and 17a are formed across the copper plating layers 4b and 5b and the front and back surfaces 9b and 9c of the embedded resin 9. FIG.
In (A), the substrate 2 is again rotated by 180 °,
a and 5a are reversed. Next, the copper plating layer 1
An etching resist (not shown) having a predetermined pattern is formed on 6a and 17a and etched. As a result, as shown in FIG.
Wiring layers 16 and 17 having a predetermined pattern are formed on a.
The wiring layers 16 and 17 are the electrodes 1 of the chip capacitor 10.
1 and 12 and also to the upper and lower ends of each through-hole conductor 8. At the same time, the filling resin 15 inside the through-hole conductor 8 is lid-plated, and the front and back surfaces 9c and 9b of the embedded resin 9 (the front and back surfaces of the substrate 2) are exposed.
In FIG. 5B, the wiring layers 16 and 17 include the remaining portions of the copper plating layers 4b and 5b.

Next, as shown in FIG.
Resin insulating layers 18 and 19 are formed by attaching an epoxy resin film by thermocompression bonding on and under 6,17. Via holes 20a and 21a are formed at predetermined positions in the insulating layers 18 and 19 such that the wiring layers 16 and 17 are exposed on the bottom surface by photolithography or the like, and the filled via conductors 20 and 21 are filled inside the via holes 20a and 21a.
It is formed. After this, the build-up layers BU1, BU
Wiring layers 22 and 23 forming resin layer 2 and resin insulating layer 2
4 and 25 are formed by a known build-up process (semi-additive method, full-additive method, subtractive method, formation of an insulating layer by laminating a film-like resin material, photolithography technique, etc.). Thus, the multilayer wiring board 1 shown in FIG. 1 can be obtained.

FIG. 6 shows a cross section of a main part in a multilayer wiring board 30 of a different form. FIG.
As shown in FIG. 7, a substrate 32 composed of insulating layers 33, 34, 35 and wiring layers 36, 37 located therebetween, wiring layers 46 formed on the front surface 34a and under the rear surface 35a,
52, 47, 53, and resin insulation layers 48, 54, 4
9, 55, and build-up layers BU3 and BU4. The substrate 32 has a square shape in plan view and an overall thickness of about 0.8 mm, and includes a core substrate (insulating layer) 33 made of an epoxy resin containing a glass cloth and inorganic fillers such as silica fillers stacked on and under the core substrate 33. Has a multi-layered structure including insulating layers 34 and 35 made of epoxy resin and copper wiring layers 36 and 37 located therebetween. In the present embodiment, the surface of the substrate 32 refers to the surface 34a of the insulating layer 34 or the surface of an embedded resin 39 described later.

As shown in FIG. 6, near the center of the insulating layers 33 and 34 in the substrate 32, a concave portion 38 is formed which is open toward the surface 34a of the substrate 32. The concave portion 38 is approximately square in plan view and has a size of 12 mm on a side. After the insulating layers 33 and 34 are drilled, the insulating layer 35 is crimped or a router process by an end mill from the surface 34a side of the substrate 32 is performed. It is formed by performing the process with the total thickness of the insulating layers 33 and 34. Incidentally, the side wall and the bottom surface of the concave portion 38 may have the same surface roughness as the through hole 8 or may be coated with the organic compound, and the corner thereof may be chamfered or rounded.

Further, as shown in FIG.
A plurality of chip capacitors (electronic components) 40 are built in via the same embedded resin 39 as described above. The capacitor 40 protrudes only at the upper end on both sides and
2, that is, a plurality of electrodes 41 symmetrically located on the surface 34 a of the embedded resin 39. Such a capacitor 40 also
This is a ceramic capacitor similar to the above. Further, FIG.
As shown in the figure, a plurality of through holes 43 penetrating between the front and back surfaces 34a and 35a of the substrate 32 are provided around the concave portion 38 with a required space, and a copper through hole conductor 44 is provided inside the through hole 43. And the filling resin 45 are formed. Each through-hole conductor 44 is located between
6 and 37.

As shown in FIG. 6, the surface 34a of the substrate 32
A wiring layer 46 made of copper and a resin insulating layer 48 made of epoxy resin containing silica filler are formed thereon, and the wiring layer 46 is connected to the electrode 41 of the chip capacitor 40 and the upper end of the through-hole conductor 44. . As shown in FIG. 6, a plurality of filled via conductors 50 are formed at predetermined positions in the insulating layer 48, and a wiring layer 52 is formed on the upper end of these via conductors 50 and on the insulating layer 48. Have been. On this wiring layer 52, a solder resist layer (insulating layer) 54 and a plurality of solder bumps (terminals) 58 penetrating therethrough and projecting higher than the first main surface 56 are formed. The above wiring layers 46 and 52 and resin insulating layers 48 and 5
4 forms the build-up layer BU3. The solder bump 58 is an IC chip mounted on the first main surface 56.
(Semiconductor element) It is individually connected to a connection terminal (not shown) protruding from the bottom surface of 29. The underfill material (not shown) between the IC chip 29 and the first main surface 56 is filled around the connection terminals of the IC chip 29 and the solder bumps 58 so as to bury them.

As shown in FIG. 6, the back surface 35a of the substrate 32
Below, a copper wiring layer 47 and a resin insulating layer 49 made of epoxy resin containing silica filler are formed. The wiring layer 47 is connected to the lower end of the through-hole conductor 44. A plurality of filled via conductors 51 are formed at predetermined positions of the insulating layer 49, and a wiring layer 53 is formed below the lower end of the via conductor 51 and under the insulating layer 49.
Under the wiring layer 53, a solder resist layer (insulating layer) 55
Is formed, and the wiring 59 in the wiring layer 53 exposed in the opening 57 opening to the second main surface 55a side is formed by Ni
And Au plating, and serve as connection terminals to a motherboard (not shown) on which the wiring board 30 itself is mounted.
The above wiring layers 47 and 53 and resin insulating layers 49 and 55
Forms the build-up layer BU4. The upper and lower wiring layers 46 and 47 sandwiching the substrate 32 are connected to the through-hole conductor 4.
4 and the electrode 41 of the chip capacitor 40
Are electrically connected to the wiring layers 47 and 53 on the back surface 35a via the wiring layer 46 and the through-hole conductor 44.

According to the wiring board 30 described above, the wiring layer 46 is provided between the electrode 41 of the chip capacitor 40 built in the recess 38 of the substrate 32 and the IC chip 29 mounted on the first main surface 56. , 52, via conductors 50, and solder bumps 58 are interposed. Therefore, the loop inductance in such a conduction path is reduced as compared with the conventional multilayer wiring board 70 of FIG. As a result, the electrical characteristics such as the occurrence of switching noise and crosstalk noise are reduced, so that the chip capacitor 40 and the IC chip 29 can operate normally and at high speed. In addition, the substrate 3
In the second insulating layers 34 and 35, via conductors may be formed to connect between the wiring layers 36 and 46 or between the wiring layers 37 and 47.

FIG. 7 shows a cross section of a main part of a multilayer wiring board 30a in an application form of the wiring board 30. As shown in FIG. 7, the wiring substrate 30a includes the same substrate 32, wiring layers 46, 52, 47, and 53 formed on the front surface 34a and the rear surface 35a, and the resin insulating layer 4
Build-up layer BU consisting of 8, 54, 49 and 55
3 and BU4. Substrate 3 including insulating layers 33, 34, 35 and wiring layers 36, 37 located therebetween.
7, a recess 38 is formed in the same manner as described above, and a plurality of chip capacitors 40a are built in the recess 38 via the same embedded resin 39 as described above. The chip capacitor 40a projects from the upper and lower ends on both side surfaces thereof, and the front surface 34a or the rear surface 35 of the substrate 32.
It has a plurality of electrodes 41 and 42 symmetrically located at a. still,
In the present embodiment, the surface of the substrate 32 refers to the insulating layer 34
Surface 34a or the surface of the embedded resin 39,
The back surface of 2 indicates the back surface 35a of the insulating layer 34.

As shown in FIG.
A wiring layer 62 located at the upper end of a plurality of through-hole conductors 60 penetrating the insulating layer 35 of the substrate 32,
It is individually connected to the electrode 42 of the capacitor 40a. Each through-hole conductor 60 is connected at its lower end to a wiring layer 47 formed on the back surface 35 a of the substrate 32.
Note that a filling resin 64 is provided inside each through-hole conductor 60.
Are formed. Further, as shown in FIG.
Above the surface 34a of the wiring layer 46, as described above.
52, resin insulating layers 48 and 54, via conductors 50, and solder bumps (terminals) 58 are formed, and the IC chip 29 can be mounted on the first main surface 56. The wiring layer 4 is also provided below the back surface 35a of the substrate 32 in the same manner as described above.
7, 53, resin insulating layers 49 and 55, via conductors 51, openings 57, and wiring 59 for connection terminals are formed.

According to the multilayer wiring board 30a as described above, the chip capacitor 4 built in the recess 38 of the board 32
A relatively short conduction path including the wiring layers 46 and 52, the via conductor 50, and the solder bump 58 is interposed between the electrode 41 of Oa and the IC chip 29 mounted on the first main surface 56. The electrode 42 of the chip capacitor 40a
Has a conduction path composed of wiring layers 62, 47, 53, through-hole conductors 60, and via conductors 51 between the motherboard on the second main surface 55 a side. For this reason, the loop inductance in the conduction path between the electrode 41 and the IC chip 29 is also reduced in the multilayer wiring board 30a as compared with the conventional multilayer wiring board 70 shown in FIG. As a result, the electrical characteristics such as the occurrence of switching noise and crosstalk noise are reduced, and the chip capacitor 40a and the IC chip 29 can be operated normally and at high speed.

The present invention is not limited to the embodiments described above. The material of the core substrates (insulating layers) 3 and 33 in the substrates 2 and 32 is bismaleimide triazine (B) in addition to the glass-epoxy resin composite material.
T) resin, epoxy resin, glass woven fabric having similar heat resistance, mechanical strength, flexibility, ease of processing, etc., glass fiber such as glass woven fabric and epoxy resin, polyimide resin,
Alternatively, a glass fiber-resin composite material which is a composite material with a resin such as a BT resin may be used. Alternatively, a composite material of an organic fiber and a resin such as a polyimide fiber, or a resin-resin composite material in which a resin such as an epoxy resin is impregnated with a fluororesin having a three-dimensional network structure such as PTFE having continuous pores is used. It is also possible.

Further, only one electronic component may be incorporated in the through hole 8 or the concave portion 38. Conversely, many substrates 2,
A plurality of through holes 8 and recesses 38 may be formed in one product unit in a multi-piece substrate (panel) including 32. Further, a unit in which a plurality of chip-shaped electronic components are bonded in advance between their side surfaces may be inserted into the through hole 8 or the concave portion 38 to be built therein. In addition, in addition to the chip capacitor 10 and the like, the chip-shaped electronic component
This includes passive components such as chip-shaped inductors, resistors, and filters, and active components such as transistors, semiconductor elements, FETs, and low-noise amplifiers (LNA). It is also possible to incorporate it inside the hole 8 or the recess 38.

Further, in the multilayer wiring board of the present invention, the electrodes such as the chip capacitor 10 are connected to the wiring layer only on the IC chip side, that is, the electrodes and the wiring layer are connected on the mother board side. A multi-layer wiring board having no form is also included. The materials of the wiring layers 16 and 17 and the through-hole conductors 14 are Ag, Ni,
It may be formed of Ni-Au or the like, or may be formed by a method such as applying a conductive resin without using the metal plating layer. Further, the material of the resin insulating layers 18 and 19 may be, for example, a polyimide resin, a BT resin, a PPE resin, or a continuous pore having the same heat resistance and pattern moldability, in addition to the epoxy resin as a main component. A resin-resin composite material in which a resin such as an epoxy resin is impregnated with a fluorine-based resin having a three-dimensional network structure such as PTFE can also be used. The insulating layer may be formed by a method of applying a liquid resin with a roll coater, in addition to a method of thermocompression bonding an insulating resin film. Further, the composition of the glass cloth or glass filler mixed into the insulating layer may be any one of E glass, D glass, Q glass, and S glass, or a combination of two or more of them. Also, the via conductor may be a conformal via conductor that is not completely filled with a conductor, instead of the filled via conductor 20 or the like.

[0041]

According to the multilayer wiring board of the present invention described above, the continuity between the electrodes of the electronic components incorporated in the substrate and the IC chip mounted on the first principal surface is higher than that of the conventional multilayer wiring board. The route can be as short as possible. As a result, the loop inductance in such a conduction path can be reduced, so that electrical characteristics such as switching noise and crosstalk noise can be reduced.
Therefore, the built-in electronic components and the mounted IC chip can be operated normally and at a high speed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a main part in one embodiment of a multilayer wiring board of the present invention.

FIGS. 2A to 2D are schematic diagrams showing main steps in a method for manufacturing the multilayer wiring board of FIG. 1;

3 (A) to 3 (C) are schematic views showing main manufacturing steps following FIG. 2 (D).

4 (A) to 4 (C) are schematic views showing main manufacturing steps following FIG. 3 (C).

5 (A) to 5 (C) are schematic views showing main manufacturing steps following FIG. 4 (C).

FIG. 6 is a sectional view showing a main part of a multilayer wiring board according to another embodiment of the present invention.

FIG. 7 is a sectional view showing a main part in an application form of the multilayer wiring board of FIG. 6;

FIG. 8 is a cross-sectional view showing a main part of a conventional multilayer wiring board.

[Explanation of symbols]

1, 30, 30a ............ Multi-layer wiring board 2, 32 ... ...... Boards 3-5, 33-35 ... Insulating layer 4a, 9c, 34a ... Front surface 5a, 9b, 35a ... Back surface 6, 7 , 16,17,22,23,36,37,46,47,5
2,53 Wiring layer 8 ……………………………………… Through hole 9,39 ……………………………………………… Resin 10, 40, 40a ...... Chip capacitors (electronic parts) 11, 12, 41, 42 ...... Electrodes 18, 19, 24, 25 , 48, 49, 54, 55 ... resin insulating layer 26, 56 ... first primary surface 28, 58 ... 58 ……… Solder bumps (terminals) 29 ………………………………… IC chips 38 …………………………………………………………… Recesses BU1 to BU4 Build-up layer

Claims (2)

[Claims] A substrate having an insulating layer and a wiring layer alternately laminated and having a front surface and a back surface; a through hole penetrating between the front surface and the back surface of the substrate, or a concave portion opening on the front surface or the back surface; An electronic component embedded in the through hole or the recess via an embedded resin; and a build-up layer formed above at least one of the front surface and the back surface of the substrate and including a resin insulating layer and a wiring layer. The multilayer wiring board according to claim 1, wherein the electrodes of the electronic component and the wiring layer of the build-up layer are connected on a surface of the board. 2. The terminal for connecting a wiring layer and a semiconductor element such as an IC chip mounted on a first main surface of the build-up layer to the first layer above the surface of the substrate. The multilayer wiring board according to claim 1, wherein the multilayer wiring board is provided near a main surface.