JP2002217425A - Electrode for semiconductor device, semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate electrode, that can prevent corrosion due to buffer fluoric acid solution and alkaline-based developer, and to provide a semiconductor device having the gate electrode. SOLUTION: There are successively laminated a Ti film 8, an Al film 9, a first Mo film 10, a transition element oxide film (MoOx film) 10A, and a second Mo film 11 on a semiconductor substrate 101 for composing the gate electrodes 13p, 13q, 13r,..., and 13w. The laminated structure film on the first Mo, MoOx, and second Mo films 10, 10A, and 11 is formed on the Al film 9, thus preventing corrosion, due to buffered fluoric acid solution and alkaline- based developer in the gate electrode. In the laminated structure film of the first Mo, MoOx, and second Mo films 10, 10A and 11, an Al atom in a foundation layer cannot be easily diffused to the surface side, and the diffusion of Au, such as a surface wiring layer on the lamination structure film to the Al film of foundation, is restrained effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrode for a semiconductor device,
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a novel structure of a Schottky gate electrode used for a semiconductor device such as a high electron mobility transistor (HEMT) or a Schottky barrier field effect transistor (MESFET) and a method of manufacturing the same. It is.

[0002]

2. Description of the Related Art A Schottky gate electrode of a field effect transistor (FET) such as MESFET or HEMT is
It is mainly formed of a titanium (Ti) / aluminum (Al) laminated film. In an FET having a bonding pad formation region, as shown in FIGS. 24 and 25, a gate pad base layer (Ti / Al
The surface of the pad underlayer 32 is covered with an interlayer insulating film 81 such as an oxide film (SiO _x ) or a nitride film (SiN _x ). The gate electrode and the gate pad base layer are integrally formed with the same structure, and the Ti layer forming the gate electrode is in direct contact with the semiconductor substrate 103 in the element main operation region. In order to electrically connect the gate pad underlayer to an external circuit, as shown in FIG. 24, the interlayer insulating film 81 above the gate pad underlayer 32 is selectively removed (opening the window). It is necessary to prepare a gate bonding pad 34A in which a gold (Au) thin film is patterned using this window as shown in FIG. An etching mask made of the resist 39 is used for selectively removing the interlayer insulating film 81. Then, a bond wire such as an Au wire is connected to the gate bonding pad 34A, and electrical connection with the outside of the package becomes possible.

In the manufacture of these FETs, a so-called "lift-off method" is used for patterning a thin Au film which is difficult to etch. That is, in the case of the gate pad base layer 32, the interlayer insulating film 8 formed in FIG.
As shown in FIG. 25, a new resist 33 is further patterned into an overhang shape on the window (opening) 1, and a thin Au film (wiring material) 34 is deposited. Then, by removing the resist 33, a pattern of the gate bonding pad 34A made of Au is formed.

[0004]

However, as shown in FIG. 24, the interlayer insulating film 8 on the gate pad underlayer 32 is formed.
1 is a buffered hydrofluoric acid solution used as an etching solution for the oxide film (SiO _x ) 81 when opening the window, and the lower layer Ti / A
There is a problem that the l layer 32 is corroded.

In the case of using the lift-off method for patterning the gate bonding pad 34A in the structure having the cross-sectional shape shown in FIG. During development, a gate pad underlayer (Ti / Al
The layer 32 may be further corroded.

As described above, in the conventional FET, since the gate electrode (Ti / Al) is corroded, the contact with the gate bonding pad 34A formed thereon becomes poor, and the gate bonding pad 34A There is a problem that the contact resistance increases.
When the contact resistance increases in this way, the characteristics of the FET deteriorate.

To solve such a problem, as shown in FIG. 26, a Ti film 38 / Al film 35 / Mo is used as a gate electrode.
It has been proposed to use an electrode made of a laminated film of the film 36. FIG. 26 shows the structure of the gate electrode in the element main operation region. The lowermost Ti film 38 of the gate electrode is in direct contact with the semiconductor substrate 104. The structure of FIG.
4 and FIG. 25, a gate pad underlayer extending from the gate electrode onto the field insulating film 85 in the bonding pad formation region is provided. The surface of the gate pad base layer is covered with an interlayer insulating film. That is, also in this case, the gate electrode and the gate pad underlayer have the same structure and are integrally formed. However, a single layer of molybdenum (Mo) film has a small effect of preventing diffusion of Al atoms,
As shown in FIG. 26, Al atoms diffuse into the surface of the Mo film 36, so that they are also corroded by an oxide film (SiO _x ) etching solution or a positive resist developing solution.
Further, as shown in FIG. 27, if the thickness of the Mo film 36 is increased, corrosion by the etching solution or the positive resist developer can be prevented. Is likely to occur, which may adversely affect the electrical characteristics.

The present invention has been made to solve the above problems. Therefore, an object of the present invention is to provide an electrode for a semiconductor device in which corrosion by an etching solution or a resist developing solution is effectively suppressed, and a desired geometric shape and electrical characteristics are obtained.

Another object of the present invention is to provide a semiconductor device having good electrical characteristics in which the contact resistance between a gate electrode and a wiring electrode connected thereto is suppressed.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device which can prevent a gate electrode from being corroded by an etching solution and a resist developing solution.

[0011]

In order to solve the above problems, a first feature of the present invention is that a barrier metal layer formed on a semiconductor substrate and an Al film disposed on the barrier metal layer The gist is to provide a semiconductor device electrode comprising a cover metal layer made of a specific material disposed on the Al film. Here, the “cover metal layer made of a specific material” means a cover metal layer made of a composite film of a group 6A transition element and an oxide film of the group 6A transition element. The “group 6A transition element” is, as is well known, chromium (Cr), molybdenum (Mo), tungsten (W), and uranium (U). However, uranium (U) is not practical because it is a radioactive element. Specifically, 6A
As the transition element of the group, Mo or Cr is preferable. As the “barrier metal layer”, titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), metal silicide, or the like can be used. The term “electrode for semiconductor device” means, for example, an individual semiconductor element such as a diode, a field effect transistor (FET), or an electrostatic induction transistor (SIT), and various electrodes used in a semiconductor integrated circuit including these elements. In particular, it is suitable for a Schottky electrode such as a Schottky diode, HEMT, MESFET, and MESSIT. This "Schottky electrode" includes not only active control electrodes located in the element main operation area, but also a control electrode lead-out portion extended from these active control electrodes, or a metal wiring layer for connecting an external circuit such as a bonding pad. And an underlayer for connection to the substrate.

According to the first feature of the present invention, the composite film of the uppermost layer of the semiconductor device electrode and the oxide film of the group 6A transition element is used for wet etching of an oxide film (SiO _x ). It has etching resistance to buffered hydrofluoric acid (buffered hydrofluoric acid) solution. The buffered hydrofluoric acid solution is hydrofluoric acid (HF): ammonium fluoride (NH ₄ F) = 1:
It is used in a composition of about 10 or 1: 7. For this reason, when the insulating film is etched to expose the electrode film, the uppermost cover metal layer prevents corrosion such as corrosion and after-corrosion from occurring in the Al film underlying the cover metal layer due to the buffered hydrofluoric acid solution. Can be prevented.

Further, the composite film of the group 6A transition element and the oxide film of the group 6A transition element has etching resistance to an alkaline resist developing solution (hereinafter referred to as "alkali developing solution"). . For this reason, when forming a wiring member as a metal wiring layer for connecting an external circuit such as a bonding pad on the cover metal layer using the lift-off method, the cover metal layer is prevented from being corroded by an alkaline developing solution. Has the effect of doing.

Further, a composite film of the group 6A transition element constituting the cover metal layer and the oxide film of the group 6A transition element is
Since Al atoms from the Al film underlying the cover metal layer are unlikely to diffuse, it functions as a barrier layer. The composite film of the group 6A transition element and the oxide film of the group 6A transition element includes:
Atoms are less likely to be diffused than a metal single-layer film made of only a Group 6A transition element, and the Group 6A transition element diffuses toward the Al film side or reacts with the surface of the semiconductor substrate through the Al film. Nor. Thus, the surface of the semiconductor substrate and 6A
Since there is no reaction with a group transition element, the electrical characteristics and crystallographic (metallurgical) characteristics of the semiconductor device are not deteriorated. In addition, when the surface wiring layer or the interlayer wiring layer made of Au is formed on the composite film of the group 6A transition element and the oxide film of the group 6A transition element, Au is used as an underlying Al film and further, It has the effect of suppressing diffusion to the semiconductor substrate side. Therefore, in the present invention, it is possible to prevent the electrical characteristics and crystallographic (metallurgical) characteristics of the semiconductor device from changing.

Specifically, the cover metal layer is made of a first transition element thin film made of a 6A transition element, an oxide film of a 6A transition element above the first transition element thin film, and an oxide film of a 6A transition element. And the second transition element thin film on the top of the above. The diffusion preventing action of the cover metal layer is 6A
This is because the laminated structure in which the oxide film of the group 6A transition element is interposed between the first and second transition element thin films is larger than the metal layer composed of only the group III transition element. In addition, by forming the oxide film of the group 6A transition element between the first and second transition element thin films, the thickness of the group 6A transition element thin film is substantially increased, and the first transition element thin film and the second transition element thin film are formed. It is also possible to prevent the adhesion between the element thin films from deteriorating.

In this case, the thickness of the first transition element thin film is 15
The thickness of the oxide film of the 6A transition element is 0.7 nm to 10 nm, and the thickness of the second transition element thin film is 1 nm to 100 nm.
It may be set to about 5 nm to 100 nm. By setting the thickness in such a range, film peeling is suppressed,
In addition, the effect of preventing diffusion can be maintained.

As described above, Mo and Cr are preferable as the transition element of Group 6A. Of these, Mo is particularly preferable. If Group 6A transition element is Mo, oxide films of Group 6A transition elements, molybdenum oxide such as MoO ₂ and MoO ₃ (M
oO _x ). The composite film of Mo and MoO _x (Mo laminated structure film) has high etching resistance to a buffered hydrofluoric acid solution. For this reason, when the insulating film is etched to expose the electrode film, the Mo laminated structure film as the cover metal layer causes corrosion such as corrosion or after corrosion of the Al film underlying the Mo laminated structure film by the buffered hydrofluoric acid solution. Can be prevented from occurring. In particular, the Mo laminated structure film has etching resistance to an alkali-based developer,
In addition, since the Al atoms in the underlayer are not easily diffused, the Al layer effectively functions as an Al diffusion barrier layer. Further, even when a surface wiring layer made of Au or the like is formed thereon, the Mo laminated structure film effectively suppresses the diffusion of Au to the underlying Al film or the semiconductor substrate.

According to a second feature of the present invention, a semiconductor substrate, a field insulating film disposed on the surface of the semiconductor substrate, a barrier metal layer formed on the semiconductor substrate at an opening of the field insulating film, and a barrier metal layer The gist of the present invention is to provide a semiconductor device including a gate electrode composed of an Al film disposed on the Al film and a cover metal layer disposed on the Al film. The “opening of the field insulating film” in which the barrier metal layer is arranged is provided in a part or all of the element main operation region of the semiconductor substrate. The “element main operation region” is a region on a planar pattern, which is called a “active region” or a “device region”, in which a main current of a semiconductor active element is controlled. For example, a source region and a drain region of the FET are arranged in the “element main operation region”, and a main current flowing between the source region and the drain region is:
It is controlled by a control electrode (gate electrode). In an integrated circuit, an element isolation region surrounds an element main operation region to prevent electrical interference with another adjacent element main operation region. The end (inner peripheral portion) of the opening of the field insulating film may be located near the boundary between the element main operation region and the element isolation region. "Cover metal layer" is the first
As described in the feature, the film is composed of a group 6A transition element and a composite film of the group 6A transition element and an oxide film. This 6A
The function, function, and the like of the group transition element and the composite film of the group 6A transition element and the oxide film are as described in the first feature.
As the “barrier metal layer”, the T
i, TiW, TiN, etc. can be used.

According to a second feature of the present invention, the semiconductor device further comprises an external circuit connection region provided adjacent to the element main operation region, and the gate electrode is formed on the field insulating film provided in the external circuit connection region. It is preferable to form a gate pad underlayer having the same laminated structure as the gate electrode in the external circuit connection region.
In other words, the “gate electrode” according to the second feature of the present invention includes not only the active control electrodes located in the element main operation region, but also a control electrode extraction portion extended from these active control electrodes and an external electrode. An underlying layer for connecting to the metal wiring layer for circuit connection is included. Here, in the “external circuit connection region”, in addition to a region for arranging bonding pads, in an integrated circuit, an interlayer wiring layer and a surface wiring layer for connecting to another element main operation region are arranged. And the upper part of the element isolation region can be used as an external circuit connection region. In other words, the “gate pad underlayer” has the same laminated structure that is metallurgically connected to the “active control electrode” having a relatively large area to enable connection with this external circuit. It will mean a metal layer.

Therefore, according to the second feature of the present invention, there is provided an interlayer insulating film disposed on the field insulating film,
It is preferable that the semiconductor device further includes an external circuit connection metal wiring layer connected to the gate pad base layer in the opening of the interlayer insulating film provided on the surface of the gate pad base layer.
As can be understood from the above description, the “metal wiring layer for external circuit connection” includes an interlayer wiring layer and a surface wiring layer for connecting to another element main operation region in the integrated circuit, in addition to the bonding pad.

The composite film of the uppermost layer of the gate electrode of the semiconductor device according to the second feature of the present invention and the oxide film of the group 6A transition element has an etching resistance to a buffered hydrofluoric acid solution. Have. For this reason, the uppermost cover metal layer is formed by using a buffered hydrofluoric acid solution when the interlayer insulating film disposed above the field insulating film is etched with a buffered hydrofluoric acid solution to expose the gate pad base layer. Corrosion, such as corrosion and after-corrosion, can be prevented from occurring in the Al film underlying the layer.

Further, the composite film of the group 6A transition element and the oxide film of the group 6A transition element has etching resistance to an alkaline developer. Therefore, when the metal wiring layer for connecting an external circuit is formed on the gate pad base layer by using the lift-off method, the gate pad base layer is prevented from being corroded by the alkaline developer. When a composite film of a group 6A transition element and an oxide film of the group 6A transition element is used to form an external circuit connection metal wiring layer made of Au, Au is used to form an Al film constituting a gate pad base layer. Has the effect of suppressing diffusion. Therefore, in the present invention, it is possible to prevent the electrical characteristics and crystallographic (metallurgical) characteristics of the semiconductor device from changing.

The third feature of the present invention is that (a) a step of forming a field insulating film on the surface of a semiconductor substrate, and (b) a part of the field insulating film is selectively removed to expose the semiconductor substrate. Forming an opening, (c) depositing a barrier metal layer over the semiconductor substrate exposed at the bottom of the opening and over the field insulating film, and (d) depositing an Al film on the barrier metal layer. (E) forming a cover metal layer comprising a group 6A transition element and a composite film with the group 6A transition element oxide film on the Al film;
A method of manufacturing a semiconductor device, comprising the steps of: selectively removing a cover metal layer, an Al film, and a barrier metal layer, and forming a gate electrode including the barrier metal layer, the Al film, and the cover metal layer inside the opening. The gist is that you have done it.
Between the step (b) of selectively removing a part of the field insulating film and the step (c) of depositing the barrier metal layer, a step of forming another electrode or the like may be included.

The cover metal layer composed of a group 6A transition element and a composite film with the group 6A transition element oxide film has etching resistance to an alkaline developing solution and a buffered hydrofluoric acid solution. Therefore, in the method of manufacturing a semiconductor device according to the third aspect of the present invention, (a) a step of depositing an interlayer insulating film on the cover metal layer, and (b) a step of applying a resist on the interlayer insulating film. (C) selectively exposing a part of the resist, (d) developing the exposed resist, and (e) using an etching mask formed by the series of exposing and developing steps. And etching the interlayer insulating film with a buffered hydrofluoric acid solution until the surface of the cover metal layer is exposed, in order to prevent the cover metal layer from being etched by the buffered hydrofluoric acid solution, Corrosion of the underlying Al film can be avoided. In particular, corrosion such as corrosion and after-corrosion in the Al film occurs.
Effectively prevent.

Further, (f) a step of removing the first resist, and (g) a step of removing the first resist on the cover metal layer and the interlayer insulating film exposed at the bottom of the opening of the interlayer insulating film formed by the etching solution. Applying a second resist,
(H) selectively exposing a part of the second resist, and (i) developing the exposed second resist with an alkaline developing solution. Etching of the cover metal layer is avoided. Therefore, when a metal wiring layer for connecting an external circuit such as a bonding pad or a surface wiring layer is formed on the cover metal layer using the lift-off method, the cover metal layer is prevented from being corroded by an alkali-based developer. Further, corrosion of the underlying Al film is effectively prevented.

In the method for manufacturing a semiconductor device according to the third aspect of the present invention, the step of forming a cover metal layer includes the steps of:
After depositing a first Mo film on the I film, the surface of the first Mo film is oxidized to form a Group 6A transition element oxide film (molybdenum oxide film such as MoO ₂ or MoO ₃ ), and then 6A
It is preferable that the second Mo film is formed by depositing a layer on the group IV oxide film. This oxidation treatment can be easily performed by exposing the surface of the first Mo film to an oxygen atmosphere in a deposition chamber of a deposition apparatus or in an oxidation treatment chamber connected to the deposition chamber via a gate valve or the like. . 1st Mo film / molybdenum oxide film / 2M
The Mo multilayer structure film made of an o film functions as a barrier layer because Al in the base layer is not easily diffused. 1st Mo
The Mo laminated structure film composed of the film / molybdenum oxide film / second Mo film suppresses the diffusion of Au atoms to the underlying Al film and the semiconductor substrate even when an interlayer wiring layer made of, for example, Au is formed thereon. Has an action. Also, the first Mo film /
The Mo multilayer structure film composed of the molybdenum oxide film / second Mo film can prevent the adhesion between the layers from deteriorating and improve the film formation efficiency.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, referring to the drawings, HEMTs and MESFETs will be exemplified and described as semiconductor devices of the present invention. That is, in the first embodiment of the present invention, the structure of a HEMT as a semiconductor device of the present invention and a manufacturing method thereof will be described. In the second embodiment, the structure of a MESFET as a semiconductor device of the present invention and the manufacturing thereof will be described. The method will be described. However, it should be noted that the drawings are schematic, and that the thicknesses and thickness ratios of the respective material layers are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it is needless to say that dimensional relationships and ratios are different between drawings.

(First Embodiment) A semiconductor device (HEMT) 201 according to a first embodiment of the present invention has Schottky gate electrodes 13p, 13q, 13 as shown in FIG.
, 13w. That is, HEMT20
1 Schottky gate electrodes 13p, 13q, 13r,.
, 13w are the semiconductor substrates 10 as shown in FIG.
1. a field insulating film 5 disposed on the surface of the semiconductor substrate 101; a barrier metal layer 8 formed on the semiconductor substrate 101 in an opening of the field insulating film 5; Film 9, this Al film 9
And at least a cover metal layer 51 disposed thereon. The field insulating film 5 is composed of Schottky gate electrodes 13p, 13q, 13r,..., 1 as shown in FIG.
It does not have to be arranged adjacent to 3w. For example, another structure is provided inside the opening of the field insulating film 5 so that the end (inner peripheral portion) of the opening of the field insulating film 5 is located near the boundary between the element main operation region and the element isolation region. May be included.

In FIG. 3, the cover metal layer 51
A first transition element thin film 10 made of a group A transition element;
An oxide film of a 6A group transition element (hereinafter, referred to as a “transition element oxide film”) 10A above the transition element thin film 10 and a second transition element thin film 11 above the transition element oxide film 10A. . As shown in FIG. 3, by adopting a laminated structure in which the transition element oxide film 10 </ b> A is interposed between the first transition element thin film 10 and the second transition element thin film 11, the diffusion of the cover metal layer 51 can be prevented. It is larger than a metal layer composed of only a 6A transition element. The “diffusion preventing function” refers to a function of preventing the Al film 9 underlying the cover metal layer 51 from diffusing into the cover metal layer 51 and coming out of the cover metal layer 51, and a function of preventing the metal laminated on the cover metal layer 51. The element passes down through the cover metal layer 51 and the cover metal layer 5
This means an action of preventing the first underlying Al film 9 from reaching.
Also, as shown in FIG. 3, the first transition element thin film 10 and the second
The formation of the transition element oxide film 10A between the transition element thin films 11 increases the substantial thickness of the group 6A transition element thin film and the adhesion between the first transition element thin film 10 and the second transition element thin film 11. It is also possible to prevent the property from deteriorating.

In this case, the first transition element thin film 10 has a thickness of 15 nm to 100 nm, the transition element oxide film 10A has a thickness of 0.7 nm to 10 nm, and the second transition element thin film 11 has a thickness of about 15 nm to 100 nm. Should be set to. By setting the thickness in such a range, the film peeling can be suppressed, and the diffusion preventing action (diffusion barrier effect) can be maintained high.

As the group 6A transition element, Mo and Cr are preferable, and Mo is particularly preferable. When the group 6A transition element is Mo, the transition element oxide film 10A in FIG.
A molybdenum oxide film (MoO _x ) 10A such as ₂ or MoO ₃ is obtained. Composite film of Mo and MoO _x (Mo laminated structure film)
Has high etching resistance to buffered hydrofluoric acid solution. Therefore, when the insulating film is etched to expose the electrode film, the Mo laminated structure film serving as the cover metal layer 51 is formed by using a buffered hydrofluoric acid solution as the base of the Mo laminated structure film.
Corrosion such as corrosion and after-corrosion can be prevented from occurring in the 1 film 9. Further, the Mo laminated structure film has an etching resistance to an alkali-based developing solution and Al atoms in the underlayer 16 are hardly diffused, and thus effectively functions as a barrier layer. In FIG. 3, the semiconductor substrate 1
01, a Ti film 8 as a barrier metal film,
An Al film 9, a first Mo film 10 as a first transition element thin film,
A MoO _x film 10A as a transition element oxide film and a second Mo film as a second transition element thin film are stacked. And T
The thickness of the i film 8 is about 5 nm, and the thickness of the Al film 9 is 500 n
The thickness of each of the first Mo film 10 and the second Mo film 11 is set to about 15 nm to 100 nm. or,
Transition element oxide film 10A is, 0.7Nm～10nm about MoO _x was oxidized in a short time the surface of the first 1Mo film 10
An extremely thin film made of (x> 0). The MoO _x film 10A having a thickness of about 10 nm or more is formed on the gate electrodes 13p, 13q, 1
3r,..., 13w resistance increase, and the second Mo
Film 11 and is not preferable because adhesion problems between the MoO _x layer 10A. On the other hand, when the thickness is 0.7 nm or less, it does not function sufficiently as a diffusion barrier for Al. In consideration of these points, the thickness of the MoO _x layer 10A is about 1nm~7nm is more preferable. Especially 4n where direct tunnel conduction becomes dominant
m or less is preferable. As MoO _x , MoO ₂ or MoO ₃ is preferable.

The opening of the field insulating film 5 where the barrier metal layer 8 is arranged is formed in the semiconductor substrate 10 as shown in FIG.
One element main operation area is provided. The element main operation region is a region on a planar pattern, which is a so-called active region or device region, in which a main current of a semiconductor active element is controlled. In FIG. . On one main surface side of the semiconductor substrate 101 shown in FIG. 1, together with the element main operation region trapezoid 2, two source pad traps 3 a located on one side of the element main operation region trapezoid 2. , 3b, and one trap pad 4 for the drain pad located on the other side of the trapezoid 2 for the element main operation area. A plurality of biting grooves 2A are formed on both sides of the element main operation area trapezoid 2 so as to face each other. The biting groove 2A is a groove for obtaining a high withstand voltage by increasing the creepage distance in the shape of a cove and can be omitted depending on the purpose. Then, as shown in FIG. 2, a plurality of source regions 61a and 61
, 61d and a plurality of drain regions 62e, 6
, 62i are arranged, and a plurality of source regions 61a, 61b,..., 61d facing each other and a plurality of drain regions 62e, 62f,. The flowing main current is controlled by the corresponding control electrodes (gate electrodes) 13p, 13q, 13r,..., 13w.

As shown in FIG. 1, there is further provided an external circuit connection region provided adjacent to the element main operation region pedestal portion 2, and a gate electrode is provided on the field insulating film 5 provided in the external circuit connection region. A gate pad base layer 16 having the same laminated structure as the gate electrode is formed in the external circuit connection region (see the cross-sectional view of FIG. 12). In FIG. 1, a gate
Although the bonding pad 19GP is provided, in the case of an integrated circuit or the like, an interlayer wiring layer or a surface wiring layer for connecting to another element main operation area may be provided. In other words, the gate pad underlayer 16 shown in FIG. 1 is a metal layer having a relatively large area for enabling connection to various external circuits, and includes active control electrodes 13p, 13q,
.., 13w are metallurgically connected and have the same laminated structure.

The semiconductor substrate 101 is, as shown in FIG.
For example, a semi-insulating semiconductor substrate (semi-insulating GaAs substrate) 1
A-type n-type GaAs having a thickness of 300 to 500 nm
buffer layer 1B made of s, n ⁻ having a thickness of 15 to 55 nm
Layer 1C made of InGaAs, thickness 2-5n
m of n ^- spacer layer 1D formed of mold AlGaAs, an electron supplying layer 1 made of n-type AlGaAs having a thickness of 3~15nm
E and a Schottky layer (Schottky contact layer) 1F made of n-type AlGaAs having a thickness of 10 to 25 nm. The n ⁻ -type channel layer 1C and the n ⁻ -type spacer layer 1D are so-called “andove layers” to which no impurity is intentionally added. Then, on the n-type Schottky layer 1F, a plurality of n ⁺ -type source regions (n ⁺ -type ohmic contact regions) 61a, 61b,.
, 62i, and a plurality of n ⁺ -type drain regions (n ⁺ -type ohmic contact regions) 62e, 62f,..., 62i are arranged by patterning. Source regions 61a, 6
.., 61d and drain regions 62e, 62
, 62i are each formed of n ⁺ -type InGaAs or n ⁺ -type GaAs having a thickness of 5 to 10 nm. Channel layer 1C made of n ^- type InGaAs
A heterojunction is formed between the spacer and the spacer layer 1D made of n ⁻ -type AlGaAs. Then, the electron supply layer 1E
, And a two-dimensional electron gas is formed near the interface between the n-type channel layer 1C and the n ⁻ -type spacer layer 1D.

A plurality of source regions (ohmic contact regions) 61a, 61 in the element main operation region trapezoid 2
, 61d, a plurality of source electrodes 7S are respectively arranged as shown in FIG. Also, a plurality of drain regions (ohmic contact regions) 62e, 6
, 62i, a plurality of drain electrodes 7
D are arranged respectively. Multiple drain electrodes 7D
The plurality of source electrodes 7S are arranged in parallel and alternately with each other.

The gate electrodes 13p, 13q, 13r,..., 1
3w is formed. That is, a set of source regions 61
a, the gate electrode 13p, and the drain region 62e constitute a first unit cell. Also, a set of source regions 61
a, a gate electrode 13q and a drain region 62f form a second unit cell with a set of source region 61b and gate electrode 1
3r and the drain region 62f constitute a third unit cell. In this way, a plurality of unit cells are connected in parallel to form a HEMT 201 having a multi-channel structure.

On the source pad bases 3a and 3b and the drain pad base 4, a source pad base layer (not shown) formed in the same process as the source electrode 7S and the drain electrode 7D. Drain pad underlayer (not shown)
(FIG. 8 shows the source pad underlayer 7S
Pa, 7SPb, a drain pad underlayer 7DP, and a gate pad underlayer 7GP are shown. ). Source electrode 7
S and the source pad base layer are connected via a window (opening) formed in the interlayer insulating film 21 by a source wiring 19S made of gold (Au). In addition, the drain electrode 7D and the drain pad underlayer are connected via a window (opening) formed in the interlayer insulating film 21 to the drain wiring 1 made of Au.
9D. As shown in FIG. 1, source bonding pads 19SPa and 19SPb made of Au are formed on the unillustrated source pad underlayer, and A is formed on the unillustrated drain pad underlayer.
A drain bonding pad 19DP made of u is formed. Source bonding pad 19SP
a, 19SPb are formed integrally with the source wiring 19S,
The drain bonding pad 19DP is formed integrally with the drain wiring 19D. A gate pad base layer 16 is disposed between the source pad base layer and the drain pad base layer (not shown).
A gate bonding pad 19GP is formed on the substrate. Then, as shown in FIG. 2, the interlayer insulating film 21 and the source wiring 19 of the HEMT 201 having such a structure.
A passivation film 22 is formed on the entire surface so as to cover the S and the drain wiring 19D.

Further, the HE according to the first embodiment of the present invention.
In the MT 201, as shown in FIG.
, 13w, as well as gate lines 14, 15 and a gate pad base layer which are connected in series to the gate electrodes 13p, 13q, 13r, ..., 13w. 16 are formed. The gate line 14 is connected to the gate electrodes 1 located on both sides of the source electrode 7S.
13p, 13q; 13r, 13s;
w is connected to the drain pad trapezoid 4 side. Also, the relatively wide gate line 15 is
The gate electrodes 13p located on both sides of the drain electrode 7D,
13q, 13r, 13s;...; 13v, 13w are connected on the side of the source pad trapezoids 3a, 3b. The gate pad base layer 16 is formed so as to be located between the two source pad trapezoids 3a and 3b, and the drain electrode 7D located at the center is formed.
Gate electrodes 13p, 13q, 13r located on both sides of
13u, 13v; 13w are connected on the side of the source pad trapezoidal portions 3a, 3b.

In the HEMT 201 having such a structure, the gate electrode 13 has a structure as shown in FIG.
The Al film 9 constituting the gate electrode 13 is formed by the upper first Mo film.
Film 10, transition element oxide film (MoO _x film) 10A, 2M
It is protected by the laminated film of the o film 11. Therefore, in the manufacturing process described below, the deterioration of the characteristics of the gate electrodes 13p, 13q, 13r,..., 13w is suppressed without being corroded by an alkaline developing solution or an oxide film etching solution. , High production yield and reliability can be achieved. Also, the gate electrodes 13p, 13q, 13r,.
13w is a first Mo film 10, a transition element oxide film (MoO _x
Since the laminated film composed of the film 10A and the second Mo film 11 is employed, Al is hardly diffused, and conversely, Mo does not pass through the Al film 9 and react with the Schottky layer 1F.
Therefore, the semiconductor substrate 101 has good Schottky characteristics. From this point, the high conversion conductance gm of the HEMT 201 can be obtained, and the high-frequency characteristics can be improved.

A method of manufacturing the semiconductor device (HEMT) 201 according to the first embodiment of the present invention will be described with reference to FIGS.

(1) First, the semi-insulating GaAs substrate 1A
On top, n-type GaAs having a thickness of 300 to 500 nm
Buffer layer 1B, n having a thickness of 15 to 55 nm⁻Type I
a channel layer 1C made of nGaAs having a thickness of 2 to 5 nm;
n⁻Layer 1D made of type AlGaAs, thickness 3 to
An electron supply layer 1E made of 15 nm n-type AlGaAs,
A 10 to 25 nm thick n-type AlGaAs
Toki layer 1F, n having a thickness of 5 to 10 nm⁺Type InGaAs?
The ohmic contact layer 1G consisting of
The semiconductor substrate 101 is obtained by char growth. For example, decompression
Thick susceptor of metal organic chemical vapor deposition (MOCVD) equipment
Semi-insulating GaAs having a thickness of about 250 μm to 450 μm
The s substrate 1A is mounted on the GaAs substrate.
Buffer layer 1B, channel layer 1C, spacer layer 1D, electrons
Supply layer 1E, Schottky layer 1F, ohmic contact
The layer 1G is continuously vapor-phase epitaxially grown. concrete
At a pressure of 50 Pa to 200 Pa, for example,
At a plate temperature of 550 ° C to 700 ° C, TEG (triethyl gall
Umm) and AsH₃(Arsine) and n-type GaAs
A buffer layer 1B is grown. In addition, TMIn
(Methylindium)⁻Type InGaAs
A channel layer 1C made of is grown. And TMIn
Of TMA (trimethylaluminum) instead
) To introduce n⁻Spacer made of AlGaAs
Layer 1D, n-type electron supply layer 1E made of n-type AlGaAs
And an n-type Schottky layer 1F made of n-type AlGaAs
grow up. Furthermore, instead of stopping the introduction of TMA, TMIn
And introduce n⁺Ohmic capacitor made of InGaAs
A tact layer 1G is grown. n-type electron supply layer 1E, n-type
Yokeki layers 1F and n⁺Ohmi made of InGaAs
In growing the contact layer 1G, an n-type dopant
SiH₄(Monosilane), Si ₂H₆
(Disilane) or DESe (diethyl selenium), D
ETe (diethyl tellurium) or the like may be used. Continuous
After the vapor phase epitaxial growth is completed, low pressure MOCVD
The semiconductor substrate 101 is taken out of the device. In addition, MOCV
In addition to the D method, molecular beam epitaxy (MBE)
Muepitaxy (CBE) method, molecular layer epitaxy (ML
E) Continuous epitaxial growth may be performed by a method or the like.
No.

(2) A resist (not shown) is applied to the entire surface of the semiconductor substrate 101 taken out of the reduced pressure MOCVD apparatus, and is exposed and developed by photolithography to pattern the resist, thereby forming a mesa etching mask. I do. Using this mask for mesa etching, as shown in FIG. 4 and FIG. 5, on one main surface side of the semiconductor substrate 101, a trapezoidal portion 2 for an element main operation area having a plurality of biting grooves 2A formed on both side edges. Two source pad pedestals 3a and 3b as connection pad formation areas located on one of the element main operation area pedestals 2, and a connection pad formation located on the other of the element main operation area pedestals 2 One drain pad trapezoid 4 as a region is formed by a mesa etching process.

(3) Next, a resist (not shown) is formed on the entire surface.
Is applied, exposure and development are performed by photolithography technology to pattern the resist, thereby forming a recess etching mask. Using this recess etching mask, reactive ion etching (RIE)
The ohmic contact layer 1G is left only at a location required as a source / drain region, and the other portion of the ohmic contact layer 1G is selectively removed. Thereby, a plurality of source regions (ohmic contact regions) 61
, 61d and a plurality of drain regions (ohmic contact regions) 62e, 62f,.
., 62i are formed. RIE is for the Schottky layer 1F
Is formed until a gate electrode is to be formed. As a result of this recess etching step, the source regions 61a and 61
.., 61d and drain regions 62e, 62
, 62i are formed in plurality. The source regions 61a, 61b, ..., 61d and the drain regions 62e, 62f, ..., 62i are formed in parallel in a plan view as a plurality of stripe-shaped patterns. And, after the end of the recess etching step,
The resist is removed, and a field insulating film 5 made of SiO _x is deposited on the entire surface of one main surface of the semiconductor substrate 101 by a CVD method or the like, as shown in FIG.

(4) Next, a new resist (not shown) is applied again on the entire surface, and is exposed and developed by photolithography to pattern the resist.
An ohmic contact opening mask is formed. Using this ohmic contact opening mask, source regions (ohmic contact regions) 61a and 61 are formed by RIE.
, 61d and the field insulating film 5 on the drain regions (ohmic contact regions) 62e, 62f, ..., 62i are selectively removed. Thereafter, the ohmic contact opening mask is removed, and another resist 6 is applied on the entire surface (note that the source pad trapezoid 3
When the structures of a, 3b and the trapezoidal portion for drain pad 4 are made the same as the element main operation region, an ohmic contact opening mask is left, and this is used as a resist 6. ). Then, the resist is patterned by photolithography to form a lift-off mask 6 having openings in portions corresponding to the plurality of ohmic metal portions (source electrode / drain electrode), the source pad underlayer, and the drain pad underlayer. As shown in FIG. 7, for example, an Au-based metal film 7 is formed on the entire surface via the lift-off mask 6.
Is deposited. Then, if the resist (lift-off mask) 6 is removed, a plurality of source regions (ohmic contact regions) 61a, 61b,..., 61d and drain regions (ohmic contact regions) 62e, 62 are formed.
A plurality of corresponding source electrodes 7S and drain electrodes 7D remain above f,..., 62i. Similarly, on the field insulating film 5, a source pad underlayer 7SP
a, 7SPb and the metal film of the drain pad underlayer 7DP remain. Thus, as shown in the plan view of FIG. 8, the plurality of source electrodes 7S and the drain electrodes 7D, the source pad underlayers 7SPa and 7SPb, and the drain pad underlayer 7DP
Are patterned.

(5) Thereafter, as shown in FIG.
l / Mo / _MoO x / Mo gate electrode 13p made of multilayer film is formed 13q, 13r, · · · · ·, a 13w.
This Ti / Al / Mo / MoO _x / Mo gate electrode 13
The method of forming p, 13q, 13r,..., 13w will be described later with reference to FIGS. As a result, as shown in the plan view of FIG.
/ Mo / MoO _x / Mo multi-layer gate electrode 1
3p, 13q, 13r,..., 13w, gate lines 14, 15 and gate pad base layer 16 are formed. Note that the gate line 14 includes gate electrodes 13p, 13q; 13r, 13s; located on both sides of the source electrode 7S.
.; 13v and 13w are formed to be connected to each other on the drain pad trapezoidal portion 4 side. The relatively wide gate lines 15 are formed on the gate electrodes 13p, 13q; 13r, 13 located on both sides of the drain electrode 7D.
, 13b and 13w are connected to each other on the side of the source pad pedestals 3a and 3b, respectively. The gate pad base layer 16 is formed so as to be located between the two source pad trapezoids 3a and 3b. The gate pad base layer 16 includes gate electrodes 13p and 13q on both sides of the centrally located drain electrode 7D;
...; 13v, 13w are connected on the side of the source pad trapezoids 3a, 3b.

(6) Next, as shown in FIG.
An interlayer insulating film 21 made of SiO _x is deposited on the entire surface by using the method. FIG. 11 is a cross-sectional view corresponding to the AA cross section in FIG. Then, a resist 17 is applied on the entire surface of the interlayer insulating film 21 and is exposed and developed using photolithography technology to form a contact hole opening mask 17 as shown in FIG. The contact hole opening mask 17 includes the source electrode 7S, the drain electrode 7D, the source pad underlayers 7SPa and 7SPb, the drain pad underlayer 7DP, and the gate pad underlayer 16.
Is a mask pattern made of a resist 17 for opening an interlayer insulating film 21 on the top of the substrate and forming a contact window.

(7) Next, the interlayer insulating film 21 is etched with an oxide film etchant using a contact hole opening mask made of the resist 17 to form a drain pad contact hole 31DP, a drain electrode contact hole 31D, and a gate pad contact. Open the hole 31GP. The oxide film etching solution is HF: NH ₄ F =
A buffered hydrofluoric acid solution consisting of 1:10 is used. Al film is
In the present invention, the Al film forming the gate electrodes 13p, 13q, 13r,..., 13w is replaced with an upper Mo film / molybdenum oxide film (M
oO _x ) / Mo film, which is protected by a laminated film.
/ Al / Mo / MoO _x / Mo gate electrodes 13p, 13
, 13w are not corroded by the buffered hydrofluoric acid solution. Although not shown in the cross section of FIG. 12, the plan view of FIG. 13 further shows a source pad contact hole 31SP and a source electrode contact hole 3SP.
1S is indicated by a dashed line. FIG. 12 is a cross-sectional view taken along the line BB of FIG.
FIG. 13 also shows a drain pad contact hole 31D.
P, the drain electrode contact hole 31D, and the gate pad contact hole 31GP are indicated by dashed lines. Thereafter, the resist 17 used as the contact hole opening mask is peeled off.

(8) Then, the exposed Ti / Al / Mo
/ MoO _x / Mo gate electrodes 13p, 13q, 13r,
... A new resist 18 is applied to the entire surface of the semiconductor substrate 101, including the surface of the 13w and the interlayer insulating film 21 therearound. Then, for this resist 18,
Mask alignment (exposure) by photolithography technology
And patterning of the resist 18 by performing development,
A lift-off mask 18 is formed. Even if an alkali-based developer is used for patterning the lift-off mask 18, Ti / Al / Mo /
MoO _x / Mo gate electrodes 13p, 13q, 13r,.
.., 13w are not corroded. The gate electrode 13p, 13q, 13r,..., 13w is composed of an upper Mo film / molybdenum oxide film (Mo).
This is because it is protected by the laminated structure film of O _x ) / Mo film. The lift-off mask 18 includes the source electrode contact hole 31S, the drain electrode contact hole 31D, and the source pad contact hole 31S shown in FIG.
This pattern has an area wider than the dimensions of P, the drain pad contact hole 31DP, and the gate pad contact hole 31GP by a margin for mask alignment. Furthermore,
The pattern of the source wiring 19S connecting the source electrode contact hole 31S and the source pad contact hole 31SP and the pattern of the drain wiring 19D connecting the drain electrode contact hole 31D and the drain pad contact hole 31DP are included. The pattern of the source wiring 19S and the pattern of the drain wiring 19D have an interdigital shape having a line width wider than the line width of the source electrode contact hole 31S and the drain electrode contact hole 31D by a margin for mask alignment. An interdigitated comb-shaped pattern is formed. The lift-off process mask 18 forms an overhang shape as shown in FIG. The overhang shape is formed by controlling the film thickness of the resist 18, exposure conditions, development conditions, post-bake conditions, cure conditions, and the like.

(9) As shown in FIG. 14, Au is vapor-deposited on one main surface of the semiconductor substrate 101 via the lift-off mask 17. The Au film 19 is separated on the bottom of the opening of the resist 17 and on the resist 17. Then, if the resist 17 serving as a lift-off mask is peeled off, that is, if lift-off is performed, the resist 17 and the Au film 19 thereon are removed. As a result, FIG. 15 and FIG.
As shown in FIG.
A source wiring 19S connecting the source pad base layers 7SPa and 7SPb is formed. On the drain electrode 7D, a drain electrode 7D and a drain pad underlayer 7D are formed.
A drain wiring 19D connecting to P is formed. A plurality of source wirings 19S and a plurality of drain wirings 19D are arranged in parallel with each other, and form a comb-shaped pattern in which the source wiring 19S and the drain wiring 19D are interdigitated with each other. As shown in FIG. 1, a source bonding pad 19 made of Au is provided on each of the pad base layers 7SPa, 7SPb, 7DP, and 7GP.
SPa, 19SPb, drain bonding pad 1
9DP and a gate bonding pad 19GP are formed.

(10) Then, as shown in FIG. 2, a passivation film (protective film) 22 is formed on the entire surface. The passivation film 22 is made of an oxide film (SiO ₂ ), PSG
A film, a BPSG film, a nitride film (Si ₃ N ₄ ), or an insulating film such as a polyimide film may be used. Furthermore, source bonding pads 19SPa, 19S made of Au
A window in which the passivation film 22 above the Pb, the drain bonding pad 19DP, and the gate bonding pad 19GP is removed, and a bonding wire made of a gold (Au) line or an aluminum (Al) line having a diameter of 30 μm to 200 μm can be connected. If you provide a part,
The HEMT 201 as the semiconductor device of the present invention is completed.

Here, Ti / Al / M used for the semiconductor device (HEMT) 201 according to the first embodiment of the present invention.
o / MoO _x / Mo gate electrodes 13p, 13q, 13
,..., 13w are described with reference to FIGS.
1 will be described.

(A) Source electrode 7S and drain electrode 7D
First, a new resist (not shown) is applied to the entire surface. Then, exposure and development are performed by photolithography to pattern the resist, thereby forming a gate electrode opening mask. Using this gate electrode opening mask, the field insulating film 5 near the source electrode 7S is selectively removed by RIE. That is, as shown in FIG. 16, a gate electrode opening 5A is formed in the field insulating film 5 between the opposing source electrode 7S and drain electrode 7D to expose the surface of the Schottky layer 1F (FIG. 16). Is a partially enlarged view of FIG. 9,
In FIG. 16, the source electrode 7S and the drain electrode 7D exist at positions protruding from the illustrated region. ). If the field insulating film 5 between the source electrode 7S and the drain electrode 7D facing each other is removed when forming the source electrode 7S and the drain electrode 7D, the field insulating film formed by photolithography and RIE at this stage can be used. The step of selective removal of 5 is unnecessary.

(B) Then, the semiconductor substrate 101 is housed on a sample table inside a vapor deposition chamber of a multi-source electron beam (EB) vapor deposition apparatus, for example. Inside the deposition chamber, EB guns for Ti deposition, Al deposition, and Mo deposition are provided. This deposition chamber,
Internal pressure is 1.3 × 10 ⁻⁵ Pa to 1.2 × 10 ⁻⁸ Pa
Vacuum is exhausted until a predetermined vapor deposition pressure (background pressure) is reached. Then, first, as shown in FIG. 16, a Ti film 8 is deposited on the entire surface so as to have a thickness of about 5 nm. Thereafter, the EB gun is switched, and as shown in FIG. The EB gun was switched again, and as shown in FIG. 18, a first Mo film 10 as a metal film made of a 6A group transition element was formed on the Al film 9 to a thickness of 15 nm.
Vapor deposition is performed so as to be in the range of 100 nm to 100 nm. The EB gun for Mo evaporation is stopped, oxygen (or air) is introduced into the bell jar of the evaporation apparatus via a needle valve or the like, and the pressure is increased, for example, from 1.3 × 10 ⁻³ Pa to 1.2 × 10 ^{−. 2} Pa
Set to. Leave at this oxidizing pressure for about 5 minutes.
As shown in FIG. 9, the surface of the first Mo film 10 has a thickness of 0.7 n.
a very thin oxide film of about 10 to 10 nm (molybdenum oxide film:
MoO _x ) 10A is formed. At this time, the temperature of the semiconductor substrate 101 is set to 200 by an infrared lamp (IR lamp).
C. to 350.degree. Thereafter, the introduction of oxygen (or air) was stopped, and the pressure in the deposition chamber was set to 1.3 × 10 ⁻⁵ P
a. Vacuum is evacuated again until the pressure becomes 1.2 × 10 ⁻⁸ Pa.
If the predetermined deposition pressure, again using an EB gun for Mo deposition, transition element oxide film second on the (MoO _x film) 10A
The Mo film 11 is deposited so as to have a thickness in the range of 15 nm to 100 nm. Thus, the Ti film 8, the Al film 9, the first
The Mo film 10 and the second Mo film 11 are continuously deposited using a multi-source EB vapor deposition apparatus. In particular, if a small-sized oxidation chamber (oxidation chamber) connected to a vapor deposition chamber (vapor deposition chamber) via a gate valve is provided, and a multi-chamber configuration in which a transport mechanism using magnetic force or the like can be used to transport the small oxidation chamber, a first Mo can be obtained. Film 10, a transition element oxide film (MoO
_x film) 10A and the second Mo film 11 can be continuously formed in a short time, and productivity is also improved. In this case, the pressure at the time of oxidation may be set to about 100 kPa to 1 Pa.

(C) Next, the semiconductor substrate 101 is taken out of the bell jar of the multi-source EB vapor deposition apparatus, and a resist 12 is applied on the entire surface of the second Mo film 11. Exposure and development are performed by photolithography to pattern the resist and form a gate electrode formation mask. The gate electrode forming mask includes a gate electrode 13.
p, 13q, 13r,..., 13w, gate line 1
The resist 12 in which openings for forming the gate pads 4 and 15 and the gate pad 16 serve as a mask is processed. Then, FIG.
As shown in FIG. 1, etching was performed by RIE using the resist 12 as a mask for forming a gate electrode, and the stacked T
The i film 8, the Al film 9, the first Mo film 10, the molybdenum oxide film (MoO _x ) 10A, and the second Mo film 11 are patterned. As a result, the gate electrodes 13p, 13q, 13r,... Connected in series as shown in the plan view of FIG.
, 13w, gate lines 14, 15 and gate pad base layer 16 are formed.

(Second Embodiment) The semiconductor device of the present invention is not limited to the HEMT described in the first embodiment. For example, the MESFET described in the second embodiment may be used.

The MESFET 20 according to the second embodiment
Reference numeral 2 denotes a spacer layer 1D and an electron supply layer 1 in the semiconductor substrate 101 described in the HEMT 201 of the first embodiment.
E corresponds to a structure in which the Schottky layer 1F is omitted. That is, as shown in FIG. 22, a buffer layer 1B made of n-type GaAs having a thickness of 300 to 500 nm and an n ⁻ layer having a thickness of 200 to 500 nm are sequentially formed on a semi-insulating GaAs substrate 1A.
Layer (channel layer) 1K made of GaAs and a plurality of source regions 61a and 61 disposed on the active layer 1K.
, 61d and a plurality of drain regions 62e, 6
, 62i constitute the semiconductor substrate 102. A plurality of source regions 61a, 61b,.
61d and a plurality of drain regions 62e, 62f,...
., 62i are n ⁺ -type Ga layers each having a thickness of 5 to 10 nm.
An ohmic contact layer made of As. Gate electrodes 13p, 13q, 13r,... Are provided between each pair of the source electrode 7S and the drain electrode 7D.
., 13w are formed. A main current flowing between the plurality of source regions 61a, 61b,..., 61d and the plurality of drain regions 62e, 62f,. electrode)
Controlled by 13p, 13q, 13r,..., 13w. Multiple source regions (ohmic contact regions)
As shown in FIG. 22, a plurality of source electrodes 7S are respectively arranged on 61a, 61b,..., 61d. A plurality of drain electrodes 7D are arranged on the plurality of drain regions (ohmic contact regions) 62e, 62f,..., 62i, respectively. The plurality of drain electrodes 7D and the plurality of source electrodes 7S are arranged in parallel and alternately with each other. The source electrode 7S is formed through the opening of the interlayer insulating film 21 through the source wiring 1 in the upper layer.
9S, the drain electrode 7D is connected to the drain wiring 1
9D. Then, as shown in FIG.
The interlayer insulating film 2 of the MESFET 202 having such a structure
1. A passivation film 22 is formed on the entire surface to cover the source wiring 19S and the drain wiring 19D.

MESFET 20 according to the second embodiment
The plan view of 2 may be the same as the HEMT 201 shown in FIG. That is, the MESFET 20
2 further includes, like FIG. 1, a trapezoidal portion 2 for an element main operation region and an external circuit connection region provided adjacent to the trapezoidal portion 2 for the element main operation region. A gate pad base layer 16 is formed extending to the upper part of the field insulating film 5 provided in the connection region and having the same laminated structure as the gate electrode in the external circuit connection region. A gate bonding pad 19GP is formed on the gate pad base layer 16. On the surface of the trapezoidal portion 2 for the element main operation area, as in FIG.
9S and the drain wiring 19D are formed in an inter-digital form.

The semiconductor device according to the second embodiment (ME
FIG. 23 shows an enlarged cross-sectional view of the structure of the unit cell in the element main operation region of the (SFET) 202. In FIG. 23, the source region 61a, the gate electrode 13q, and the drain region 62f
The unit cell is constituted from one set of the above. On the left side, the source region 61a includes a set of a source region 61a, a gate electrode 13p, and a drain region 62.
e constitutes another unit cell. On the right side of the drain region 62f, not shown in FIG. 23, one set of the source region 61b, the gate electrode 13r, and the drain region 6
2f constitutes another unit cell (see FIG. 22). In this way, as shown in FIG. 22, a plurality of unit cells are connected in parallel to form a multi-channel MESFET.
202.

FIG. 23 shows the structure of one Schottky gate electrode 13q of the MESFET 20. Of course, the other gate electrodes 13p, 13r,..., 13w have exactly the same sectional structure. That is, the Schottky gate electrode 13q includes the semiconductor substrate 1, the field insulating film 5 disposed on the surface of the semiconductor substrate 1, the barrier metal layer 8 formed on the semiconductor substrate 1 in the opening of the field insulating film 5, the barrier, Al film 9 disposed on metal layer 8, cover metal layer 51 disposed on Al film 9
At least. In FIG. 23, the field insulating film 5 between the source electrode 7S and the drain electrode 7D can be omitted. For example, the field insulating film 5
The opening may be configured to expose substantially the entire surface of the element main operation region. That is, a structure in which the field insulating film 5 also functions as an element isolation insulating film in an element isolation region may be used. When the field insulating film 5 also serves as an element isolation insulating film in the element isolation region, a plurality of source electrodes 7S and drain electrodes 7D are arranged inside the opening of the field insulating film 5. In other words, a structure in which the field insulating film 5 between the opposing source electrode 7S and drain electrode 7D has already been removed when the plurality of source electrodes 7S and drain electrodes 7D are formed may be used.

In FIG. 23, the cover metal layer 51
As in the first embodiment, the first element made of a 6A group transition element is used.
It is composed of a transition element thin film 10, a transition element oxide film 10A on the first transition element thin film 10, and a second transition element thin film 11 on the transition element oxide film 10A. First
As described in the first embodiment, the first transition element thin film 10
With the laminated structure in which the transition element oxide film 10A is interposed between the second transition element thin film 11 and the second transition element thin film 11, the diffusion prevention effect of the cover metal layer 51 is smaller than that of the metal layer composed of only the 6A transition element. growing. First transition element thin film 10
The transition element oxide film 10A is formed between the second transition element thin film 11 and the second transition element thin film 11, thereby increasing the substantial thickness of the group 6A transition element thin film and the first transition element thin film 10 and the second transition element thin film 11 It is also possible to prevent the adhesion between them from deteriorating.

As described in the first embodiment, the first
The thickness of the transition element thin film 10 is 15 nm to 100 nm,
The thickness of the element oxide film 10A is 0.7 nm to 10 nm,
The thickness of the transition element thin film 11 is about 15 nm to 100 nm.
Should be set to. The thickness should be set in such a range.
With this, film peeling is suppressed, and the diffusion preventing action (diffusion
Barrier effect) can be kept high. Group 6A transition element
In this case, the transition source in FIG.
The silicon oxide film 10A is a molybdenum oxide film (MoO _x) 10
A. Mo and MoO_xComposite film (Mo laminated structure)
Film) against buffered hydrofluoric acid solution and alkaline developer
It has etching resistance and Al atoms in the underlayer 16 are expanded.
Since it hardly disperses, it functions effectively as a diffusion barrier layer.
In FIG. 23, a barrier metal is
Ti film 8, Al film 9, and first transition element thin film
First Mo film 10, MoO as transition element oxide film_x
Film 10A, second Mo film as second transition element thin film laminated
are doing.

The MESF according to the second embodiment of the present invention
The method of manufacturing the ET 202 is basically the same as that of the HEMT 201 shown in FIGS.

(1) First, on a semi-insulating GaAs substrate 1A, a buffer layer 1B made of n-type GaAs having a thickness of 300 to 500 nm and an n ⁻ layer having a thickness of 200 to 500 nm are sequentially formed.
Layer 1K made of n-type GaAs, n having a thickness of 5 to 10 nm
^An ohmic contact layer (not shown) made of ⁺ type GaAs is continuously epitaxially grown to form a semiconductor substrate 10.
Get 2. A resist (not shown) is applied to the entire surface of the semiconductor substrate 102, and is exposed and developed by photolithography to pattern the resist, thereby forming a mesa etching mask. Using this mesa etching mask, as shown in FIG. 4 and FIG.
The element main operation region trapezoidal portion 2 where A is formed, two source pad trapezoidal portions 3a and 3b as connection pad formation regions located on one side of the element main operation region trapezoidal portion 2, element main operation One drain pad trap portion 4 as a connection pad formation region located on the other side of the region trap portion 2 is formed by a mesa etching process.

(2) Next, a resist (not shown) is formed on the entire surface.
Is applied, exposure and development are performed by photolithography technology to pattern the resist, thereby forming a recess etching mask. Using this recess etching mask, reactive ion etching (RIE)
The ohmic contact layer is left only at a location required as a source / drain region, and the other portion of the ohmic contact layer 1G is selectively removed to expose the active layer 1K. Thereby, a plurality of source regions (ohmic contact regions) 61a, 61b,..., 61d and a plurality of drain regions (ohmic contact regions) 62e,
62f,..., 62i are formed. The RIE is performed until the active layer 1K is exposed, and a recess (recess) is formed in a portion where a gate electrode is to be formed. By this recess etching step, the source region 61 is formed as a convex portion surrounded by the concave portion.
, 61d and the drain region 62e,
, 62i are formed in plurality. Then, after the end of the recess etching process, the resist is removed, a CVD method, or the like as shown in FIG. 6, the field insulating film 5 made of SiO _x on the surface of the active layer 1K
Is deposited on the entire surface.

In the subsequent steps, considering that the cross-sectional structure of the semiconductor substrate 102 is different from that of the semiconductor substrate 101,
Since it is completely the same as the method of manufacturing the HEMT 201 according to the first embodiment, a duplicate description will be omitted. In the MESFET 202 manufactured by such a manufacturing method, FIG.
Since the structure of the gate electrode 13 is as shown in FIG. 1, the Al film 9 constituting the gate electrode 13 includes an upper first Mo film 10, a transition element oxide film (MoO _x film) 10A, and a second Mo film.
The film 11 is protected by the laminated structure film. Therefore, the gate electrode 13 is not corroded by an alkaline developing solution or an oxide film etching solution during the manufacturing process.
Deterioration of the characteristics of p, 13q, 13r,..., 13w is suppressed, and a high production yield and high reliability can be achieved. or,
Gate electrodes 13p, 13q, 13r,..., 13w
Is a first Mo film 10, a transition element oxide film (MoO _x film) 1
Since the laminated structure film including the first Mo and the second Mo film 11 is employed, Al is not easily diffused, and conversely, Mo does not pass through the Al film 9 and react with the Schottky layer 1F. For this reason, the semiconductor substrate 1 has good Schottky characteristics. Therefore, a high conversion conductance gm of the MESFET 202 is obtained, and the high frequency characteristics can be improved.

(Other Embodiments) It should not be understood that the description and drawings constituting a part of the disclosure of the first and second embodiments of the present invention limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, in the first and second embodiments,
Although Mo is exemplified as the group 6A transition element, Cr, W, and the like can be used in addition to Mo, as is well known. When Cr is used as the group 6A transition element, it is preferable that the cover metal layer be composed of a first Cr film / CrO _x / second Cr film. Further, the first transition element thin film and the second transition element thin film may be made of different Group 6A transition elements. For example, Cr film / MoO _x / Mo film, Cr film / Cr
O _x / Mo film, Mo film / _MoO x / Cr film, Mo film / C
rO _x / Cr film, W film / WO _x / Mo film, W film / MoO
A structure such as an _x / Mo film may be used.

In the first and second embodiments, Ti is exemplified as the barrier metal layer 8.
W, TiN, metal silicide, or the like can be used.

Further, the HEMT described in the first embodiment
Has various structures, and H is disclosed in the first embodiment.
The invention is not limited to EMT. For example, an n-type AlGaAs having a thickness of 3 to 15 nm is formed on a semi-insulating GaAs substrate via an n-type GaAs buffer layer.
Electron supply layer made of n ^- type AlGa having a thickness of 2 to 5 nm
A spacer layer made of As, a channel layer made of n ^- type GaAs having a thickness of 15 to 55 nm, and an n layer having a thickness of 10 to 25 nm.
A HEMT having an inverted structure formed by laminating a Schottky layer made of GaAs may be used. Further, a HEMT having a first electron supply layer (lower electron supply layer) and a second electron supply layer (upper electron supply layer) in which these are combined may be used. Have been. Instead of semi-insulating GaAs substrate, semi-insulating In
A P substrate may be used, and AlGaAs / InGaAs,
AlInAs other than AlGaAs / GaAs heterojunction
A HEMT using a heterojunction such as / InGaAs or Si / SiGe may be used.

In the first and second embodiments of the present invention, the element main operation region is provided on the element main operation region base 2 as shown in FIG. The structure provided on the trapezoidal portion different from the trapezoidal portion 2 or on the bottom of the concave portion between the trapezoidal portions is shown. However, the surface of the semiconductor substrate may be flattened to provide an element isolation region by proton irradiation, and the surface of the element isolation region may be used as an external circuit connection region. Alternatively, an element isolation region may be provided by a U-groove and an element isolation insulating film embedded in the U-groove, and the surface of the element isolation region may be used as an external circuit connection region.

The semiconductor device of the present invention is not limited to the HEMT described in the first embodiment or the MESFET described in the second embodiment.
For example, Schottky diode, Schottky gate type S
Needless to say, it may be an individual semiconductor element such as an IT or a Schottky gate thyristor, or a semiconductor integrated circuit composed of these. Furthermore, the semiconductor device is not limited to a semiconductor device based on a compound semiconductor, and may be a single element semiconductor such as Si.

Further, in the description of the first embodiment, the gate wiring pad 19GP, the source wiring 19S, the drain wiring 19D, and the like are formed by the lift-off method. However, the present invention is not limited to this. Alternatively, a technique using ordinary resist patterning and etching techniques may be used.

A silicon nitride film having a stoichiometric composition (Si ₃
N ₄ ) is not etched by the buffered hydrofluoric acid solution. However, a non-stoichiometric silicon nitride film (Si
N _x ) or a silicon oxynitride film containing oxygen (SiO
_{Some of xN y} ) are etched with a buffered hydrofluoric acid solution. An oxide film containing impurities such as phosphorus glass (PSG) can also be etched with a buffered hydrofluoric acid solution.
Therefore, the interlayer insulating film of the present invention is an oxide film (SiO _x ).
However, the present invention is not limited to this, but covers all insulating films that can be etched with a buffered hydrofluoric acid solution.

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0075]

According to the present invention, the uppermost cover metal layer of the electrode film has an etching resistance to the buffered hydrofluoric acid solution. By Schottky metal layer (Al)
Has the effect of preventing corrosion such as corrosion and after-corrosion.

According to the present invention, since the uppermost cover metal layer of the electrode film has etching resistance to an alkali-based developer, connection pads and interlayer wiring members are formed on the cover metal layer by a lift-off method. In the case of forming Al, it is possible to prevent the Al film as the Schottky metal layer from being corroded by the alkali-based developer.

Further, according to the present invention, the peeling of the film can be suppressed by setting the structure of the cover metal layer to a predetermined structure. Further, the Al film and the cover metal layer do not react with each other, so that it is possible to prevent the characteristics of the gate electrode forming the Schottky junction with the semiconductor layer from deteriorating.

Further, according to the present invention, it is possible to provide a manufacturing method capable of preventing the occurrence of corrosion such as corrosion and after-corrosion in the Al film. And
A semiconductor device having a gate electrode with good Schottky characteristics can be manufactured efficiently.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device (HEMT) according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line CC of FIG.

FIG. 3 is a schematic sectional view illustrating a structure of a gate electrode of the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 4 is a plan view showing a manufacturing process in a first embodiment of the present invention in a method for manufacturing a semiconductor device (HEMT) according to the present invention.

FIG. 5 is a perspective view illustrating a manufacturing process of the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 8 is a plan view showing a manufacturing step of the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step of manufacturing the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 10 is a plan view illustrating a manufacturing step of the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 11 is a sectional view taken along line AA of FIG. 10;

FIG. 12 is a sectional view taken along line BB of FIG.

FIG. 13 is a plan view showing a manufacturing step of the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a step of manufacturing the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 16 is an essential part cross sectional view showing the step of forming the gate electrode of the semiconductor device (HEMT) according to the first embodiment of the present invention;

FIG. 17 is an essential part cross sectional view showing the step of forming the gate electrode of the semiconductor device (HEMT) according to the first embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view showing a step of forming a gate electrode of the semiconductor device (HEMT) according to the first embodiment of the present invention.

FIG. 19 is a fragmentary cross-sectional view showing a step of forming a gate electrode of the semiconductor device (HEMT) according to the first embodiment of the present invention;

FIG. 20 is an essential part cross sectional view showing the step of forming the gate electrode of the semiconductor device (HEMT) according to the first embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view showing a step of forming a gate electrode of the semiconductor device (HEMT) according to the first embodiment of the present invention;

FIG. 22 is a schematic sectional view of a semiconductor device (MESFET) according to a second embodiment of the present invention.

FIG. 23 is a schematic cross-sectional view showing a structure of a gate electrode of a semiconductor device (MESFET) according to a second embodiment of the present invention.

FIG. 24 is a fragmentary cross-sectional view showing a step of forming a gate electrode of a conventional semiconductor device.

FIG. 25 is a fragmentary cross-sectional view showing a step of forming a gate electrode of a conventional semiconductor device.

FIG. 26 is an explanatory cross-sectional view illustrating Al diffusion of a gate electrode of a conventional semiconductor device.

FIG. 27 is an explanatory sectional view showing film peeling at a gate electrode of a conventional semiconductor device.

[Explanation of symbols]

1A Semiconductor substrate (semi-insulating GaAs substrate) 1B Buffer layer (n-type GaAs) 1C Channel layer (n ^- type InGaAs) 1D Spacer layer (n ^- type AlGaAs) 1E Electron supply layer (n-type AlGaAs) 1F Schottky layer (n Type AlGaAs) 1G ohmic contact layer (n ⁺ type InGaAs) 1K active layer (n ⁻ type GaAs) 2 trapezoid for element main operation area 2A biting groove 3a, 3b trapezoid for source pad 4 trapezoid for drain pad 5,85 field insulating film 6,18,33,39 resist 7S source electrode 7SPa, 7SPb source pad underlayer 7D drain electrode 7DP drain pad underlayer 8 barrier metal layer (Ti film) 9 Schottky metal layer (Al film) 10th 1 transition element thin film (first Mo film) 10A transition element oxide film ( oO _x film) 11 second transition element thin film (first 2Mo film) 13p, 13q, 13r, ····· , 13w gate electrodes 14 and 15 gate line 16, 32 a gate pad underlayer 19S source wiring 19SPa, 19SPb source Bonding pad 19D drain wiring 19DP drain bonding pad 19GP, 34A gate bonding pad 21, 81 interlayer insulating film 21A opening 31SP source pad contact hole 31S source electrode contact hole 31DP drain pad contact hole 31D drain electrode contact hole 31GP gate pad contact hole 34 Thin film of Au (wiring material) 35 Al film 36 Mo film 37 Peeling of film 38 Ti film 51 Cover metal layer 61a, 61b,..., 61d saw Regions 62e, 62f, ·····, 62i drain regions 101, 102, 103, 104 semiconductor substrate 201 HEMT 202 MESFET

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/812 F-term (Reference) 4M104 AA05 BB14 BB30 CC05 DD64 DD68 FF17 GG12 HH08 HH20 5F005 AE09 BB02 GA01 5F102 FB01 GA01 GB01 GC01 GD01 GJ05 GJ06 GK05 GL04 GM04 GM05 GM06 GM08 GN04 GN05 GQ01 GQ03 GR04 GT00 GT02 GT03 GV03 GV07 GV08 HC01 HC19

Claims (18)

[Claims] A barrier metal layer formed on a semiconductor base; and an aluminum (A) disposed on the barrier metal layer.
1) An electrode for a semiconductor device, comprising: a film; and a cover metal layer formed of a composite film of a group 6A transition element and an oxide film of the group 6A transition element disposed on the aluminum film. 2. The cover metal layer includes a first transition element thin film made of the group 6A transition element, the oxide film on the first transition element thin film, and a second transition element thin film on the oxide film. 2. The method according to claim 1, wherein
The electrode for a semiconductor device according to the above. 3. The film thickness of the first transition element thin film is 15n.
3. The electrode for a semiconductor device according to claim 2, wherein the thickness is from m to 100 nm. 4. The oxide film has a thickness of 0.7 nm to 10 nm.
The semiconductor device electrode according to claim 2, wherein the thickness is nm. 5. The film thickness of the second transition element thin film is 15 n
The electrode for a semiconductor device according to claim 2, wherein the thickness is from m to 100 nm. 6. The electrode for a semiconductor device according to claim 1, wherein the transition element of Group 6A is molybdenum (Mo). 7. A semiconductor substrate, a field insulating film disposed on a surface of the semiconductor substrate, and an opening of the field insulating film provided in an element main operation area of the semiconductor substrate, wherein A barrier metal layer formed, and aluminum (A) disposed on the barrier metal layer.
1) A semiconductor device comprising: a gate electrode including a film and a cover metal layer formed of a composite film of a group 6A transition element and an oxide film of the group 6A transition element disposed on the aluminum film. . 8. The semiconductor device further includes an external circuit connection region provided adjacent to the element main operation region, and the gate electrode is provided on the field insulating film provided in the external circuit connection region. 8. The semiconductor device according to claim 7, wherein a gate pad base layer is formed so as to extend to the external circuit connection region and has the same laminated structure as the gate electrode in the external circuit connection region. 9. An interlayer insulating film disposed on the field insulating film and an external portion connected to the gate pad underlayer at an opening of the interlayer insulating film provided on a surface of the gate pad underlayer. 9. The semiconductor device according to claim 8, further comprising a metal wiring layer for circuit connection. 10. The cover metal layer includes a first transition element thin film made of the group 6A transition element, the oxide film on the first transition element thin film, and a second transition element thin film on the oxide film. The semiconductor device according to claim 7, wherein the semiconductor device comprises: 11. The film thickness of the first transition element thin film is 15
The semiconductor device according to claim 10, wherein the thickness is in the range of nm to 100 nm. 12. The oxide film has a thickness of 0.7 nm to 1 nm.
The semiconductor device according to claim 7, wherein the thickness is 0 nm. 13. The film thickness of the second transition element thin film is 15
The semiconductor device according to claim 10, wherein the thickness is from 100 nm to 100 nm. 14. The semiconductor device according to claim 7, wherein said group 6A transition element is molybdenum (Mo). 15. A step of forming a field insulating film on a surface of a semiconductor substrate; a step of selectively removing a part of the field insulating film to form an opening exposing the semiconductor substrate; Depositing a barrier metal layer on the upper portion of the semiconductor substrate exposed on the bottom of the semiconductor device and on the field insulating film; depositing an aluminum (Al) film on the barrier metal layer; , 6A transition element and said 6A
Forming a cover metal layer comprising a composite film with a group III transition element oxide film; and selectively removing the cover metal layer, the aluminum film and the barrier metal layer, and forming the barrier metal layer inside the opening. Forming a gate electrode comprising the aluminum film and the cover metal layer. 16. The method according to claim 16, wherein the cover metal layer is formed by depositing a first molybdenum (Mo) film on the aluminum film.
The surface of the first molybdenum film is oxidized to form the group 6A transition element oxide film, and then a second molybdenum film is formed by depositing a layer on the group 6A transition element oxide film. A method for manufacturing a semiconductor device according to claim 15. 17. A step of depositing an interlayer insulating film on the cover metal layer, a step of applying a first resist on the interlayer insulating film, and selectively exposing a part of the first resist. A step of developing the first resist after the exposure; and an etching mask formed by the step of exposing and the step of developing. 17. The method for manufacturing a semiconductor device according to claim 15, further comprising a step of performing etching until the surface is exposed. 18. A step of removing the first resist, and a step of removing a second resist on the cover metal layer and the interlayer insulating film exposed at a bottom of an opening of the interlayer insulating film formed by the etching process liquid. A step of applying a resist, a step of selectively exposing a part of the second resist, and a step of developing the exposed second resist with an alkaline developer. 18. The method for manufacturing a semiconductor device according to item 17.