JP2002202765A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit for a display device, which can actualize low power consumption, while using a level shifter capable of securely converting the level of a signal with a low-voltage amplitude. SOLUTION: A source signal line drive circuit is divided into a plurality of stages of units and the operation of a source for current supply to level shifters of the respective units is subjected to on/off control. The current supply to the level shifters of stages which do not include circuits outputting pulses is stopped, and the current is supplied to only units including shift registers of stages in operation, so the power consumption can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display device and a driving circuit of the display device, and more particularly to an active matrix type display device having a thin film transistor formed on an insulator and a driving circuit of the active matrix type display device.

[0002]

2. Description of the Related Art In recent years, the miniaturization of semiconductor manufacturing technology has advanced,
With the accompanying miniaturization of LSIs, applications to small devices such as portable terminals have been progressing, and low power consumption has been required. Currently, low power supply voltage driving such as 3.3 [V] driving is required. Is the mainstream. On the other hand, LCDs (Liquid Crystal Displays), whose demand has been remarkably increasing in recent years as applications for mobile terminals and computer monitors, are often driven by signals having a voltage amplitude of 10 [V] to 20 [V]. The drive circuit has at least a circuit section driven by a corresponding high power supply voltage. Therefore, it is indispensable to connect the controller LSI driven by the low power supply voltage and the liquid crystal drive circuit driven by the high power supply voltage with a level shifter that changes the amplitude voltage width of the signal.

In recent years, not only LCDs but also electroluminescent devices (hereinafter referred to as EL devices. Here, both singlet emission and triplet emission are EL devices).
Is defined. ) Was developed,
Here, too, there is a strong demand for lower drive voltage.

[0004]

FIG. 9 shows an example of a circuit diagram of a source signal line driving circuit of a display device. Here, the start pulse, the clock signal, the digital video signal, and the like are signals input from outside the display device. Since these are supplied from the above-described controller LSI, the voltage amplitude is generally 3.3 [V]. ] Low voltage amplitude. Therefore,
In the driving circuit shown in FIG. 9, the digital video signal is subjected to the conversion of the voltage amplitude (level conversion) by the level shifter 905 immediately after the input. Clock signal,
A signal input from an external controller LSI, such as a start pulse, is similarly subjected to level conversion although not shown.

The operation of the circuit will be described. A pulse is output from the shift register 901 in accordance with the clock signal and the start pulse, and two adjacent pulses are NAND
The signal is input to the circuit 903. In the NAND circuit 903, only when a pulse having a Hi potential is input to both of the two input terminals, a pulse having a Lo potential is output from the output terminal, and this pulse is output to a buffer (referred to as Buf.) At a subsequent stage. After passing, it becomes the first latch pulse. afterwards,
The level is input to the first latch circuit 906, and the level shifter 90 is input in accordance with the input timing of the first latch pulse.
5, the latch operation of the digital video signal having undergone the level conversion is performed. After the completion of this latch operation from the first stage to the final stage, a second latch pulse is input to the terminal 19 within a retrace period, and the digital signal for one horizontal period held in the first latch circuit 906 is held. The video signal is simultaneously transferred to the second latch circuit 907. After that, a signal is written to a pixel in a row in which the gate signal line is selected, and an image is displayed.

FIG. 10A shows an example in which the level shifter 905 in FIG. 9 is constituted by a conventional level shifter. In the level shifter having such a configuration, when the voltage amplitude of the input signal (In, Inb) is as small as about 3.3 [V], normal level conversion is performed due to the influence of the threshold value of the TFT constituting the level shifter. You may not be able to do it.

Therefore, a level shifter having a configuration as shown in FIG. 10B is used. The level shifter shown in FIG. 10B performs level conversion by a differential amplifier, and can realize a reliable level conversion function even when the voltage amplitude of an input signal is small. This is a very effective circuit for voltage conversion. The level shifter using the differential amplifier shown here is disclosed in Japanese Patent Application
No. 193498.

[0008]

On the other hand, the level shifter shown in FIG. 10B requires a current source. That is, a constant current is always supplied during driving of the circuit (regardless of whether the level shifter is being driven or stopped), which hinders the reduction in power consumption of the entire display device.

[0009] Originally, the drive voltage of the drive circuit and the like has been intended to reduce the power consumption with the spread of portable terminals and the like, and the power consumption is increased by the circuit corresponding to the drive voltage reduction. It is not allowed.

The present invention has been made in view of the above-described problems, and provides a driving circuit of a display device which can cope with a low driving voltage of a peripheral circuit and can realize low power consumption. The purpose is to do.

[0011]

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention takes the following measures.

In the source signal line driving circuit shown in FIG. 9, a constant current is supplied to the level shifter 905 using a differential amplifier irrespective of whether a sampling pulse, a digital video signal, or the like is input. Therefore, in the present invention, the drive circuit is divided into a plurality of units, and a shift register is operated from a current source independent of each unit to a plurality of level shifters included in each unit (a sampling pulse is output. Current supply only in the unit. In a unit that does not output a pulse from the shift register, that is, the latch operation of the digital video signal is not performed, and thus the current supply to the level shifter of the unit is stopped. Thus, power consumption during an unnecessary period can be suppressed.

Hereinafter, the configuration of the driving circuit of the display device of the present invention will be described.

According to a display device of the present invention, in a display device in which a source signal line driving circuit and a pixel portion are formed on a substrate, the source signal line driving circuit includes a shift register for sequentially outputting pulses in accordance with a clock signal. A level shifter that converts a voltage amplitude of an input signal, and a current source that supplies a current to the level shifter, wherein the current source is configured to output a current only during a period in which a pulse is sequentially output from the shift register. It is characterized by supplying

In a display device according to the present invention, wherein a source signal line drive circuit and a pixel portion are formed on a substrate, the number of the source signal line drive circuits is 1 to x (where x is A (where a is a natural number, 1 ≦ a ≦ x) unit includes a shift register that sequentially outputs pulses according to a clock signal, and a conversion of a voltage amplitude of an input signal. Multiple level shifters to perform
An a-th current source for supplying a current to the plurality of level shifters, wherein the a-th current source is connected to the a-th unit only during a period in which a pulse is sequentially output from the shift register in the a-th unit. The current supply is performed to the plurality of level shifters in the unit (a).

In a display device according to the present invention, wherein a source signal line drive circuit and a pixel portion are formed on a substrate, the number of the source signal line drive circuits is 1 to x (where x is A unit having a natural number, x ≧ 2), a b-th unit (b is a natural number, 1 <b ≦ x) includes a shift register that sequentially outputs pulses in accordance with a clock signal, and conversion of a voltage amplitude of an input signal. Multiple level shifters to perform
A b-th current source for supplying a current to the plurality of level shifters, wherein the b-th current source is a part of a period during which pulses are sequentially output from the shift register in the (b-1) -th unit. The current is supplied to the plurality of level shifters in the b-th unit only during a period in which pulses are sequentially output from the shift register in the b-th unit.

In a display device according to the present invention, wherein a source signal line drive circuit and a pixel portion are formed on a substrate, the number of the source signal line drive circuits is 1 to x (where x is A c-th unit (where c is a natural number and 1 ≦ c <x) includes a shift register that sequentially outputs pulses in accordance with a clock signal, and a conversion of a voltage amplitude of an input signal. Multiple level shifters to perform
A c-th current source that supplies a current to the plurality of level shifters, wherein the c-th current source is a part of a period during which pulses are sequentially output from the shift register in the (c + 1) th unit; A current is supplied to the plurality of level shifters in the c-th unit only during a period in which pulses are sequentially output from the shift register in the c-th unit. 6. The display device according to claim 5, wherein the drive circuit of the display device according to claim 5 is a display device in which a gate signal line drive circuit and a pixel portion are formed on a substrate. Has a shift register that sequentially outputs pulses in accordance with a clock signal, a level shifter that converts a voltage amplitude of an input signal, and a current source that supplies a current to the level shifter, wherein the current source includes the shift register Only during the period when pulses are output sequentially from
It is characterized in that current is supplied.

In a display device according to the present invention, wherein a gate signal line drive circuit and a pixel portion are formed on a substrate, the number of the gate signal line drive circuits is 1 to y (where y is A d-th (d is a natural number, 1 ≦ d ≦ y) unit having a natural number, y ≧ 2) unit, a shift register that sequentially outputs pulses according to a clock signal, and a voltage amplitude conversion of an input signal Multiple level shifters to perform
A d-th current source for supplying a current to the plurality of level shifters, wherein the d-th current source is connected to the d-th unit only during a period in which a pulse is sequentially output from the shift register in the d-th unit. A current is supplied to the plurality of level shifters in the unit d.

In a display device according to the present invention, wherein a gate signal line driving circuit and a pixel portion are formed on a substrate, the number of the gate signal line driving circuits is 1 to y (where y is An e-th unit (e is a natural number, 1 <e ≦ y) includes a shift register that sequentially outputs pulses in accordance with a clock signal, and a conversion of a voltage amplitude of an input signal. Multiple level shifters to perform
An e-th current source for supplying a current to the plurality of level shifters, wherein the e-th current source is a part of a period during which pulses are sequentially output from the shift register in the (e-1) -th unit. The current is supplied to the plurality of level shifters in the e-th unit only during a period in which pulses are sequentially output from the shift register in the e-th unit.

In a display device according to the present invention, wherein a gate signal line drive circuit and a pixel portion are formed on a substrate, the number of the gate signal line drive circuits is 1 to y (where y is A unit having a natural number, y ≧ 2), an f-th unit (where f is a natural number, 1 ≦ f <y) is a shift register that sequentially outputs pulses in accordance with a clock signal, and a conversion of a voltage amplitude of an input signal. Multiple level shifters to perform
An f-th current source for supplying a current to the plurality of level shifters, wherein the f-th current source is configured to output a part of a period during which pulses are sequentially output from the shift register in the (f + 1) -th unit; A current is supplied to the plurality of level shifters in the f-th unit only during a period in which pulses are sequentially output from the shift register in the f-th unit.

According to a display device of the present invention, in a display device in which a source signal line driving circuit and a pixel portion are formed on a substrate, the source signal line driving circuit outputs a pulse according to an input signal; And a current source for supplying a current to the level shifter, and the current source supplies a current only during a period in which a pulse is output from the decoder. It is characterized by:

According to a display device of the present invention, in a display device in which a source signal line driving circuit and a pixel portion are formed on a substrate, the number of the source signal line driving circuits is 1 to x (where x is A (where a is a natural number, 1 ≦ a ≦ x) unit has a decoder that outputs a pulse in accordance with an input signal, and converts the voltage amplitude of the input signal. A plurality of level shifters and an a-th current source for supplying current to the plurality of level shifters, wherein the a-th current source is provided only during a period in which a pulse is output from the decoder in the a-th unit. And supplying current to the plurality of level shifters in the a-th unit.

The display device of the present invention is a display device in which a source signal line drive circuit and a pixel portion are formed on a substrate, wherein the number of the source signal line drive circuits is 1 to x (where x is A unit having a natural number, x ≧ 2), and a b-th unit (b is a natural number, 1 <b ≦ x) performs a decoder that outputs a pulse according to an input signal and converts a voltage amplitude of an input signal. A plurality of level shifters; and a b-th current source for supplying a current to the plurality of level shifters, wherein the b-th current source is connected to the b-th unit during a period when a pulse is output from the decoder in the (b-1) -th unit. In some embodiments, current is supplied to the plurality of level shifters in the b-th unit only during a period in which a pulse is output from the decoder in the x-th unit.

According to a display device of the present invention, in a display device in which a source signal line drive circuit and a pixel portion are formed on a substrate, the first to x-th source signal line drive circuits (x is A unit having a natural number, x ≧ 2), and a c-th unit (c is a natural number, 1 ≦ c <x) performs a decoder that outputs a pulse according to an input signal and converts a voltage amplitude of an input signal. A plurality of level shifters, and a c-th current source that supplies current to the plurality of level shifters, wherein the c-th current source is a part of a period during which a pulse is output from the decoder in the (c + 1) th unit. And supplying a current to the plurality of level shifters in the c-th unit only during a period in which a pulse is output from the decoder in the c-th unit.

According to a display device of the present invention, in a display device having a gate signal line driving circuit and a pixel portion formed on a substrate, the gate signal line driving circuit includes a decoder for outputting a pulse according to an input signal; And a current source for supplying a current to the level shifter, and the current source supplies a current only during a period in which a pulse is output from the decoder. It is characterized by:

According to a display device of the present invention, in a display device in which a gate signal line driving circuit and a pixel portion are formed on a substrate, the number of the gate signal line driving circuits is 1 to y (where y is A unit having a natural number, y ≧ 2), and a d-th unit (d is a natural number, 1 ≦ d ≦ y) performs a decoder that outputs a pulse in accordance with an input signal, and converts a voltage amplitude of an input signal. A plurality of level shifters, and a d-th current source that supplies current to the plurality of level shifters, wherein the d-th current source is provided only during a period in which a pulse is output from the decoder in the d-th unit. And supplying current to the plurality of level shifters in the d-th unit.

In a display device according to the present invention, wherein a gate signal line driving circuit and a pixel portion are formed on a substrate, the number of the gate signal line driving circuits is 1 to y (where y is An e-th unit (e is a natural number, 1 <e ≦ y) includes a decoder that outputs a pulse according to an input signal and a conversion of a voltage amplitude of an input signal. A plurality of level shifters; and an e-th current source for supplying current to the plurality of level shifters, wherein the e-th current source is connected to a pulse output from the decoder in the (e-1) -th unit. In some embodiments, current is supplied to the plurality of level shifters in the e-th unit only during a period in which a pulse is output from the decoder in the e-th unit.

According to a display device of the present invention, in which a gate signal line driving circuit and a pixel portion are formed on a substrate, the number of the gate signal line driving circuits is 1 to y (where y is A unit having a natural number, y ≧ 2), and an f-th unit (where f is a natural number, 1 ≦ f <y) performs a decoder that outputs a pulse in accordance with an input signal and converts a voltage amplitude of an input signal. A plurality of level shifters; and an fth current source for supplying current to the plurality of level shifters, wherein the fth current source is a part of a period during which a pulse is output from the decoder in the (f + 1) th unit. And supplying current to the plurality of level shifters in the f-th unit only during a period in which a pulse is output from the decoder in the f-th unit.

[0029] In the display device of the present invention, the source signal line driving circuit, the gate signal line driving circuit, and the pixel portion may include:
It is formed on a glass substrate, a plastic substrate, a stainless steel substrate, or a single crystal wafer.

The display device according to the present invention is characterized in that the driving circuit and the pixel portion are formed integrally on the same substrate.

The display device according to the present invention is characterized in that the drive circuit and the pixel portion are formed on different substrates.

[0032]

FIG. 1 is a diagram showing a configuration of a drive circuit of a display device according to the present invention. The source signal line drive circuit is divided for each appropriate number of stages, and the division unit (hereinafter, referred to as the division unit)
Each unit has a current source to the level shifter. A source signal line driving circuit is formed by repeating a unit indicated by a dotted frame 100 in a plurality of stages, for example, x stages. At this time, the number of shift register stages per unit is necessarily set to “the total number of shift register stages /
It is not necessary to divide equally as in “x”. The source signal line driver circuit includes a shift register 101, a NAND circuit 102,
Buffer 103, NOR circuit 104, level shifter current source 105, level shifter 106, first latch circuit 1
07, a second latch circuit 108, a pixel 109, and the like.

The level shifter current source 105 and the level shifter 106 have a configuration as shown in FIG. As in the case of the level shifter used in the source signal line driving circuit shown in FIG. 9, the signal level is converted using a differential amplifier. The level shifter current source 105 corresponds to a block indicated by 201 in FIG.
03 and 204 are conducted, and current can be supplied to each level shifter.

However, the present invention can be used for general level shifters having a current source, and the configuration of the level shifter itself is not limited to this form, but may be another form.

The signal input to the input terminal 31 is NOR
This is a pulse obtained by inverting the output pulse of the circuit 104. NO
The output pulse (first latch pulse) from the NAND circuit of each stage is input to the R circuit 104. That is, in a certain unit, a pulse having a Hi potential is input to any of the input terminals of the NOR circuit 104 during a period in which any one of the shift registers is operating, and a pulse having a Lo potential is output from the NOR circuit 104. Pulse is output.
This pulse is inverted by an inverter or the like, is input to the input terminal 31 of the level shifter current source 105, and supplies a current as described above. While the operation of the shift register is stopped, the Lo potential is input to any of the input terminals of the NOR circuit 104 (the first latch pulse is not output), so that the level shifter current source 10
The Lo potential is input to the input terminal 31 of No. 5 to cut off the current.

The operation will be described with reference to the timing chart shown in FIG. The first unit outputs the first latch pulse from the first stage to the k-th stage.
It has an ND circuit. The outputs of these NAND circuits are connected to the level shifter current source 105 connected to the first unit.
Is input to a NOR circuit 104 for controlling. The second unit has a NAND circuit that outputs the first latch pulse of the (k + 1) th stage to the mth stage. Outputs of these NAND circuits are input to a NOR circuit 110 for controlling the level shifter current source 105 connected to the second unit. The third unit is the (m + 1) th unit
N for outputting the first latch pulse from the stage to the n-th stage
It has an AND circuit. The output of these NAND circuits is
Level shifter current source 11 connected to third unit
3 is input to a NOR circuit 112 for controlling the control circuit 3.
The same applies to the subsequent steps, and the processing is repeated up to the last x stages.

During the period from the first stage NAND output to the k-th stage NAND output, a pulse is sequentially input to the NOR circuit 104, and during that period, the NOR circuit 104 is connected to the first unit. A current is supplied from a current source 105 (described as LS power supply 1 in FIG. 4). Here, the current is supplied only to the level shifter belonging to the first unit. After the completion of the k-th NAND output, the shift register to the NAND circuit in the first unit do not operate. Therefore, all inputs to the NOR circuit 104 become Lo potential, and the current source 105 is cut off.

Subsequently, a pulse is output from the (k + 1) th stage NAND circuit. The k + 1-th stage NAND circuit has
The output pulse belonging to the second unit is input to a NOR circuit 110 which continues to a current source 111 (denoted as LS power supply 2 in FIG. 4) connected to the second unit, and the supply of current is started. . Here, the current is supplied only to the level shifter belonging to the second unit. M-th NAN
After the D output ends, the shift register to the NAND circuit in the second unit do not operate. Therefore NO
All the inputs to the R circuit 110 have the Lo potential, and the current source 1
Block 11

By repeating this procedure from the third unit to the last x-th unit, current is supplied only to the operating unit, that is, the unit including the pulse output stage. Compared to the case where the entire source signal line drive circuit controls the current source using one NOR circuit,
Current supply can be performed only to necessary parts.

According to the above method, the supply of the constant current to the level shifter can be stopped during a period in which no pulse is output from the shift register, which contributes to low power consumption. In particular, Japanese Patent Application No. 2000-240332 and Japanese Patent Application No. 2
In the inventions described in Japanese Patent Application Nos. 000-249083 and 2000-305624, when a still image is displayed, a part of the driving circuits is stopped to reduce the power consumption. Power can be used.

In the present invention, the level conversion of a digital video signal in the source signal line driving circuit has been described by way of example. However, the present invention is not particularly limited. Can be applied to any display device that performs level conversion of each signal using a level shifter that requires a current source, and of course can be applied to a gate signal line driving circuit. .

Further, the source signal line drive circuit shown in this embodiment is of a type in which pulses are sequentially output by the operation of the shift register. It can be easily applied to other types of driving circuits that perform the above.

[0043]

Embodiments of the present invention will be described below.

[Embodiment 1] FIG. 3 is a diagram showing a configuration example of a source signal line drive circuit of a display device according to the present invention. Shift register 301, scanning direction switching analog switch 30
2. NAND circuit 303, buffer 304, NOR circuit 305, inverter 306, level shifter current source 30
7, a level shifter 308, a first latch circuit 309, a second latch circuit 310, a pixel 311 and the like.

In the embodiment, the source signal line drive circuit is divided into a plurality of units, each unit is provided with a current source, and only the current source in the operating unit supplies current. As described above, the first latch pulse output from the NAND circuit without being unitized may be input to the NOR circuit to perform ON / OFF control of the operation of the current source. However, the NOR circuit 3 shown in FIG.
05 is merely a schematic example, and it is not practical to use a NOR circuit having terminals to which output pulses of all stages are actually input. May be appropriately configured. In the circuit shown in this embodiment, the current source can be stopped and the current supply can be stopped during the flyback period.

Example 2 Consider the operation of the power supply for the level shifter in the drive circuit shown in the embodiment and Example 1. The first latch pulse output from the NAND circuit is input to the first latch circuit via a buffer. At the same time, it is input to the NOR circuit, and as a result, the current source for the level shifter is turned on, and the level conversion of the digital video signal is performed. At this time, the ON timing of the level shifter current source may be delayed from the input timing of the latch pulse to the first latch circuit due to rounding or delay of the pulse. In such a case, there is a possibility that the current supply to the level shifter may not be performed normally at the timing between the units. In order to actually apply the present invention to a driving circuit, it is necessary to give a margin to the ON / OFF timing of the current source in consideration of such points. Therefore, in this embodiment, a configuration for solving such a problem will be described.

Referring to FIG. Embodiment and Example 1
In the control of the level shifter power supply, that is, NO
In the present embodiment, the output from the shift register is used, while the NAND output is used as the input to the R circuit. As an example of the circuit configuration, as in the embodiment, it is preferable to control the level shifter power supply for each unit as shown in FIG.

As the shift register included in the driving circuit of this embodiment shown in FIG. 6, a general D-flip-flop (D-FF) type as shown in FIG. 17A is used. This D-FF holds the potential of the input terminal at the timing of the falling edge of the clock signal (CK), and remains in the holding state until the next falling edge of the clock signal. Therefore, the input and output are as shown in FIG. The output pulses are sequentially output with twice the pulse width of the clock signal, and each pulse has a form in which half of the pulse width of each pulse overlaps.

As shown in the timing chart of FIG. 8A, the output of the shift register input to the NAND circuit is such that the pulses of the adjacent stages overlap. This is Figure 1
7 as described above. The period in which the LS power supply 1 is ON is a period from when a pulse is output from the first-stage shift register in the first unit to when the pulse output from the k-th stage shift register ends. is there. Subsequently, when a pulse is output from the (k + 1) th stage shift register in the second unit, the LS power supply 2 is turned on. Here, since the output pulse of the k-th stage shift register and the output pulse of the (k + 1) -th stage shift register overlap, the LS power source 1 and the LS power source 2
A period during which both are ON can be provided. That is, since the pulse of the last stage of the a-th unit (a is a natural number, 1 ≦ a ≦ x) and the pulse of the first stage of the (a + 1) -th unit overlap each other, the period of the a-th unit is
The current sources of the (a + 1) th unit both supply current. With such a timing, current can be normally supplied even at the time of level conversion at a timing across units due to the above-described pulse delay or the like.

[Embodiment 3] In this embodiment, Embodiment 2
A method of supplying a current at the time of level conversion of timing across units by a method different from that described above will be described.

In the second embodiment, in order to provide an overlap period in the ON timing of the level shifter current source,
A means using an output pulse from the shift register as an input to the R circuit was adopted. In the present embodiment, the input to the NOR circuit uses the output pulse from the NAND circuit in the same manner as in the embodiment.
By inputting an output pulse from the circuit to the NOR circuit, an overlap period is provided at the ON timing of the level shifter current source.

Referring to the circuit diagram of FIG. 7 and the timing chart shown in FIG. Focusing on the input to the NOR circuit 710 for controlling the ON / OFF of the level shifter current source 711 connected to the second unit, the unit from the preceding stage, that is, the last stage NAND circuit 702 in the first unit, The output is input to both NOR circuits 704 and 710. Therefore, at the timing when the pulse is output from the NAND circuit 702,
The level shifter power supplies 705 and 711 are both ON.

This will be described with reference to a timing chart. The final stage NAND output in the first unit is described as NAND output k. The first stage NAND output in the second unit is described as NAND output k + 1. Here, the NAND output k is used to control the ON / OFF of the level shifter current source 705 in the first unit and the ON / OFF of the level shifter current source 711 in the second unit. Are input to both the NOR circuit 710 and the level shifter current sources 705 and 711. For example, the pulse of the last stage of the b-th unit is
NO for controlling the current source for the level shifter of the +1 unit
By being input to the R circuit, during this period, the current sources of the b-th (b is a natural number, 1 ≦ b <x) unit and the (b + 1) -th unit both supply current. In this way, by a method different from that of the second embodiment, it is possible to supply current normally even at the time of level conversion at a timing that straddles each unit due to the above-described pulse delay or the like.

In this embodiment, the case of one-directional scanning has been described as an example. However, a driving circuit capable of switching the scanning direction can be implemented by a similar method. A pulse may be obtained from the first stage or the next stage of the subsequent unit. Further, in the operation between the units, it is not necessary to obtain only the last-stage pulse of the preceding unit, and other pulses may be obtained.

[Embodiment 4] In this embodiment, the TFTs of the pixel portion of the display device of the present invention and the drive circuit portions (source signal line side drive circuit and gate signal line side drive circuit) provided around the pixel portion are provided.
Will be described at the same time. However, for the sake of simplicity, a CMOS circuit, which is a basic unit for the drive circuit unit, is illustrated.

Referring to FIG. First, in this embodiment, a substrate 5 made of glass such as barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass, etc.
001 is used. Note that the substrate 5001 is not limited as long as it has a light-transmitting property, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a base film 5002 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 5001. In this embodiment, the base film 5002
Is used, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. Base film 500
As the first layer of No. 2, a plasma CVD
₄ , a silicon oxynitride film 5001a formed using NH ₃ and N ₂ O as reaction gases is formed in a thickness of 10 to 200 [nm] (preferably 50 to 100 [nm]). In this embodiment, the film thickness 50
[nm] silicon oxynitride film 5002a (composition ratio Si = 32
[%], O = 27 [%], N = 24 [%], H = 17 [%]. Next, as the second layer of the base film 5002,
Using a plasma CVD method, a silicon oxynitride film 5002b formed by using SiH ₄ and N ₂ O as reaction gases is reduced to 50 to 50%.
The layer is formed to a thickness of 200 [nm] (preferably 100 to 150 [nm]). In this embodiment, a silicon oxynitride film 5002b having a thickness of 100 nm (composition ratio: Si = 32%, O = 59)
[%], N = 7 [%], H = 2 [%]).

Next, semiconductor layers 5003 to 5005 are formed on the underlying film.
006 is formed. As the semiconductor layers 5003 to 5006, a semiconductor film having an amorphous structure is formed by a known method (sputtering,
After forming a film by LPCVD or plasma CVD, a known crystallization treatment (laser crystallization, thermal crystallization, or thermal crystallization using a catalyst such as nickel) is performed. The formed crystalline semiconductor film is patterned and formed into a desired shape. The semiconductor layers 5003 to 50
06 is 25 to 80 [nm] (preferably 30 to 60 [nm])
Formed with a thickness of Without limitation on the material of the crystalline semiconductor film, preferably silicon (silicon) or silicon germanium _{(Si X Ge 1-X (} X = 0.0001~0.0
2)) It is good to form with an alloy etc. In this example, after a 55 [nm] amorphous silicon film was formed by a plasma CVD method, a solution containing nickel was held on the amorphous silicon film. After dehydrogenation (500 [° C.], 1 hour) of this amorphous silicon film, thermal crystallization (550 [° C.], 4 hours) is performed, and laser annealing for further improving crystallization is performed. Then, a crystalline silicon film was formed by performing a heat treatment. Then, semiconductor layers 5003 to 5006 were formed from the crystalline silicon film by a patterning process using a photolithography method.

After the formation of the semiconductor layers 5003 to 5006, a slight amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 [Hz], and the laser energy density is 100 to 40.
0 [mJ / cm ² ] (typically 200 to 300 [mJ / cm ² ]). When a YAG laser is used, its second harmonic is used to set the pulse oscillation frequency to 1 to 10 kHz and the laser energy density to 300 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ / cm ^2]. ]) Then, a laser beam condensed linearly with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is irradiated.
May be set as 50 to 90 [%].

Next, a gate insulating film 5007 covering the semiconductor layers 5003 to 5006 is formed. Gate insulating film 50
07 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by using a plasma CVD method or a sputtering method. In this embodiment, 110 [nm] is obtained by the plasma CVD method.
Silicon oxynitride film (composition ratio Si = 32 [%], O =
59 [%], N = 7 [%], H = 2 [%]). Needless to say, the gate insulating film 5007 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicat
e) and O ₂ were mixed, the reaction pressure was 40 [Pa], and the substrate temperature was 30.
It can be formed by discharging at a high-frequency (13.56 [MHz]) power density of 0.5 to 0.8 [W / cm ₂ ] at 0 to 400 [° C.]. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

Next, a film thickness of 2 is formed on the gate insulating film 5007.
A first conductive film 5008 of 0 to 100 [nm] and a film thickness of 100
A second conductive film 5009 of about 400 [nm] is stacked. In this embodiment, a first conductive film 5007 made of a TaN film having a thickness of 30 [nm] and a second conductive film 5008 made of a W film having a thickness of 370 [nm] are formed by lamination. The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set it to 0 [μΩcm] or less. The resistivity of the W film can be reduced by enlarging the crystal grains.
When there are many impurity elements such as oxygen in the film, crystallization is hindered and the resistance is increased. Therefore, in this embodiment, high-purity W
(Purity: 99.9999 [%]) by forming a W film with sufficient care so as not to mix impurities from the gas phase at the time of film formation by a sputtering method using a target having a resistivity of 9 to 9%. 20 [μΩcm] was achieved.

In this embodiment, the first conductive film 500
8 was TaN, and the second conductive film 5009 was W. However, the present invention is not limited thereto, and any of Ta, W, Ti, Mo, Al, and C may be used.
It may be formed of an element selected from u, Cr, and Nd, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, A
An alloy composed of g, Pd, and Cu may be used. Further, the first conductive film is formed of a Ta film, the second conductive film is formed of a W film, and the first conductive film is formed of a TiN film.
The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of an Al film, the first conductive film is formed of a TaN film,
The second conductive film may be a combination of a Cu film.

Next, as shown in FIG. 11B, a mask 5010 made of a resist is formed by photolithography.
Is formed, and a first etching process for forming an electrode and a wiring is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, as the first etching condition, ICP (Inductively Coupled Plas
ma: Inductively coupled plasma) Using an etching method, using CF ₄ , Cl _2, and O ₂ as etching gases, setting the respective gas flow ratios to 25/25/10 [sccm], and applying a pressure of 1 [Pa]. And 500 [W] RF (13.56 [M]
Hz]) Power was applied to generate plasma to perform etching. Here, a dry etching apparatus (Model E645-IC) using ICP manufactured by Matsushita Electric Industrial Co., Ltd.
P) was used. 150 [W] on substrate side (sample stage)
(13.56 [MHz]), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered. The etching rate for W under the first etching condition is 200.39 [nm / min.], And TaN
Is 80.32 [nm / min.], And the selectivity ratio of W to TaN is about 2.5. Further, the taper angle of W is about 26 ° under the first etching condition.

Thereafter, as shown in FIG. 11B, the second mask was changed to the second etching condition without removing the mask 5010 made of resist, and CF ₄ and Cl ₂ were used as etching gases. The ratio is 30/30 [sccm] and 1
At a pressure of [Pa], 500 [W] RF (1
3.56 [MHz]) power was supplied to generate plasma, and etching was performed for about 30 seconds. An RF (13.56 [MHz]) power of 20 [W] is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF
_Under the second etching condition in which ₄ and Cl ₂ are mixed, both the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 [n].
m / min.], and the etching rate for TaN is 66.43.
[nm / min.]. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased at a rate of about 10 to 20%.

In the first etching process, the shape of the resist mask is made appropriate,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 degrees. Thus, the first-shaped conductive layers 5011 to 5015 including the first conductive layer and the second conductive layer by the first etching process.
(First conductive layers 5011a to 5015a and second conductive layers 5011b to 5015b) are formed. Gate insulating film 5
007, the first shape conductive layers 5011 to 50
The region not covered with 15 is etched to about 20 to 50 [nm] to form a thinned region.

Then, a first doping process is performed without removing the resist mask to add an impurity element imparting n-type to the semiconductor layer (FIG. 5B). The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose is 1 × 10 ¹³
５5 × 10 ¹⁵ [atoms / cm ² ] and the acceleration voltage is 60-1
It is performed as 00 [keV]. In this embodiment, the dose is 1.5
The measurement was performed at × 10 ¹⁵ [atoms / cm ² ] and the acceleration voltage was 80 [keV]. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the first
The conductive layers 5011 to 5015 having the above-mentioned shape serve as masks for the impurity element imparting n-type, and the high-concentration impurity regions 5016 to 5019 are formed in a self-aligned manner. 1 × 10 ²⁰ to 1 × 10 ^{21 in the} high concentration impurity regions 5016 to 5019
An impurity element imparting n-type is added in a concentration range of [atoms / cm ³ ].

Next, as shown in FIG. 11C, a second etching process is performed without removing the resist mask. Here, CF ₄ , Cl _2, and O are used as etching gases.
₂ and the respective gas flow ratios are 20/20/20
[sccm] and a pressure of 1 [Pa] on the coil-type electrode
An RF (13.56 [MHz]) power of [W] was supplied to generate plasma to perform etching. An RF (13.56 [MHz]) power of 20 [W] is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Second
The etching rate for W in the etching process is 12
At 4.62 [nm / min.], The etching rate for TaN is 20.67 [nm / min.], And the selectivity ratio of W to TaN is 6.05. Therefore, the W film is selectively etched. The taper angle of W became 70 ° by the second etching. By this second etching process, second conductive layers 5020b to 5024b are formed. on the other hand,
The first conductive layers 5011a to 5015a are hardly etched to form first conductive layers 5020a to 5024a.

Next, a second doping process is performed. The doping is performed using the second conductive layers 5020b to 5024b as a mask for the impurity element, so that the semiconductor layer below the tapered portion of the first conductive layer is doped with the impurity element. In this embodiment, P is used as the impurity element.
(Phosphorus) with a dose of 1.5 × 10 ¹⁴ [atoms / c
m ² ], a current density of 0.5 [μA], and an acceleration voltage of 90 [keV]. Thus, low-concentration impurity regions 5025 to 5028 overlapping with the first conductive layer are formed in a self-aligned manner. These low concentration impurity regions 5025 to 502
The concentration of phosphorus (P) added to 8 was 1 × 10 ^{17 to} 5 ×
10 ¹⁸ [atoms / cm ³ ], and has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer.
Note that in the semiconductor layer overlapping with the tapered portion of the first conductive layer, the impurity concentration is slightly reduced from the end of the tapered portion of the first conductive layer toward the inside, but is approximately the same. . Further, the high-concentration impurity regions 5016 to
An impurity element is also added to 5019 (FIG. 12).
(A)).

Next, as shown in FIG. 12B, the mask made of the resist is removed, and then a third etching process is performed by using a photolithography method. This third etching treatment is performed in order to partially etch the tapered portion of the first conductive layer so that the tapered portion overlaps with the second conductive layer. However, a mask made of the resist 5029 is formed in a region where the third etching is not performed.

Etching in Third Etching Process
The condition is that Cl is used as an etching gas. _TwoAnd SF₆And
The first and second gas flow ratios were 10/50 [sccm].
And ICP etching method as in the second etching.
Do it. Note that TaN in the third etching process is
The etching rate is 111.2 nm / min.
The etching rate for the gate insulating film is 12.8 [nm / mi
n.].

In this embodiment, etching was performed by applying a 500 [W] RF (13.56 [MHz]) power to the coil-type electrode at a pressure of 1.3 [Pa] to generate plasma. . The RF (13.56) of 10 [W] is also provided on the substrate side (sample stage).
[MHz]) Power is applied and a substantially negative self-bias voltage is applied. As described above, the first conductive layers 5030a to 5030a-5
032a is formed.

By the third etching, impurity regions (LDD regions) 5033 to 5034 which do not overlap with the first conductive layers 5030a to 5032a are formed. Note that impurity regions (GOLD regions) 5025 and 5028
Remain over the first conductive layers 5020a and 5024a, respectively.

As described above, in the present embodiment, the impurity regions (LDD regions) 5033 to 533 which do not overlap with the first conductive layer
034 and an impurity region (GOLD) overlapping the first conductive layer.
Regions) 5025 and 5028 can be formed at the same time, and can be separately formed according to the TFT characteristics.

Next, after removing the resist mask, the gate insulating film 5007 is etched. The etching process here is performed using CHF ₃ as an etching gas and a reactive ion etching method (RIE method). In this embodiment, the chamber pressure is 6.7 [Pa], and the RF is
The third etching process was performed at a power of 800 [W] and a CHF ₃ gas flow rate of 35 [sccm]. As a result, a part of the high-concentration impurity regions 5016 to 5019 is exposed, and the gate insulating film 5
007a to 5007d are formed.

Next, a new mask 50 made of resist is used.
35 is formed and a third doping process is performed. This third
Is obtained by adding an impurity element imparting a second conductivity type (p-type) opposite to the first conductivity type (n-type) to a semiconductor layer serving as an active layer of a p-channel TFT by the doping process. A region 5036 is formed (FIG. 12C). First
Is used as a mask for an impurity element, and an impurity element imparting p-type is added to form an impurity region in a self-aligned manner.

In this embodiment, the impurity region 5036 is formed by an ion doping method using diborane (B ₂ H ₆ ). At the time of the third doping process, the semiconductor layer forming the n-channel TFT is made of a resist mask 5.
035. First doping process and second doping
Is added to the impurity regions 5036 at different concentrations by the doping process, but the concentration of the impurity element imparting p-type is 2 × 10 ²⁰ to 2 × 10 ²¹ [atoms / By performing the doping treatment so as to obtain cm ³ ], there is no problem because it functions as the source region and the drain region of the p-channel TFT.

Through the above steps, impurity regions are formed in the respective semiconductor layers. In this embodiment, the method of doping the impurity (B) after etching the gate insulating film is described; however, the impurity may be doped without etching the gate insulating film.

Next, a mask 5035 made of resist is used.
Is removed to form a first interlayer insulating film 5037 as shown in FIG. The first interlayer insulating film 5037 is formed of an insulating film containing silicon with a thickness of 100 to 200 [nm] by a plasma CVD method or a sputtering method. In this embodiment, a film thickness of 15
A silicon oxynitride film of 0 [nm] was formed. Needless to say, the first interlayer insulating film 5037 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 1 [ppm] or less,
Preferably in a nitrogen atmosphere of 0.1 [ppm] or less,
The heat treatment may be performed at 700 ° C., typically 500 to 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA)
Law) can be applied.

In this embodiment, at the same time as the above-described activation treatment, Ni used as a catalyst during crystallization is gettered into an impurity region containing a high concentration of P, and the semiconductor layer mainly serving as a channel formation region is formed. The nickel concentration in is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

The activation process may be performed before forming the first interlayer insulating film 5037. However, when the wiring material used is weak to heat, after forming an interlayer insulating film 5037 (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment. Preferably, an activation treatment is performed.

Alternatively, a doping process may be performed after the activation process to form the first interlayer insulating film 5037.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film 5037. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When a laser annealing method is used as the activation treatment, it is preferable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, as shown in FIG. 13B, a second interlayer insulating film 5038 made of an organic insulating material is formed on the first interlayer insulating film 5037. In this embodiment, the film thickness is 1.
An acrylic resin film of 6 [μm] was formed. Next, patterning for forming a contact hole reaching each of the impurity regions 5016, 5018, 5019, and 5036 is performed.

As the second interlayer insulating film 5038, a film made of an insulating material containing silicon or an organic resin is used. As the insulating material containing silicon, silicon oxide, silicon nitride, or silicon oxynitride can be used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used.

In this embodiment, a silicon oxynitride film formed by a plasma CVD method was formed. Note that the thickness of the silicon oxynitride film is preferably 1 to 5 μm (more preferably 2 to 4 μm). In addition, dry etching or wet etching can be used for forming the contact hole. However, considering the problem of electrostatic breakdown at the time of etching, it is preferable to use a wet etching method.

Further, since the first interlayer insulating film 5037 and the second interlayer insulating film 5038 are simultaneously etched in the formation of the contact hole, the material for forming the second interlayer insulating film 5038 in consideration of the shape of the contact hole. It is preferable to use a material having a higher etching rate than the material for forming the first interlayer insulating film 5037.

Then, each impurity region 5016, 501
Wirings 5039 to 5044 electrically connected to the wirings 8, 5019 and 5036 are formed. Here, the film thickness 50
[nm] Ti film and 500 [nm] thick alloy film (Al and Ti
An alloy film is formed by patterning, but another conductive film may be used.

As described above, the n-channel type TFT,
a driving circuit having a p-channel TFT, a pixel TFT,
The pixel portion having a storage capacitor can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate.

As for the storage capacitor, a necessary portion may be selectively doped with impurities before forming the gate conductive film to form a capacitor. According to this method, the number of photoresist masks is increased by one, but a storage capacitor can be formed without applying a bias.

Subsequently, a third interlayer insulating film 5045 is formed. In this step, the surface on which the TFT is formed is flattened to form a subsequent pixel electrode. Therefore, it is desirable that the insulating film be formed of an insulating film made of a resin film such as acrylic, which has excellent flatness. Next, a pixel electrode (reflective electrode) 5046 is formed by forming and patterning an MgAg film thereon (FIG. 1).
3 (C)).

On the other hand, a counter substrate 5047 is prepared. FIG.
As shown in FIG. 4A, a color filter layer 5048 to 5050 and an overcoat layer 505 are provided on the opposite substrate 5047.
Form one. The color filter layer is located above the TFT,
Color filters 5048 and 5049 of different colors are formed so as to overlap with each other and also serve as a light shielding film. The color filter layer of each color is made of a mixture of a resin and a pigment.
It is formed to a thickness of about 3 [μm]. For this, a photosensitive material can be used to form a predetermined pattern using a mask. At the same time, a spacer is formed using this color filter layer (not shown). This may be formed by overlapping color filters. The height of the spacer is 1 to 4 times the thickness of the overcoat layer 5051.
By considering [μm], the thickness can be set to 2 to 7 [μm], preferably 4 to 6 [μm], and the height can reduce the gap when the active matrix substrate and the counter substrate are bonded to each other. Form. The overcoat layer 5051 is formed using a photocurable or thermosetting organic resin material, and for example, polyimide or an acrylic resin may be used.

After forming the overcoat layer 5051,
A counter electrode 5052 made of a transparent conductive film is formed by patterning. After that, an alignment film 5053 is formed on both the active matrix substrate and the counter substrate, and a rubbing process is performed.

After that, the active matrix substrate and the counter substrate are bonded with a sealant 5055. A filler is mixed in the sealant 5055, and the two substrates are bonded at a uniform interval by the filler and the spacer. Subsequently, a liquid crystal material 50 is provided between the two substrates.
Inject 54 and completely seal with sealant (not shown). As the liquid crystal material 5054, a known liquid crystal material may be used. As described above, an active matrix liquid crystal display device as shown in FIG. 14A is completed.

Although the TFT in the active matrix type liquid crystal display device manufactured by the above-described process has a top gate structure, a TFT having a bottom gate structure is used.
This embodiment can be easily applied to TFTs having other structures. Further, by forming the pixel electrode with a transparent conductive film, a transmissive display device can be obtained.

Although a glass substrate is used in this embodiment, the present invention is not limited to a glass substrate but can be applied to a case other than a glass substrate such as a plastic substrate, a stainless steel substrate, or a single crystal wafer. It is.

[Embodiment 5] The display device of the present invention has various uses. In this embodiment, an application example of an electronic device in which the display device of the present invention is incorporated will be described.

Examples of such electronic devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, digital cameras, personal computers, televisions, projectors, and the like. Examples of these are shown in FIGS.

FIG. 15A shows a liquid crystal display (LC).
D), the housing 3301, the support 3302, and the display unit 3
303 and the like. The display device of the present invention can be used for the display portion 3303.

FIG. 15B shows a video camera, which includes a main body 3311, a display section 3312, an audio input section 3313, an operation switch 3314, a battery 3315, and an image receiving section 331.
6 and so on. The display device of the present invention can be used for the display portion 3312.

FIG. 15C shows a personal computer, which includes a main body 3321, a housing 3322, a display portion 3323,
A keyboard 3324 and the like are included. The display device of the present invention can be used for the display portion 3323.

FIG. 15D shows a portable information terminal, which includes a main body 3331, a stylus 3332, a display portion 3333, operation buttons 3334, an external interface 3335, and the like. The display device of the present invention can be used for the display portion 3333.

FIG. 16A shows a mobile phone, and the main body 34 is provided.
01, audio output unit 3402, audio input unit 3403, display unit 3404, operation switch 3405, antenna 3406
including. The display device of the present invention can be used for the display portion 3404.

FIG. 16B shows an audio reproducing apparatus, specifically, a car audio system.
2. Including operation switches 3413 and 3414. The display device of the present invention can be used for the display portion 3412. In this embodiment, the in-vehicle audio is shown, but the present invention may be applied to a portable or home-use audio reproducing apparatus.

FIG. 16C shows a digital camera, which includes a main body 3501, a display section (A) 3502, an eyepiece section 3503,
An operation switch 3504, a display portion (B) 3505, and a battery 3506 are included. The display device of the present invention can be used for the display portion (A) 3502 and the display portion (B) 3505.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electronic devices in various fields. In addition, any of the configurations shown in the first to fourth embodiments may be applied to the electronic device of the present embodiment.

According to the present invention, an external controller LSI
It is possible to provide a driving circuit of a display device which can cope with a constant driving voltage and realize low power consumption.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a drive circuit of a display device of the present invention.

FIG. 2 is a circuit diagram of a level shifter and a current source.

FIG. 3 illustrates an example of a drive circuit configuration of a display device of the present invention.

FIG. 4 is an operation timing chart of a driving circuit of a display device.

FIG. 5 illustrates an example of a drive circuit configuration of a display device of the present invention.

FIG. 6 illustrates an example of a drive circuit configuration of a display device of the present invention.

FIG. 7 illustrates an example of a drive circuit configuration of a display device of the present invention.

FIG. 8 is an operation timing chart of a driver circuit of a display device.

FIG. 9 is a schematic diagram of a drive circuit of a display device before the present invention.

FIG. 10 is a circuit diagram of a level shifter and a current source.

FIG. 11 illustrates an example of a manufacturing process of a display device.

FIG. 12 illustrates an example of a manufacturing process of a display device.

FIG. 13 illustrates an example of a manufacturing process of a display device.

FIG. 14 illustrates an example of a manufacturing process of a display device.

FIG. 15 illustrates an example of an electronic device to which the present invention is applied.

FIG. 16 illustrates an example of an electronic device to which the present invention is applied.

FIG. 17 illustrates an example of a shift register using a D-flip-flop.

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Claims (24)

[Claims] 1. A display device in which a source signal line driving circuit and a pixel portion are formed on a substrate, wherein the source signal line driving circuit outputs a pulse sequentially according to a clock signal, and an input signal. And a current source for supplying a current to the level shifter, wherein the current source supplies a current only during a period in which pulses are sequentially output from the shift register. A display device characterized by the above-mentioned. 2. A display device in which a source signal line drive circuit and a pixel portion are formed on a substrate, wherein the number of the source signal line drive circuits is 1 to x (where x is a natural number and x ≧ 2). A) (a is a natural number, 1 ≦ a ≦ x) a unit, a shift register that sequentially outputs pulses according to a clock signal, and a plurality of level shifters that convert the voltage amplitude of an input signal. And an a-th current source for supplying a current to the plurality of level shifters, wherein the a-th current source is provided only during a period in which pulses are sequentially output from the shift register in the a-th unit. A display device, wherein current is supplied to the plurality of level shifters in the a-th unit. 3. A display device in which a source signal line drive circuit and a pixel portion are formed on a substrate, wherein the number of the source signal line drive circuits is 1 to x (where x is a natural number and x ≧ 2). A (b is a natural number, 1 <b ≦ x) unit, a shift register that sequentially outputs pulses according to a clock signal, and a plurality of level shifters that convert the voltage amplitude of an input signal. And a b-th current source that supplies a current to the plurality of level shifters, wherein the b-th current source is one of a period during which a pulse is sequentially output from the shift register in the (b-1) -th unit. And only during a period in which pulses are sequentially output from the shift register in the b-th unit,
A display device, wherein current is supplied to the plurality of level shifters in the b-th unit. 4. A display device in which a source signal line drive circuit and a pixel portion are formed on a substrate, wherein the number of the source signal line drive circuits is 1 to x (where x is a natural number and x ≧ 2). C) (c is a natural number, 1 ≦ c <x) a unit, a shift register that sequentially outputs pulses according to a clock signal, and a plurality of level shifters that convert the voltage amplitude of an input signal. And a c-th current source that supplies current to the plurality of level shifters, wherein the c-th current source is a part of a period during which pulses are sequentially output from the shift register in the (c + 1) th unit. , Only during a period in which pulses are sequentially output from the shift register in the c-th unit,
A display device, wherein current is supplied to the plurality of level shifters in the c-th unit. 5. A display device in which a gate signal line drive circuit and a pixel portion are formed on a substrate, wherein the gate signal line drive circuit sequentially outputs pulses in accordance with a clock signal, and an input signal. And a current source for supplying a current to the level shifter, wherein the current source supplies a current only during a period in which pulses are sequentially output from the shift register. A display device characterized by the above-mentioned. 6. A display device in which a gate signal line drive circuit and a pixel portion are formed on a substrate, wherein the gate signal line drive circuits include first to y-th y circuits (y is a natural number and y ≧ 2). A (d is a natural number, 1 ≦ d ≦ y) unit, a shift register that sequentially outputs pulses according to a clock signal, and a plurality of level shifters that convert the voltage amplitude of an input signal. And a d-th current source for supplying a current to the plurality of level shifters, wherein the d-th current source is provided only during a period in which pulses are sequentially output from the shift register in the d-th unit. A display device, wherein current is supplied to the plurality of level shifters in the d-th unit. 7. A display device in which a gate signal line drive circuit and a pixel portion are formed on a substrate, wherein the gate signal line drive circuits include first to y-th y circuits (y is a natural number, y ≧ 2). An e-th unit (e is a natural number, 1 <e ≦ y), a shift register for sequentially outputting pulses in accordance with a clock signal, and a plurality of level shifters for converting a voltage amplitude of an input signal. And an e-th current source for supplying a current to the plurality of level shifters, wherein the e-th current source is one of periods during which pulses are sequentially output from the shift register in the (e-1) -th unit. And only during a period in which pulses are sequentially output from the shift register in the e-th unit,
A display device, wherein current is supplied to the plurality of level shifters in the e-th unit. 8. A display device in which a gate signal line drive circuit and a pixel portion are formed on a substrate, wherein the gate signal line drive circuits include first to y-th (y is a natural number, y ≧ 2) An f-th unit (where f is a natural number, 1 ≦ f <y) is a shift register that sequentially outputs pulses according to a clock signal, and a plurality of level shifters that convert the voltage amplitude of an input signal. And an f-th current source that supplies current to the plurality of level shifters, wherein the f-th current source is a part of a period during which pulses are sequentially output from the shift register in the (f + 1) -th unit. , Only during a period in which pulses are sequentially output from the shift register in the f-th unit,
A display device, wherein current is supplied to the plurality of level shifters in the f-th unit. 9. A display device in which a source signal line driving circuit and a pixel portion are formed on a substrate, wherein the source signal line driving circuit comprises: a decoder for outputting a pulse in accordance with an input signal; A level shifter that performs amplitude conversion; and a current source that supplies a current to the level shifter. The current source supplies a current only during a period in which a pulse is output from the decoder. Display device. 10. A display device in which a source signal line drive circuit and a pixel portion are formed on a substrate, wherein the source signal line drive circuits include first to x-th (where x is a natural number, x ≧ 2) )
A unit (a is a natural number, 1 ≦ a ≦ x), a decoder that outputs a pulse according to an input signal, a plurality of level shifters that convert the voltage amplitude of the input signal, An a-th current source that supplies a current to a plurality of level shifters, wherein the a-th current source is connected to the a-th unit only during a period in which a pulse is output from the decoder in the a-th unit. Wherein the current is supplied to the plurality of level shifters. 11. A display device in which a source signal line drive circuit and a pixel portion are formed on a substrate, wherein the number of the source signal line drive circuits is 1 to x (where x is a natural number and x ≧ 2). B) (b is a natural number, 1 <b ≦ x) a unit that outputs a pulse according to an input signal, a plurality of level shifters that convert the voltage amplitude of the input signal, A b-th current source for supplying a current to the plurality of level shifters, wherein the b-th current source includes a part of a period during which a pulse is output from the decoder in the (b-1) -th unit; A display device, wherein current is supplied to the plurality of level shifters in the b-th unit only during a period in which a pulse is output from the decoder in the x-th unit. 12. A display device in which a source signal line drive circuit and a pixel portion are formed on a substrate, wherein the number of the source signal line drive circuits is 1 to x (where x is a natural number and x ≧ 2). )
A c-th unit (c is a natural number, 1 ≦ c <x), a decoder that outputs a pulse according to an input signal, a plurality of level shifters that convert the voltage amplitude of the input signal, A c-th current source for supplying a current to a plurality of level shifters, wherein the c-th current source includes a part of a period during which a pulse is output from the decoder in the (c + 1) -th unit; The display device, wherein current is supplied to the plurality of level shifters in the c-th unit only during a period in which a pulse is output from the decoder in the unit. 13. A display device in which a gate signal line driving circuit and a pixel portion are formed on a substrate, wherein the gate signal line driving circuit outputs a pulse according to an input signal, and a voltage of an input signal. A level shifter that performs amplitude conversion; and a current source that supplies a current to the level shifter. The current source supplies a current only during a period in which a pulse is output from the decoder. Display device. 14. A display device in which a gate signal line drive circuit and a pixel portion are formed on a substrate, wherein the gate signal line drive circuits include first to y-th (y is a natural number, y ≧ 2) D) (d is a natural number, 1 ≦ d ≦ y) a unit that outputs a pulse according to an input signal, a plurality of level shifters that convert the voltage amplitude of the input signal, A d-th current source for supplying a current to the plurality of level shifters, wherein the d-th current source is connected to the d-th unit only during a period in which a pulse is output from the decoder in the d-th unit. A display device, wherein current is supplied to the plurality of level shifters in a unit. 15. A display device in which a gate signal line drive circuit and a pixel portion are formed on a substrate, wherein the gate signal line drive circuits include first to y-th (y is a natural number, y ≧ 2) )
An e-th unit (e is a natural number, 1 <e ≦ y), a decoder that outputs a pulse according to an input signal, a plurality of level shifters that convert a voltage amplitude of an input signal, An e-th current source that supplies a current to a plurality of level shifters, wherein the e-th current source is configured to output part of a pulse from the decoder in the (e-1) th unit; A display device, wherein current is supplied to the plurality of level shifters in the e-th unit only during a period in which a pulse is output from the decoder in the e-th unit. 16. A display device in which a gate signal line drive circuit and a pixel portion are formed on a substrate, wherein the gate signal line drive circuits include first to y-th (y is a natural number, y ≧ 2) An f-th unit (where f is a natural number, 1 ≦ f <y), a decoder that outputs a pulse according to an input signal, a plurality of level shifters that convert the voltage amplitude of the input signal, An f-th current source for supplying a current to the plurality of level shifters, wherein the f-th current source includes a part of a period during which a pulse is output from the decoder in the (f + 1) -th unit; A current supply unit that supplies current to the plurality of level shifters in the f-th unit only during a period in which a pulse is output from the decoder in the unit. 17. The display device according to claim 1, wherein the source signal line driving circuit, the gate signal line driving circuit, and the pixel portion are formed on a glass substrate, A display device formed on a substrate, a stainless steel substrate, or a single crystal wafer. 18. The display device according to claim 1, wherein the driving circuit and the pixel portion are formed integrally on a same substrate. apparatus. 19. The display device according to claim 1, wherein the drive circuit and the pixel portion are formed on different substrates. . 20. A liquid crystal display using the display device according to claim 1. Description: 21. A personal computer using the display device according to any one of claims 1 to 19. 22. A portable information terminal using the display device according to any one of claims 1 to 19. 23. A car audio using the display device according to any one of claims 1 to 19. 24. A digital camera using the display device according to any one of claims 1 to 19.