JP2002201358A - Sealing material for electronic part, method for sealing electronic part, semiconductor package, and method for making semiconductor package - Google Patents
Sealing material for electronic part, method for sealing electronic part, semiconductor package, and method for making semiconductor packageInfo
- Publication number
- JP2002201358A JP2002201358A JP2000398728A JP2000398728A JP2002201358A JP 2002201358 A JP2002201358 A JP 2002201358A JP 2000398728 A JP2000398728 A JP 2000398728A JP 2000398728 A JP2000398728 A JP 2000398728A JP 2002201358 A JP2002201358 A JP 2002201358A
- Authority
- JP
- Japan
- Prior art keywords
- sealing material
- filler
- base resin
- specific gravity
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品を封止す
るための封止材料と、電子部品の封止方法に関し、特
に、基板上に半導体チップを封止するための封止材料、
この封止材料を用いた半導体パッケージ、および半導体
パッケージの作製方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sealing material for sealing an electronic component and a method for sealing an electronic component, and more particularly to a sealing material for sealing a semiconductor chip on a substrate.
The present invention relates to a semiconductor package using the sealing material and a method for manufacturing the semiconductor package.
【０００２】[0002]
【従来の技術および発明が解決しようとする課題】基板
上に搭載される半導体チップ等の電子部品は、外部環境
からの保護と、電子部品動作時の熱エネルギーの放散を
目的として、樹脂等により封止され、パッケージングさ
れる。封止樹脂としては、通常、加工性にすぐれたエポ
キシ樹脂やポリイミド樹脂が用いられる。2. Description of the Related Art Electronic components such as semiconductor chips mounted on a substrate are made of resin or the like for the purpose of protection from the external environment and dissipation of heat energy during operation of the electronic components. Sealed and packaged. As the sealing resin, an epoxy resin or a polyimide resin excellent in workability is usually used.
【０００３】しかし、基板上に高周波集積回路を搭載す
る場合、従来のエポキシ樹脂やポリイミド樹脂の封止材
料では、誘電損失が大きく、信号の伝送損失が大きくな
るという問題がある。誘電損失とは、誘電体に交流電場
を印加すると、分極Ｐが電場の変化に追随できず、電束
密度Ｄ（Ｄ＝ε0Ｅ＋Ｐ）が電場Ｅに対して位相の遅れ
を生じ、この結果、電気エネルギーの一部が熱となって
失われることを言う。誘電損失の量を表わすのに、誘電
正接（loss tangent）が用いられる。すなわち、高周波
印加時の位相の遅れをδとしたとき、位相角δのタンジ
ェント（正接値）を誘電正接と呼び、誘電損失特性を表
わす量として用いる。誘電正接が大きいほど（すなわち
位相の遅れが大きいほど）誘電損失が大きく、信号処理
速度の高速化に対応することができなくなり、伝送損失
が大きくなる。１００ＭＨｚ以上の高周波になると誘電
損失が大きく、発熱の原因にもなる。However, when a high-frequency integrated circuit is mounted on a substrate, there is a problem that a conventional epoxy resin or polyimide resin sealing material has a large dielectric loss and a large signal transmission loss. The dielectric loss means that when an AC electric field is applied to a dielectric, the polarization P cannot follow the change in the electric field, and the electric flux density D (D = ε 0 E + P) causes a phase delay with respect to the electric field E, and as a result, , Says that part of the electrical energy is lost as heat. Loss tangent is used to describe the amount of dielectric loss. That is, assuming that the phase delay at the time of applying a high frequency is δ, the tangent (tangent value) of the phase angle δ is called a dielectric tangent and is used as an amount representing a dielectric loss characteristic. As the dielectric loss tangent increases (that is, as the phase delay increases), the dielectric loss increases, and it becomes impossible to cope with an increase in the signal processing speed, and the transmission loss increases. When the frequency is higher than 100 MHz, the dielectric loss is large, which also causes heat generation.
【０００４】通常の樹脂封止剤の誘電正接は、０．０２
〜０．０３と、一般に高い。そこで、樹脂中に低い誘電
率の充填剤を混合することが考えられる。この場合、充
填剤は樹脂中に均一に混合され、高周波集積回路を封止
していた。しかし、樹脂中への充填剤の混合にも限度が
あり、高周波集積回路で信号の伝送損失が十分に防止さ
れているとは言いがたかった。例えば、シリカ粉なら
ば、均一に樹脂中に分散させても７０vol％が限度であ
り、この場合、誘電正接は０．０１５程度にまでしか低
減できない。The dielectric loss tangent of a normal resin sealant is 0.02
Generally 0.03 to 0.03. Therefore, it is conceivable to mix a filler having a low dielectric constant into the resin. In this case, the filler was uniformly mixed in the resin and sealed the high-frequency integrated circuit. However, there is a limit to the mixing of the filler into the resin, and it has not been said that the signal transmission loss is sufficiently prevented in the high-frequency integrated circuit. For example, in the case of silica powder, even if the powder is uniformly dispersed in a resin, the limit is 70 vol%.
【０００５】[0005]
【課題を解決するための手段】そこで、本発明では、ベ
ース樹脂と充填剤との比重の差を利用して、封止される
半導体チップなどの電子部品の表面近傍に、誘電正接値
の小さい充填剤を集中的に偏在させる。これにより、電
子部品表面に形成された高周波伝送線路の伝送損失を効
果的に防止し、付随的な効果として、パッケージ内での
発熱を防止する。Accordingly, the present invention utilizes a difference in specific gravity between a base resin and a filler to reduce the dielectric loss tangent near the surface of an electronic component such as a semiconductor chip to be sealed. The filler is unevenly distributed. Thus, transmission loss of the high-frequency transmission line formed on the surface of the electronic component is effectively prevented, and as an additional effect, heat generation in the package is prevented.
【０００６】具体的には、本発明の第１の目的として、
誘電損失を低減し、高周波伝送線路の伝送損失を防止す
ることのできる封止材料を提供する。この封止材料は、
ベース樹脂と、このベース樹脂の比重の０．７倍以下ま
たは１．７倍以上の比重を有し、かつ、誘電正接の値が
０．００５以下である充填剤とを含む。比重を０．７倍
以下または１．７倍以上に異ならせることによって、封
止材料の注入後に、低い誘電正接値の充填剤を効率的に
電子部品の表面近傍に集めることができる。Specifically, as a first object of the present invention,
Provided is a sealing material capable of reducing dielectric loss and preventing transmission loss of a high-frequency transmission line. This sealing material
It contains a base resin and a filler having a specific gravity of 0.7 times or less or 1.7 times or more of the specific gravity of the base resin, and having a dielectric loss tangent of 0.005 or less. By making the specific gravity 0.7 times or less or 1.7 times or more, the filler having a low dielectric loss tangent can be efficiently collected near the surface of the electronic component after the injection of the sealing material.
【０００７】ベース樹脂は、たとえば、フェノール樹
脂、尿素樹脂、メラミン樹脂、アルキド樹脂、アクリル
樹脂、不飽和ポリエステル樹脂、ジアリルフタレート樹
脂、エポキシ樹脂、シリコーン樹脂、シクロペンタジエ
ンから合成した樹脂、トリス（２−ヒドロキシエチル）
イソシアヌラートを含む樹脂、芳香族ニトトリルから合
成した樹脂、３量化芳香族ジシアナミド樹脂、トリアリ
ルトリメタリレートを含む樹脂、フラン樹脂、ケトン樹
脂、キシレ樹脂、縮合多環芳香族を含む熱硬化性樹脂で
ある。好ましくは、エポキシ樹脂を用いるのがよく、こ
のようなエポキシ樹脂は、分子内にエポキシ基を有する
ものであればどのようなものでもよく、ビスフェノール
Ａ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、
ビスフェノールＳ型エポキシ樹脂、脂環式エポキシ樹
脂、脂肪族鎖状エポキシ樹脂、フェノールノボラック型
エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、
ビスフェノールＡノボラック型エポキシ樹脂、ビフェノ
ールのジグリシジリエーテル化物、ナフタレンジオール
のジグリシジリエーテル化物、フェノール類のジグリシ
ジリエーテル化物、アルコール類のジグリシジルエーテ
ル化物、及びこれらのアルキル置換体、ハロゲン化物、
水素添加物などがある。これらは併用してもよく、エポ
キシ樹脂以外の成分が不純物として含まれていてもよ
い。The base resin is, for example, a resin synthesized from phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, cyclopentadiene, tris (2- Hydroxyethyl)
Resin containing isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimethacrylate, furan resin, ketone resin, xyle resin, thermosetting containing condensed polycyclic aromatic Resin. Preferably, an epoxy resin is used, and such an epoxy resin may be any one having an epoxy group in a molecule, such as a bisphenol A epoxy resin, a bisphenol F epoxy resin,
Bisphenol S type epoxy resin, alicyclic epoxy resin, aliphatic chain epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin,
Bisphenol A novolak epoxy resin, diglycidyl etherified biphenol, diglycidyl etherified naphthalene diol, diglycidyl etherified phenols, diglycidyl etherified alcohols, and alkyl-substituted and halogenated compounds thereof ,
And hydrogenated products. These may be used in combination, and components other than the epoxy resin may be contained as impurities.
【０００８】本発明において、ハロゲン化ビスフェノー
ルＡ型エポキシ樹脂、ハロゲン化ビスフェノールＦ型エ
ポキシ樹脂、ハロゲン化ビスフェノールＳ型エポキシ樹
脂等のテトラブロモビスフェノールＡ等のハロゲン化ビ
スフェノール化合物とエピクロルヒドリンを反応させて
得られるべきエポキシ樹脂のようにエーテル基が結合し
ているベンゼン環のエーテル基に対してオルト位が塩
素、臭素等のハロゲン原子で置換されているエポキシ樹
脂を使用したときに、本発明の処理液によるエポキシ樹
脂硬化物の分解及び／又は溶解の効率が特によい。In the present invention, a halogenated bisphenol compound such as tetrabromobisphenol A such as halogenated bisphenol A type epoxy resin, halogenated bisphenol F type epoxy resin or halogenated bisphenol S type epoxy resin is reacted with epichlorohydrin. When an epoxy resin in which the ortho position is substituted with a halogen atom such as chlorine or bromine with respect to the ether group of the benzene ring to which the ether group is bonded as in the case of the epoxy resin to be used, the treatment solution of the present invention The efficiency of decomposition and / or dissolution of the cured epoxy resin is particularly good.
【０００９】本発明で使用するエポキシ樹脂用硬化剤
は、エポキシ樹脂を硬化させるものであれば、限定する
ことなく使用でき、例えば、多官能フェノール類、アミ
ン類、イミダゾール化合物、酸無水物、有機リン化合物
およびこれらのハロゲン化物などがある。The curing agent for an epoxy resin used in the present invention can be used without any limitation as long as it can cure an epoxy resin. Examples thereof include polyfunctional phenols, amines, imidazole compounds, acid anhydrides, organic anhydrides, and the like. Phosphorus compounds and their halides.
【００１０】多官能フェノール類の例として、単環二官
能フェノールであるヒドロキノン、レゾルシノール、カ
テコール,多環二官能フェノールであるビスフェノール
Ａ、ビスフェノールＦ、ナフタレンジオール類、ビフェ
ノール類、及びこれらのハロゲン化物、アルキル基置換
体などがある。更に、これらのフェノール類とアルデヒ
ド類との重縮合物であるノボラック、レゾールがある。Examples of the polyfunctional phenols include monocyclic bifunctional phenols such as hydroquinone, resorcinol, catechol, and polycyclic bifunctional phenols such as bisphenol A, bisphenol F, naphthalene diols, biphenols, and halides thereof. There are alkyl group substituents and the like. Further, there are novolaks and resols which are polycondensates of these phenols and aldehydes.
【００１１】アミン類の例としては、脂肪族あるいは芳
香族の第一級アミン、第二級アミン、第三級アミン、第
四級アンモニウム塩及び脂肪族環状アミン類、グアニジ
ン類、尿素誘導体等がある。Examples of amines include aliphatic or aromatic primary amines, secondary amines, tertiary amines, quaternary ammonium salts and aliphatic cyclic amines, guanidines, urea derivatives and the like. is there.
【００１２】これらの化合物の一例としては、Ｎ、Ｎ−
ベンジルジメチルアミン、２−（ジメチルアミノメチ
ル）フェノール、２、４、６−トリス（ジメチルアミノ
メチル）フェノール、テトラメチルグアニジン、トリエ
タノールアミン、Ｎ、Ｎ’−ジメチルピペラジン、１、
４−ジアザビシクロ［２、２、２］オクタン、１、８−
ジアザビシクロ［５、４、０］−７−ウンデセン、１、
５−ジアザビシクロ［４、４、０］−５−ノネン、ヘキ
サメチレンテトラミン、ピリジン、ピコリン、ピペリジ
ン、ピロリジン、ジメチルシクロヘキシルアミン、ジメ
チルヘキシルアミン、シクロヘキシルアミン、ジイソブ
チルアミン、ジ−ｎ−ブチルアミン、ジフェニルアミ
ン、Ｎ−メチルアニリン、トリ−ｎ−プロピルアミン、
トリ−ｎ−オクチルアミン、トリ−ｎ−ブチルアミン、
トリフェニルアミン、テトラメチルアンモニウムクロラ
イド、テトラメチルアンモニウムブロマイド、テトラメ
チルアンモニウムアイオダイド、トリエチレンテトラミ
ン、ジアミノジフェニルメタン、ジアミノジフェニルエ
ーテル、ジシアンジアミド、トリルビグアニド、グアニ
ル尿素、ジメチル尿素等がある。Examples of these compounds include N, N-
Benzyldimethylamine, 2- (dimethylaminomethyl) phenol, 2,4,6-tris (dimethylaminomethyl) phenol, tetramethylguanidine, triethanolamine, N, N'-dimethylpiperazine, 1,
4-diazabicyclo [2,2,2] octane, 1,8-
Diazabicyclo [5,4,0] -7-undecene, 1,
5-diazabicyclo [4,4,0] -5-nonene, hexamethylenetetramine, pyridine, picoline, piperidine, pyrrolidine, dimethylcyclohexylamine, dimethylhexylamine, cyclohexylamine, diisobutylamine, di-n-butylamine, diphenylamine, N -Methylaniline, tri-n-propylamine,
Tri-n-octylamine, tri-n-butylamine,
Examples include triphenylamine, tetramethylammonium chloride, tetramethylammonium bromide, tetramethylammonium iodide, triethylenetetramine, diaminodiphenylmethane, diaminodiphenylether, dicyandiamide, tolylbiguanide, guanylurea, and dimethylurea.
【００１３】イミダゾール化合物の例としては、イミダ
ゾール、２−エチルイミダゾール、２−エチル−４−メ
チルイミダゾール、２−メチルイミダゾール、２−フェ
ニルイミダゾール、２−ウンデシルイミダゾール、１−
ベンジル−２−メチルイミダゾール、２−ヘプタデシル
イミダゾール、４、５−ジフェニルイミダゾール、２−
メチルイミダゾリン、２−フェニルイミダゾリン、２−
ウンデシルイミダゾリン、２−ヘプタデシルイミダゾリ
ン、２−イソプロピルイミダゾール、２、４−ジメチル
イミダゾール、２−フェニル−４−メチルイミダゾー
ル、２−エチルイミダゾリン、２−フェニル−４−メチ
ルイミダゾリン、ベンズイミダゾール、１−シアノエチ
ルイミダゾールなどがある。Examples of the imidazole compound include imidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-methylimidazole, 2-phenylimidazole, 2-undecylimidazole,
Benzyl-2-methylimidazole, 2-heptadecylimidazole, 4,5-diphenylimidazole, 2-
Methylimidazoline, 2-phenylimidazoline, 2-
Undecylimidazoline, 2-heptadecylimidazoline, 2-isopropylimidazole, 2,4-dimethylimidazole, 2-phenyl-4-methylimidazole, 2-ethylimidazoline, 2-phenyl-4-methylimidazoline, benzimidazole, 1- And cyanoethylimidazole.
【００１４】酸無水物の例としては、無水フタル酸、ヘ
キサヒドロ無水フタル酸、ピロメリット酸二無水物、ベ
ンゾフェノンテトラカルボン酸二無水物等がある。Examples of the acid anhydride include phthalic anhydride, hexahydrophthalic anhydride, pyromellitic dianhydride, benzophenonetetracarboxylic dianhydride and the like.
【００１５】有機リン化合物としては、有機基を有する
リン化合物であれば特に限定せれずに使用でき、例え
ば、ヘキサメチルリン酸トリアミド、リン酸トリ（ジク
ロロプロピル）、リン酸トリ（クロロプロピル）、亜リ
ン酸トリフェニル、リン酸トリメチル、フェニルフォス
フォン酸、トリフェニルフォスフィン、トリ−ｎ−ブチ
ルフォスフィン、ジフェニルフォスフィンなどがある。As the organic phosphorus compound, any phosphorus compound having an organic group can be used without particular limitation. Examples thereof include hexamethylphosphoric triamide, tri (dichloropropyl) phosphate, tri (chloropropyl) phosphate, Examples include triphenyl phosphite, trimethyl phosphate, phenylphosphonic acid, triphenylphosphine, tri-n-butylphosphine, and diphenylphosphine.
【００１６】これらの硬化剤は、単独、或いは、組み合
わせて用いることもできる。These curing agents can be used alone or in combination.
【００１７】これらエポキシ樹脂用硬化剤の配合量は、
エポキシ基の硬化反応を進行させることができれば、特
に限定することなく使用できるが、好ましくは、エポキ
シ基１モルに対して、０．０１〜５．０当量の範囲で、
特に好ましくは０．８〜１．２当量の範囲で使用する。The amounts of these epoxy resin curing agents are as follows:
It can be used without any particular limitation as long as the curing reaction of the epoxy group can proceed, but is preferably in the range of 0.01 to 5.0 equivalents per 1 mol of the epoxy group.
It is particularly preferably used in the range of 0.8 to 1.2 equivalents.
【００１８】また、本発明の熱硬化性エポキシ樹脂組成
物には、必要に応じて硬化促進剤を配合してもよい。代
表的な硬化促進剤として、第三級アミン、イミダゾール
類、第四級アンモニウム塩等があるが、これに限定され
るものではない。The thermosetting epoxy resin composition of the present invention may optionally contain a curing accelerator. Representative curing accelerators include, but are not limited to, tertiary amines, imidazoles, quaternary ammonium salts, and the like.
【００１９】一方、充填剤は、シリカ、テフロンパウ
ダ、中空ガラス球の中の１種または複数種類を組み合わ
せたものである。複数種類を組み合わせた場合、ベース
樹脂内での充填剤の分布制御が容易になり、より効果的
にチップ表面の誘電損失を低減できる。たとえば、ベー
ス樹脂としてエポキシ樹脂を用い、充填剤としてシリカ
を用いた場合、これらの比重はそれぞれ、ベース樹脂が
約１．１、充填剤が２．２であり、比重が約２倍とな
る。On the other hand, the filler is one or a combination of silica, Teflon powder and hollow glass spheres. When a plurality of types are combined, the distribution of the filler in the base resin is easily controlled, and the dielectric loss on the chip surface can be reduced more effectively. For example, when an epoxy resin is used as a base resin and silica is used as a filler, the specific gravities are about 1.1 for the base resin and 2.2 for the filler, respectively, and the specific gravity is about twice.
【００２０】封止材料はまた、ベース樹脂と、このベー
ス樹脂の比重の０．７倍以下または１．７倍以上の比重
を有し、かつ、誘電正接の値が０．００５以下である充
填剤と、溶剤とを含む。揮発性の溶剤と混合することに
よって、封止材料を樹脂ワニスとすることができ、取り
扱いが容易になり、封止後の外観にも優れる。ベース樹
脂と充填剤の混合物に対する溶剤の割合は、ベース樹脂
と充填剤の混合物１００重量部に対して４０から９００
重量部の範囲であるのが好ましい。溶剤の割合が４０重
量部未満であると粘度が高く樹脂中で充填剤が偏在する
ようにならないという問題があり、９００重量部を超え
ると粘度が低く成形性が低下するおそれがあるという問
題があるからである。The encapsulating material is also filled with a base resin having a specific gravity of 0.7 times or less or 1.7 times or more of the specific gravity of the base resin and a dielectric loss tangent of 0.005 or less. Agent and a solvent. By mixing with a volatile solvent, a resin varnish can be used as a sealing material, handling is easy, and the appearance after sealing is excellent. The ratio of the solvent to the mixture of the base resin and the filler is from 40 to 900 per 100 parts by weight of the mixture of the base resin and the filler.
Preferably it is in the range of parts by weight. When the proportion of the solvent is less than 40 parts by weight, there is a problem that the viscosity is so high that the filler is not unevenly distributed in the resin, and when it exceeds 900 parts by weight, there is a problem that the viscosity is low and the moldability may be reduced. Because there is.
【００２１】本発明の第２の目的として、上述した封止
材料を用いた電子部品の封止方法を提供する。この封止
方法は、まず、基板上に電子部品を搭載する。一方で、
ベース樹脂と、このベース樹脂の比重の０．７倍以下ま
たは１．７倍以上の比重を有し、かつ、誘電正接の値が
０．００５以下である充填剤とを含む封止材料を準備す
る。次に、この封止材料を基板上に注入して、電子部品
を封じ込める。注入した封止材料を所定時間放置して、
充填剤とベース樹脂の比重の差を利用して、充填剤を電
子部品の表面近傍に偏在させる。最後に、封止材料を硬
化させる。As a second object of the present invention, there is provided a method of sealing an electronic component using the above-described sealing material. In this sealing method, first, an electronic component is mounted on a substrate. On the other hand,
Preparation of a sealing material including a base resin and a filler having a specific gravity of 0.7 times or less or 1.7 times or more of the specific gravity of the base resin and having a dielectric loss tangent value of 0.005 or less I do. Next, this sealing material is injected onto the substrate to encapsulate the electronic component. Leave the injected sealing material for a predetermined time,
Utilizing the difference in specific gravity between the filler and the base resin, the filler is localized near the surface of the electronic component. Finally, the sealing material is cured.
【００２２】封止材料に溶剤を混合する場合は、封止材
料を注入して所定時間放置した後に、溶剤を蒸散させて
から、あるいは蒸散させながら硬化させる。When a solvent is mixed with the sealing material, after the sealing material is injected and left for a predetermined time, the solvent is evaporated and then cured while being evaporated.
【００２３】ベース樹脂の比重よりも比重の小さい充填
剤、たとえば中空ガラス球を用いる場合は、基板上に搭
載した電子部品の表面を下側に向け（フェイスダウンの
状態で）、封止材料を所定時間放置する。充填剤は、時
間の経過とともに上方に浮上し、電子部品の表面に集中
する。また、ベース樹脂の比重よりも比重の大きい充填
剤、たとえばシリカやテフロンパウダを用いる場合は、
基板上に搭載した電子部品の表面を上側に向けて、封止
材料を所定時間放置する。この場合は、時間の経過とと
もに、誘電正接の小さい充填剤が沈下し、同じく、電子
部品の表面近傍に集中することになる。したがって、電
子部品表面に形成された高周波の伝送線路における位相
遅延、電気エネルギーの損失、発熱といった問題が解決
される。When a filler having a specific gravity lower than the specific gravity of the base resin, for example, a hollow glass sphere is used, the surface of the electronic component mounted on the substrate is directed downward (in a face-down state), and the sealing material is used. Leave for a predetermined time. The filler floats upward with time and concentrates on the surface of the electronic component. Also, when using a filler having a specific gravity larger than the specific gravity of the base resin, for example, silica or Teflon powder,
The sealing material is left for a predetermined time with the surface of the electronic component mounted on the substrate facing upward. In this case, as the time elapses, the filler having a small dielectric loss tangent sinks down, and also concentrates near the surface of the electronic component. Therefore, problems such as phase delay, loss of electric energy, and heat generation in the high-frequency transmission line formed on the surface of the electronic component are solved.
【００２４】本発明の第３の目的として、高周波集積回
路を搭載してパッケージにした半導体パッケージを提供
する。半導体パッケージは、基板と、基板上に搭載され
る半導体チップと、基板上に半導体チップを封止する封
止材料とを含み、封止材料は、ベース樹脂と、このベー
ス樹脂に混合された誘電正接値が０．００５以下の充填
剤とを含む。この半導体パッケージの特徴として、誘電
正接の小さい充填剤が半導体チップの表面近傍に集中し
て偏在する。充填剤は、ベース樹脂の比重の０．７倍以
下または１．７倍以上の比重を有し、たとえば、シリ
カ、テフロンパウダ、中空ガラス球から選択される１種
以上を含む。これにより、伝送損失が少なく、高周波の
応答特性にすぐれた半導体パッケージが提供される。A third object of the present invention is to provide a semiconductor package in which a high-frequency integrated circuit is mounted and packaged. The semiconductor package includes a substrate, a semiconductor chip mounted on the substrate, and a sealing material for sealing the semiconductor chip on the substrate. The sealing material includes a base resin and a dielectric mixed with the base resin. And a filler having a tangent value of 0.005 or less. As a feature of this semiconductor package, a filler having a small dielectric loss tangent is concentrated and localized near the surface of the semiconductor chip. The filler has a specific gravity of 0.7 times or less or 1.7 times or more of the specific gravity of the base resin, and includes, for example, at least one selected from silica, Teflon powder, and hollow glass spheres. As a result, a semiconductor package having low transmission loss and excellent high-frequency response characteristics is provided.
【００２５】本発明の第４の目的として、高周波回路を
搭載する半導体パッケージの作製方法を提供する。半導
体パッケージの作製方法では、まず基板上に半導体チッ
プを搭載する。一方で、ベース樹脂と、このベース樹脂
の比重の０．７倍以下又は１．７倍以上の比重を有し、
かつ、誘電正接の値が０．００５以下である充填剤とを
含む封止材料を準備する。次に、準備した封止材料を基
板上に注入して、半導体チップを封じ込める。封止材料
を所定時間放置して、ベース樹脂と充填剤の比重の差を
利用して、低い誘電正接値の充填剤を半導体チップの表
面近傍に集中させる。最後に、封止材料を硬化させる。A fourth object of the present invention is to provide a method for manufacturing a semiconductor package on which a high-frequency circuit is mounted. In a method for manufacturing a semiconductor package, first, a semiconductor chip is mounted on a substrate. On the other hand, the base resin has a specific gravity of 0.7 times or less or 1.7 times or more of the specific gravity of the base resin,
In addition, a sealing material containing a filler having a dielectric loss tangent of 0.005 or less is prepared. Next, the prepared sealing material is injected onto the substrate to encapsulate the semiconductor chip. The sealing material is left for a predetermined time, and the filler having a low dielectric loss tangent is concentrated near the surface of the semiconductor chip by utilizing the difference in specific gravity between the base resin and the filler. Finally, the sealing material is cured.
【００２６】このような半導体パッケージの作製方法
は、充填剤とベース樹脂の比重の差を利用しているの
で、充填剤の濃度を過度に高めなくとも、簡単な方法
で、高周波回路の表面近傍に低い誘電正接値を有する充
填剤を集中的に偏在させることが可能になる。The method of manufacturing such a semiconductor package utilizes the difference in specific gravity between the filler and the base resin. Therefore, even if the concentration of the filler is not excessively increased, the vicinity of the surface of the high-frequency circuit can be easily determined. In this case, the filler having a low dielectric loss tangent can be concentratedly distributed.
【００２７】上記封止材料に溶剤を混合して用いる場合
は、封止材料を注入して所定時間放置した後に、溶剤を
蒸散させる。溶剤を混合して樹脂ワニスとして用いるこ
とにより、粘度の調整が容易になり、充填剤の偏在する
速度や偏在の度合いを制御するのが容易となる上、封止
材料の保存、注入、取り扱いがより簡便になる。When a solvent is mixed with the above-mentioned sealing material and used, the sealing material is injected and left for a predetermined time, and then the solvent is evaporated. By mixing the solvent and using it as a resin varnish, the viscosity can be easily adjusted, the rate of uneven distribution of the filler and the degree of uneven distribution can be easily controlled, and the storage, injection, and handling of the sealing material can be facilitated. It becomes simpler.
【００２８】[0028]
【発明の実施の形態】上述したように、本発明の封止材
料は、ベース樹脂と、このベース樹脂との比重が０．７
倍以下または１．７倍以上異なり、かつ誘電正接が０．
００５以下である充填剤とを含む。表１は、本発明の封
止材料において、ベース樹脂にエポキシ樹脂を用いた場
合の、充填剤の種類と誘電正接値、およびエポキシ樹脂
との比重の差を示す。また、エポキシ樹脂のみを封止材
料として用いた場合と比較した伝送損失の低減率を示
す。DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, the sealing material of the present invention has a specific gravity between the base resin and the base resin of 0.7.
Times or 1.7 times or more, and the dielectric loss tangent is 0.7 times or less.
005 or less. Table 1 shows the type of filler, the dielectric loss tangent value, and the difference in specific gravity between the filler and the epoxy resin when an epoxy resin is used as the base resin in the sealing material of the present invention. In addition, the transmission loss reduction ratio is shown in comparison with the case where only an epoxy resin is used as a sealing material.
【００２９】伝送損失の測定は、高周波集積回路の伝送
線路幅が８００μｍ、線路長が２００ｍｍの回路に、
０．１Ｖの交流電圧を印加して測定したものである。The transmission loss was measured for a high-frequency integrated circuit having a transmission line width of 800 μm and a line length of 200 mm.
It was measured by applying an AC voltage of 0.1 V.
【００３０】[0030]
【表１】 表１の充填剤のうち、中空ガラス球の比重は、エポキシ
樹脂よりも軽く、シリカとテフロンパウダの比重はエポ
キシ樹脂よりも重い。また、いずれの充填剤もその誘電
正接値は０．００５以下である。充填剤を２種類以上混
合した場合は、平均誘電正接値および平均比重差を示し
ている。いずれの充填剤も、その粒径は１μｍ〜２０μ
ｍの範囲内にある。[Table 1] Among the fillers in Table 1, the specific gravity of the hollow glass sphere is lighter than that of the epoxy resin, and the specific gravity of silica and Teflon powder is heavier than the epoxy resin. The dielectric loss tangent of each filler is 0.005 or less. When two or more fillers are mixed, the average dielectric loss tangent value and the average specific gravity difference are shown. Each filler has a particle size of 1 μm to 20 μm.
m.
【００３１】表１の充填剤をベース樹脂に混合して封止
材料とすると、ベース樹脂と充填剤との比重の差によっ
て、時間の経過とともに充填剤が沈下または浮上する。
このような特質を利用して、高周波集積回路を半導体基
板上に封止する場合に、低い誘電正接値の（すなわち、
低い誘電損失率の）充填剤を故意に集積回路の表面近傍
に偏在させることができる。この結果、表１に示すよう
に、従来の樹脂に比較して、伝送損失を６０％〜７０％
も低減することが可能となる。When the filler shown in Table 1 is mixed with the base resin to form a sealing material, the filler sinks or floats over time due to a difference in specific gravity between the base resin and the filler.
Utilizing such characteristics, when a high-frequency integrated circuit is sealed on a semiconductor substrate, a low dielectric loss tangent value (that is,
Fillers (of low dielectric loss) can be deliberately localized near the surface of the integrated circuit. As a result, as shown in Table 1, the transmission loss was 60% to 70% as compared with the conventional resin.
Can also be reduced.
【００３２】ベース樹脂と充填剤に加えて揮発性の溶剤
を混合して封止材料としてもよい。この場合、樹脂ワニ
スを構成し、保存や取り扱いが容易になる。樹脂ワニス
は、通常容器内に保存され、使用直前に均一に攪拌され
る。樹脂ワニスの塗布後は、溶剤の揮発（蒸散）により
乾燥する。A sealing material may be prepared by mixing a volatile solvent in addition to the base resin and the filler. In this case, a resin varnish is formed to facilitate storage and handling. The resin varnish is usually stored in a container, and is uniformly stirred just before use. After application of the resin varnish, drying is performed by volatilization (evaporation) of the solvent.
【００３３】図１は、上述した封止材料を用いた半導体
パッケージ１０の断面図である。半導体パッケージ１０
は、基板１１と、基板上に搭載される半導体チップ（高
周波集積回路）１３と、基板１１上に半導体チップ１３
を封止する封止材料１５を含む。封止材料は、ベース樹
脂と、ベース樹脂に混合された充填剤１６を含む。充填
剤１６は、たとえばシリカであり、その誘電正接値は
０．０００１である。半導体パッケージ１０において、
充填剤１６は、半導体チップ１３の表面近傍に集中して
偏在する。図１の例では、充填剤１６の比重は１．１で
あり、ベース樹脂としてのエポキシ樹脂の比重と約２倍
比重が異なる。FIG. 1 is a sectional view of a semiconductor package 10 using the above-described sealing material. Semiconductor package 10
Are a substrate 11, a semiconductor chip (high-frequency integrated circuit) 13 mounted on the substrate, and a semiconductor chip 13 on the substrate 11.
And a sealing material 15 for sealing. The sealing material includes a base resin and a filler 16 mixed with the base resin. The filler 16 is, for example, silica, and its dielectric loss tangent is 0.0001. In the semiconductor package 10,
The filler 16 is concentrated and localized near the surface of the semiconductor chip 13. In the example of FIG. 1, the specific gravity of the filler 16 is 1.1, which is different from the specific gravity of the epoxy resin as the base resin by about twice.
【００３４】半導体パッケージ１０を作製するには、ま
ず、まず基板１１上に半導体チップ１３を搭載する。一
方で、ベース樹脂と、このベース樹脂の比重の０．７倍
以下又は１．７倍以上の比重を有し、かつ、誘電正接の
値が０．００５以下である充填剤とを含む封止材料を準
備する。In order to manufacture the semiconductor package 10, first, the semiconductor chip 13 is mounted on the substrate 11. On the other hand, encapsulation including a base resin and a filler having a specific gravity of 0.7 times or less or 1.7 times or more of the specific gravity of the base resin and a dielectric tangent value of 0.005 or less. Prepare the ingredients.
【００３５】次に、半導体チップ１３を搭載した半導体
基板１１を、図示しない金型の中に設置し、準備した封
止材料を金型の内部の基板上に注入して、半導体チップ
を封じ込める。封止材料に含まれる充填剤の比重によっ
て、半導体基板を金型の内部に上向きに配置するか下向
きに配置するかが決まる。たとえば充填剤がテフロンパ
ウダなどベース樹脂に比べて比重が高い充填剤である場
合は、半導体チップ１３の表面が上を向くように金型の
内部に配置され、充填剤がシリカや中空ガラス球など、
比重の低いものである場合は、半導体チップ１３の表面
が下を向くように金型の中に設置する。Next, the semiconductor substrate 11 on which the semiconductor chip 13 is mounted is placed in a mold (not shown), and the prepared sealing material is injected onto the substrate inside the mold to encapsulate the semiconductor chip. The specific gravity of the filler contained in the sealing material determines whether the semiconductor substrate is placed upward or downward inside the mold. For example, when the filler is a filler having a specific gravity higher than that of the base resin such as Teflon powder, the filler is disposed inside the mold so that the surface of the semiconductor chip 13 faces upward, and the filler is formed of silica or hollow glass spheres. ,
If the specific gravity is low, the semiconductor chip 13 is placed in a mold such that the surface of the semiconductor chip 13 faces downward.
【００３６】次に、注入した封止材料を所定時間放置し
て、充填剤を半導体チップ１３の表面近傍に偏在させ
る。比重の高い充填剤を含む封止材料の場合は、低い誘
電正接値の充填剤が沈下して、上向きに配置した半導体
チップ１３の表面近傍に集まる。比重の低い充填剤を含
む封止材料を用いた場合は、充填剤が浮上して、下向き
に配置した半導体チップ１３の表面近傍に集まる。Next, the injected sealing material is allowed to stand for a predetermined time, and the filler is unevenly distributed near the surface of the semiconductor chip 13. In the case of a sealing material containing a filler having a high specific gravity, the filler having a low dielectric tangent value sinks and gathers near the surface of the semiconductor chip 13 arranged upward. When a sealing material containing a filler having a low specific gravity is used, the filler floats and gathers near the surface of the semiconductor chip 13 arranged downward.
【００３７】最後に、封止材料を硬化させ、金型から取
り出して半導体パッケージ１０が完成する。Finally, the sealing material is cured and taken out of the mold to complete the semiconductor package 10.
【００３８】このような半導体パッケージの作製方法に
よれば、簡単な方法で、効果的に高周波回路の表面近傍
に誘電正接値の低い成分を集中させ、伝送損失を低減す
ることが可能になる。According to such a method of manufacturing a semiconductor package, a component having a low dielectric loss tangent can be effectively concentrated near the surface of a high-frequency circuit by a simple method, and transmission loss can be reduced.
【００３９】また、上記のような金型を用いずに、基板
の上に半導体チップを搭載した箇所に、ポッティングに
より封止することもあり、封止材料として、上述したベ
ース樹脂に充填剤の混合物に溶剤を加えて樹脂ワニスの
形態で用いる場合は、所定時間放置後、あるいは放置の
際に、溶剤を蒸散させる。この方法によれば、表面がな
めらかで光沢のある樹脂封止を形成することができる。In some cases, a portion where a semiconductor chip is mounted on a substrate is sealed by potting without using a mold as described above. When a solvent is added to the mixture and the mixture is used in the form of a resin varnish, the solvent is allowed to evaporate after standing for a predetermined time or at the time of standing. According to this method, a glossy resin seal having a smooth surface can be formed.
【００４０】[0040]
【発明の効果】以上説明したように、本発明の封止材料
は調整が容易であり、高周波集積回路の封止に最適に用
いられて効果的に伝送損失を低減することができる。As described above, the sealing material of the present invention is easy to adjust, and is optimally used for sealing a high-frequency integrated circuit, so that transmission loss can be effectively reduced.
【００４１】本発明の電子部品の封止方法は、ベース樹
脂と充填剤の比重の差を利用するので、簡便かつ効率的
に電子部品を封止し、かつ、電子部品の誘電損失を低減
することができる。Since the method for sealing an electronic component of the present invention utilizes the difference in specific gravity between the base resin and the filler, the electronic component is easily and efficiently sealed, and the dielectric loss of the electronic component is reduced. be able to.
【００４２】本発明の半導体パッケージは、基板に搭載
した高周波集積回路の表面近傍に誘電正接値の低い充填
剤が集中して偏在するので、高周波集積回路の伝送損失
を効果的に低減し、かつパッケージ内での発熱を防止す
ることが可能になる。In the semiconductor package of the present invention, since the filler having a low dielectric loss tangent is concentrated and unevenly distributed near the surface of the high frequency integrated circuit mounted on the substrate, the transmission loss of the high frequency integrated circuit is effectively reduced, and Heat generation in the package can be prevented.
【００４３】本発明の半導体パッケージの作製方法は、
従来のパッケージ作製方法と工程的には同じ程度で、基
板上の高周波集積回路の伝送損失と発熱を大幅に低減す
ることが可能になる。The method for manufacturing a semiconductor package of the present invention is as follows.
The transmission loss and heat generation of the high-frequency integrated circuit on the substrate can be significantly reduced, in the same degree of process as the conventional package manufacturing method.
【図１】本発明の一実施形態に係る半導体パッケージの
断面図である。FIG. 1 is a sectional view of a semiconductor package according to an embodiment of the present invention.
１０ 半導体パッケージ １１ 基板 １３ ＬＳＩチップ １５ 封止材料 １６ 充填剤 １７ ボンディングワイヤ １８ ハンダボール １９ メタルワイヤ DESCRIPTION OF SYMBOLS 10 Semiconductor package 11 Substrate 13 LSI chip 15 Encapsulation material 16 Filler 17 Bonding wire 18 Solder ball 19 Metal wire
フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/56 Ｈ０１Ｌ 21/56 Ｔ 23/29 Ｂ２９Ｋ 101:10 23/31 105:16 // Ｂ２９Ｋ 101:10 Ｂ２９Ｌ 31:34 105:16 Ｈ０１Ｌ 23/30 Ｒ Ｂ２９Ｌ 31:34 (72)発明者 島田 靖 茨城県下館市大字小川1500番地 日立化成 工業株式会社総合研究所内 (72)発明者 大塚 和久 茨城県下館市大字小川1500番地 日立化成 工業株式会社総合研究所内 (72)発明者 平田 善毅 茨城県下館市大字小川1500番地 日立化成 工業株式会社総合研究所内 (72)発明者 山本 和徳 茨城県下館市大字小川1500番地 日立化成 工業株式会社総合研究所内 Ｆターム(参考） 4F204 AA39 AB17 AB19 AH37 EA03 EA06 EB01 EE22 EF02 4J002 AA021 BD152 BF051 BG001 BK001 CC031 CC161 CC181 CD001 CD011 CD021 CD041 CD051 CD061 CF011 CF211 CP031 DJ016 DL006 FA082 FA086 FA106 FD012 FD016 FD140 GQ05 4M109 AA01 BA03 CA04 CA21 EA11 EB03 EB04 EB12 EB13 EB14 5F061 AA01 BA03 CA04 CA21 CB02. Front page continued (51) Int.Cl 7 identification marks FI Theme coat Bu (Reference) H01L 21/56 H01L 21/56 T 23/29 B29K 101: 10 23/31 105: 16 // B29K 101: 10 B29L 31 : 34 105: 16 H01L 23/30 R B29L 31:34 (72) Inventor Yasushi Shimada 1500 Oji Ogawa, Shimodate City, Ibaraki Pref.Hitachi Chemical Industry Co., Ltd. 1,500 Hitachi Chemical Industry Co., Ltd. (72) Inventor Yoshiki Hirata 1500, Oji Ogawa, Shimodate City, Ibaraki Prefecture Hitachi Chemical Industry Co., Ltd. (72) Inventor Kazunori Yamamoto 1500 Ogawa Ogawa, Shimodate City, Ibaraki Hitachi F-term in Kasei Kogyo R & D Co., Ltd. (reference) 4F204 AA39 AB17 AB19 AH37 EA03 EA06 EB01 EE22 EF02 4J002 AA021 BD152 BF051 BG001 BK001 CC031 CC161 CC181 CD001 CD011 CD021 CD041 CD051 CD061 CF011 CF211 FA031 0 AA01 BA03 CA04 CA2 1 EA11 EB03 EB04 EB12 EB13 EB14 5F061 AA01 BA03 CA04 CA21 CB02
Claims (16)
上の比重を有し、かつ、誘電正接の値が０．００５以下
である充填剤とを含む電子部品の封止材料。1. A base resin, comprising: a filler having a specific gravity of 0.7 times or less or 1.7 times or more of a specific gravity of the base resin, and a dielectric loss tangent value of 0.005 or less. Sealing material for electronic components.
ことを特徴とする請求項１に記載の封止材料。2. The sealing material according to claim 1, wherein the base resin is a thermosetting resin.
であることを特徴とする請求項１に記載の封止材料。3. The filler has a particle size of 1 μm to 20 μm.
The sealing material according to claim 1, wherein
ダ、中空ガラス球から選択された１種類以上を含むこと
をを特徴とする請求項１〜３のいずれかに記載の封止材
料。4. The sealing material according to claim 1, wherein the filler contains at least one selected from silica, Teflon powder, and hollow glass spheres.
上の比重を有し、かつ、誘電正接の値が０．００５以下
である充填剤と、 溶剤と、を含む電子部品の封止材料。5. A base resin, a filler having a specific gravity of 0.7 times or less or 1.7 times or more of a specific gravity of the base resin, and a dielectric loss tangent value of 0.005 or less; And a sealing material for an electronic component including:
求項１〜５のうちいずれかに記載の封止材料。6. The sealing material according to claim 1, wherein said filler is 20 to 80 vol%.
合物に対する割合は、ベース樹脂と充填剤の混合物１０
０重量部に対して４０から９００重量部の範囲であるこ
とを特徴とする請求項５に記載の封止材料。7. The ratio of the solvent to the mixture of the base resin and the filler is defined as a mixture of the base resin and the filler.
The sealing material according to claim 5, wherein the amount is in the range of 40 to 900 parts by weight based on 0 part by weight.
と、 ベース樹脂と、このベース樹脂の比重の０．７倍以下ま
たは１．７倍以上の比重を有し、かつ、誘電正接の値が
０．００５以下である充填剤とを含む封止材料を準備す
るステップと、 前記封止材料を前記基板上に注入して、前記電子部品を
封じ込めるステップと、 前記注入した封止材料を所定時間放置して、前記充填剤
を前記電子部品の表面近傍に偏在させるステップと、 前記封止材料を硬化させるステップと、を含む、電子部
品の封止方法。8. A step of mounting an electronic component on a substrate, comprising: a base resin; a specific gravity of 0.7 times or less or 1.7 times or more of a specific gravity of the base resin; Preparing a sealing material including a filler that is 0.005 or less; injecting the sealing material onto the substrate to encapsulate the electronic component; A method for sealing an electronic component, comprising: leaving the filler unbalanced in the vicinity of the surface of the electronic component by leaving it to stand; and curing the sealing material.
記ベース樹脂および充填剤に溶剤を混合するステップを
さらに含み、 前記方法は、前記封止材料を所定時間放置後に前記溶剤
を蒸散させるステップをさらに含むことを特徴とする請
求項８に記載の電子部品の封止方法。9. The step of preparing the sealing material further comprises the step of mixing a solvent with the base resin and the filler, and the method comprises the step of evaporating the solvent after leaving the sealing material for a predetermined time. The method for sealing an electronic component according to claim 8, further comprising:
の比重よりも軽く、前記基板上に搭載した電子部品の表
面を下側に向けて前記封止材料を所定時間放置すること
を特徴とする請求項８または９に記載の電子部品の封止
方法。10. The specific gravity of the filling material is lower than the specific gravity of the base resin, and the sealing material is left for a predetermined time with the surface of the electronic component mounted on the substrate facing downward. The method for sealing an electronic component according to claim 8.
比重よりも重く、前記基板上に搭載した電子部品の表面
を上側に向けて前記封止材料を所定時間放置することを
特徴とする請求項８または９に記載の電子部品の封止方
法。11. The specific gravity of the filler is greater than the specific gravity of the base resin, and the sealing material is left for a predetermined time with the surface of the electronic component mounted on the substrate facing upward. Item 10. The method for sealing an electronic component according to item 8 or 9.
含み、前記封止材料は、ベース樹脂と、このベース樹脂
に混合された誘電正接値が０．００５以下の充填剤とを
含み、前記半導体チップの表面近傍に前記充填剤が集中
して偏在することを特徴とする半導体パッケージ。12. A substrate, comprising: a semiconductor chip mounted on the substrate; and a sealing material for sealing the semiconductor chip on the substrate, wherein the sealing material is a base resin; And a filler having a dielectric loss tangent value of 0.005 or less mixed therein, wherein the filler is concentrated and unevenly distributed near the surface of the semiconductor chip.
の０．７倍以下または１．７倍以上の比重を有すること
を特徴とする請求項１２に記載の半導体パッケージ。13. The semiconductor package according to claim 12, wherein the filler has a specific gravity of 0.7 times or less or 1.7 times or more of the specific gravity of the base resin.
ダ、中空ガラス球から選択される１種以上であることを
特徴とする請求項１２または１３に記載の半導体パッケ
ージ。14. The semiconductor package according to claim 12, wherein the filler is at least one selected from silica, Teflon powder, and hollow glass spheres.
ップと、 ベース樹脂と、このベース樹脂の比重の０．７倍以下ま
たは１．７倍以上の比重を有し、かつ、誘電正接の値が
０．００５以下である充填剤とを含む封止材料を準備す
るステップと、 前記封止材料を前記基板上に注入して、前記半導体チッ
プを封じ込めるステップと、 前記注入した封止材料を所定時間放置して、前記充填剤
を前記半導体チップの表面近傍に偏在させるステップ
と、 前記封止材料を硬化させるステップと、を含む半導体パ
ッケージの作製方法。15. A step of mounting a semiconductor chip on a substrate, comprising: a base resin; a specific gravity of 0.7 times or less or 1.7 times or more of a specific gravity of the base resin; Preparing a sealing material containing a filler that is 0.005 or less; injecting the sealing material onto the substrate to encapsulate the semiconductor chip; and applying the injected sealing material for a predetermined time. A method for manufacturing a semiconductor package, comprising: leaving the filler unbalanced in the vicinity of the surface of the semiconductor chip, and curing the sealing material.
前記ベース樹脂および充填剤に溶剤を混合するステップ
をさらに含み、 前記方法は、前記封止材料を所定時間放置後に、前記溶
剤を蒸散させるステップをさらに含むことを特徴とする
請求項１５に記載の半導体パッケージの作製方法。16. The step of providing a sealing material,
The method according to claim 15, further comprising: mixing a solvent with the base resin and the filler; and the method further comprising, after allowing the sealing material to stand for a predetermined time, evaporating the solvent. A method for manufacturing a semiconductor package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000398728A JP2002201358A (en) | 2000-12-27 | 2000-12-27 | Sealing material for electronic part, method for sealing electronic part, semiconductor package, and method for making semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000398728A JP2002201358A (en) | 2000-12-27 | 2000-12-27 | Sealing material for electronic part, method for sealing electronic part, semiconductor package, and method for making semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002201358A true JP2002201358A (en) | 2002-07-19 |
Family
ID=18863632
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000398728A Pending JP2002201358A (en) | 2000-12-27 | 2000-12-27 | Sealing material for electronic part, method for sealing electronic part, semiconductor package, and method for making semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002201358A (en) |
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