JP2002196980A - Data loading method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, when an access pattern from a central processing unit to a disk device is changed with time in a same storage region, the using efficiency of a cache memory cannot be held optimally, because the operation mode in the divided and individual storage region of the disk device is fixed. SOLUTION: A disk control device is connected to the disk device and the central processing unit and provided with the cache memory with a physical region on the disk device set to a cache control unit. When no data in a cache control unit including a region to be an access target exists in the cache memory inside, only data in the region to be the access target of the central processing unit is loaded in the cache memory. In this case, when there is an access to data except for those already stored in the cache memory among the data in the cache control unit, the data except for those already stored in the cache memory is loaded in the cache memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data loading method suitable for loading data in a cache memory in a control device having the cache memory.

[0002]

2. Description of the Related Art A magnetic disk device used as an external storage device has an advantage that a large storage capacity can be realized relatively inexpensively. However, there is a natural limit to improving the access speed in data recording and reproduction due to the rotation waiting of the magnetic disk as a storage medium and the seek operation of the head.

For this reason, an electronic computer system having a magnetic disk device or the like as an external storage device is configured as follows. A cache memory such as a semiconductor memory that can be accessed at a higher speed than a magnetic disk device is provided in a magnetic disk control device or the like that is interposed between a central processing unit and a magnetic disk device and controls transmission and reception of data between the two. . By storing a part of the data stored in the magnetic disk device in the cache memory and responding to the access from the central processing unit, a large difference in operation speed between the magnetic disk device and the central processing unit is obtained. To relax. As described above, it is general to efficiently exchange data between the magnetic disk device and the central processing unit.

In such a case, the probability that the target data accessed from the central processing unit exists in the cache memory,
That is, it is important to increase the hit ratio as much as possible from the viewpoint of making the cache memory function more effectively. For that purpose, the following various techniques have been conventionally proposed.

For example, in the "Electronic Information Communication Handbook" (1988) published by Ohm, data loading to a cache memory is performed in track units.

Further, for example, Japanese Patent Application Laid-Open No. 55-15464
The technique disclosed in Japanese Patent Publication No. 8 is as follows. The storage area of the magnetic disk drive is divided into a plurality. A different operation mode is set in advance according to each of the divided storage areas. The operation mode is switched to the operation mode corresponding to the storage area specified by the input / output command from the central processing unit. An attempt is made to improve the hit rate as described above.

Further, for example, Japanese Patent Application Laid-Open No. Sho 60-14360
In the technology described in Japanese Patent Laid-Open Publication No. H10-209, the following is performed. Statistical data such as hits / misses is collected by the disk controller. The collected statistical data is transferred to the central processing unit. Based on these statistical data, an operator or a system administrator determines whether the current use state of the cache memory is optimal. Based on the determination result, the range of data loaded from the magnetic disk device onto the cache memory, that is, the cache target range is appropriately controlled. In this way, an attempt is made to improve the data transfer efficiency between the central processing unit and the magnetic disk device.

Further, the Information Processing Society of Japan, 29th National Convention, pp. In 169-170, recognition of sequential access is performed by the disk controller, and after sequential access to a certain track is completed,
A method has been proposed in which this track is treated as data that is most likely to be evicted from the cache memory.

[0009]

SUMMARY OF THE INVENTION However,
In the "Electronic Information Communication Handbook", there is no problem if the loading overhead is large and the probability that the data to be accessed exists in the cache is high, but if the probability of existence is low, the performance is rather degraded due to the introduction of the cache. There was a possibility.

To deal with this, a method of loading only the record to be accessed into the cache is conceivable. However, in general, the record length in a track is variable, and management on a track basis is basically performed. A proper loading method is required.

In Japanese Patent Application Laid-Open No. 55-154648, the disk control device instructs an access characteristic from the central processing unit and selects a loading method (operation mode) according to the instruction. Therefore, a burden is imposed on the central processing unit. If the access characteristics cannot be fully recognized by the central processing unit, an appropriate loading method to the cache memory cannot be selected.

In addition, since the operation mode is fixed with respect to each divided storage area, if the access pattern from the central processing unit to the disk device fluctuates in the same storage area over time, the cache memory is There is a problem that the use efficiency cannot be maintained optimally.

That is, it is difficult to cope with a case where a file provided in the same storage area is shared by, for example, online processing mainly for random access and main batch processing for sequential access.

In Japanese Patent Application Laid-Open No. Sho 60-14360, it is an operator or a system administrator who judges statistical information obtained in a magnetic disk control device. Therefore,
If the access pattern from the central processing unit to the magnetic disk device differs depending on the task, it is possible to optimally control the cache target range (the range of data to be loaded into the cache memory) every moment according to the task to be performed. There is a problem that it is practically impossible.

Further, in the above-mentioned paper of the IPSJ, sequential access, which is a typical access pattern to a disk device, is recognized. As a result of the recognition, only the track that has been accessed is easily controlled to be evicted from the cache, but the loading method is not selected.

An object of the present invention is to provide a loading method capable of reducing the loading overhead based on a track-based management method when the records constituting the tracks of the magnetic disk are of variable length. is there.

Another object of the present invention is to provide a loading method in a disk control device, which grasps the access characteristics of each input / output request, thereby improving the hit rate and reducing the loading overhead. It is in.

[0018]

The object of the present invention is achieved as follows. The disk control device is connected to the disk device and the central processing unit, and has a cache memory that uses a certain physical area on the disk device as a cache management unit (a cache memory management unit). When no data in the cache management unit including the area accessed from the central processing unit exists in the cache memory, only the data in the area accessed from the central processing unit is loaded into the cache memory. Perform initial loading. Thereafter, when the data in the cache management unit accesses data other than the data already stored in the cache memory, the data in the cache management unit other than the data stored in the cache memory is accessed. This is achieved by a data loading method characterized by additionally loading data into a cache memory.

Further, another object of the present invention is achieved as follows.

I / O requests are classified into sequential access and other I / O requests. With sequential access, it is easy to grasp the access characteristics, and it is easy to determine an efficient loading method.

When the access is recognized as sequential access, a plurality of tracks are pre-read / loaded from the track currently being accessed.

When it is recognized that the access is not a sequential access, a portion to be accessed from the central processing unit while the cache management unit (usually a track) containing the data to be accessed by the input / output request stays in the cache memory. Is predicted by statistical information, and only this part is loaded, thereby achieving a good balance between the hit ratio and the reduction of the loading.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a conceptual diagram illustrating the operation of an example of a cache control method according to an embodiment of the present invention. FIG.
FIG. 1 is a block diagram showing a configuration of an example of an information processing system to which the cache control method is applied.

First, an outline of the configuration of the information processing system according to the present embodiment will be described with reference to FIG.

For example, a central processing unit (Central Processes) which constitutes a part of a general-purpose computer or the like.
sing Unit) 1 (also referred to as an upper system) and a magnetic disk device 2 as an external storage device, a disk control device 3 (control device) for controlling transmission and reception of data and commands between the two. Is provided.

FIG. 2 shows one disk drive 2, but generally one disk controller is connected.

The central processing unit 1 is provided with a channel device 11 for controlling transmission and reception of data and commands between the central processing unit 1 and the outside.

On the other hand, the disk control unit 3 is provided with a channel interface control unit 31 and a device interface control unit 32, for exchanging data and commands between the channel device 11 and the disk control unit 3, respectively. Disk controller 3
And the magnetic disk device 2 for exchanging data.

Further, between the channel interface control section 31 and the device interface control section 32, there is provided a processor 33 for controlling these, and a control memory 34 storing a control program for the processor 33 and the like. .

The channel interface control unit 3
1 and the device interface control unit 32 are connected by a data path 35.

A part of the data path 35 is provided with a cache memory 36 composed of, for example, a semiconductor memory which operates much faster than the magnetic disk device 2.

Then, of the data stored in the magnetic disk device 2, those having a high probability of being accessed from the central processing unit 1 via the higher-level channel device 11 are copied in advance, and the cache memory 36 is copied. Responds to an access request from the upper central processing unit 1 with the data stored in the high-speed channel device 11.
And the efficiency of data transfer between the hard disk drive 2 and the magnetic disk device 2 which operates slowly.

Further, on the data path 35, a data buffer 37 is provided on a side closer to the device interface control unit 32 than the cache memory 36, and the device interface control unit 32, the cache memory 36 and the channel interface control unit are controlled. The data exchanged with the unit 31 and the like is configured to be temporarily stored.

The operations of the cache memory 36 and the data buffer 37 are controlled by the microprocessor 33.

On the other hand, in the magnetic disk device 2, as shown in FIG. 4, a plurality of tracks 22 are provided concentrically on both surfaces of a plurality of magnetic disks 21 as a storage medium. As shown in FIG. 3, the track 22 stores a plurality of records which are a kind of data recording unit.

On both surfaces of each magnetic disk 21, the magnetic disks 21 are simultaneously moved in the same direction in the radial direction with the distances from the center of rotation of the magnetic disk 21 being equal to each other, and onto the target track. A plurality of heads (not shown) for performing the positioning operation, that is, the seek operation, are arranged to face each other, and the recording / reproducing operation of the data such as the record for an arbitrary track 22 is performed via the head (not shown).

Furthermore, the plurality of heads can be moved at high speed only by selecting the heads without displacing the plurality of heads in the radial direction of the magnetic disk 21, that is, at equal distances from the center of rotation and without performing a seek operation that requires a long time. A cylinder 23 is constituted by a group of tracks 22 that can be accessed continuously.

Access to an arbitrary record from the upper central processing unit 1 is performed by designating a cylinder number, a head number (track number) (not shown), a record number, and the like. is there.

In this case, as shown in FIG. 1, the cache memory 36 is provided with a plurality of track slots 361 to 367... Corresponding to arbitrary some of the plurality of tracks 22 in the magnetic disk drive 2. I have. Data such as a record R stored in an arbitrary track 22 of the magnetic disk device 2 is copied (loaded) to the track slots 361 to 167... At any time in a recording format equivalent to that stored in the track 22. .

As a result, the channel device 11 can perform high-speed access when the target data exists in the cache memory 36 at the time of the access.

Further, the plurality of track slots 361 to 368...
Are managed by the cache memory management table 4.

The cache management table 4 is provided with a plurality of entries 41 corresponding to individual track slots. Each entry 41 includes storage position information (cylinder number, track number, etc.) of the track 22 from which data stored in each track slot is copied on the magnetic disk 21, and the track slot information in the cache memory 36. A pointer (not shown) indicating the storage position is recorded.

Further, each entry 41, that is, each track slot belonging to each entry 41 is stored in the cache management table 4 in the LRU method (Least
Recently Used low).

That is, when there is a request from the central processing unit 1 to access predetermined data in the magnetic disk device 2 via the channel device 11, first, the cache management table 4 is searched and stored in the cache memory 36. It is checked whether or not there is target data. If the target data exists (hereinafter, referred to as hit), high-speed access using the data in the cache memory 36 becomes possible. On the other hand, when the target data does not exist (hereinafter, referred to as a mistake), the magnetic disk device 2 is directly accessed.

In the case of this mistake, for example, data read from the magnetic disk device 2 to the channel device 11 is simultaneously copied to the cache memory 36 to prepare for the next access. In this copying, a track slot to be released is selected. A plurality of track slots 361 to 3 provided in the cache memory 36
67..., The one corresponding to the lowest (OUT side) entry 41 in the LRU management of the cache management table 4 is selected. An operation is performed to position the entry 41 corresponding to the copied track slot at the highest level (IN side) of the LRU management.

That is, since recently accessed data is highly likely to be accessed next, it is held in the cache memory 36 as long as possible. The track slot storing the data accessed at the oldest point in time is released for copying new data. In this way, the hit rate is improved.

In the present embodiment, at least the following two types of cache operation modes for defining the manner of loading desired data from the magnetic disk device 2 to the cache memory 36 at the time of the above-described mistake are provided. Is provided. Loading mode and record mode.

[0049] As shown in FIG. 3, among the plurality of records stored in any track 22 of the magnetic disk device 2, when there is access to any record R _n, behind the record R _n ( (It is not necessarily contiguous). The next record R _n, copying all records to the track end a predetermined track slot of the cache memory 36. This is the loading mode. Record mode is a mode for copying only the record R _p that was in view of the access to minimize such time occupied duration and data path 35 of the copying.

Each of the plurality of entries 41 of the cache management table 4 is configured as follows. As shown in FIG. 1, when accessing a track slot belonging to the entry 41, a counter 41a that is incremented according to a predetermined condition described later and mode identification information 41b that identifies a current cache operation mode in the track slot are included. Each entry 41 is organized as recorded.

Further, in the case of the present embodiment, the cylinder 23 including a group of tracks 22 (track slots) equidistant from the rotation center on the magnetic disk 21 is used.
Is provided with a cylinder statistical information table 5 having a plurality of entries 51 corresponding to each of them. The cache operation mode in each track slot is managed on a cylinder basis.

That is, in each entry 51 of the cylinder statistical information table 5, mode identification information 51a for recording the current cache operation mode of the cylinder 23 corresponding to the entry 51 and the total number of accesses to the cylinder 23 are stored. Access frequency recording unit 51 to be recorded
b, a loading mode counter 51c, which is incremented by +1 based on the value of the counter 41a in the cache management table 4, and the like, which will be described later, and a record mode counter 51d.

In this embodiment, the above-described cache operation may be performed in units of individual cylinders 23 according to the ratio of the value of the access count recording unit 51b to the loading mode counter 51c or the record mode counter 51d. The operation of switching the mode is automatically performed.

Hereinafter, an example of the operation of the cache control system of this embodiment will be described with reference to FIG.

The central processing unit 1 requests the disk control unit 3 to access the magnetic disk unit 2 by instructing the cylinder number, head number (track number), record number and the like via the channel unit 11. In response to this request, the processing in FIG. 5 starts.

The disk controller 3 increments the access number recording unit 51b of the corresponding cylinder number CYL # in the cylinder statistical information table 5 by 1 (step 60). next,
The cache operation mode of this cylinder is determined (step 61).

The case of the loading mode will be described. The cache memory 36 is searched according to the designated cylinder number, track number, etc., and a target record is searched (step 62). When the target record is not found (step 63), the following processing is performed.

The track slot for loading the target record is released (step 64). The release of the track slot will be described later. The subsequent records R _{m + 1} and R _{m + 2} subsequent to the target record R _m requested to be accessed by the central processing unit 1 are loaded (step 6).
6). This loading is realized by loading from the track 22 of the corresponding cylinder number and track number of the magnetic disk device 2 to a predetermined track slot 362 managed by the LRU method, for example. The loading simultaneously with or, after storing the track slot, channel device requested record R _m 11
(Step 67). The mode identification information 41b of the corresponding entry 41 in the cache management table 4 indicates the loading mode (step 68). Cache management table 4 corresponding to the track slot
The initial value 1 is set in the counter 41a of the corresponding entry 41 (step 69).

Thereafter, the track slot 36
2, if there is an access request to the subsequent records R _{m + 1} and R _{m + 2} , the records R _{m + 1} and R _{m + 2} can be accessed at high speed because they are held in the cache (step 70). In this case, the disk controller 3
Is the counter 41a of the entry 41 corresponding to the track slot 362 in the cache management table 4.
Is incremented by 1 (step 71).

[0060] Thus, the track slot 362 in the current loading mode, once at the beginning of the record _{R m,} which was the impetus of the road, behind the record _{R m + 2} 1
The value of the counter 41a of the cache management table 4 becomes 2 since the access has been made twice in total.

That is, the number of accesses to the corresponding track slot in the current loading mode can be known from the counter 41a.

That is, when access is made only once
(Only when loading), the counter remains at the initial value 1.
is there. For example, tracks in the same loading mode
Since the value of the counter 41a of the slot 365 is 1,
Leading R that triggered the code _nIs only accessed
I understand that

The track slot 365 currently in the loading mode is released from the cache memory 36 when new data is next loaded into the cache (except when the track slot 365 is accessed). is there. That is, it is assumed that the order of the LRU method of the entry 41 of the cache management table 4 corresponding to the track slot 365 is the lowest.

At this time, in this embodiment, when the track slot 365 in the loading mode is released (step 64), the entry 4 corresponding to the track slot 365 in the cache management table 4 is set.
If the counter 41a of No. 1 is equal to or smaller than the prescribed value (in the case of the present embodiment), the cylinder statistical information table 5
In, the loading mode counter 51c in the entry 51 of the cylinder 23 to which the track slot 365 belongs is incremented by 1 (step 65).

That is, the value of the loading mode counter 51c in the cylinder statistical information table 5 is such that, after loading into the cache memory 36 in the loading mode, records other than the head record of the track slot that triggered the loading have never been recorded. This indicates how many track slots in the cylinder 23 have been opened without access.

[0066] Then, the disk control unit 3 determines the ratio _{X L} with respect to the value of the access count record unit 51b of the value of the loading mode counter 51c each time comes access to the cylinder 23 (step 72).

[0067] Then, if it exceeds the prescribed percentage of where this ratio _{X L} (K) (in the present example K = 0.8) (step 73), when loaded from the magnetic disk device 2 to the cache memory 36 It is determined that it is useless to copy a plurality of records in the same track in the loading mode, and the cache operation mode is switched from the current loading mode to the record mode (step 74).

At the same time, the access count recording unit 51b and the loading mode counter 51c of the entry 51 corresponding to the cylinder 23 in the cylinder statistical information table 5
Is cleared (step 75).

For example, in the cylinder statistical information table 5 of FIG. 1, in the entry 51 having the cylinder number CYL # of 248, the values of the access number recording section 51b and the loading mode counter 51c are 14
And a 12, the _{X L = 12/14 ≒ 0.85} . Change of the operation mode because X _L exceeds 0.8 prescribed is determined to be necessary.

For this reason, the disk control device 3 thereafter
Loading from the group of tracks 22 belonging to the cylinder 23 having the cylinder number CYL # of 248 to the cache memory 36 is performed in the record mode until the record mode is determined to be inappropriate.

On the other hand, if the cylinder 23 for which an access request has been made from the upper central processing unit 1 is currently in the record mode (step 61), first, the cache memory is designated by the designated cylinder number, track number, record number and the like. 36 is searched for a target record (step 76).

Here, in the track slot 367 currently in the record mode, the track slot 36
Subsequent record R on track 22 corresponding to 7
_In the case of access to _{p + 2} , the cache memory 36
There is no target record _{Rp + 2} above (step 7
7) Therefore, the data must be loaded from the track 22 of the magnetic disk device 2 to the cache memory 36 (step 78). Then, the record is output to the channel device 11 (step 79).

At this time, the disk controller 3 of this embodiment
Increments the record mode counter 51d of the entry 51 of the cylinder statistical information table 5 corresponding to the cylinder 23 to which the track belongs (step 80).

That is, the record mode counter 51d of the entry 51 corresponding to an arbitrary cylinder 23 loads only a single record from an arbitrary one of a group of tracks 23 belonging to the cylinder into the cache memory 36 in the record mode. Indicates the number of times that a succeeding record on the same track as the record is accessed, and the loading in the record mode is insufficient.

[0075] Then, a ratio _{X R} for the values of the access count record unit 51b of the value of the record mode counter 51d each time comes access to the cylinder (step 81). If it exceeds the prescribed value is the ratio X _R (L) (in the case of the present example L = 0.6) (Step 8
2) The cache operation mode is automatically switched from the current record mode to the loading mode (step 83).

The access count recording unit 5 of the entry 51 corresponding to the cylinder 23 in the cylinder statistical information table 5
1b and the record mode counter 51d are cleared (step 84).

For example, the entry 51 whose cylinder number CYL # is 249 in the cylinder statistical information table 5 of FIG.
In the current value of the access count record unit 51b and the record mode counter 51d are respectively 13 and 8, the _{X R = 8/13 ≒ 0.62} . Since X _R exceeds a prescribed value 0.6 is necessary to change the cache operation mode.

Therefore, the disk control device 3 thereafter loads data from the track 23 belonging to the cylinder 23 having the cylinder number CYL # of 249 to the cache memory 36 in the loading mode until it is determined that the loading mode is inappropriate.

If there is a target record in the cache memory 36 in the record mode, the record is output to the channel device (step 85).

As described above, in this embodiment, the counter 41a and the mode information section 41b provided in each entry 41 of the cache management table 4 and the entry 51 of the cylinder statistical information table 5 are provided. The disk control device 3 controls the cylinder 23 and the like according to the operation status of each cache operation mode, which is grasped by statistical information based on the access number recording unit 51b, the loading mode counter 51c, the record mode counter 51d, and the like. The unit has a learning function of automatically switching the cache operation mode between the loading mode and the record mode.

Therefore, even if the access pattern from the central processing unit 1 to the data stored in the magnetic disk device 2 changes every moment due to various circumstances,
It is possible to always maintain the optimal cache operation mode without human intervention.

As a result, the cache memory 36 can be always and effectively used.

In an information processing system including the central processing unit 1, the magnetic disk unit 2, the disk control unit 3, etc., the efficiency of data transfer between the central processing unit 1 and the magnetic disk unit 2 is greatly improved. .

The invention made by the present invention has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the scope of the invention. Needless to say.

For example, in the above embodiment, the case where the magnetic disk device is controlled by one disk controller has been described. However, the present invention is not limited to this, and the magnetic disk device may be controlled by a plurality of magnetic disk controllers. . In that case, the statistical information is shared between the respective disk control devices.

In the above embodiment, the magnetic disk subsystem including the magnetic disk unit and the disk control unit is connected to one central processing unit. Needless to say, this may be done.

Further, in the above-described embodiment, a case has been described in which the cache operation mode and the statistical information are managed in cylinder units. However, the present invention is not limited to this, and may be managed in volume or data set units.

Further, it goes without saying that the cache operation mode is not limited to the one exemplified in the above embodiment.

According to the cache control method of the present invention, in a control device having a cache memory interposed between a central processing unit and an external recording device and storing a part of data of the external storage device, It has a cache operation mode, and has a learning function of automatically switching the cache operation mode according to the operation status of each cache operation mode. By monitoring whether the value of statistical information obtained as the ratio of the number of accesses from the central processing unit to the number of times the currently selected cache operation mode has been enabled or disabled has exceeded a specified threshold value It is possible to judge whether or not the operation status of the current cache operation mode is appropriate. If necessary, it is possible to automatically switch to another more suitable cache operation mode.

As a result, even if the access pattern from the central processing unit changes every moment, there is an effect that the optimum cache operation mode can be always maintained and the cache memory can be effectively used.

In the information processing system of the present invention, a central processing unit, an external storage device, and a part of the data in the external storage device are interposed between the central processing device and the external storage device. An information processing system, comprising: a control device having a cache memory to perform, comprising a plurality of cache operation modes, and having a learning function of automatically switching the cache operation mode according to the operation status of each cache operation mode. are doing. By monitoring whether the value of statistical information obtained as the ratio of the number of accesses from the central processing unit to the number of times the currently selected cache operation mode has been enabled or disabled has exceeded a specified threshold value It is possible to judge whether or not the operation status of the current cache operation mode is appropriate. If necessary, it can be automatically switched to another more suitable cache operation mode.

Thus, even if the access pattern from the central processing unit changes every moment,
It is possible to always maintain the optimal cache operation mode and to make the cache memory function effectively, and it is possible to improve the information transfer efficiency between the central processing unit and the external storage device in which the cache memory is interposed. effective.

Next, another embodiment for improving the efficiency of information transfer between a central processing unit and an external storage device by a disk control device having a cache memory, as in the above-described embodiment, will be described. In this embodiment, a method for improving the hit ratio and reducing the loading overhead will be described.

FIG. 6 shows the structure of the cache memory 36. The cache memory 36 is divided into fixed-length segments 30. In order to store one track of the magnetic disk drive 2, one or more constant segments 30 are required.

First, a case where one track is stored in a plurality of segments 30 will be described. Note that the number of segments is n. The empty segment pointer 38 is
Points to a pointer in the set of empty segments 30. Each segment 30 has a pointer and a segment 3
When 0 is free, it points to the next free segment.
However, the pointer of the last empty segment 30 is null.
And

FIG. 7 shows the structure of the cache management table 6. The cache management table 6 is the same as that shown in FIG. 1, but shows only the parts necessary for explaining the present embodiment. The cache management table 6 includes a cache management block 40. The cache management block 40 includes the cache memory 36 described above.
Is assigned to one or more tracks corresponding to one or more tracks. The empty block pointer 42 is a pointer to the first cache management block 40 of the set of empty cache management blocks 40.

FIG. 8 shows the cache management block 40.
It shows the configuration of FIG. The device ID 58, the cylinder ID 59, and the track ID 52 are identifiers relating to the disk device 2, cylinder, and track of the track on the disk device 2 corresponding to the cache management block.
The segment pointers (a) 53 to (n) 54 are n
A pointer to the number of segments 30 is shown. Of these pointers, only the number of segments that store the portion stored in the cache memory 36 in the corresponding track is valid, and the rest are null. A valid pointer becomes a pointer to the corresponding segment 30.

The storage start record identifier 55 is an identifier of a record whose storage has started in the cache memory 36. For example, the storage start position of a track of this record on the disk device 2 and the storage end record identifier 56 are 36 shows the identifier of the record that was last stored. That is, the cache memory 36
, A record group in the range indicated by the storage start record identifier 55 and the storage end record identifier 56 is stored. The next pointer 57 is a pointer to the next cache management block 40 when the cache management block 40 is empty. However, when there is no other empty cache management block 40, the value becomes null.

FIG. 9 shows a processing flow of the processor 33. FIG. 9 is a processing flowchart when the processor 33 receives an input / output request from the central processing unit 1. Here, only processing relating to one of the points of the present invention will be described. In step 90, the storage status of the input / output target track in the cache memory 36 is checked. next,
If the entire target track of the received I / O request does not exist in the cache memory 36, the central processing unit 1
Issue a positioning request to the disk device 2 in accordance with the positioning request (instruction to the disk device 2 so that necessary data can be read out) (step 91). At this time, a sufficient number of segments 30 for storing one track is secured.

Although a part of a track to be subjected to an input / output request is stored in the cache memory 36, a record to be accessed is a part of the track after the group of records stored in the cache memory 36. If there is, process as follows. If there is a record to be accessed in a portion behind the storage end record identifier 56, as shown in step 92, the data from the record following the record indicated by the storage end record identifier 56 to the last record in the track is stored. Therefore, a positioning request is issued to the disk device 2. At this time, there are enough segments 3 to store the last record of this track.
Reserve the number 0.

If the record to be accessed is a part before the record group existing in the cache memory 36, the following processing is performed. Storage end record identifier 5
If there is a record to be accessed in a part ahead of the record No. 6, as shown in step 93, the data from the record following the record indicated by the storage end record identifier 56 to the last record in the track is loaded. In order to store from the first record to the record before the record indicated by the storage start record identifier 55, a positioning request is issued to the disk device 2. In this case, if the last record of this track has been stored, loading is started from the first part of the track. At this time, as many segments 30 as necessary for the load processing are secured.

Next, the processing flow of the processor 33 when receiving the positioning completion report from the disk device 2 will be described.
This will be described with reference to FIGS.

First, a case where a record in a track to be accessed from the central processing unit 1 does not exist in the cache memory 36 will be described. FIG. 10 step 94
As shown in (1), an input / output process is performed in accordance with an input / output request from the central processing unit 1. At this time, when a record is read from the disk device 2, the record is loaded into the cache memory 36. The record received from the central processing unit 1 is written to the disk device 2 and also to the cache memory 36 at the same time as writing to the disk device 2. Thereafter, a storage start record identifier 55 and a storage end record identifier 56 are set. In this case, records to be accessed from the central processing unit 1 (records to be written to the disk device 2) are a continuous record group.

FIG. 13 shows the data storage format at this time. As shown in the figure, the first record to be accessed is stored from the beginning of the segment 30. As a result, if the number of records to be accessed is small, not only the loading overhead but also the used capacity of the cache memory 36 can be reduced.

FIG. 11 shows a case where a positioning completion request has been received for the process of loading from the record following the record indicated by the storage end record identifier 56 to the last record of this track into the cache memory 36. is there. In this case, as shown in step 95, processing for loading from the record following the record indicated by the storage end identifier 56 to the last record is executed. The storage end record identifier 56 is set as the position of the end point of the track.

FIG. 14 shows the data storage format at this time. Thereafter, in step 96, the CPU is logically reconnected to the central processing unit 1 and the input / output processing with the central processing unit 1 is started. At this time, the newly loaded record is added after the previously loaded record.

FIG. 12 shows that from the next record indicated by the storage end record identifier 56 to the last record of this track is loaded into the cache memory 36, and then the storage start record identifier is read from the head record of the track. This is a process when the positioning completion process is received from the disk device 2 in order to execute the process of loading the records up to the record indicated by 55 into the cache 21. This processing is executed in step 95. However, if the last record of the track has already been loaded, loading is started from the first record of the track. At this time, the storage start record identifier 56 is set to the record before the storage start record identifier 55.

FIG. 15 shows this storage format. Thereafter, in step 96, input / output processing with the central processing unit 1 is started. At this time, the record group up to the last record of the track is stored after the record group stored in the cache memory 36, and the record group from the head of the track is stored thereafter.

In the above embodiment, when an access request is made to a record after the group of records loaded in the cache memory 36, as shown in FIG.
Although an example has been described in which the record is loaded from the record next to the record group loaded in the cache memory 36, as shown in FIG. 12, all records other than the record group loaded in the cache memory 36 are deleted. , May be loaded into the cache memory 36.

The above is the case where a plurality of segments 30 for storing tracks are allocated. In this case, when the entire track is not stored in the cache memory 36, the capacity can be saved as compared with the case where the segments 30 are assigned one-to-one with the tracks.

Next, an embodiment in which one segment 30 is assigned to one track will be described. In this case, the format of the cache management block 40 shown in FIG.
a. The difference from FIG. 8 is that only one segment pointer 150 is required.

The storage format in the segment 30 may be such that a record accessed first by the central processing unit 1 may be stored from the beginning of the segment 30, as shown in FIG. You may take. That is, as shown in FIG. 17, the storage position of this record is determined according to the relative position from the beginning of the track. In this case, the first record in the track is stored at the first record in the segment 30.

The processing of the processor 33 may basically be the contents shown in the processing flow of FIGS. However, the timing for allocating the segment may be only when there is an access when the record of this track does not exist in the cache memory 36, that is, only the portion corresponding to step 91 in FIG. In the case of the storage format shown in FIG. 17, when a record at a position before the record indicated by the storage start record identifier 55 is accessed, the record of the record indicated by the storage start record identifier 55 from the beginning of the track is Up to the previous record may be stored.

In the above-described embodiment, the number of processors 33 in the control unit 3 is one. A plurality may be provided. The data transfer process between the central processing unit 1 and the cache memory 36 and the data transfer process between the disk device 2 and the cache memory 36 may be executed in parallel. Essentially, in this embodiment, the cache memory 36
The other components are not indispensable.

As described above, according to the present embodiment, the record to be loaded into the cache memory based on the existence state in the cache memory of the record in the access target track of the input / output request from the central processing unit. Since the group is determined, it is remarkable that a data loading method capable of reducing the loading overhead based on the track-by-track management method can be realized even when the records constituting the track are of variable length. It is effective.

Further, another embodiment for reducing the loading overhead to the cache memory and improving the hit ratio will be described.

FIG. 18 shows the structure of the control memory 34.
The control memory 34 stores modules for realizing the functions of the processor 33. Here, portions related to the present embodiment will be described. The access characteristic check unit 7 checks the access characteristic of the input / output request and stores information relating to the access pattern. The loading selection unit 8 determines a loading pattern according to the information collected by the access characteristic check unit. The loading execution unit 9 has a function of performing loading execution control according to the loading pattern selected by the loading selection unit 8.

FIG. 19 shows a further different structure of the cache management table 4. Cache management table 10
Shows parts related to the present embodiment. The cache management block 40b is provided corresponding to a track to which one or more segments 30 in the cache memory 36 are allocated (meaning that a certain portion of the track is stored in the cache). Each cache management block 40b
Is calculated by the forward pointer 48 and the backward pointer 47.
They are chained in RU (Most Recently Used) order. The MRU pointer 42 points to the cache management block 40b of the track most recently subjected to input / output. LRU (Least Recentl)
y Used) pointer 43 is stored in the cache memory 36.
Indicates the cache management block 40b of the track that has not been the input / output target for the longest time in the set of tracks stored in the list. Therefore, a miss (the data to be accessed does not exist in the cache memory 36).
Occurs, a new segment 30 needs to be allocated, and if there is no empty segment, the segment 30 storing the track corresponding to the cache management block 40b indicated by the LRU pointer 43, and the cache management block 40b Will be released. The access time 44 corresponds to the cache management block 40b.
Stores the time when the track corresponding to is the most recent input / output target. (Accordingly, if the forward pointer 48 is followed from the MRU pointer 42, the access time 44 in each cache management block 40b will be slowed down.) The track is not allocated, and the empty cache management is not performed. The block 40b is based on the free block pointer 45,
0b is pointed to and each cache management block 40b
Is pointed by the forward pointer 48 and the backward pointer 47.

The access characteristic information 46 stores information collected by the access characteristic check unit 7 for each input / output request in cache management units, that is, in this embodiment, in track units. In the present embodiment, the access characteristic information 4
6 is provided. A part of this information may be provided in the cache management block 40b to reduce the required storage capacity.

FIG. 20 shows the structure of the access characteristic information 46. In this embodiment, it is determined whether the received input / output request is a sequential access. If it is determined that the access is sequential access, a plurality of tracks that can be accessed thereafter are loaded. Hereinafter, this is simply referred to as multi-track loading.

When it is recognized that the access is not a sequential access, the data of the track is
The part actually accessed by the central processing unit 1 during a period from when the data is partially or wholly loaded into the cache memory 36 until the entire data of the track is expelled from the cache memory 36 from the state where it is not present at all. Understand and select a loading method based on this.

First, information necessary for sequential access recognition will be described. sequential·
The checking flag 100 is a flag indicating that it is checking whether data in the track is sequentially accessed. Specifically, when the first record of the track corresponding to the access characteristic information is accessed, this flag is turned on. Thereafter, when access from the first record onward is not performed sequentially, or when access to the last record of this track is completed sequentially (when it is recognized that this track has been sequentially accessed), Turn off the flag. The sequential identification address 101 indicates the position from the beginning of the track where the record to be accessed when the next access is performed sequentially is stored. The sequential recognition flag 102 is turned on when the first record of the track is sequentially accessed. The timing of turning off is when the next input / output request is received for this track.

For an access other than the sequential access, when an input / output request is accepted, the record of the track to be accessed does not exist in the cache 21 (hereinafter, this is referred to as a track miss), and this track is started. Based on the idea that the part to be accessed by the central processing unit 1 is to be loaded, during the period until the data of
The loading method shall be determined.

Next, information for recognizing a part of the track which is actually accessed by the central processing unit is shown.
One idea is that a track is represented by a track bit pattern 108 of a plurality of bits as shown in FIG. 21 with a unit of a fixed length (P bytes in FIG. 21) as one bit, and when a certain record is accessed, The bit corresponding to the area where this record is stored on the track is turned on. (In FIG. 21, record 1 and record m are accessed, and record 2 is not accessed. ) In the cache memory 36, only the area where the bit is ON is loaded. However, when a track is missed and all the tracks are not loaded, and when this track is subsequently subjected to input / output, a part of the data of this track exists in the cache memory 36 but the record to be accessed is May not exist in the cache memory 36. In this case, a method of newly loading the accessed record into the cache memory 36 is adopted. However, since the disk device 2 is a rotating body, if there is a gap in a set of ON bits, the loading time itself does not become short. Therefore, in the present embodiment, a case where the part accessed by the central processing unit is recognized based on the concept shown in FIG. 22 will be described below in detail.

In FIG. 22, the tracks are divided into a higher-level access section 110, a front section 109, and a rear section 111. The upper access unit 110 is a record group to which the central processing unit 1 has access when an input / output request for the track is received and a track or a mistake occurs. Front part 1
Reference numeral 09 denotes a record group at a position before the upper access unit 110, and a rear part 111 is a record group at a position after the upper access unit 110.

In the present embodiment, it is assumed that the following pattern is used as a loading pattern at the time of a track miss for accesses other than the sequential access. (The present invention is effective even if it has a loading pattern other than these.) (A) Track loading: Loading the entire track. (B) Upper access + backward loading ... Loading the upper access unit + backward. (C) Upper Access Unit / Loading ... Only the upper access unit is loaded.

Even when the above-described loading pattern is prepared, (b) the upper access unit + backward loading is executed, and when the record exists in the cache memory 36, the record of the front portion 109 of the track is recorded. A mistake occurs when there is access to. This is called a front miss. (C) When the upper access unit / loading is executed, a mistake occurs even when a record in the rear unit 111 is accessed. This is called a rear miss. The processing when a front mistake or a rear mistake occurs is described below. (1) Front miss: All records in the track that have not been loaded into the cache memory 36 are loaded into the cache memory 36. (2) Rear miss: Only the rear part 111 is loaded into the cache.

When the above loading is performed, the upper access section 110, the front section 109, and the upper section from the occurrence of a track miss (front miss, rear miss) until the entire track is evicted from the cache memory 36.
The part of the rear part 111 actually accessed by the central processing unit 1 is grasped and stored. The statistical information on the accessed portion is collected, and when a track miss occurs, a loading method determined to be appropriate is selected. In this embodiment, the most frequently used loading pattern in the past q times is selected.

For example, when the rear part 111 is accessed most frequently, (b) the upper access part + the rear part loading is selected.

Information to be obtained in the access characteristic information 46 as information to be acquired to realize the above method will be described below.

The start / end address 103 is a track
At the time of a miss, the start / end address on the track of the upper access unit 110 accessed by the central processing unit 1 is shown.

The front part access flag 104 and the rear part access flag 105 are information indicating whether the central processing unit 1 has accessed the front part 109 and the rear part 111 after a track miss. The access part checking flag 106 is a flag indicating that it is under check whether the front part 109 and the rear part 111 are accessed.

The statistical information 107 includes information indicating whether the front or rear part has been accessed during the entire track is expelled from the cache memory 36 after the occurrence of a track miss, that is, the front access flag 104, The information of the rear access flag 105 is past r
It is the one that accumulated.

However, in order to save storage capacity, the statistical information 107 may be stored in a unit larger than a track, for example, for each cylinder.

Hereinafter, the processing flow chart of the access characteristic check section 7 and the loading selection section 8 will be described. The loading execution unit 9 only performs loading according to the instruction of the loading selection unit 8.

First, the processing flow of the access characteristic check unit 7 will be described. The access characteristic check unit 7 includes:
There is recognition of sequential access and recognition of other access characteristics. First, the part relating to recognition of sequential access will be described.

FIG. 23 shows the processing when the head record of the track is accessed. In step 120, the sequential check flag 100 is turned on, and the process is terminated.

FIG. 24 shows a process executed when the sequential check flag 50 of the track is turned on when the process for the input / output request is received. First, in step 121, it is checked whether or not the position of the record to be accessed by the received input / output request from the beginning of the track matches the sequential determination address 101. If they match, the record is being accessed sequentially, so no particular processing is performed. If they do not match, in step 122 the sequential check flag 100 is turned off.

FIG. 25 shows a process executed when the sequential check flag 100 of the track is ON when the process for the input / output request is completed. In step 123, it is checked whether the input / output processing has been completed up to the last record of the track. If not completed, in step 124, the relative address from the beginning of the track of the record next to the record processed by this input / output request is stored in the sequential determination address 101.

When completed, the records of this track are accessed sequentially, so that
In step 125, the sequential recognition flag 1
02 on, sequential check flag 1
Turn off 01.

FIG. 26 shows a process when the sequential recognition flag 102 of the track is turned on when an input / output request is received. In this case, in step 126, the sequential recognition flag 102 is turned off.

Next, processing for an access recognized as not a sequential access will be described.

FIG. 27 shows the processing executed after loading other than the multiple track loading in the case of a track error. (Multi-track loading is performed when sequential access is recognized.) In step 127, the central processing unit 1 sets a record group in the track to which an input / output request is actually accessed. That is, the start position and the end position of the upper access unit 110 from the beginning of the track in FIG. Further, in step 128, the access part checking flag 106 is turned on.

FIG. 28 shows an access unit checking flag 1
This is a process when an input / output request is received for the track when 06 is ON. In step 129, the record to be accessed by the received input / output request is
Of the front part 109, the high-order access part 110, and the rear part 111 shown in FIG.

If the upper access unit 110 is to be accessed, the process is terminated without doing anything.

In the case where the front part 109 is to be accessed, in step 130 the front part access flag 10
When 4 is off, it is turned on (there is no processing when it is on). In step 131, if the entire track has not been loaded into the cache memory 36, an instruction is given to the loading execution unit 9 to load the unloaded portion.

If the rear part 111 is to be accessed, at step 132, the rear part access flag 10
If 5 is off, it is turned on (there is no processing if it is on). In step 133, the rear unit 111 instructs the loading execution unit 9 to load the rear unit 111 that has not been loaded into the cache memory 36.

FIG. 29 shows a process executed when the track is removed from the cache memory 36 and the front / rear part checking flag 106 is ON.

First, in step 134, the access unit checking flag 106 is turned off. Next, step 135
, The forward access flag 10 for the past r times
4. Of the statistical information of the rear access flag 105,
Except for the oldest information, the current forward access flag 1
04, the contents of the rear access flag 105 are stored. Thereafter, in step 136, the front access flag 104 and the rear access flag 105 are turned off.

Next, a processing flow of the loading selection section 9 is shown in FIG. FIG. 30 is executed when a track miss occurs.

First, at step 137, it is checked whether this input / output request is an access to the first record of the track. Otherwise, jump to step 140. In the case of access to the first record, in step 138, it is checked whether the sequential recognition flag 102 of the access characteristic information 46 of the two tracks before the track to be accessed is on. In the case of this embodiment, only two tracks are checked, but the present invention is effective even if the number of tracks is not two. If not on, jump to step 140.

If it is on, it is determined that this access is a sequential access, and in step 139, the loading execution unit 9 is instructed to load a plurality of tracks, and the processing is terminated.

The process started from step 140 is a process for selecting a loading method when it is determined that the access is not a sequential access. In step 140, based on the statistical information 107, the past q access patterns include patterns in which neither the front part 109 nor the rear part 111 are accessed, patterns in which only the rear part 111 is accessed, and patterns other than the above two patterns. Are classified into 3 categories. As a result, if the number of patterns in which neither the front section 109 nor the rear section 111 has been accessed is the largest, in step 141, the upper access section loading is instructed to the loading execution section.

If the number of patterns accessed by the rear part 111 is the largest, the loading of the upper access part + the rear part is performed in step 142 by the loading execution part 9.
Instruct to.

If the number of other patterns is the largest,
In step 143, a track loading is instructed to the loading execution unit 9.

Here, when loading is selected,
Although only the statistical information 107 of the track is referred to, the statistical information 107 other than the track may be referred to.

In the embodiment described above, in order to recognize the sequential access, only one sequential identification address 101 is provided to check whether the records in the track are continuously accessed. For this reason, when a relatively frequent process of sequentially updating records that have been sequentially read occurs, it cannot be recognized as sequential access. Therefore, this problem is solved by recognizing sequential access of read processing and write processing. In this case, the configuration of the access characteristic information 46 is as shown in FIG. 31 instead of FIG. The difference from FIG. 20 is that the sequential check flag 100, the sequential identification address 101, and the sequential recognition flag 102 in FIG. Which information is handled depends on
It depends on whether the received I / O request is a read request or a write request, and the operation timing, method, etc.
This is the same as the embodiment described above.

Also, when performing sequential access recognition, the condition that the position from the beginning of the track of the record which is the access effect of the input / output request for reception is exactly the same as the sequential identification address 101 has been used. However, it may be recognized that the access is a sequential access even though it has a certain width.

In the embodiment described above, the loading pattern when a track miss occurs for an access other than the sequential access includes three patterns of upper access section loading (upper access section + rear section), loading, and track loading. But this 3
It is conceivable to add a pattern without loading to one pattern. This is because, after loading at the time of a track miss, the entire track concerned is
This is effective when there is no access to the track before being ejected from the track.

In this case, it is necessary for the central processing unit 1 to monitor not only the front section 109 and the rear section 111 but also the upper access section 110 after the loading at the time of the track miss, in order to monitor the portions as the access effects. .

Further, when a pattern without loading is executed, the following recognition needs to be performed. That is, when a track miss occurs, this track
Whether a miss occurred because the previous track miss occurred because no loading was performed, or whether a track miss occurred due to the long access time interval to the track even if loading was performed There is a need to. In the former case, there is no need for loading. However, in the latter case, if the access at this time is to the upper access unit 110, it means that it was necessary to load the upper access unit at the time of the previous track miss. Similarly, if the access at this time is for the rear part 111, it is necessary to execute the loading of (upper access part + rear part). If it is for the front part 109, it means that track loading had to be performed. Therefore, it is necessary to make these distinctions, store the loading method that should have been selected at the time of the previous track miss in the statistical information 107, and reflect it in the subsequent selection of the loading method. At this time, if the contents stored in the statistical information 107 indicate that no loading was necessary at the time of the previous track miss, the statistical information 107 indicates that the upper access unit 110, the front unit 109, and the rear unit 111 were not accessed. Will be stored. If it is necessary to perform some kind of loading at the time of the previous track miss, if the access at this time is (a) the upper access unit 110, the upper access unit 11
The statistical information 107 indicates that there has been an access to 0, (b) that the rear part 111 has been accessed for the rear part 111, and (c) that the front part 109 has been accessed for the front part 109. Will be stored.

In order to determine whether some kind of loading was necessary at the time of the previous track error, the time at which the track error occurred is stored in the access characteristic information 46a. Next, when a track miss occurs, this time is compared with the access time 44 in the cache management block 40b pointed to by the LRU pointer 43. In the case where the flushing method from the cache memory 36 is the LRU method, if this time is later than the access time, even if the loading was performed at the time of the previous track miss, the cache memory 3
You have been kicked out of 6. Otherwise,
It still depends on the cache memory 36, which means that loading is necessary.

FIG. 32 shows the structure of the access characteristic information 46b when a pattern without loading is provided. Similarly, FIG. 33 shows a configuration 46c when a pattern without loading is considered in the access characteristic information 46a of FIG.

Hereinafter, newly provided information will be described. The upper access flag 170 is a flag for checking access to the upper access unit 110. The track miss occurrence time 171 is provided to store the track miss occurrence time. The purpose of using the upper access flag 170 and the track miss occurrence time 171 is as described above.

The difference between the statistical information A 172 and the statistical information 107 is that the statistical information 107 is past information of the forward access flag 104 and the backward access flag 105, whereas
The statistical information A172 is obtained by adding past information of the upper access flag to this. The relationship between the contents of the statistical information A172 and the loading method to be selected at the time of a track miss is shown below. (A) Upper access section 110, front section 109, rear section 1
When there are the most patterns with no access to 11 ...
… No loading. (B) The case where the pattern of accessing only the upper access unit 110 is the largest. Loading of the upper access unit. (C) The rear part 111 or the upper access part 110
+ When the pattern that accesses only the rear part 111 is the most frequent ... Upper access two parts + rear part loading. (D) Other than the above three cases: Track loading.

The basic concept when a pattern without loading is provided, the purpose of using the newly provided information, and the method of determining the loading to be selected when a track miss occurs have been described above. The processing flow is omitted because there is not much difference from the case where the pattern without loading is not provided.

In the above embodiment, a case has been described in which the upper computer system grasps the area actually accessed by the host computer system as the grasp of the access characteristics for accesses other than sequential and access. As other content,
There is a track hit rate (the rate at which records to be accessed exist in the cache memory 36). At this time, when the hit ratio becomes equal to or less than a certain value, a control may be considered in which this track is not set as a target to be loaded into the cache memory 36.
There are cases where the access characteristics change and it becomes better to load. However, the cache memory 36
The hit rate can be measured if it is targeted for loading, but if it is not targeted for loading,
It is difficult to measure the hit rate. For this reason, the approximate value of the hit ratio is grasped from some information. FIG.
FIG. 35 shows the data structure of the access characteristic information section 46c in this case, and FIG. 35 shows the processing flow. FIG. 34 shows a structure corresponding to FIG. 20 (a figure corresponding to FIG. 31 is omitted). Hereinafter, records other than the sequential access will be described. The track miss occurrence time 171 is the same as the track miss occurrence time 171 as shown in FIG. 32, but a track miss has occurred, but the time at which this track is determined not to be loaded on the cache memory 36 is recorded. . How to use the miss function 192 and the hit function 191 will be described in the description of the processing flow in FIG. However, FIG.
In the processing flow of (1), the track determines that loading is not performed on the cache memory 36, so that all input / output requests result in a track miss. In step 144, when this track is to be accessed, the track miss occurrence time 171 is compared with the access time 44 of the cache management block 40b indicated by the LRU pointer 43. Track miss occurrence time 17
If 1 is an older time, even if loading was performed at the time of the last track mistake,
In step 145, the miss function 191 of FIG.
increase. Otherwise, in step 146, the hit function 192 is increased and the track miss occurrence time 18
1 is updated. Hit function 192 and Miss function 191
Becomes larger than a certain value, and when the hit ratio {hit function 1921 (hit function 191 + miss function 191)} becomes a certain value or more from these two values, it becomes possible to load the data into the cache 21 again. .

[0168]

As described above, according to the present invention, a group of records to be loaded into the cache is determined based on the existence state in the cache of the record in the access target track of the input / output request from the host system. Therefore, even when the records constituting the track are of variable length, there is a remarkable effect that a data loading method can be realized in which the loading overhead can be reduced based on the track-based management method. be able to.

Further, according to the present invention, the reduction of the loading overhead to the disk cache and the improvement of the hit ratio can be realized in a well-balanced manner.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating the operation of an example of a cache control method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an example of an information processing system to which a cache control method is applied.

FIG. 3 is a conceptual diagram illustrating a cache operation mode in a cache control method according to one embodiment of the present invention.

FIG. 4 is a conceptual diagram showing an example of a configuration of an external storage device.

FIG. 5 is a flowchart showing the operation of a cache control method according to one embodiment of the present invention.

FIG. 6 illustrates a configuration example of a cache memory.

FIG. 7 is a diagram showing a configuration of a cache management table.

FIG. 8 is a diagram showing a configuration of a cache management block.

FIG. 9 is a processing flowchart of a processor in one embodiment of the present invention.

FIG. 10 is a processing flowchart of a processor according to another embodiment of the present invention.

FIG. 11 is a processing flowchart of a processor according to another embodiment of the present invention.

FIG. 12 is a processing flowchart of a processor according to another embodiment of the present invention.

FIG. 13 is a diagram showing a data storage format according to the embodiment of the present invention.

FIG. 14 is a diagram showing a data storage format in the embodiment of the present invention.

FIG. 15 is a diagram showing a data storage format according to the embodiment of the present invention.

FIG. 16 is a diagram showing another embodiment of the cache management block.

FIG. 17 is a diagram showing a data storage format in the embodiment of the present invention.

FIG. 18 is a diagram showing a configuration example of a program for executing main functions of the present invention.

FIG. 19 is a diagram showing a configuration of a cache management table.

FIG. 20 is a diagram showing a configuration of access characteristic information.

FIG. 21 is a diagram showing an example of a method of recognizing a part accessed by a CPU in a track.

FIG. 22 is a diagram showing another example of a method of recognizing a portion accessed by a CPU in a track.

FIG. 23 is a processing flow diagram when a head record of a track is accessed.

FIG. 24 is a processing flowchart executed when the sequential check flag of the track to be accessed by the received input / output request is on.

FIG. 25 is a processing flowchart executed when the sequential check flag of the track is ON when the processing for the input / output request is completed.

FIG. 26 is a processing flowchart executed when an input / output request is received and a sequential recognition flag of the track is turned on.

FIG. 27 is a processing flowchart executed after a loading other than the multiple track loading is executed at the time of a track miss.

FIG. 28 is a processing flowchart executed when an input / output request is received for the track when the access unit checking flag is on.

FIG. 29 is a processing flowchart executed when the track is evicted from the cache memory and the access unit checking flag is on.

FIG. 30 is a processing flowchart of a loading selection unit.

FIG. 31 is a configuration diagram of access characteristic information when recognition of sequential access is performed independently for read and for write.

FIG. 32 is a configuration diagram of access characteristic information when a pattern without loading is prepared.

FIG. 33 is a configuration diagram of access characteristic information when sequential access recognition is performed independently for reading and writing, and a pattern without loading is prepared.

FIG. 34 is a configuration diagram of access characteristic information when an approximate value of a hit ratio is grasped.

FIG. 35 is a processing flowchart when an approximate value of the hit ratio is grasped.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiaki Tsuboi 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Hitachi SRL Systems Co., Ltd. (72) Inventor Shigeo Honma Odawara, Kanagawa Prefecture 2880 Kozu, Kochi, Hitachi, Ltd.Odawara Plant, Hitachi, Ltd. (72) Inventor Katsunori Nakamura 2880 Kozu, Kozuhara, Kanagawa, Japan Inside Odawara Plant of Hitachi, Ltd. Hitachi, Ltd. Odawara Plant (72) Inventor Hiroyuki Kitajima 1099, Ozenji, Aso-ku, Kawasaki, Kanagawa Prefecture, Ltd.Hitachi, Ltd.System Development Laboratory Co., Ltd. (72) Inventor Akira Kurano 2880, Kofu, Hitachi, Ltd. (72) Inventor Masafumi Nozawa Odawara City, Kanagawa Prefecture Hutu 2880 address stock company Hitachi Odawara plant in the F-term (reference) 5B005 JJ13 MM11 NN12 NN22 5B065 CE14

Claims (9)

[Claims] 1. A data loading method in a control device connected to a processing device and a storage device and having a cache memory, wherein a first record is stored in a storage area of the storage device based on a request from the processing device. When being read, the first record is transferred to the cache memory, and the first record is stored in the storage area based on a request from the processing device while the first record is present in the cache memory. When the second record is read,
A data loading method, wherein records other than the first record and the second record stored in the storage area are transferred to the cache memory together with the second record. 2. The record stored in the storage area is assigned a number, and the number assigned to the first record is smaller than the number assigned to the second record. 2. The data loading method according to claim 1, wherein: 3. The record transferred to the cache memory together with the second record is a record assigned a number larger than the number assigned to the first record. 2. The data loading method according to 2. 4. A record transferred to the cache memory together with the second record, except for the second record, a record assigned a number next to the number assigned to the first record. 3. The data loading method according to claim 2, wherein data from the storage area to the record with the largest number in the storage area are included. 5. The record stored in the storage area is assigned a number, and the number assigned to the first record is larger than the number assigned to the second record. 2. The data loading method according to claim 1, wherein: 6. The record transferred to the cache memory together with the second record is a record assigned a number smaller than the number assigned to the first record. 5. The data loading method according to 5. 7. A record transferred to the cache memory together with the second record, except for the second record, from a record having the smallest number in the storage area to the first record. 6. The data loading method according to claim 5, further including a record up to a record assigned a number immediately before the number assigned to the data. 8. The data loading method according to claim 1, wherein the storage area is one track. 9. A data loading method in a control device connected to a processing device and a storage device and having a cache memory, wherein data to be accessed from the processing device is not stored in the cache memory. Loading the target data from the storage device, outputting the loaded target data to the processing device, storing the loaded target data in the cache memory,
Loading the data excluding the target data to be stored in the management unit of the cache memory storing the target data from the storage device, and storing the loaded data excluding the target data in the cache memory. A data loading method, comprising: