JP2002176146A - I/o circuit in semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent breakdown of an output buffer transistor in a case where surge is applied to power source potential. SOLUTION: In an I/O circuit in a semiconductor integrated circuit device using a floating N-well type, an output buffer 18 constituted of a P-channel transistor turning to a pull-up transistor, and N-channel transistors 14, 15 turning to pull-down transistors are connected in series. The connection points of them are connected with an output terminal 30. A surge protecting circuit 40 constituted of a P-channel transistor is arranged between the output buffer 18 and the output terminal 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit in a semiconductor integrated circuit device, and more particularly, to an input / output circuit which interfaces with a voltage level higher than its own power supply voltage.

[0002]

[Prior art]

For example, there is an input / output circuit that enables connection of a 5 V chip while taking advantage of the high speed and low power consumption of a 3 V process. For example, one using a floating N-well circuit disclosed in Japanese Patent Publication No. Hei 7-118644 is known.

A conventional floating N-well type input / output circuit will be described with reference to FIG.

[0005] This circuit is connected to a suitable known output control circuit 10. Output control circuit 1
0 is composed of a NAND circuit, a NOR circuit, etc., and outputs two signals.

In the input / output circuit shown in FIG. 1, an output from the input / output controller circuit 10 is provided to a first input terminal IN and a second input terminal IN '. The first input terminal IN is connected to a P-channel output buffer transistor 18 acting as a pull-up transistor. One end of the buffer transistor 18 is connected to VCC1. This first
A P-channel transistor 24 and an N-channel transistor 16 are inserted between the input terminal IN and the transistor 18 in parallel. The gate of this transistor 24 has V
CC1 is provided.

A second input terminal IN 'is an N-channel MOS transistor 1 acting as a pull-down transistor.
4 is connected. One of the transistors 14 is grounded, and the other is connected in series with a transistor 18 via an N-channel transistor 15. The common point between the transistors 18 and 15 arranged in series forms a data output terminal 30. The gate of the transistor 15 is supplied with VCC1. P-channel MOS transistor 26 acting as N-well bias transistor
Is connected between VCC1 and the N well, and its gate electrode is connected to the data output terminal 30. The transmission gate is connected between the first input terminal IN and the transistor 18. This transmission gate includes a P-channel MOS transistor 12. The transmission gate further includes a P-channel MOS transistor 16 connected in parallel to N-channel MOS transistor 24, and its gate electrode is connected to data output terminal 30.

The output terminal 30 is connected to the internal input circuit 28. Further, the output terminal 30 is provided with an input protection diode D11.

In the above-mentioned PMOS, the transistor 1
8, the transistor 26, the transistor 16, and the transistor 12 are formed in the same floating N well. The potential of this well changes according to an external system signal to prevent a leak current.

The well in the floating state is charged to around 5 V through a parasitic diode. When the potential of the external bus becomes "0" level, the potential again becomes 3.3 V through the transistor 26. External bus potential is “0”
At this time, the transistor 12 is off. When the external net potential becomes 5 V, the transistor 12 conducts,
The gate electrode of the transistor 18 is charged to 5V. Then, the normally-on transistor 24 is turned off, and current can be prevented from flowing back to the output control circuit 10 side. The gate voltage of the transistor 18 that the output control circuit 10 can drive only through the transistor 24 is equal to the difference between 3.3V and the threshold voltage of the transistor 24. Then the external net is made by another device. "
When the level becomes 0 ", a leak current flows through the transistor 18. Therefore, the transistor 24 and the transistor 16 are inserted in parallel. As a result, the output control circuit 10 sets the gate of the transistor 18 to 3
V, and the transistor 18 is completely turned off.

As described above, in the input / output circuit shown in FIG. 1, its own power supply voltage (VC) is applied to the output terminal 30 (pad).
C1) The circuit configuration is such that no current flows into its own power supply even when a higher voltage is applied. Although the circuit configuration shown in FIG. 1 is a configuration of one power supply of only VCC1, FIG.
Of the same potential as the high voltage applied to the pad 30 as shown in FIG.
There is also a general configuration that uses the CC2 to eliminate the flow of current.

In FIG. 2, electrostatic breakdown (ES
There is current flowing from the external system to the power supply through the input protection diode for D). In order to eliminate this leakage current, the ES with the junction diode connected to VCC2
A D device is provided.

[0013]

In the conventional input / output circuit described above, when a surge is applied to the power supply voltage VCC1, the P-channel output buffer transistor 1
When the transistor size of P8 (P11 in FIG. 1, P12 in FIG. 2) is sufficiently large, the transistor 18 functions as a protection element. However, the transistor size of the P-channel side output buffer transistor 18 is determined by the output current of the input / output buffer, and may not be sufficiently large. In this case, the surge may damage the P-channel output buffer transistor 18.

The present invention has been made in consideration of the above-described problems, and has as its object to prevent the output side buffer transistor from being destroyed even when a surge is applied to VCC1.

[0015]

SUMMARY OF THE INVENTION The present invention relates to an input / output circuit in a semiconductor integrated circuit device using a floating N-well system, and an output buffer comprising a P-channel transistor serving as a pull-up transistor and an N-channel serving as a pull-down transistor. Transistors are connected in series, this connection point is connected to an output terminal, and a surge protection circuit composed of a P-channel transistor is provided between the output buffer and the output terminal.

Further, the present invention is characterized in that the output buffer and the surge protection circuit are constituted by a plurality of P-channel transistors, and the output current is changed by the metal wiring with the wiring to the transistor gate being the metal wiring.

Further, the present invention is characterized in that a ground surge protection circuit comprising a plurality of N-channel transistors is provided at the output terminal.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those in the conventional example are denoted by the same reference numerals.

FIG. 3 is a block circuit diagram showing a first embodiment of the present invention, and has basically the same configuration as the circuit shown in FIG.

As shown in FIG. 3, this embodiment employs V
As a countermeasure against CC surge, a VCC1 protection circuit 40 is provided between the P-channel output buffer transistor 18 and the output pad 30. The protection circuit 40 includes three P-channel transistors P31, P41 and P51. These transistors P31, P41, P
51 also has the same floating n as the transistors 18, 26, 16 and 12.
Formed in the well. The gate of the transistor P41 is connected to the output terminal 30, one end is connected to VCC1, and the other end is connected to the gate of the transistor P31. or,
The gate of the transistor P51 is connected to VCC1, one end is connected to the output terminal 30, and the other end is connected to the gate of the transistor P31. One end of the transistor P31 is VCC
1, the other end is connected to the output terminal 30.

With this configuration, the size of the transistor that can sufficiently protect against a surge can be reduced.
8 (P21) and the transistor P31.

The transistor P3 of the added protection circuit 40
Since the transistors P41 and P51 other than 1 do not affect the characteristics of the input / output buffer, the transistor size may be small and has little effect on the circuit scale (area).

In this case, the transistors P21, P21
If 31 is composed of a plurality of transistors, it is possible to change the connection to the gate only by changing the metal wiring, and the output current can be changed only by changing the metal wiring.

FIG. 4 is a block circuit diagram showing a second embodiment of the present invention, and has basically the same configuration as the circuit shown in FIG.

As shown in FIG. 4, this embodiment employs V
As a countermeasure against CC surge, VC between the output buffer transistor 18 (P22) and the output pad 30 on the P channel side
The C1 protection circuit 40 is provided. This protection circuit 4
0 indicates three P-channel transistors P32, P42,
P52. These transistors P32,
P42 and P52 are also transistors 18 and 2
6, are formed in the same floating n-well as the transistors 16 and 12. The gate of the transistor P42 is connected to the output terminal 30, and one end is connected to V
The other end of the transistor CC1 is connected to the gate of the transistor P32. The gate of the transistor P52 is connected to VCC1, one end is the output terminal 30, and the other end is the transistor P5.
32 gates. One end of the transistor P32 is connected to VCC1, and the other end is connected to the output terminal 30.

With this configuration, the size of the transistor which can sufficiently protect against a surge can be reduced.
8 (P22) and the transistor P32.

The transistor P3 of the added protection circuit 40
Since the transistors P42 and P52 other than 2 do not affect the characteristics of the input / output buffer, the transistor size may be small, and has little effect on the circuit scale (area).

In this case, the transistors P22, P22
If 32 is composed of a plurality of transistors, it is possible to change the connection to the gate only by changing the metal wiring, and the output current can be changed only by changing the metal wiring.

Further, regarding the surge with respect to the ground (GND), instead of the diodes (D21, D22) of FIGS. 3 and 4, instead of the diode (D21, D22) of FIG.
It can be composed of a plurality of N-channel transistors (N3a ...). As described above, if the transistors N1a and N1b (N2a and N2b) in FIG. 3 (FIG. 4) and the transistors N3a and N3b in FIG. It can be easily used for gate arrays and the like.

[0030]

As described above, according to the present invention, a transistor size sufficient for protection against surge may be constituted by the sum of the output buffer transistor and the transistor of the protection circuit, and damage due to surge can be prevented.

If the surge protection circuit is composed of a plurality of transistors, the output current can be changed only by connecting the wiring to the gate, and can be easily used in a gate array or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional floating n-well type input / output circuit.

FIG. 2 is a block diagram showing a conventional floating n-well type input / output circuit.

FIG. 3 is a block circuit diagram showing a first embodiment of the present invention.

FIG. 4 is a block circuit diagram showing a first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a protection circuit against a GND surge.

[Explanation of symbols]

 Reference Signs List 10 output control circuit 18 P-channel output buffer transistor 14, 15 N-channel transistor 30 output pad 40 protection circuit

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H03K 17/687 H03K 19/00 101F 19/0175 F term (reference) 5F038 BH07 BH15 CA04 CD08 DF06 EZ20 5F048 AB02 AB03 AB05 AB06 AB07 AC03 AC10 BF00 BF15 CC06 CC09 CC16 CC19 5J055 AX47 AX64 BX16 CX24 DX17 DX22 EX07 EY12 EY21 EZ62 FX05 FX33 GX01 GX02 5J056 AA01 AA04 BB47 BB49 BB59 DD28 DD55 EE14 EE15 FF08 GG09

Claims (3)

[Claims] In an input / output circuit in a semiconductor integrated circuit device using a floating N-well method, an output buffer comprising a P-channel transistor serving as a pull-up transistor and an N-channel transistor serving as a pull-down transistor are connected in series. An input / output circuit in a semiconductor integrated circuit device, wherein a connection point is connected to an output terminal, and a surge protection circuit including a P-channel transistor is provided between the output buffer and the output terminal. 2. The output buffer according to claim 1, wherein the output buffer and the surge protection circuit are composed of a plurality of P-channel transistors, and the wiring to the transistor gate is changed to a metal wiring, and the output current is changed by a metal wiring. An input / output circuit in a semiconductor integrated circuit device. 3. The input / output circuit in a semiconductor integrated circuit device according to claim 1, wherein a ground surge protection circuit including a plurality of N-channel transistors is provided at said output terminal portion.