JP2002171525A - Simd type arithmetic unit provided with bit plane arithmetic instruction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SIMD(Single Instruction Multiple Data) arithmetic unit that realizes plane data by each bit position of each of data from a data stream utilized for image compression coding by one instruction so as to considerably reduce the calculation time. SOLUTION: A bit plane instruction discrimination section 106 of an instruction decoder section 102 discriminates whether or not an instruction is a bit plane processing arithmetic instruction with respect to an image. As a result, a bit plane arithmetic section 107 receives n-sets of m-bit data in source data 1 stored in a source register, respectively integrates bit information at the same bit location of the n-sets of data and generates m-sets of n-bit element data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit used for encoding various information, in particular, entropy encoding of an encoding algorithm for encoding image information such as a still image and a moving image. is there.

[0002]

2. Description of the Related Art In encoding image information and the like, there is a case where the image information is not treated as it is, but is encoded after a bit plane is generated. In the following example, an image processing method in which an image is decomposed into bit planes, and a quadtree is further created and compressed will be described.

FIG. 4 shows a method of expressing a color image or a gray scale image. When these images are encoded and compressed, a frequency analysis result such as a wavelet transform may be used. In such a case, in the image data subjected to the wavelet transform, there is a high probability that the upper bit of each pixel data of the image is “0”. Therefore, instead of treating each pixel data for each pixel when encoding a frequency-analyzed image,
As shown in FIG. 5, a bit plane may be generated and encoded. Since the same data at the bit position of each pixel data is collected in each bit plane, most of the upper bit planes are 0, and a lot of information is collected in the lower bit planes. FIG. 6 shows an example of such image compression. In this example, the upper three bit planes out of the eight bit planes do not contain any data. Therefore, the flag information indicating whether or not there is information in the bit plane is represented by binary “0001”.
By setting it to 1111 "(8-bit flag information indicating that the upper three planes are zero), encoding is possible by continuing the information of the remaining lower five bit planes. Converting data to a bit-plane representation may be useful for encoding images.

In the following, a SIMD (Single Instruction Multiple Data) for calculating a plurality of pieces of information collectively and in parallel is described.
The information processing apparatus of type a) will be described.

In a SIMD type information processing apparatus, a single operation instruction performs an operation on n m-bit information elements in a register (m is a natural number, and n is a natural number of 2 or more). The operations include arithmetic operations such as addition, subtraction, and multiplication, bit logical operations such as logical sum and logical product, and shift operations and comparison operations. This SIMD
The instruction of the type information processing apparatus includes a field for specifying the type of operation, a field for specifying two or one source register, and a field for specifying one destination register. However, one source register may also serve as the destination register. The instruction also has a field for designating a method of dividing elements in the register. The register is divided into n m-bit elements in some cases, and 2n m / m in other cases. It is divided into two-bit elements. Normally, register division is often divided into elements having data lengths of 8, 16 and 32 bits, and the total register length is often 64 bits or 128 bits, but is not limited thereto.

In such a SIMD type information processing apparatus,
The operation is performed between the corresponding elements between the two designated registers as shown in FIG. In this figure, the case where n = 4 is shown, but in other cases, the operation is similarly performed between all the elements. Also, depending on the designation in the instruction (a specific field is reserved), rather than between corresponding elements between two registers, as shown in FIG. (Lower element)
And an operation with each element of the other register. In this figure, the case where n = 4 is shown, but in other cases, the operation is similarly performed on all elements of one register. Further, instead of performing an operation between two registers, an operation may be performed on a value embedded in a bit pattern of an instruction and each element of a source register as shown in FIG.

[0007] In the information processing apparatus, the above-described operation instructions are all realized by hardware to realize the operation function (hard-wired logic system), or the apparatus has a program for performing the operation inside the apparatus. There is a case where an arithmetic function is realized according to a program (microprogram method). However, this is a difference in the internal structure, and does not have any effect on the program operating on the information processing device.

[0008]

At the time of encoding image information as described above, particularly when a bit plane of image information is generated on a SIMD type information processing apparatus, conventionally, a bit operation instruction, a bit shift instruction, The operation is performed by performing a logical sum of bits, and when a bit plane is generated, a large number of instructions are required only with general-purpose instructions, which causes a problem that the calculation time becomes long.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been developed in view of the problems described above. An SI that enables bit plane conversion to be processed more simply and in a shorter time.
An MD type arithmetic unit is to be provided.

[0010] In order to solve this problem, the SI of the present invention is used.
The MD type arithmetic unit has the following configuration. That is, a SIMD-type arithmetic device that calculates and outputs a plurality of data with one command, a determining unit that determines whether the calculation instruction is related to bit-plane conversion of an image, If it is determined that the instruction is a bit-plane operation instruction, m-bit data of n bits relating to the image stored in the source register is input, and the bit information at the same bit position of each of the n data is collected. , N-bit element data, and output means for outputting the arithmetic means.

[0011]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

<First Embodiment> FIG. 1 is a block diagram showing a SIMD type information processing apparatus. In particular, the characteristic features are a bit plane instruction discrimination unit, a bit plane operation unit, and an operation data selection unit.

In the SIMD type information processing apparatus, 101
Of the instruction supply unit realizes a function of reading the instruction from the storage device. The instruction read unit extracts the type of operation, the source register number, and the destination register number from the bit string of the instruction by the instruction decoder unit 102, and registers the instruction in the register file 103. To read the source data. The operation unit 104 performs an operation on the source data based on the control signal indicating the type of operation passed from the instruction decoder unit. According to the type of operation, the operation is divided into an operation requiring two source data and an operation using only one source data. This calculation result is passed to the memory access unit 105 and the register writing unit. If it is a memory access command, the memory access is performed here. Otherwise, the memory access unit does nothing and the operation result and the memory access result are written in the destination register in the register writing unit. The above is the flow of the calculation in the information processing device.

In this embodiment, a bit plane instruction determining unit 106 is provided in the instruction decoder unit, and it is determined whether the read instruction is a specially prepared bit plane instruction. If the instruction is a bit plane instruction, a signal indicating that the instruction is a bit plane instruction is output in the control signal passed to the operation unit. The operation unit 104 is provided with a bit plane operation unit 107 that generates a bit plane from source data. Further, the operation data selection unit 1
08 is provided with a circuit for selecting the operation result by the bit plane operation unit as operation data when a signal indicating a bit plane instruction is output from the instruction decoder unit. By adding the modules as described above, an information processing apparatus for generating a bit plane according to the present invention is realized.

In the following, in the embodiment, in order to unify the description, the order of the data stored in the register is such that the lower order data of the storage address is stored at the top of the register, and the generation of the bit plane is performed in the upper order of the register. It will be described as starting from the element of. However, when the bit plane of each element in the register is generated, by making the lower element of the register the upper bit of the result of the bit plane, it can be used as a bit plane result similar to the above. This does not limit the present invention.

FIG. 10 shows an operation example when a bit plane instruction is received in the embodiment. Here, the source and destination registers are 6
It is 4 bits (= 8 bits × 8).

In the figure, it is easy to understand that the value (8 bits) obtained at the time of the wavelet transform is considered to be used at the time of bit plane. In other words, what is stored in the source register is eight consecutive frequency components in a certain row (or column) after the wavelet transform.
Each value is “0C”, “1A”,.
When “CE” (all in hexadecimal notation), the value of the MSB (bit 7) of each frequency component value is extracted. As a result, "00000001" in binary, that is, "01" in hexadecimal, is obtained, and is stored in the upper 8 bits of the destination register as a first result. Hereinafter, the destination register as shown is obtained by extracting the bit 6, bit 5,..., The least significant bit 0 of the eight data of the source register.

FIG. 3 is a block diagram of a bit plane operation unit 107 in the embodiment for realizing the above processing. This is an example in which the bit plane operation unit inside the information processing device is implemented by hard wired logic.

The data of each element is obtained by the extraction section of each element of the source register 201. From this element, all the lower bits are extracted from the upper bit by the bit extracting unit 202. The data is stored in a bit rearrangement unit 203
To generate a bit plane. Specifically, the most significant bit (bit 7) of the first element is substituted for the most significant bit of the first element of the output data, and the second bit is substituted for the most significant bit of the second element of the output data. , And other bits are similarly assigned to the most significant bit of each element of the output data and rearranged. The bit of the second element is assigned to the second bit of each element of the output data. Other elements are similarly sorted. Then, the output data is passed to the operation data generation unit 204, and operation data is generated. This operation result is passed to the destination register 204.

The output of each bit rearranging unit is provided with eight OR gates each having an 8-bit input and a 1-bit output, and the result is output to, for example, the lower 8 bits of the second destination. , An information flag as shown in FIG. 6 can be generated.

As described above, according to the present embodiment, when eight pieces of 8-bit data are input, the same bit position of each piece of data, that is, bit plane data can be generated. Moreover, since the processing can be performed in parallel as described above, the required clock can be extremely reduced and the processing can be speeded up.

Here, an example has been described in which eight pieces of 8-bit data are input and converted into eight pieces of bit plane data. However, n elements of m-bit information are input, and
The present invention is not limited to the above example because the present invention can be applied to a case where m bit planes of n-bit elements are generated.

<Second Embodiment> FIG. 3 is a flow chart of a bit plane operation method according to a second embodiment, and is a flow chart of a micro program in a case where the bit plane section inside the information processing apparatus is implemented by a micro program. Is shown.

The instruction read from the storage device is determined in step 301 of bit plane instruction determination as to whether it is a bit plane instruction. If the instruction is not a bit plane instruction, it is another instruction, and the process proceeds to the execution step 302 of the other instruction. If the instruction is a bit plane instruction, each element is extracted from the source register in step (step 303). After initializing the loop variable i to 1, in step 304, the i-th high-order bit of each element is taken out and assigned to the first bit of the output data to generate n-bit output data. After incrementing the variable i, it is determined in step 305 whether i has become greater than m and all the bits have been extracted, and if not, the process returns to step 304. If all the bits have already been extracted, the step destination register Is substituted for the output data (step 306). By incorporating the microprogram as described above, a bit plane instruction can be implemented in the information processing device.

As described above, an internal register can hold n (m is a natural number) information elements of m bits (n is a natural number of 2 or more). And a means for determining a bit plane instruction, and extracting and arranging a bit sequence of each element of one source register in order from a higher-order bit to an n-bit element. Means for generating m number of bit planes, and means for storing the above result in the destination register if it is a bit plane instruction, so that many instructions are required when only conventional general-purpose instructions are used. The time-consuming bit plane generation can now be performed with one bit plane instruction of the present embodiment, and the effect that the calculation time can be shortened is obtained. is there.

[0026]

As described above, according to the present invention, it is possible to generate plane data for each bit position of each data from a data sequence used in image compression encoding by one instruction. Thus, the calculation time can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a SIMD type information processing apparatus according to an embodiment.

FIG. 2 is a block diagram illustrating details of a bit plane calculation unit in the embodiment.

FIG. 3 is a flowchart in a case where a bit plane operation in the second embodiment is realized by a microprogram;

FIG. 4 is a diagram illustrating an example of a method of expressing an image.

FIG. 5 is a diagram illustrating an example of a bit plane representation of image data.

FIG. 6 is a diagram illustrating an example in which information for each bit plane is represented by one bit.

FIG. 7 is a conceptual diagram illustrating an operation between elements of two registers in the SIMD type information processing apparatus.

FIG. 8 is a conceptual diagram showing operations of all elements of a register and the lowest element of another register in the SIMD type information processing apparatus.

FIG. 9 is a conceptual diagram showing the operation of all elements of a register and an immediate value embedded in an instruction in a SIMD type information processing apparatus.

FIG. 10 is a diagram illustrating an example of a bit plane operation in the embodiment.

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (reference) H04N 1/41 G06F 7/00 A F term (reference) 5B022 AA02 BA10 DA06 FA12 5B045 AA01 GG14 5B057 CG01 CH01 CH08 5C059 KK11 KK15 LA01 ME01 RC24 SS12 UA02 UA36 UA38 5C078 AA04 BA53 CA31 DA00 DB19 EA00

Claims (7)

[Claims] 1. A SIMD-type operation device for calculating and outputting a plurality of data with one instruction, and determining means for determining whether the operation instruction relates to bit-plane conversion of an image, and determining the determination. When it is determined by the means that the instruction is a bit-plane conversion operation instruction relating to an image, n pieces of m-bit data relating to the image stored in the source register are input, and bit information at the same bit position of each of the n pieces of data is input. SIMD-type operation device, comprising: an operation unit that generates m pieces of n-bit element data; and an output unit that outputs the operation unit. 2. The SIMD type arithmetic device according to claim 1, wherein said output means outputs to a destination register. 3. The arithmetic means includes a bit i (i = 0,..., N) of each of n data stored in a source register.
The SIMD type arithmetic device according to claim 1, wherein the SIMD type arithmetic device is configured by wired logic configured to receive the information of m-1). 4. The SI according to claim 1, wherein said arithmetic means is constituted by a microprogram.
MD type arithmetic unit. 5. The data processing apparatus according to claim 1, wherein data of a lower address of a memory storing data to be processed is stored in an upper part of said source register. The SIMD-type operation device according to the paragraph. 6. The SIMD-type operation device according to claim 1, wherein said operation means generates from an upper bit plane and outputs the data as upper data. 7. The SIMD type arithmetic device according to claim 1, wherein said arithmetic means generates from a lower bit plane and outputs it as lower data.