JP2002169786A - Transaction issuing control method for parallel computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a deadlock due to the issuing order of BCTx and the deadlock occurred in the congestion of BCTx receive buffers in a parallel computer system where a broadcast transaction (BCTx) and a unicast transaction (UCTx) are defined and to increase chances of issuing the BCTx. SOLUTION: Respective function units 1, 2 and 3 are provided with a control means issuing the UCTx generated later even if the BCTx cannot be issued, a control means confirming that the BCTx receive buffers of all the function units in a distribution destination have capacity for receiving all BCTx and issuing them and the control means 16, 26 and 36 issuing the BCTx for only one time when the self-function unit does not issue a BCTx request if an ABRDY signal is moved from on to off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a broadcast transaction and a unicast transaction in a parallel computer system equipped with a plurality of functional units (processor, memory, IO bus unit, etc.) and connected through a crossbar switch. Issue control method.

[0002]

2. Description of the Related Art In general, in a parallel computer system having a crossbar switch configuration connecting a plurality of functional units and connecting them, a unicast transaction (UCTx) and a broadcast request transaction (BCTx) are defined for the exchange between the functional units. used. UC
Tx is a transaction with one destination, and BCTx is a transaction with multiple destinations.

In a functional unit that issues UCTx, normally, a functional unit serving as a destination prepares a data buffer in advance, so it is not necessary to confirm whether or not this buffer is empty when issuing UCTx. .
On the other hand, since BCTx occurs asynchronously and there is not always a free space in the BCTx reception buffers of all the functional units of the distribution destination, when distributing, it is necessary to confirm that the BCTx reception buffers of the functional units of the distribution destination are free. There is Also, it is assumed that the distributed BCTx is analyzed by a plurality of functional units, and that only one functional unit can output a result, and that the operation specification includes an operation specification in which a reply is returned using UCTx.

[0004] Under such a premise, in a parallel computer system in which UCTx and BCTx coexist, a deadlock may occur due to the issue order of BCTx.
In addition, deadlock may occur even when the contention of the BCTx reception buffer occurs.

[0005] It is assumed that BCTx occurs first in a certain functional unit and then UCTx occurs. When the transaction issuance process is performed in this temporal order, BC
There is a case where the Tx reception buffer is not empty no matter how long it waits.

The BCTx generated earlier in time is first
Input to the transaction issuing circuit of the functional unit,
It is assumed that a request is issued to the crossbar switch when inserted here.

[0009] Now, it is assumed that the BCTx receiving buffer of the functional unit of the distribution destination is confirmed to be empty before the BCTx is input and the request is issued, and that the state changes from empty to empty. This change is assumed that the BCTx reception buffer of the own device has no space since the BCTx from another functional unit is received and stored. Then, the BCTx that previously occupied the transaction issuing circuit cannot issue a request. Further, since UCTx, which will later empty the BCTx receiving buffer, cannot be input to the transaction circuit, the BCTx receiving buffer does not become empty and the BCTx cannot be distributed no matter how long. That is, it is hardened here.

[0008] Next, the BCTx is used for all the distribution destination BCs.
If there is no free space in the Tx reception buffer, it is not input to the transaction issuing circuit, and if there is free space, it is input.
Further, even if UCTx occurs after BCTx,
If Tx cannot be input and it is suspended, UC
It is assumed that Tx can be input first.

However, even if BCTx is input to the transaction issuing circuit when there is a vacancy, if the BCTx is vacant so that only one BCTx can be received, some BCTx requests cannot be accepted. This is because BCTx competition occurs in a plurality of functional units. Then, the unreceivable BCTx remains in the transaction issuing circuit of the functional unit, thereby preventing subsequent issuance of UCTx. If the BCTx request is such that its own BCTx reception buffer is left empty at that time, it will not be accepted no matter how long it waits, and it will solidify here as well.

[0010] A mechanism for notifying when one BCTx receiving buffer is always available. When the BCTx receiving buffer becomes available, a signal corresponding to the prior request of BCTx is collected in advance in, for example, a crossbar switch unit, and one is selected. If the permission signal is returned to the functional unit, the BCTx can be prevented from staying in the transaction issuing circuit. If the BCTx reception buffer of any functional unit is to be notified when there are two empty spaces, it is necessary to return a permission signal to the two functional units. In any case, a dedicated permission signal generation circuit is required on the crossbar switch side.

[0011]

SUMMARY OF THE INVENTION A first object of the present invention is to prevent deadlock due to the order of issuance of BCTx and UCTx. Specifically, the BC of the distribution destination
If there is no free space in the Tx reception buffer and the BCTx that occurred earlier in time cannot be sent,
The purpose is to allow CTx to overtake BCTx and issue a request. This is because BCTx occurs and then UC
In the case where Tx occurs, the transaction issuance processing may be performed in the order in which the transaction distribution conditions are satisfied, not in the order of occurrence in some cases.

A second object of the present invention is to prevent deadlock due to contention of a BCTx reception buffer. Specifically, the BCTx is input to the transaction issuing circuit when the BCTx receiving buffer of the distribution destination functional unit has a free space, and the BCTx requests of all the issued functional units are accepted. is there. This means that when the BCTx reception buffer becomes full, BCTx occupies resources (circuits) necessary for the UCTx issuance processing, and does not create a circuit for waiting for the BCTx reception buffer to become empty. If the capacity of the free area of the buffer is always prepared by the amount that can accept requests from all the functional units, a dedicated permission signal generation circuit is not required on the crossbar switch side.

A third object of the present invention is to effectively use a BCTx reception buffer. A signal notifying that there is room to store all BCTx,
In the method of determining whether or not to issue a request, there is a case where even if this signal indicates that the buffer is not full, there is actually a vacancy and a request can be issued. The purpose is to detect this condition and increase the chance of issuing BCTx. It is assumed that the buffer is vacated in units of n units. When the number becomes less than n, the state becomes empty, but it does not mean that n requests actually come. This vacancy notification signal is transmitted simultaneously with n
It only indicates whether or not you can make requests. Therefore, even if there is no space, BC
In some cases, Tx can be input.

[0014]

In order to address the first problem, in one embodiment of the present invention, each of the functional units selects one of the outputs of UCTx and BCTx which are separately stored, and executes a transaction. Input to the issuing circuit and BCT
Control means is provided for enabling UCTx generated after BCTx to be input even when x cannot be input to the transaction issuing circuit.

Further, in order to address the second problem, in one embodiment of the present invention, at least all the BCTx requests that issue BCTx requests to the BCTx reception buffers of all the distribution destination functional units are provided to each functional unit. A control means is provided for confirming that there is a free space in a buffer capable of receiving a request from the functional unit and for setting a condition for inputting BCTx.

Further, in order to cope with the third problem, in one embodiment of the present invention, when the condition for inputting the BCTx to the transaction issuing circuit shifts from a state in which it can be input to a state in which it cannot be input, the function unit automatically executes the operation. If the functional unit has not issued a BCTx request, BCTx
Is provided at least once.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a parallel computer system according to the present invention. FIG.
, 1, 2 and 3 are instruction processors and other functional units (processing nodes), and 4 is a crossbar switch connecting these functional units. Generally, a plurality of functional units are prepared, but three units are provided here for convenience of explanation. The exchange of information between the functional units 1, 2 and 3 is performed using a transaction via the crossbar switch 4. The transaction includes a broadcast transaction (BCTx) and a unicast transaction (UCTx). Here, it is assumed that BCTx is distributed to all three functional units 1, 2, and 3.
UCTx is sent to a specific functional unit.

Transactions take the form of packets,
As shown in FIG. 3, it comprises a header part and a body part. The header portion is, for example, 8 bytes, and indicates information such as the destination of the transaction, the distinction between BCTx and UCTx, read / write, other commands, and the length of the body portion. The body part is composed of an address and data. The address is, for example, 8 bytes and indicates a memory address or a register address. There are several types of data such as 8-byte length to 64-byte length, which are added in the case of read data or write data of a memory or a register.

Each of the functional units 1, 2, and 3 has UCTx
The transmission buffers 10, 20, 30 and the BCTx transmission buffers 11, 21, 31 are provided separately, and the UCTx
And BCTx, each is stored separately. U
The read registers 14, 24, 34 are connected to the CTx transmission buffers 10, 20, 30, and store the UCTx read from the UCTx transmission buffers 10, 20, 30, for example, in units of 8 bytes. This read register is called a U register. The BCTx transmission buffers 11, 21, 31 also have read registers 15, 2,
5, 35 are connected, which will be called the B register.

Each of the functional units 1, 2, and 3 has a transaction issuing circuit. This is the selector 100, 2
00, 300 and transmission register (D register) 17, 2
7, 37, and control circuits 16, 26, and 36. The control circuits 16, 26 and 36 determine whether UCTx or BCTx can be input to the transaction issuing circuit, and if they can be input, the UCTx of the U registers 14, 24 and 34 or the BCT of the B registers 15, 25 and 35
x is set in the D registers 17, 27 and 37. Further, the control circuits 16, 26, and 36 notify the crossbar switch 4 of the HRQ (header request), and request a route in the crossbar switch 4.

The crossbar switch 4 comprises three input ports and three output ports, corresponding to the three functional units 1, 2, and 3 here. Each input port has a reception register 51, 61, 71. This is a register (In register) that receives the header or body of UCTx or BCTx from each of the functional units 1, 2, and 3. Each input port has an input port control circuit 50,
There are 60 and 70. On the other hand, each output port has a selector 5
2, 62, and 72, and the data of the selected path is input to the transmission registers 53, 63, and 73 (Ot registers). The output of each Ot register 53, 63, 73 is returned to each functional unit 1, 2, 3.

Although not shown in FIG. 1, the output port of the crossbar switch 4 has a control unit, and receives a request from each of the input port control units 50, 60, 70 to select the selector 52, 6
Which route of 2, 72 is selected is determined by the priority.
In UCTx, one output port is selected from one input port. In BCTx, one input port In is selected.
Registers are provided for selectors 50 and 6 of all output ports.
2 and 72, all Ot registers 53 and 6
3 and 73, and distributed to each of the functional units 1, 2, and 3.

Each of the functional units 1, 2, and 3 has UCTx
The receiving buffers 12, 22, 32 and the BCTx receiving buffers 13, 23, 33 are provided separately. Each of the functional units 1, 2, and 3 receives the data distributed from the crossbar switch 4 and receives the data from the reception registers (R registers) 18, 2
Received at 8, 38, if UCTx, UCTx receive buffer 1
2, 22, and 32, and if it is BCTx, it is stored in the BCTx reception buffers 13, 23, and 33.

The D registers 17, 27, 37 of the functional units 1, 2, 3 and the In registers 51, 61, 71 of the input ports of the crossbar switch 4, the Ot registers 53, 63, Data is exchanged between the R 73 and the R registers 18, 28, 38 of the functional units 1, 2, 3 via an 8-byte data line.

Each of the functional units 1, 2, and 3 has a buffer empty state detecting circuit 19, 2 which constantly detects the empty state of the BCTx receiving buffers 13, 23, 33, respectively.
There are 9, 39. This buffer empty state detection circuit 19,
At 29 and 39, respectively, the BCTx reception buffer 13,
23, 33, B from all functional units 1, 2, 3
If there is a free buffer that can receive CTx, BRDY
A (buffer ready) signal is generated. This signal indicates that there is free space in the BCTx reception buffer of the functional unit,
This signal indicates that the BCTx from all the functional units is ready to be received. The operation of the buffer empty state detection circuit will be described later.

The BRDY signal of each of the functional units 1, 2, and 3 is sent to the crossbar switch 4, and the AND gate 8
0, and the output is sent as an ABRDY signal to the control circuits 16, 26, 36 of the respective functional units 1, 2, 3. Here, the AND operation of each BRDY signal is performed when the BCTx reception buffers 13, 23, and 33 of all the functional units 1, 2, and 3 are not all BRDY.
Cannot be executed. Each functional unit 1, 2, 3
The control circuits 16, 26, 36 determine whether or not to issue a BCTx request to the crossbar switch 4 based on the ABRDY signal.

Further, each of the functional units 1, 2, and 3 has a control flip-flop (QSAI) in the control circuits 16, 26, and 36, respectively. This QSAI is BR
It shows an on / off condition in which a BCTx request can be issued even when the DY signal (ABRDY signal) is off. This will be described later.

FIG. 2 shows the control circuits 16 and 26 in the transaction issuing circuit in each of the functional units 1, 2, and 3.
36 is an operation flowchart of FIG. Here, the control circuit 16 of the functional unit (0) 1 will be described as an example.

In the control circuit 16, the U register 14 is always
And the B register 15 to determine whether to input UCTx or BCTx to the transaction issuing circuit (steps 101 and 106). Here, U
It is assumed that UCTx exists in the register 14 and the transaction to be input is determined to be UCTx. In this case, the control circuit 16 sends the header request HRQ (0) to the crossbar switch 4 and sets the header portion read first in the U register 14 to the D register 17 via the selector 100, and The information is transmitted to the switch 4 (step 102). After that, the ACP from the crossbar switch 4 side
Wait for a signal (step 103). This is ACP
This is a waiting sequence. The waiting time is determined by, for example, the race condition of the path acquisition of the crossbar switch.

The crossbar switch 4 determines whether the transaction is UCTx by looking at the contents of the header. In response to the header request HRQ (0), the crossbar switch 4 sends an ACP signal to the functional unit (0) 1 when the path is ready.

When the ACP signal arrives, the body portion is sequentially read from the UCTx buffer 10 to the U register 14 under the control of the control circuit 16, and the selector 100 and the D register 17 are read.
(Step 1)
04). This is the transfer sequence. After repeating the transfer sequence for the number of words of UCTx, an end sequence is executed (step 105). In the end sequence,
A predetermined cycle is counted to determine the pitch at which the next HRQ will be issued.

When the UCTx end sequence is over, the control circuit 16 determines whether or not BCTx exists in the B register 16 (step 106). Then, steps 101 and 106 are looped until UCTx or BCTx is read out to the U register 15 or the B register 16.

Here, it is assumed that BCTx exists in the B register 16. In this case, the control circuit 16 first sets the ABR
It is determined whether the DY signal is on (step 107). ABR
When the DY signal is on, each of the functional units 1, 2, and 3 has a free space in the BCTx receiving buffers 13, 23, and 33, and is ready to receive BCTx from all the functional units. Therefore, the control circuit 16 sends the header request HRQ (0) to the crossbar switch 4, and at the same time, sets the BCTx (header portion) of the B register 14 in the D register 17 and transmits the same to the crossbar switch 4 (step 109). . Thereafter, an ACP waiting sequence (Step 110), a transfer sequence (Step 111), and an end sequence (Step 112) are executed. These are basically the same as in the case of UCTx. However, it is assumed that the functional units 1, 2, and 3 update the empty state of the BCTx receiving buffers 13, 23, and 33, respectively, while counting the predetermined cycles in the BCTx end sequence.

On the other hand, if the ABRDY signal is off at step 107, the control circuit 16 next proceeds to QSAI (0)
Is turned on (step 108). QSAI (0)
Is on, it means that a BCTx request can be issued even if ABRDY (BRDY signal) is off.
Therefore, the control circuit 16 continues to execute steps 109 to 112 as in the case where the ABRDY signal is on.
Execute When QSAI is off, BCT
The process returns to step 101 without executing x. In this case, the processing of the BCTx existing in the B register 16 is thereafter waited until the ABRDY signal is turned on. At this time, if UCTx exists in the U register 14, the UCTx is processed before BCTx.

FIG. 4 shows each BCTx receiving buffer 13, 2.
FIG. 3 is a diagram illustrating the operation of empty state detection circuits 19, 29, and 39 of Nos. 3 and 33. Here, the BCTx reception buffer 13 of the functional unit (0) 1 will be described as an example.

If the BRDY signal of the BCTx reception buffer 13 falls (turns off) in the end sequence,
The functional unit (0) 1 cannot continuously input BCTx to the transaction issuing circuit. In this case, BCTx
The minimum buffer empty area to be prepared in the reception buffer 13 may be three. If the empty state of the BCTx reception buffer 13 is updated after the end sequence, the next BCTx can be issued from the functional unit (0) 1 during that time. In this case, the BCTx reception buffer 1
The minimum number of empty areas prepared by 3 requires more than the number of functional units (here, three). In FIG. 4, the BCTx reception buffer 13 has the number of functional units of 3
It is larger and doubled to six. In FIG. 4, wp is a write pointer, and rp is a read pointer. The buffer empty state detection circuit 19 calculates the empty area by 6- (wp-rp), and the value is 6, 5,
If it is 4, 3, the BRDY (0) signal is turned on. If the value is 2, 1, 0, the BRDY (0) signal is turned off.

In the example of FIG. 4, the write pointer wp is 2
, Indicating that writing has been made to addresses 0 and 1. The read pointer rp points to 0, indicating that the contents of BCTx at address 0 are being read. Therefore, the free area becomes 6- (2-0) = 4, and the BRDY signal is turned on. That is, in this case, the BCTx reception buffer 13 can receive the BCTx of all the functional units (three).

FIG. 5 shows an on / off condition that a BCTx request can be issued by the flip-flop QSAI even when the BRDY signal is off. QSAI is
The function unit is provided for each functional unit, and is turned on if the ABRDY signal is not in the BCTx request issuing sequence (ACP waiting sequence, transfer sequence, or end sequence) in the cycle in which the ABRDY signal is dropped. Thus, even if the ABRDY signal is off, it is possible to issue the BCTx request only once. The QSAI is turned off in the cycle in which the ACP comes.

FIGS. 6 and 7 show a specific example of an operation time chart of the transaction issuance control according to the present invention. In both FIGS. 6 and 7, the sequence of the transaction issuing circuit is represented by a for ACP waiting, b for transferring, and c for termination.

FIG. 6 shows that even if BCTx occurs first, UCTx generated later overtakes it, and the UCTx transaction is issued first.

At time 0 at the beginning, functional unit (0) 1
Of the BCTx reception buffer 13 is 2
It is assumed that the BRDY (0) signal is off. Therefore, the ABRDY signal is also off. Also, QSAI
It is assumed that (0) is also off.

Assume that in the functional unit (0) 1, BCTx is output to the B register 15 at time 1 and UCTx is determined in the U register 14 at time A. It is assumed that the functional unit (0) 1 has received BCTx which requires a UCTx response, and that the UCTx has been output as a response. Generally, when a UCTx response is required, the BCTx data is left in the BCTx reception buffer until the UCTx comes out, and when the UCTx is sent to the response destination, the BCTx data in the BCTx reception buffer is deleted.

In FIG. 6, at time 1, no transaction issuance circuit of the functional unit (0) 1 is used, but BCTx is not input to the transaction issuance circuit. That is, in step 106 of the flowchart of FIG. 2, it is determined that BCTx is present, and the process goes to step 107. However, since the ABRDY signal is off, the process goes to step 108. Here, since the QSAI (0) signal is also off, the process returns to step 101. Since UCTx has not come yet at this point, the process jumps to step 106 again. Hereinafter, this is repeated, and even if BCTx occurs, ABRD
If the Y signal is off, BCTx is not issued.

On the other hand, the UCTx generated later is determined in step 101 in FIG. 2 as having the UCTx, and is input to the transaction issuing circuit at time F. As a result, a header request HRQ (0) is issued to the crossbar switch in step 102, and the AC
It enters P (0) wait. When the priority of the route is taken by the crossbar switch 4 and the transfer becomes possible, an ACP (0) signal comes. At step 104, the body data D00 is sent. Assuming that the destination of the UCTx is the functional unit (1) 2, the data D00 is determined at the time (second time) 5 in the input of the R register 28 of the functional unit (1) 2.

When the UCTx of the functional unit (0) is issued, the corresponding BC in the BCTx reception buffer 13 is output.
Since the Tx data is deleted, the BCTx reception buffer 1
Time B (2nd time) because one empty area of 3 increases
Thus, the free space is reduced from 2 to 3. Therefore, here B
The RDY (0) signal turns on. Also, the ABRDY signal is turned on from off. Thereafter, BCTx can be issued.

FIG. 7 shows that the functional unit (0) 1 and the functional unit (1) 2 issue a BCTx request at time 1 and the functional unit (2) 3 issues a BCTx request at time 1 (second time). Even if the BCTx reception buffer is not ready, the functional unit (2) 3
This shows how Tx can be output.

At time 0 at the beginning, functional unit (0) 1
The BCTx reception buffer 13 has three vacancies. In addition, B of functional unit (1) 2 and functional unit (2) 3
There are six CTx reception buffers available. Therefore,
BRDY (0), BRDY (1) and BRDY (2) are all on, and ABRDY is also on. In addition, QSA
I (0), QSAI (1), and QSAI (2) are all turned off (reset).

Now, it is assumed that the BCTx request of the functional unit (0) 1 is accepted by the crossbar switch 4, the ACP (0) arrives at time 7 and enters the transfer sequence, and then enters the end sequence at time E. The free space in the BCTx receiving buffer 13 of the functional unit (0) 1 is reduced from three to two. At this point, the functional unit (0) 1 turns off the BRDY (0) signal, that is, the buffer ready.
The functional unit (1) 2 and the functional unit (2) 3 have five empty spaces. The BRDY (1) and BRDY (2) signals remain on. The ABRDY signal is BRDY
(0) Since the signal has been turned off, it changes from on to off at this point.

The HRQ (1) of the functional unit (1) 2 is
It is issued at the same time as the functional unit (0) 1 (time 1), but the ACP (1) comes at the time C after the transfer sequence of the functional unit (0) 1 ends. . The order of ACP (0) and ACP (1) depends on the priority of the crossbar switch 4. HRQ
This is why the time length of the ACP waiting sequence a differs between (0) and HRQ (1).

When the ACP comes, the BCTx is distributed to all the functional units at the distribution destination. Here, the body data D0 of BCTx of the functional unit (0) 1 is distributed to three functional units. Input of R register 18 of functional unit (0) 1, R register 2 of functional unit (1)
Looking at the input of 8 and the input of the R register 38 of the functional unit (2) 3, the same body data D0 is distributed. The same applies to the body data D1 of the functional unit (1) 2.

When the BCTx end sequence of the functional unit (1) 2 runs, the BCTx reception buffer 13 of the functional unit (0) 1 has one free space and the BCTx reception of the functional unit (1) 2 and the functional unit (2) 3 Buffers 23, 33
There are four vacancies.

When the functional unit (0) 1 turns off BRDY (0), the ABRDY signal turns off (time E), but the BCTx issuance sequence is not executed in the first cycle in which the ABRDY signal turns off. Is only the functional unit (2) 3, and its QSAI (2) is turned on. Therefore, the BCTx of the functional unit (2) 3
Occurs at time 1 (second time) after ABRDY is turned off, but the answer to step 108 in FIG. 2 is YES, and the functional unit (2) 3 inputs the BCTx to the transaction issuing circuit, and outputs the HRQ ( 2) can be issued.
For HRQ (2), ACP from crossbar switch 4
When (2) comes, QSAI (2) returns to off. When the BCTx end sequence of the functional unit (2) 3 runs, the BCTx receiving buffer 13 of the functional unit (0) has no space, and the BCTx receiving buffers 23 and 33 of the functional unit (1) 2 and the functional unit (2) 3 have no space. Space is 4
Individual. It is assumed that the BCTx reception process has not progressed in any of the functional units 1, 2, and 3 during this time.

As described above, even when ABRDY is turned off from on and the state in which a BCTx request cannot be normally issued is issued, a functional unit that has not issued a BCTx request at that time issues BCTx only once. can do.

As in the embodiment, there are three functional units,
Assuming that each functional unit has six BCTx receive buffers, if only one of the functional units issues a request, the number of empty units can be used up to 6, 5, 4, and 3, so that a total of four BCTx receive buffers are used. Area can be used. If three functional units are simultaneously competing and issuing a request, each functional unit will have two of the BCTx receive buffers.
Number of areas can be used. One area can be used even if the conditions are poor.

[0055]

According to the present invention, it is possible to prevent a deadlock due to the issue order of the transaction issuance controls BCTx and UCTx in the parallel computer system of the present invention. In addition, deadlock due to contention of the BCTx receiving buffer for competing for a small free area can be prevented, and further, the opportunity for issuing the BCTx can be increased.

[Brief description of the drawings]

FIG. 1 is a hardware configuration diagram of a parallel computer system according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a flowchart of transaction issue control according to the present invention.

FIG. 3 is a diagram showing a format example of a transaction.

FIG. 4 is a diagram for explaining the operation of an empty state detection circuit of a BCTx reception buffer;

FIG. 5 shows an FF (Q
FIG. 3 is a diagram showing on / off conditions of SAI).

FIG. 6 is a diagram showing a specific example of a transaction issuance operation time chart according to the present invention.

FIG. 7 is a diagram showing another specific example of a transaction issuance operation time chart according to the present invention.

[Explanation of symbols]

1, 2, 3 Functional unit 4 Crossbar switch 10, 20, 30 UCTx transmission buffer 11, 21, 31 BCTx transmission buffer 12, 22, 32 UCTx reception buffer 13, 23, 33 BCTx reception buffer 14, 24, 34 Read register (U) 15, 25, 35 Read register (B) 16, 26, 36 Transaction issue control circuit 17, 27, 37 Transmit register (D) 18, 28, 38 Receive register (R) 19, 29, 39 BCTx receive buffer Empty state detection circuit 50, 60, 70 Input port control circuit 51, 61, 71 Receive register (In) 52, 62, 723 3-input 1-output selector 53, 63, 73 Transmit register (Ot) 80: AND gate

Claims (3)

[Claims] 1. A communication system comprising a plurality of functional units and a crossbar switch for connecting the functional units, wherein a broadcast transaction (hereinafter, BCTx) and a unicast transaction (hereinafter, UCTx) are defined for exchange between the functional units. A transaction issuance control method in a parallel computer system, in which requests are normally issued in the order of occurrence for BCTx and UCTx, and when a BCTx request cannot be issued,
A transaction issuance control method for a parallel computer system, wherein a UCTx request generated after the BCTx is issued first. 2. The transaction issuance control method for a parallel computer system according to claim 1, wherein the issuance of the BCTx request is such that all the functional units that issue the BCTx request can receive the BCTx requests of all the functional units that issue the BCTx request. A transaction issuance control method for a parallel computer system, characterized in that a buffer is available. 3. The transaction issuance control method for a parallel computer system according to claim 2, wherein when the state shifts from a state in which the BCTx request can be issued to a state in which the BCTx request cannot be issued, at least one time when the own function unit has not issued the BCTx request. A transaction issuance method for a parallel computer system, wherein a BCTx can be issued as long as possible.