JP2002156414A - Semiconductor device tester with timing calibration function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable calibration by a synchronizing signal generator even without a synchronizing signal generation function set in a semiconductor device tester, by setting the synchronizing signal generator in a timing measurement method in which a rise or a fall timing of a signal to be measured is measured synchronously with a synchronizing signal and it is judged whether a phase of the signal to be measured advances or delays to a reference timing. SOLUTION: The synchronizing signal generator for generating the synchronizing signal is constituted of a dummy cycle generator 10 for generating a dummy cycle so as to stabilize the operation of the semiconductor device tester before the calibration is started, a cycle period generator 20 for generating a cycle period of a comparison operation, and a comparison execution time generator 30 for generating the number of comparison execution times at an analog comparator. A calibration function is applied to any kinds of semiconductor device testers by adding the synchronizing signal generator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test apparatus for testing a semiconductor device such as a memory or a logic IC constituted by a semiconductor integrated circuit, and more particularly to a test of each channel for supplying a test pattern signal to a device under test. The present invention relates to a semiconductor device test apparatus provided with a timing calibration function for adjusting a propagation delay time existing in a pattern signal supply path to a desired relationship for each channel.

[0002]

2. Description of the Related Art FIG. 4 shows a schematic configuration of a semiconductor device test apparatus. In the figure, TES indicates the entire semiconductor device test apparatus. Semiconductor device test equipment TES is main controller 1
11, a pattern generator 112, a timing generator 11
3. Waveform formatter 114, logical comparator 115, driver 116, analog comparator 117, failure analysis memory 1
18, logic amplitude reference voltage source 121, comparison reference voltage source 12
2. It is composed of a device power supply 123 and the like.

The main controller 111 is generally constituted by a computer system, controls mainly a pattern generator 112 and a timing generator 113 in accordance with a test program created by a user, and generates test pattern data from the pattern generator 112. The test pattern data is converted into a test pattern signal having an actual waveform by the waveform formatter 114, and the test pattern signal is converted into a logical amplitude reference voltage source 1
The voltage is applied to the semiconductor device under test 119 through the driver 116 that amplifies the voltage to the waveform having the amplitude value set to 21 and stored.

The response signal read from the semiconductor device under test 119 is converted by the analog comparator 117 into the comparison reference voltage source 1.
22 to determine whether the signal has a predetermined logic level (H logic voltage, L logic voltage). The signal determined to have the predetermined logic level is a logical comparison. The device 115 compares the value with the expected value output from the pattern generator 112 to determine pass / fail. Here, the timing generator 113 determines the timing for defining the rising timing and the falling timing of the waveform of the test pattern signal given to the semiconductor device under test 119 and the timing for capturing the logic value of the response signal in the analog comparator 117. A specified strobe pulse timing is generated.

Each of these timings is described in a test program created by the user, and is configured to operate the semiconductor device 119 under test at a timing intended by the user and to test whether the operation is normal or not. ing.
From the pattern generator 112 to the semiconductor device under test 119
Is referred to as a test pattern signal supply path or a channel in general here. The number of channels of the test pattern signal supply path is provided corresponding to the number of pins of the semiconductor device 119 to be tested as a semiconductor device test apparatus, and is generally several hundred channels.

[0006] Each channel is provided with a variable delay circuit, and the signal propagation delay time of each channel can be freely set on the leading phase side and the lagging phase side around a reference value. The operation of adjusting the signal propagation delay time of each channel to the reference value is generally called calibration, and the signal propagation delay time of all channels is calibrated to the reference value by performing the calibration. FIG.
FIG. 1 shows a configuration of a circuit used for conventional calibration. Reference numeral 116 shown in FIG. 5 denotes the driver shown in FIG.
Reference numeral 117 denotes an analog comparator. A variable delay circuit 124 is provided on the input side of the driver 116, and the delay time of the variable delay circuit 124 is arbitrarily adjusted to calibrate the propagation delay time of all channels.

Here, an analog comparator 117 is connected to the output side of the driver 116, and the semiconductor device under test 119 is connected.
2 shows the configuration of the driver 116 and the analog comparator 117 connected to the input / output pins of the first embodiment. The calibration is performed using the analog comparator 117 having this configuration as a timing comparator. When performing the calibration, the semiconductor device under test 119 is connected to the output side of the driver 116.
Are not connected, and the test pattern signal PAT output from the driver 116 is directly applied to the analog comparator 117. To the other input terminal of the analog comparator 117, for example, a comparison voltage VOH that defines a high level (H logic) of the test pattern signal PAT is applied. Therefore, the logic value of the signal FAIL output from the analog comparator 117 is H depending on whether the voltage of the test pattern signal PAT applied to the analog comparator 117 is higher or lower than the comparison voltage VOH at the application timing of the strobe pulse STRB1A.
Sorted into logic or L logic.

The phase of the test pattern signal PAT is adjusted in the leading direction or the lagging direction according to the setting of the delay time of the variable delay circuit 124. The timing of the strobe pulse STRB1A applied to the analog comparator 117 is used as a reference timing, and the test pattern signal PAT of each channel is used.
Falling edge or rising edge of strobe pulse ST
By making the timing coincide with the timing of RB1A, the delay time of the variable delay circuit 124 can be made uniform for all channels. A counter 126 is provided on the output side of the analog comparator 117 to measure whether the phase of the test pattern signal PAT is ahead or behind the timing of the strobe pulse STRB1A. The counter 126 counts the logical value of the signal FAIL output as a result of the timing comparison by the analog comparator 117, whereby the falling or rising edge of the test pattern signal PAT is advanced with respect to the timing of the strobe pulse STRB1A. , Or is in a lag phase state, or coincides with the timing of the strobe pulse STRB1A.

The reason will be described below. FIG. 6 shows a timing comparison operation in the analog comparator 117. The example shown in FIG. 6 shows a state in which the falling timing of the test pattern signal PAT is compared with the timing of the strobe pulse STRB1A. If the test pattern signal PAT1 shown in FIG. 6 is set to the phase of the test pattern signal in the initial state, the L logic of the test pattern signal PAT1 is always detected at the application timing of the strobe pulse STRB1A. Assuming that the number of timing comparisons of the analog comparator 117 is previously set to, for example, N (256 times) and the counter 126 counts N timing comparison results of L logic, the test pattern signal PAT1 is too advanced from the reference timing. I understand that

For this purpose, the setting is changed to increase the delay time of the variable delay circuit 124 by the time T1, and the timing comparison is executed again N times. Assuming that the phase of the test pattern signal at this time is the test pattern signal PAT2 shown in FIG. 6, in this case, the counter 126 counts only N logics of H logic. (Actually, since the number N of timing comparisons is already known, the counter 126 counts only one of the L logic and the H logic and obtains the count values of the L logic and the H logic.) This indicates that the test pattern signal PAT2 is too late from the reference timing.

Therefore, this time, the setting is changed so that the delay time of the variable delay circuit 124 is advanced by T2 smaller than the time T1, and at this time, the timing at which the test pattern signal PAT3 crosses the comparison voltage VOH and the strobe pulse S
Assuming that the timing of TRB1A coincides, the counter 126 counts H logic and L logic by half. That is, assuming that the phase of the test pattern signal PAT3 coincides with the reference timing, the phase of the test pattern signal PAT3 slightly fluctuates around the reference timing during the execution of the timing comparison N times, and on the average the leading direction. And a phenomenon of shifting in the delay direction.

As a result, in this type of calibration, the timing of the edge of the test pattern signal PAT and the timing of the strobe pulse STRB1A coincide with each other when the count value of the counter 126 counts about 1/2 of the number N of timing comparison operations. It has been determined that it has been done. Although the timing-related calibration in the semiconductor device test apparatus can be understood from the above, the point that the counter 126 further performs the count operation by defining the timing comparison result of the analog comparator 117 as N times, which is defined in advance, will be described. I do.

In order to regulate the count operation of the counter 126 to a predetermined N times, in the example shown in FIG.
25 are provided. In this example, the synchronization circuit 125 is configured by an AND gate. A signal FAIL output as a timing comparison result of the analog comparator 117 is input to one input terminal of the AND gate, and a synchronization signal CPE for permitting timing comparison is input to the other input terminal. This synchronization signal CPE is shown in FIG.
Are generated by the pattern generator 112 shown in FIG. The pattern generator 112 generates a pulse train having a constant period, which is a source of the synchronization signal CPE. This pulse train is controlled by the program shown in FIG.
Generate E.

According to the description of the program shown in FIG. 7, as shown in FIG. 8, four dummy cycles and four test cycles (0), (1),
(2), (3) An operation of repeating the application of the synchronization signal CPE to the synchronization circuit 125 three times at a rate of one every TS (one test cycle) is realized. Actually, several hundred test cycles are allocated to the dummy cycle DMS, and the number of times of execution of the comparison operation is set to, for example, about 256 times.
Here, the dummy cycle DMS refers to a period during which the apparatus is idle until the operation of the apparatus is stabilized before the propagation delay time of the test pattern signal supply path is measured in order to perform timing calibration. In general, a number of test cycles giving a time corresponding to about several milliseconds are executed.

PAT shown in FIG. 8C is a test pattern signal applied to the analog comparator 117 with a given delay time, and STRB1A shown in FIG.
8E, a strobe pulse giving reference timing, FIG.
Is the strobe pulse STR shown in FIG. 8D.
An output signal of the analog comparator 117 representing a timing comparison result punched by the pulses ST1, ST2, ST3, and ST4 in B1A. This output signal FAIL is generated by the following pulses ST1 ', ST2', ST3 ', ST4 following the respective strobe pulses ST1, ST2, ST3, ST4.
At the timing of ', the logic of the test pattern signal PAT is punched out and returned to the logic of the test pattern signal PAT. FIG.
Pulse EN shown in F shows the logical comparison results applied through a synchronizer 125 to the enable terminal T _EN of the counter 126. Only when the logical comparison result EN is low, the counter 126 outputs the strobe pulse STRB1B.
Is counted.

Therefore, the counter 126 outputs the synchronization signal CPE
Is the period during which the signal has risen to the H logic (the period when the pulse EN is at the L logic)
Only the counting operation is permitted, whereby the total number N of timing comparisons is defined by the number of generations of the synchronization signal CPE.

[0017]

As described above, conventionally, the number N of timing comparisons is defined by the number of generations of the synchronization signal CPE. Some models do not have a function of generating a synchronization signal CPE for defining the number of comparisons N. Even if an attempt is made to implement the calibration function on a model that cannot generate the synchronization signal CPE, it cannot be implemented because the total number N of the timing comparison operations cannot be specified.

An object of the present invention is to provide a semiconductor device test apparatus which does not have a function of generating a synchronization signal CPE and which has a calibration function on a semiconductor device test apparatus.

[0019]

According to a first aspect of the present invention, there is provided an analog comparator for detecting the phase of a calibration signal passing through a test pattern signal supply system, and a synchronizing signal with a calibration signal passing through the test pattern signal supply system. A synchronization circuit for taking out the comparison result of the analog comparator, and a counter for counting the comparison result taken out by the synchronization circuit, and adjusting the delay time of the variable delay circuit provided in the test pattern signal supply system. When the count value of the counter converges to almost half the total number of comparisons of the analog comparator, it is determined that the phase of the calibration signal matches the comparison timing of the analog comparator, and the test pattern signal supply system In semiconductor device test equipment equipped with a timing calibration function for calibrating the propagation delay time of Suggest a period generator, the semiconductor device testing apparatus equipped with a structure with the timing calibration function be generated by the synchronization signal generator constituted by a number of comparisons generator for generating a number of comparisons of the analog comparator.

According to a second aspect of the present invention, in the semiconductor device test apparatus having the timing calibration function according to the first aspect, the dummy cycle generator includes a test cycle counter for counting test cycles of the semiconductor device test apparatus, and a desired cycle counter. A dummy cycle setting device that sets and stores the number of dummy cycles, and detects a state in which the count value of the test cycle counter matches the number of dummy cycles set in the dummy cycle setting device and stops counting operation of the test cycle counter. The present invention proposes a semiconductor device test apparatus equipped with a coincidence detector and a timing calibration function constituted by the coincidence detector.

According to a third aspect of the present invention, in the semiconductor device test apparatus equipped with the timing calibration function according to the first aspect, the repetition period generator detects that a dummy cycle generator has passed a predetermined dummy cycle since the start of the test. A gate, a test cycle counter that starts counting test cycles immediately after the gate detects the passage of the dummy cycle, and a match detector that detects that the coefficient value of the test cycle counter matches a desired cycle number. And a repetition period setting device for applying a desired number of repetition periods to the coincidence detector, and a semiconductor device test apparatus equipped with a timing calibration function.

According to a fourth aspect of the present invention, in the semiconductor device test apparatus equipped with the timing calibration function according to the first aspect, the comparison number generator detects that the dummy cycle generator has passed a predetermined dummy cycle. When,
A gate for detecting that a condition for detecting a cycle of a test cycle in which a repetition cycle occurrence period is set matches, a test cycle counter for counting test cycles based on a condition match signal output from the gate, and a total of the test cycle counter A semiconductor device test apparatus equipped with a timing calibration function constituted by a coincidence detector for detecting that a numerical value matches a predetermined number of comparisons, and a comparison number setting unit for giving the number of times of execution of the comparison operation to the coincidence detector. suggest.

[0023]

According to the present invention, since a synchronization signal is generated by the synchronization signal generator for the timing comparison operation, even a model having no function of generating the synchronization signal CPE for the timing comparison from the pattern generator is used. A timing calibration function can be added. Therefore, according to the present invention, there is obtained an advantage that a calibration function can be added without selecting a model of a semiconductor device test apparatus.

[0024]

FIG. 1 shows the configuration of a main part of a semiconductor device test apparatus having a calibration function according to the present invention. In FIG. 1, parts corresponding to those in FIG. 5 are denoted by the same reference numerals. As described with reference to FIG. 5, here, a test pattern signal supply path is constituted by the variable delay circuit 124 and the driver 116, and the semiconductor device under test 119 is connected to the output side of the driver 116 in the test mode.

An analog comparator 117 is connected to the output side of the driver 116. In the test mode, the analog comparator 117 has a logic level of a response signal output from the semiconductor device 119 under test having a normal H logic level. Is determined, or whether it has the L logic level. In the calibration mode, the analog comparator 11
Reference numeral 7 is used as a timing comparator, and compares the timing of the strobe pulse STRB1A with the timing of a test pattern signal PAT used as a calibration signal.

The result of the timing comparison performed by the analog comparator 117 is synchronized by a synchronization circuit 125, and only the result of the timing comparison falling within a predetermined comparison timing range is supplied to the counter 126 as valid.
At step 6, either H logic or L logic (L logic in this example) is counted. The present invention is characterized in that a synchronization signal applied to the synchronization circuit 125 is generated by the synchronization signal generator 127. Synchronous signal generator 12
7 is a dummy cycle generator 1 for defining a dummy cycle.
0, a repetition period generator 20 for defining the repetition period of the timing comparison operation, and a comparison number generator 30 for defining the total number N of comparison execution times.

Each time the conditions output by the dummy cycle generator 10, the repetition period generator 20, and the comparison number generator 30 match, the counting operation of the counter 126 is permitted.
The timing comparison result of the analog comparator 117 is counted. Therefore, the timing comparison operation is started when the operation of the semiconductor device test apparatus is stabilized by executing the dummy cycle defined by the dummy cycle generator 10. The total number N of the timing comparison operations is defined by a set value set in the comparison number generator 30. Further, the repetition period of the comparison cycle is defined by a set value set in the repetition period generator 20.

The configuration and operation of each unit will be described below with reference to FIG. The synchronization circuit 125 can be constituted by an AND gate. The example shown in FIG. 2 shows a case where a four-input inverted AND gate is used. The inversion type AND gate outputs L logic to its output when L logic is given to all input terminals. In this state, the counter 1 shown in FIG.
When the strobe pulse STRB1B is input to 26,
The counter 126 counts the number of inputs. That is, the number of times the output of the synchronization circuit 125 falls to L logic is counted.

A dummy cycle generator 10 has a test cycle counter 11 for counting the number of test cycle repetitions.
A dummy cycle setter 14 for setting a desired number of dummy cycles; a match detector 12 for detecting that the count value of the test cycle counter 11 matches the set value set in the dummy cycle setter 14; And can be configured by: The coincidence detector 12 outputs L logic when the count value of the test cycle counter 11 does not coincide with the set value of the dummy cycle setter 14. In this state, the test cycle counter 11 outputs the strobe pulse STRB output at a rate of one per test cycle.
The number of 1C inputs is counted. Dummy cycle setting device 14
Is set to the number of dummy cycles necessary for the operation of the test apparatus to be stable. Generally, several hundred test cycles are set. The timing chart shown in FIG. 3 shows a case where “4” is set in the dummy cycle setting unit 14. As a result, when four strobe pulses STRB1C shown in FIG. 3B are input, output signal Q1 of dummy cycle generator 10 falls to L logic as shown in FIG. 3C. Once the output signal Q1 of the dummy cycle generator 10 falls to L logic, it is maintained at L logic until the next clear signal CLR (FIG. 3A) is input.

The repetition cycle generator 20 can be constituted by a gate 25, a test cycle counter 21, a coincidence detector 22, an inverter 23, and a repetition cycle setter 24. Gate 25 is dummy cycle generator 1
0 indicates that the generation of the dummy cycle has been completed, and a detector for detecting that the output signal Q3 of the comparison number generator 30, which will be described later, is in the L logic state and the measurement operation for timing calibration is being executed. Works as Therefore, the state where the dummy cycle generator 10 completes the generation of the dummy cycle and the output signal Q1 falls to the L logic and the state where the comparison number generator 30 outputs the L logic indicating that the measuring operation is being performed. When they match, the gate 25 outputs L logic, and the test cycle counter 21 counts the number of input strobe pulses STRB1C based on the L logic signal. In the repetition period setting unit 24, the number of test cycles in which the counting operation of the counter 126 is performed is set. In the timing chart shown in FIG.
Is set to "4-1", and every four test cycles (0), (1), (2), (3), (0), (1),
(2), (3)... Show cases where the counter 126 is set to perform a counting operation. Therefore, the test cycle counter 21 counts the number of input strobe pulses STRB1C from the time when the output signals Q1 and Q3 of the dummy cycle generator 10 and the comparison cycle generator 30 are set to L logic, and the count value is (0), (1), (2), and (3). When the count value of the test cycle counter 21 reaches (3), the coincidence detector 22 detects a coincidence and outputs its output to L.
Fall to logic. The output signal Q2 of the inverter 23 rises to the H logic due to the fall of the L logic, and the rise of the H logic causes the load input terminal LD of the test cycle counter 21 to rise.
, The count value (3) of the test cycle counter 21 is returned to (0), and the count operation of the next cycle is enabled. As a result, as shown in FIG. 3D, repetition period generator 20 outputs an output signal Q2 that falls to L logic every four test cycles.

The comparison number generator 30 can be constituted by a gate 35, a test cycle counter 31, a coincidence detector 32, and a comparison number setting unit 34. The gate 35 determines whether the dummy cycle generator 10 has completed the generation of the dummy cycle, the state in which its own coincidence detector 32 detects the state of non-coincidence, and the coincidence detector 22 of the repetition cycle generator 20 that coincides. It operates as a detector that detects the detecting state. Each time these conditions are satisfied, the test cycle counter 31 sets the strobe pulse STRB1
The number of C inputs is counted. That is, specifically, when the strobe pulse STRB1C is input while the output signal Q2 of the repetition cycle generator 20 falls to L logic, the test cycle counter 31 increments the count value by one, and the repetition cycle generator 20 The number of times that the signal of L logic is generated (equivalent to the number of times of execution of the comparison operation in the analog comparator 117) is counted.

The comparison number setting unit 34 includes an analog comparator 1
At 17, the number of comparisons to be executed is set. The timing chart shown in FIG. 3 shows a case where “3” is set as the number of times of execution of the comparison operation. Therefore, when the output signal Q2 of the repetition cycle generator 20 falls to L logic three times, the coefficient value of the test cycle counter 31 becomes "3", and the coincidence detector 32 detects coincidence and outputs H logic, The comparison operation ends.
Actually, the numerical value set in the comparison number setting unit 34 is, for example, a numerical value of about “256”.
The averaged comparison result is obtained when the falling (or rising) timing of the test pattern signal BAT is set to a state close to the reference timing.

As is apparent from the above description, the synchronization signal generator 127 generates the dummy cycle DMS after the occurrence of the predetermined dummy cycle DMS.
At each repetition period set in repetition period generator 20, output signals Q1, Q2, and Q3 all output a synchronization signal that matches L logic. As a result, the counter 126 performs an operation of counting the state of the analog comparator 117 in a cycle (cycle of the signal Q2) in which the repetition cycle generator 20 outputs L logic.
That is, in the embodiment shown in FIGS. 1 and 2, the number of times that the comparison result FAIL (FIG. 3H) of the analog comparator 117 is L logic is counted. If the propagation delay time of the test pattern signal supply path is too advanced or too late with respect to the reference timing as described with reference to FIG.
The count value of 6 is equal to the number of executions of the comparison operation set in the comparison number setting unit 34, or indicates “0”. According to the example shown in FIG. 6, when the count value of the counter 126 matches the count set in the comparison number setting unit 34, the phase of the PAT is too advanced, and when “0” is shown, the phase of the PAT is too late. Is determined. When the falling timing of the test pattern signal matches the timing of the strobe pulse STRB1A (FIG. 6), the count value of the counter 126 becomes almost 1/2 of the number of times of comparison execution according to the fluctuation of the phase of the test pattern signal.
Value.

[0034]

As described above, according to the present invention, when the analog comparator 117 is used to measure the propagation delay time of the test pattern signal supply path, the number of comparisons of the analog comparator 117 is determined by a known value. The configuration is such that a synchronization signal is generated from the synchronization signal generator 127 to limit the number of synchronization signals. Therefore, even if the pattern generator 112 is not equipped with a function of generating this kind of synchronization signal CPE, a calibration function can be provided even in a model of a semiconductor device test apparatus. The advantage that it can be added is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a synchronization signal generator that is a main part of the present invention and a synchronization circuit that operates using a synchronization signal output from the synchronization signal generator.

FIG. 2 is a block diagram for explaining a specific embodiment of the synchronization signal generator shown in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG. 2;

FIG. 4 is a block diagram illustrating an outline of a general semiconductor device test apparatus.

FIG. 5 is a block diagram for explaining a conventional technique.

6 is a waveform chart for explaining the operation of the block diagram shown in FIG.

FIG. 7 is a diagram showing a description example of a program used in the conventional technique.

FIG. 8 is a timing chart for explaining the operation of the conventional technique shown in FIG.

[Explanation of symbols]

 Reference Signs List 111 Main controller 112 Pattern generator 113 Timing generator 114 Waveform formatter 115 Logical comparator 116 Driver 117 Analog comparator 118 Failure analysis memory 119 Semiconductor device under test 121 Logical amplitude reference voltage source 122 Comparison reference voltage source 123 Device power supply 124 Variable Delay circuit 125 Synchronization circuit 126 Counter 127 Synchronization signal generator 10 Dummy cycle generator 11 Test cycle counter 12 Match detector 13 Inverter 14 Dummy cycle setter 20 Repeat cycle generator 21 Test cycle counter 22 Match detector 23 Inverter 24 Repeat Period setting unit 25 Gate 30 Comparison number generator 31 Test cycle counter 32 Match detector 33 Comparison number setting unit 35 Gate

Claims (4)

[Claims] An analog comparator for capturing a phase of a calibration signal passing through a test pattern signal supply system, and a synchronization for extracting a comparison result of the analog comparator in synchronization with a calibration signal passing through a test pattern signal supply system. And a counter for counting the comparison result taken out by the synchronization circuit, and adjusting the delay time of the variable delay circuit provided in the test pattern signal supply system to adjust the count value of the counter to the analog value. When the phase of the calibration signal coincides with the comparison timing of the analog comparator in a state in which the value converges to almost half of the total number of comparisons of the comparator, the propagation delay time of the test pattern signal supply path is determined. In a semiconductor device test apparatus equipped with a timing calibration function for calibrating, a synchronization signal given to the synchronization circuit is provided by a dummy cycle generator and a repetition cycle. Raw device, the semiconductor device testing apparatus equipped with a timing calibration function, characterized in that a configuration for generating the synchronizing signal generator constituted by a number of comparisons generator, for generating a number of comparisons of the analog comparator. 2. A semiconductor device test apparatus equipped with a timing calibration function according to claim 1, wherein said dummy cycle generator sets a test cycle counter for counting test cycles of the semiconductor device test apparatus and a desired number of dummy cycles. A dummy cycle setting device for storing and storing, and a coincidence detector for detecting a state where the number of dummy cycles set in the dummy cycle setting device matches the count value of the test cycle counter and stopping the counting operation of the test cycle counter. And a semiconductor device test apparatus equipped with a timing calibration function. 3. A semiconductor device test apparatus equipped with a timing calibration function according to claim 1, wherein said repetition period generator includes a gate for detecting a lapse of a predetermined dummy cycle from the start of the test by said dummy cycle generator. A test cycle counter that starts counting test cycles immediately after the gate detects the elapse of the dummy cycle, a match detector that detects that the coefficient value of the test cycle counter matches a desired number of cycles, A semiconductor device test apparatus equipped with a timing calibration function, comprising: a repetition period setting device for applying a desired number of repetition periods to a detector. 4. A semiconductor device test apparatus provided with a timing calibration function according to claim 1, wherein said comparison number generator detects that said dummy cycle generator has detected a state in which a predetermined dummy cycle has passed, and A gate for detecting that a condition for detecting a cycle of a test cycle in which a cycle occurrence period is set matches, a test cycle counter for counting test cycles by a condition match signal output from the gate, and a total of the test cycle counter A timing calibration function characterized by comprising a coincidence detector for detecting that a numerical value matches a predetermined number of comparisons, and a comparison number setting device for giving the number of times of performing a comparison operation to the coincidence detector is provided. Semiconductor device test equipment.