JP2002152247A - Packet switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a packet switch that can conduct high-speed switching to a variable length packet and can efficiently utilize a buffer memory. SOLUTION: In the packet switch of a structure, where a variable length packet received from each input channel LI is written into a common buffer memory 22 in units of data blocks of a fixed length, a buffer control section 30 forms an input queue by each input channel at data write. When the final data block of a variable length packet is registered to an input queue, the linked address list of the input queue is linked to an output queue, corresponding to a transfer destination output channel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a packet switch applied as a node device in a variable length packet communication network, and more particularly, to a packet switch using a common buffer memory as a memory for temporarily storing received packets. The present invention relates to a buffer type variable length packet switch.

[0002]

2. Description of the Related Art In recent years, an Internet Protocol (hereinafter, referred to as IP), which has attracted attention, employs a variable-length packet (I) called an IP datagram.
The message transfer is performed using the P packet as a transfer unit. In a conventional node device that configures an IP packet network, a received packet is switched to a destination path by software processing. However, a fixed-length packet (data A device configuration that performs switching using a block as a transfer unit has been proposed.

As a node device for transferring an IP packet at a high speed, for example, “A 50-Gb / s IPRouter” (Craig Part
ridge et al., IEEE / ACM TRANSACTIONS ON NETWORKING, V
ol. 6, No. 3, June 1998), there are multiple line cards (boards) each supporting multiple network interfaces and a Forwarding Engine card with a routing table. And a point-to-point type switch represented by a crossbar switch, each line card transmits a data block including a header portion of a received packet to the transfer engine, and a new header updated by the transfer engine is processed. The data block containing the information is returned to the line card on the packet input side, and each line card on the input side transfers the data block containing the new header information and the remainder of the packet to the line card on the output side. A router device has been proposed.

According to the above-mentioned paper, each line card on the input side disassembles packets into 64-byte chained pages (data blocks) and sends them, and each line card on the output side converts these pages. Assembles into a linked list representing the packets and passes the assembled packets to the QoS processor, which places the packets in the appropriate location in the transmit queue based on the packet length, destination, and flow identifier specified by the forwarding engine. It is disclosed.

[0005] As a switching device having a fixed length packet transfer unit, an ATM (Asynchronous Transfer Mod- ule) is used.
e) Switches. In the ATM switch, a fixed-length packet of 53 bytes (AT) received from each input line is used.
After temporarily storing the stored cells in the buffer memory, the stored cells are stored in the connection identification information (V
(PI / VCI).

If the ATM switch adopts a common buffer type structure in which a buffer memory is shared by a plurality of input lines, a variable length queue can be formed for each output line in the buffer memory. Even if the incoming cell row is received simultaneously from multiple input lines, it is possible to buffer received cells from each input line without discarding, as long as there is an empty area in the common buffer as a whole, thus saving memory resources. The switch used for can be realized.

Japanese Patent Application Laid-Open No. 11-261584 proposes a switching device for variable-length messages, which makes use of the advantages of the common buffer memory. In the above prior art, the common buffer memory is divided into a plurality of memory blocks corresponding to messages, one empty memory block is assigned to each received message, and a message received from each input line is divided into a plurality of fixed-length messages. The cell is divided into cells, and cells belonging to the same message are sequentially stored in the same memory block.

[0008]

In the router described in the above-mentioned IEEE document, the line card on the input side is
Prior to the transmission of each packet, it negotiates with the output line card via the switch allocator, and starts transmitting when the output card acknowledges the reception of the packet.
There is a problem with the packet processing speed. Also,
Each line card on the input side needs a buffer for holding packets, and each line card on the output side also needs a buffer for packet assembly, so there is a problem in the efficiency of use of the buffer memory.

On the other hand, in the switching device described in Japanese Patent Application Laid-Open No. H11-261584, when the last part of each message is input, all cells stored in the memory block corresponding to the received message are separated. Since the transfer is made to the memory area (message queue), there is a problem in the time required for transferring the message between the memory areas and the use efficiency of the buffer memory.

It is an object of the present invention to provide a packet switch that can efficiently switch a variable-length packet by using a common buffer memory efficiently.

[0011]

In order to achieve the above object, a packet switch according to the present invention comprises a common buffer memory shared by a plurality of input lines, and a fixed length data block for receiving packets from each input line. Multiplexing means for multiplexing the data in units and supplying the same to the common buffer memory, and buffer control means for controlling writing and reading of each fixed-length data block to and from the common buffer memory, wherein the buffer control means When each fixed-length data block output from the multiplexing means is written to the common buffer, an input queue for each variable-length packet is formed, and when the last data block of the variable-length packet is registered in the input queue, The input queue is linked to an output queue corresponding to a destination output line of a variable-length packet.

More specifically, the buffer control means forms a plurality of input queues by linking the write address of each fixed-length data block in the common buffer memory for each variable-length packet, and forms the last of the variable-length packets. First control means for linking an input queue whose fixed-length data block has been written to the common buffer memory to an output queue corresponding to a transfer destination output line;
A second control unit that accesses a plurality of output queues formed corresponding to the output lines in a predetermined order and reads a fixed-length data block from the common buffer memory based on a linked address indicated by each output queue. The input queue for each variable-length packet writes, for example, each fixed-length data block to the common buffer memory based on a write address extracted from an empty address memory,
It is formed by storing the write address of the next fixed-length data block in the same variable-length packet corresponding to each write address in the next address memory.

In the present invention, each output queue comprises, for example, an address table for storing a next read address indicating the next data block to be read and a final read address indicating the last data block. By moving the write address of the first data block and the write address of the last data block of each variable length packet to the next read address and the last read address of the address table corresponding to the transfer destination output line, respectively, the input to the output queue described above is performed. Complete the queue link. In this case, the second control means reads the fixed-length data block and the address of the next fixed-length data block from the common buffer memory and the next address memory, respectively, based on the next read address registered in each output queue. By using the address read from the next address memory as a new next read address in the output queue, data blocks constituting each variable-length packet can be read one after another.

When the input queue of the succeeding variable length packet is linked to the output queue in which the final read address of the preceding variable length packet has already been registered, the first control means operates in the next address memory. The write address of the first data block of the succeeding variable length packet may be linked to the last read address.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a packet switch according to the present invention. The packet switch 1 divides a variable-length packet 100 input from each of the input lines LI-1 to LI-n into a plurality of fixed-length data blocks 110, and adds an internal header 110A to each data block and outputs the data block. An input line interface 10-1 to 10-n, a multiplexing unit 21 for performing time-division multiplexing of data blocks input from the input line interfaces 10-1 to 10-n, and outputting to a signal line L21; A common buffer memory 22 connected to the line L21;
And a buffer controller 30 for controlling the writing and reading of the data blocks to and from the common buffer memory 22.
An input counter 24 that counts a clock CLK0 indicating a write cycle and generates an input line selection signal;
An output counter 25 counts a clock CLK1 indicating a read cycle and generates an output line selection signal.

A variable length packet input from each input line LI-i (i = 1 to n) includes a packet header 100A including a destination address and a data section 100B. Each input line interface 10-i (i = 1 to n) divides the variable-length packet 100 received from the input line LI-i into a plurality of fixed-length data blocks 110, for example, an input line number and a packet header. An internal header 110A including an output line number determined by the destination address extracted from the data block 100A and block position display information indicating whether each data block 110 corresponds to the first block, the intermediate block, or the last block in the variable length packet.
Is generated, added to each data block, and output.

Writing and reading of data blocks to and from the common buffer memory 22 are performed by clocks CLK0 and CLK1.
Are performed alternately according to The multiplexing unit 21 cyclically selects the input line interfaces 10-1 to 10-n according to the input line selection signal generated on the signal line L24 by the input counter 24, and outputs the data output from each input line interface. The blocks 110 are sequentially multiplexed on the signal line L21. On the other hand, the separation unit 23 converts the data block read from the common buffer memory 22 to the signal line L22 into an output line interface 20-j specified by the output line selection signal generated by the output counter 25 on the signal line L25.
(J = 1 to n). The output line interfaces 20-1 to 20-n remove the internal header 110A from the data block 110 received from the separation unit 23,
The signals are transmitted to the output lines LO-1 to LO-n corresponding to each of them.

The buffer controller 30 controls the clock CLK0
In each write cycle indicated by, a data block is written to the common buffer memory 22 while forming a linked address list corresponding to the input line number i indicated by the internal header 110A appearing on the signal line L21. The buffer control unit 30 forms a new input queue corresponding to the input line each time the first block of the received packet appears on the signal line L21, and transfers the data of the subsequent intermediate block and last block to the input line, as described later. Registered one after another in the corresponding input queue, and when the last block of the received packet is written into the common buffer memory 22, the input queue is linked to the output queue corresponding to the transfer destination output line of the received packet. -Dynamic control of the address list.

Reading of data blocks from the common buffer memory 22 is performed based on an output queue address list formed corresponding to each output line. The buffer control unit 30 checks the presence / absence of a data block to be read for the output queue corresponding to the output line selection signal given on the signal line L25, and if the data block address is linked to the output queue, the output The next read address registered in the queue address list is used as the read address RA as the common buffer memory 2.
Two data blocks are read from the signal line L22, and the next read address in the address list is rewritten to the next data block address in the linked address list.

FIG. 2 is a block diagram showing details of the buffer control unit 30. The buffer control unit 30 includes a header analysis unit 31, an input queue control unit 32, an output queue control unit 33, a next address management unit 34, and an empty address memory (FIFO) for storing empty addresses in the common buffer memory 20. ) 35.

The header analyzer 31 analyzes the internal header of each data block appearing on the signal line L21, and determines that the input line number IN-i, the output line number OUT-j, and the input data block is the first block of the received packet. And a final display flag signal EP indicating whether or not the input data block is the last block of the received packet.

The input queue control unit 32 provides, for each input line,
Address of the head data block registered in the input queue (packet head address: BAi (i = 1 to n)) 30
1 and the address of the latest data block registered in the input queue (latest address: WAi (i = 1 to n))
And an input queue address table 300 indicating the input queue address 302.

The output queue control unit 33 provides, for each output line,
Read address of the data block located at the head of the output queue (next read address RAj (j = 1 to n)) 31
1 and the read address of the last data block located in the output queue (final read address EAj (j = 1 to
n)) 312 and an output queue address table 310 indicating a queue flag (Fj (j = 1 to n)) 313 indicating the presence or absence of registered data in the output queue.

The next address management unit 34 includes a next address memory 340 including a plurality of address storage areas NA1 to NAm equal to the number m of data blocks that can be stored in the common buffer memory 22. Each storage area of the next address memory 340 is used to form a linked address list for reading out the data block sequence registered in the input queue in the order of registration.

Hereinafter, assuming that a variable length packet destined for the same output line LO-3 is input from the input lines LI-1 and LI-2, the packet head of the input queue corresponding to the input line LI-1 is input. The address BA1 and the latest address WA1, and the packet head address BA2 and the latest address WA2 of the input queue corresponding to the input line LI-2.
Focusing on the queue flag F3 of the output queue corresponding to the output line LO-2, the next read address RA3 and the final read address EA3, the function of the buffer control unit 30 will be described with reference to FIGS. Will be described in detail.

The header analyzer 31 analyzes the internal header 110A of each data block output to the signal line L21 and generates an input line number IN-i and an output line number OUT-i. If the data block is the first block of the variable length packet, the first display flag signal FP is turned on, and if the data block is the last block, the last display flag signal EP is turned on.

The data block output to the signal line L21 is stored in the common buffer memory 2 using the empty address extracted from the empty address FIFO 35 as the write address WA.
Written to 0. At this time, the input queue control unit 32
Input line number IN-i output from header analysis unit 31
And updates the input queue address table 300 according to the state of the head display flag signal FP. If the head display flag signal FP is on, the write address WA extracted from the free address FIFO 35
Of the packet entry address BAi and the latest address WAi of the table entry corresponding to the input line number IN-i.
Write to. If the head display flag signal FP is off, the write address WA is written to the latest address WAi. When a new address WA is written in the input queue address table 300, the address that has been stored so far as the latest address WAi is output to the next address management unit 34. The next address management unit 34 stores the free address F in the storage area NAi corresponding to the address WAi.
New write address WA extracted from IFO 35
Is stored.

Thus, each time a fixed-length data block divided from one variable-length packet is written into the common buffer memory 22, the write address of the data block is stored in the next address memory 340, and the latest address WAi is stored. Updated, and finally, the packet head address BAi indicates the address of the head data block of the variable length packet, and the latest address WAi indicates the address of the last data block of the variable length packet.

FIG. 3 shows that the data blocks D1-1 to D1-4 output from the input line interface 10-1 and the input line interface 1 are stored in the common buffer memory 22.
Data blocks D2-1 to D2- output from 0-2
2 shows the state of the input queue address table 300 at the time when 2 is written. Here, WA1-1 to WA1-
4 is the value of the write address WA of the data blocks D1-1 to D1-4 obtained from the free address FIFO 35,
WA2-1 to WA2-2 are data blocks D2-1 to D2-1.
D2-2 shows the value of the write address WA. Also, RA
3, EA3 and F3 correspond to the data blocks D1-1 to D1-1.
1-4, transfer destination output line LO-3 of D2-1 to D2-2
Output queue address table entry 31 corresponding to
The contents of 0-3 are shown.

The input queue corresponding to the input line LI-1
In the address table, the write address WA1-1 of the head data block D1-1 is the packet head address BA
1 and the content of the latest address WA1 is updated every time a data block is written, and the contents of WA1-1 and WA1-1 are updated.
1-2, WA1-3, and WA1-4. In the next address memory 340, as shown in FIG. 3, the write address of the next data block is sequentially stored in a storage area corresponding to the latest address WA1, and the packet head address BA1 and the next address memory of the input queue address table 300 are stored. 340 forms a linked address list for each input line.

For example, based on the address WA1-1 indicated by the packet head address BA1, the common buffer memory 2
2 and the next address memory 340, the head data block D1-1 and the address WA1-2 of the next data block D1-2 can be read, and this address WA1-2 is used in the next read cycle. By using it as read address RA,
The next data block D1-2 and the address WA1-3 of the next data block D1-3 can be read, and by repeating the same operation, all data blocks registered in the input queue can be read. Becomes possible.

Like the input line LI-1, the input line LI-
2, the write address WA2-1 of the head data block D2-1 is stored as the packet head address BA2, the contents of the latest address WA1 are updated each time a data block is written, and WA2- 1, WA2-2,...

FIG. 3 shows the input line interface 10-1.
And 10-2 show the state before outputting the last data block of the variable length packet. There is no registered data in the output queue corresponding to the output line LO-3, and the output queue address table entry 310-3 is empty. Has become. According to the present invention, when the last data block of a packet is written to the common buffer memory 22, the buffer control unit 30
The packet head address BAi and the latest address WAi (= WA) in the input queue of the last data block are moved to the output queue address table 310.

When the transfer destination output queue of the data block stored in the input queue is in an empty state, that is, when the queue flag Fj corresponding to the output line number OUT-j output by the header analysis unit 31 is in the off state, the packet header The contents of the address BAi and the latest address WAi are transferred to the next read address RAj and the last read address EAj of the output queue / address table entry 310-j, respectively, and the queue flag Fj is rewritten to the ON state.

FIG. 4 shows the input line interface 10-1.
Data block D of variable length packet output from
The operation of the buffer control unit 30 when 1-5 is written to the common buffer memory 22 will be described. In this case, after storing the write address WA1-5 of the last data block D1-5 in the next address memory 340, the buffer controller 30 stores the contents (WA1-1) of the packet head address BA1 of the input queue and the latest address WA1. Contents (WA1-
5) is output to RA3 and EA3 of the output queue address table.
And rewrite the queue flag F3 to the ON state.
The content of the latest address WA1 is the new write address W extracted from the free address FIFO 35 this time.
A, EA3 of the output queue address table contains the write address W extracted from the vacant address FIFO 35 instead of the latest address WA1.
A may be stored.

When the transfer destination output queue of the data block accumulated in the input queue is in use, that is, when the queue flag Fj corresponding to the output line number OUT-j output by the header analysis unit 31 is on, The buffer control unit 30 combines the linked address list of the input queue with the linked address list of the destination output queue. The linking of the linked address list stores the contents of the packet start address BAi of the input queue in the next address memory 340 as the next address paired with the last data block of the output queue, and outputs the contents of the latest address WAi of the input queue. This is achieved by setting the last read address EAj in the queue address table 310.

FIG. 5 shows that when the output queue of the output line LO-3 is already in use, the input line interface 10-
2 shows the operation of the buffer control unit 30 when writing the final data block D2-3 of the variable length packet output from the buffer control unit 30 to the common buffer memory 22. In this case, after storing the write address WA2-3 of the last data block D2-3 in the next address memory 340, the buffer control unit 30 registers the contents (WA2-1) of the packet head address BA2 of the input queue in the output queue. The next address is written to the next address memory 340 as a next address paired with the completed last data block D1-5. Writing of the head address WA2-1 to the next address memory 340 is performed using the last read address WA1-5 (see FIG. 4) indicated by EA3 in the output queue address table at that time as a write address. Thereafter, EA3 of the output queue address table contains the contents of the latest address WA2 (WA2-3).
Is rewritten as

When the variable-length packet received by the line interface is short and can be accommodated in one fixed-length data block, when this data block is written into the common buffer memory 22, a head display flag signal output from the header analysis unit 31 is output. The FP and the final display flag signal EP are simultaneously turned on. In this case, the contents of the packet head address BAi and the latest address WAi registered in the input queue address table 300 in response to the head display flag signal FP are output in response to the final display flag signal EP.
Immediately moved to address table 310.

If the output queue of the output line LO-j to which the data block is to be transferred is empty, the packet head address BAi and the latest address WAi are used as in FIG.
Is written to RAj and EAj, and if the output queue is already in use, the contents of the packet start address BAi become the next address paired with the last data block of the output queue, as in FIG. 5, and the latest address WAi Becomes the new EAj.

The reading of the data blocks from the common buffer memory 22 is performed by the output queue control unit 33. The output queue control unit 33 refers to the output queue address table entry 310-j specified by the output line selection signal output to the signal line L25 in the read cycle, and if the queue flag Fj is on, the next read The data block is read from the common buffer memory 22 according to the address RAj, and the next address NAj is read from the next address memory 340. The used next read address RAj is released to the free address FIFO 35. The next address NAj read from the next address memory 340 is stored in the output queue address table as a new next read address RAj.

FIG. 6 shows an embodiment of the input queue control unit 32. The input queue control unit 32 outputs the packet start address BA1
To 3031 to 301 for storing .about.BAn.
-N, registers 302-1 to 302-n for storing the latest addresses WA1 to WAn, and a header analyzer 31.
Decoder 321 that decodes input line number IN-i received from, and turns on one of enable signals WEN-1 to WEN-n, and registers 302-1 to 302-3
A selector 322 for selecting one of the output addresses from the address 02-n and registers 301-1 to 301-
selector 323 for selecting one of the output addresses from n, and AND circuits 324-1 to 32 for controlling the write enable signal of the packet head address.
4-n.

A register 302 for storing the latest address
The addresses WA extracted from the empty address FIFO 35 are input to 1 to 302-n, and the enable signal WEN-1 output from the decoder 321 is input to each of the addresses 1 to 302-n.
~ WEN-n controls the update of the latest address. When the input line number IN-i indicates the i-th input line, the enable signal WEN-i is turned on, and the address WA extracted from the empty address FIFO 35 is set in the register 302-i. At this time, the write address {WAi} of the previous data block previously stored in the register 302-i is selected by the selector 322 and supplied to the next address management unit 34 as an address WAi for writing the next address (pointer address). You.

The addresses WA fetched from the free address FIFO 35 are packet head addresses BA1 to BA
n is also input to registers 301-1 to 301-n that store n. Writing to these registers is controlled by AND circuits 324-1 to 324-n, and is limited to the input line number I only during the write cycle in which the head display flag FP output from the header analysis unit 31 is in the ON state.
Address WA to register 301-i corresponding to Ni
Is written. The selector 323 selects an output address from the register 301-i corresponding to the input line number IN-i, and outputs the selected address as a packet head address BAi.

FIG. 7 shows an embodiment of the output queue control unit 33. The output queue control unit 33 outputs the next read address R
Registers 311-1 to 31-1 for storing A1 to RAn
11-n, registers 312-1 to 312-n for storing final read addresses EA1 to EAn, and a register 313-1 for storing queue flags F1 to Fn.
313-n, a selector 331 for selecting one of the output addresses from the registers 311-1 to 311-n, and one of the output addresses from the registers 312-1 to 312-n. Selector 332 for selecting
And a selector 333 for selecting one of output flags from the registers 313-1 to 313-n, and a decoder 334 for decoding an output line selection signal output from the output counter 25 to the signal line 25. And a decoder 335 that decodes the output line number OUT-j output from the header analysis unit 31 and turns on one of the enable signals EN-1 to EN-n. When the final display flag signal EP is turned on, the AND circuits 336-1 to 336 -n for enabling the enable signals EN- 1 to EN-n are enabled.
, AND circuits 336-1 to 336-n and register 31
Delay circuit 337 inserted between 3-1 to 313-n
−1 to 337-n and registers 313-1 to 313-n
And AND circuits 338-1 to 338-n inserted between the registers 311-1 to 311-n.

The registers 312-1 to 312-n for storing the final read addresses EA1 to EAn are supplied with the write addresses WA extracted from the empty address FIFO 35, and the AND circuits 336-1 to 336-3, respectively.
The output of 36-n is a write enable signal.
When the final display flag signal EP is turned on, the write enable signal from the AND circuit 336-j corresponding to the output line number OUT-j becomes valid and the register 312
The write address WA is set to -j. Since the write address WA in this case is the write address WAi of the last data block of the variable-length packet in the input queue address table 300, the address WAi of the input queue becomes the final read address ENj of the output queue. It has been moved to.

The outputs of the registers 312-1 to 312-n are output line numbers O output from the header analysis unit 31.
The register 3 which is connected to the selector 332 which uses UT-j as a selection signal and which is designated by the output line number OUT-j
The output address EAj from 12-j is selected and supplied to the next address management unit 34.

The registers 313-1 to 313-n for storing the queue flags F1 to Fn have AND
The outputs of the circuits 336-1 to 336-n are given as set signals. These registers 313-1 to 313
The output of −n is connected to a selector 333 that uses the output line number OUT-j as a selection signal.
The queue flag Fj of the register 313-j specified by T-j is selected and supplied to the next address management unit 34.

Here, the registers 313-1 to 31
The outputs of AND circuits 336-1 to 336-n are supplied to 3-n through delay circuits 337-1 to 337-n. Therefore, the register 31 selected by the selector 333
The cue flag Fj from 3-j indicates the state of the cue flag before being rewritten by the final display flag signal EP, and after the cue flag Fj is output,
A new queue flag is set in the register 313-j.

Registers 311-1 to 311-n for storing the next read addresses RA1 to RAn are provided with the packet start address B output from the input queue control unit 32.
Ai and the next address NAi output from the next address management unit 34 are input. These registers 311
In the write cycle, -1 to 311-n receive the outputs of the AND circuits 336-1 to 336-n and the negative outputs of the registers 313-1 to 313-n, respectively.
Output signals from the ND circuits 318-1 to 318-n are provided as enable signals, and when the final display flag signal EP is turned on, the register 313-j specified by the output line number OUT-j is output. The packet start address BAi is stored in the register 311-j specified by the output line number OUT-j on condition that the corresponding queue flag Fj is in the off state.

In the read cycle, the decoder 31-j specified by the output line select signal is supplied to the decoder 33-j.
4 receives an enable signal from the register 311-j.
Are selected by the selector 331 and supplied to the common buffer memory 22 and the next address management unit 34. The next address NAj read from the next address memory 340 by the next address management unit 34 is stored in the register 311-j as a new next read address RAj.
Is written as

Although the reset circuit is not shown in FIG. 7 for simplicity, the result of comparison between the last address EAj and the packet start address RAj is used as the reset signal of the register 313-j. That is, when the last read address EAj matches the next read address RAj, the output queue becomes empty in the next read cycle, so that the queue flag Fj is reset. Register 313
For resetting -j, for example, a comparison circuit for detecting a match between the output of the selector 332 and the output of the selector 331 is provided, and a match detection signal output from the comparison circuit is used.

FIG. 8 shows an embodiment of the next address management section 34. The next address management unit 34 stores the next addresses NA1 to NA1.
Registers 340-1 to 340- for storing NAm
m, a selector 341 for selecting an output address from these registers, and a selector 342 for selecting one of the write address WA extracted from the free address FIFO 35 and the packet head address BAi supplied from the input queue control unit 32. And the latest address WAi supplied from the input queue control unit 32 and the output queue control unit 3
And a selector 343 for selecting one of the final read addresses EAj supplied from the selector 343 and the selector 343.
, And an AND circuit 345.

The AND circuit 345 receives the final display flag signal EP supplied from the header analysis unit 31, the cue flag Fj supplied from the output queue control unit 33, and the clock signal CLK0. CLK0
Is Lo in the first half of the write cycle of each data block.
w is a signal that changes to a high state in the latter half.

In the write cycle, the selector 342 selects the write address WA when the output signal of the AND circuit 345 is in the off state, and selects the packet start address BAi when the output signal is in the on state.
-1 to 340-m are input data. Selector 343
Selects the write address WAi of the previous data block when the output signal of the AND circuit 345 is off, and selects the final read address EAj of the preceding packet when the output signal is on, and supplies the selected address to the decoder 344. input.
The decoder 344 decodes the address input from the selector 343, and registers the input address and the corresponding register 3
A write enable signal is given to 40-k.

Of the three signals EP, Fj, and CLK0 input to the AND circuit 345, CLK0 is always in the Low state in the first half of each write cycle. Therefore, in the first half of each write cycle, the input signals EP and Fj are low. Regardless of the state, the output of the AND circuit 345 is turned off, and the selectors 342 and 343 select WA and WAi, respectively. Therefore, the write address WA of the latest data block is stored in the storage area (register 340-k) corresponding to the write address WAi of the previous data block.
The linked address list for each input queue shown in FIG. 3 is formed.

In the latter half of each write cycle, CLK0 is in the High state, so that the output of AND circuit 345 is
It depends on the state of the input signals EP and Fj,
When both P and Fj are in the High state, the AND circuit 3
The output at 45 changes to the ON state. That is, when the data block written to the common buffer is the last data block of the variable-length packet registered in the output queue in use (signal Fj is High) (signal EP is High),
The output of the AND circuit 345 is turned on, and the selectors 342 and 343 select BAi and EAj, respectively.
The head address BAi of the variable-length packet is stored in the storage area (register 340-q) specified by the last write address EAj of the output queue. Thus, the data block sequence (linked address list) of the succeeding packet can be linked to the last data block of the preceding packet in the output queue.

When the data block written to the common buffer is the first data block or intermediate data block of the variable length packet (signal EP is low), or is registered in an empty output queue (signal Fj is low). In the case of the last data block of the variable length packet, the above A
Since the write cycle is completed while the output of the ND circuit 345 is in the Low state, the link to the output queue described above is output.
No additional operation of the address list occurs.

In the read cycle, the selector 341
Read address R supplied from output queue control unit 33
Aj, and selects the register 340-p corresponding to Aj, and stores the address stored in the register 340-p in the next address N
The value is returned to the output queue control unit 33 as Aj. Next address N
Aj is output by the output queue control unit 33 as a new next read address RAj used in the next read cycle.
It is stored in the register 311-j.

In the above embodiment, the buffer control unit 30
Formed an input queue for each input line number, and moved the linked address list of the input queue to the output queue when the last data block of the variable-length packet arrived. Since the queue only needs to be formed for each variable length packet, other identification information unique to each variable length packet may be used instead of the input line number. In the embodiment, the input line number is set in the internal header of each data block, and the header analysis unit 31 outputs the input line number IN-j based on the internal header. Alternatively, it may be generated based on an input line selection signal output from 24.

In the above-described embodiment, each input line interface 10-i (i = 1 to n) divides the variable length packet 100 received from the input line into a plurality of fixed-length data blocks 110. The data block is output to the multiplexing unit 21 with the internal header 110A attached thereto, and the data block with the internal header is read and written to the common buffer memory 22. However, as another embodiment of the present invention, For example, as shown in FIG. 9, the multiplexing unit 21 separates the data block 110 from the internal header 110A, supplies the internal header 110A to the header analysis unit 31 of the buffer control unit 30, and stores the data in the common buffer memory 22. You may make it input only the block 110 part. According to the above configuration, the memory capacity of the common buffer memory 22 can be used effectively, and each output line interface 2
0-i eliminates the need to remove the internal header from the data block.

As still another embodiment of the present invention, each input line interface 10-i outputs the fixed-length data block 110 to the multiplexing unit 21 without adding an internal header, and outputs the fixed-length data block 110 to the header analyzing unit of the buffer control unit 30. 31 analyzes a packet header included in the head data block of each variable-length packet, manages an output line number and the number of subsequent data blocks for each input line on a management table, and receives an input from an input counter 24. The management table is referred to according to the line selection signal, and the above-described IN-i, FP, E
Control signals such as P and OUT-j may be generated. The conversion from the variable-length packet 100 to the fixed-length data block 110 is performed by each input line interface 1.
Instead of using 0-i, the multiplexing unit 21 may perform it.

In the embodiment, a packet switch connected to a plurality of input / output lines has been described. However, the buffer control according to the present invention employs a switch structure for outputting variable length packets received from a plurality of input lines to one output line. (Multiplexing device).

[0063]

As is clear from the above description, according to the present invention, an input queue is formed for each variable-length packet, and 1
When the last data block of one variable-length packet is written to the buffer memory, the input queue is moved to an output queue corresponding to the output line of the variable-length packet. Therefore, according to the present invention, even when a plurality of variable-length packets destined for the same output line are input in parallel, the data block sequence belonging to one variable-length packet in the output queue has the data of another packet. Blocks can be prevented from being mixed, and by sequentially sending data blocks extracted from the output queue to the output line, it becomes possible to correctly transfer received packets to the destination device.

In the present invention, the variable-length packet received from the input line is divided into fixed-length data blocks and stored in the common buffer memory in fixed-length block units. Is stored in the common buffer memory, and only the linked address list for reading the data block sequence is moved to the output queue without moving the data block sequence stored in the common buffer memory. High-speed switching of long packets becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a packet switch to which the present invention is applied.

FIG. 2 is a diagram showing details of a buffer control unit 30 of the packet switch shown in FIG. FIG. 3 is a conceptual diagram illustrating a first state of an input queue and an output queue.

FIG. 3 shows data blocks stored in a common buffer memory 22, a next address memory 340, and an input queue.
FIG. 4 is a diagram for explaining a state of an address table 300.

FIG. 4 is a diagram for explaining a relationship between an input queue address table 300 and an output queue address table 310 when the last data block of a variable length packet arrives.

FIG. 5 is a diagram for explaining the relationship between the input queue address table 300 and the output queue address table 310 when the last data block of another variable length packet arrives while the output queue is in use.

FIG. 6 is a diagram showing one embodiment of the input queue control unit 32 shown in FIG. 2;

FIG. 7 is a diagram showing one embodiment of an output queue control unit 33 shown in FIG. 2;

FIG. 8 is a diagram showing one embodiment of the next address management unit shown in FIG. 2;

FIG. 9 is a diagram showing another embodiment of the packet switch to which the present invention is applied.

[Explanation of symbols]

1: packet switch, 10: input line interface, 20: output line interface, 21: multiplexer
22: common buffer memory, 23: separation unit, 24: input counter, 25: output counter, 30: buffer control unit, LI: input line, LO: output line, 31: header analysis unit, 32: input queue control unit, 33: output queue control unit, 34: next address management unit, 35: free address F
IFO, 300: input queue address table, 30
1 (BA1 to BAn): packet start address, 302
(WA1 to WAn): latest address, 310: output queue address table, 311 (RA1 to RAn): next read address, 312 (EA1 to EAn): last read address, 313 (F1 to Fn): queue flag.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Naohiko Ozaki 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Communications Division (72) Inventor Mitsuhiro Wada 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd.Communications Division (72) Inventor Norihiko Moriwaki 1-280 Higashi Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. (72) Inventor Masazumi Fukano 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa-ken, Ltd. Hitachi, Ltd. Communications Division (72) Inventor Yumasa Futami 216, Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture In-house Hitachi Ltd. Communications Division (72) Takayuki Kanno 216, Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa, Japan 5K030 GA01 HA08 HB28 JA01 KA13 KX02

Claims (6)

[Claims] 1. A packet switch for transferring variable-length packets received from a plurality of input lines to at least one output line in fixed-length data block units, wherein: a common buffer memory shared by the plurality of input lines; Multiplexing means for multiplexing received packets from each input line in fixed-length data block units and supplying the multiplexed data to the common buffer memory; and a buffer for controlling writing and reading of the fixed-length data blocks to and from the common buffer memory The buffer control means links a write address of each fixed-length data block in the common buffer memory for each variable-length packet to form a plurality of input queues, and forms the last fixed-length packet of the variable-length packet. Input for which a long data block has been written to the common buffer memory First control means for linking a queue to an output queue corresponding to a transfer destination output line; and accessing a plurality of output queues formed for the output line in a predetermined order, based on a linked address indicated by each output queue. A second control unit for reading a fixed-length data block from the common buffer memory. 2. The buffer control means according to claim 1, further comprising: a free address memory for holding a free address in said common buffer memory; and a next address memory for storing a write address of a fixed-length data block in said common buffer memory. The first control means writes each fixed-length data block in the common buffer memory based on a write address taken out from the free address memory, and the same variable corresponding to each write address in the next address memory. The packet switch according to claim 1, wherein the input queue is formed by storing a write address of a next fixed-length data block in a long packet. 3. Each of the output queues comprises an address table for storing a next read address indicating a data block to be read next and a final read address indicating a last data block. 3. The packet switch according to claim 2, wherein the write address of the first data block and the write address of the last data block of the long packet are respectively a next read address and a last read address of an address table corresponding to the transfer destination output line. . 4. When linking an input queue of a subsequent variable length packet to an output queue in which a final read address of a preceding variable length packet is already registered,
The first control means includes:
4. The packet switch according to claim 2, wherein a write address of a leading data block of the succeeding variable length packet is linked to the final read address. 5. An address of a fixed-length data block and a next fixed-length data block from the common buffer memory and the next address memory, respectively, based on a next read address registered in each of the output queues. And reading the next read memory, moving the next read memory to the free address memory, and setting the address read from the next address memory as a new next read address in the output queue. 5. The packet switch according to 4. 6. The apparatus according to claim 1, further comprising a separating unit for allocating the fixed-length data block read from the common buffer memory to a plurality of output lines. Packet switch.