JP2002139551A - Semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus reducing the number of signal lines extending from the I/F part of a mainframe to the pin electronics control portion of a test head. SOLUTION: In the semiconductor testing apparatus, a test head bus electrically connects between the mainframe and the test head, and a pin electronics control circuit for each channel of the test head is used to control signals at each channel. Each pin electronics control circuit is provided with a first register capable of designating one of the channels of data in advance in response to the data of the test head bus and a second register capable of designating in advance one of blocks each consisting of plural channels. Only signals at a prescribed channel are masked.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor test apparatus in which the number of signal lines between a main frame and a test head is reduced.

[0002]

2. Description of the Related Art FIGS.
The configuration and operation will be described with reference to FIG. First, an outline of an example of the overall configuration of the semiconductor test apparatus will be described. FIG.
As shown in FIG. 1, the semiconductor test apparatus includes a workstation 10, a main frame 20, a test head 30,
It comprises a performance board 80 and an IC socket 90.

The workstation 10 is an input / output means which is electrically connected to the main frame 20 by a signal line and serves as an interface between a semiconductor test apparatus and a person.

[0004] The main frame 20 contains a power supply section of a semiconductor test apparatus, a tester processor, and various test units.

[0005] The test head 30 includes a main frame 20.
And pin electronics 40 of an electronic circuit corresponding to the number of test channels, electrically connected to the test head bus and the like.
Many are built-in.

[0006] The performance board 80 is a board in which an IC socket 90 corresponding to a device under test is mounted, and can be replaced and mounted by a device under test (hereinafter, referred to as a DUT) to be tested.

The IC socket 90 is a socket corresponding to the number of pins of the DUT 91 and the package. Multiple DUTs
When measuring 91 simultaneously, a plurality of IC sockets 90 are mounted on the performance board 80.

Next, a configuration example and operation of the semiconductor test apparatus will be described with reference to a block diagram of FIG. As shown in FIG. 7, the mainframe 20 includes the computer 3 and
Timing generator 4, pattern generator 5, waveform shaper 6, logical comparator 7, DC tester 8, I / F unit 9
Each unit is connected to the tester bus 100 and controlled.

However, FIG. 7 shows the I / F unit 9 as one unit, but the circuit may be distributed to other units or boards. For simplicity of the figure, the number of test channels of the semiconductor test apparatus is assumed to be one and the number of pin electronics 40 is shown as one. However, when the number of test channels is 1024, the number of pin electronics is 1024. It is provided and configured.

The pin electronics 40 comprises a pin electronics control unit 41, a driver D1, a comparator 1, and relays S11 and S12.

The I / F unit 9 supplies a control signal to the driver D1 of the pin electronics 40 via the test head bus 200 and the mask enable signal line 301 (VIH / VIL) and a control signal to the pin electronics control unit 41. Supply.

Next, a test method of the semiconductor test device will be described. When performing the voltage applied current measurement of the DC parametric test, turn off (break) the relay S12,
The relay S11 is turned on (make), a test voltage is generated from the DC tester 8, applied to the pins of the DUT 91, and the flowing current is measured.

The function test is performed by the I / O of the DUT 91.
The case where the operation is performed on pins will be described below.

The pattern generator 5 generates logical data in synchronization with the basic clock signal output from the timing generator 4.

In the waveform shaper 6, the pattern generator 5
And a clock signal from the timing generator 4 to generate a test pattern.

In the pin electronics 40, the relay S11 is turned off and the relay S12 is turned on, and the test pattern is set to a desired voltage level (VI) by the driver D11.
H / VIL) and outputs it to the test pin of the DUT 91.

The output signal from the test pin of the DUT 91 is turned on by the relay S11 and turned on by the relay S12, and the voltage is compared by the comparator C11 (VOH / VO).
L) and outputs it as a logic signal.

In the logical comparator 7, the logical output signal of the DUT 91 and the expected value from the pattern generator 5 are logically compared at the timing of the strobe signal from the timing generator 4, and the pass / fail judgment is made based on the match / mismatch. Perform

Next, the above-mentioned pin electronics 40
The signal control for each channel for turning ON (make) / OFF (break) the relays S11 and S12 will be described with reference to FIGS.

As shown in FIG. 8, the I / F unit 9 of the main frame 20 transmits data to the pin electronics control units 41 to 4n of the pin electronics 40 by the test head bus 200 and the mask enable signal lines 301 to 30n. Supply. However, although there are n other signal lines for enabling the pin electronics control units 41 to 4n of each channel, they are omitted.

Pin electronics control units 41 to 4n
Are provided corresponding to each channel, and each channel is independently controlled. For example, when an error occurs in a device under test DUT, the ON / OFF relay of the driver output is masked (OFF) in order to prohibit the driver output only for the specific pin where the error occurs. Further, when simultaneously measuring a plurality of DUTs, when a specific DUT fails, only the test channel of the defective DUT is masked in order to prohibit only input / output of the test channel of the defective DUT. .

Therefore, a mask enable signal line is provided independently for each channel. Therefore, the number of mask enable signal lines 301 to 30n and the number of pin electronics control units 41 to 4n need to be equal to the number of test channels. For example, if the semiconductor test apparatus has 1024 test channels, the number of mask enable signal lines is 1024.

As shown in FIG. 9, the pin electronics control section 41 includes a register 75 of a flip-flop, an inverter 76, and an AND gate 77. However, for the sake of simplicity, the output of the pin electronics control unit 41 is shown only when a control signal for turning ON / OFF the relay S12 is output.

The test head bus 200 is, for example, 16
As shown in FIG. 10, in the case of transferring 32-bit data, 16-bit data is transferred twice. Also, bits 0, 1, 2,..., 31 of the 32-bit data are channels 32, 31,.
30,... 1

The pin electronics control section 41
Is the channel 1, the pin electronics control unit 41 is enabled, the command signal of the channel test head bus 200 is taken into the register 51, and a signal for turning on / off the relay S12 of the driver is output.

The mask enable signal line 301 has one bit for each channel, and stores a mask signal in a register 75 of a flip-flop by a clock. Then, the mask signal of the register 75 is inverted by the inverter 76, and the ON signal of the relay S12 is inhibited by the AND gate 77 to mask the driver output.

Therefore, as shown in FIG. 8, in the semiconductor test apparatus, the pin electronics control sections 41 to 4n of the test head 30 are connected to the I / F section 9 of the main frame 20.
Is usually about 5 m, so if the number of channels is increased to 1024, the number of signal lines is also increased to 1024, so that cost, maintainability, reliability, and the like become problems.

[0028]

As described above, in a semiconductor test apparatus, the distance between the I / F section of the main frame and the pin electronics control section of the test head is usually five.
As the number of signal lines increases, there are practical problems such as cost, maintainability, and reliability. The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor test apparatus in which a signal line from an I / F section of a mainframe to a pin electronics control section of a test head is reduced. .

[0029]

That is, a first aspect of the present invention, which has been made to achieve the above object, is to electrically connect a main frame and a test head by a test head bus, and to provide pin electronics of each channel of the test head. In a semiconductor test device that performs signal control of the channel with a control circuit, receiving data of a test head bus,
Each pin electronics control circuit is provided with a first register capable of designating one channel of data in advance and a second register capable of designating one of a plurality of channels in response to the data of the test head bus. Accordingly, a gist of the present invention is a semiconductor test apparatus characterized in that only a signal of a predetermined channel can be masked.

That is, a second aspect of the present invention to achieve the above object is to electrically connect a main frame and a test head by a test head bus, and to provide a pin electronics control circuit for each channel of the test head. In a semiconductor test device that performs signal control of
A first register which receives data of the test head bus and can designate one channel of data in advance, and a multiplexer which selects and outputs one of the test head bus channel data using the output of the first register as a selection signal. A register of a flip-flop which receives a selection output of the multiplexer as data and outputs a mask signal, and a second register which receives data of a test head bus and can designate one of a plurality of blocks of channels, A match detection unit for detecting a match between the second register and the block data of the test head bus, and an AND gate that uses the sum of the match detection unit and a clock as a clock input of the register of the flip-flop. Provided in the electronics control circuit, it is possible to mask only the signal of a predetermined channel. Are summarized as semiconductor testing apparatus characterized by.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. An example of a schematic configuration of the entire semiconductor test apparatus is the same as that of the related art, and has been described in the related art, so that the description is omitted.

However, the semiconductor test apparatus of the present invention is different in the control signal to the I / F section 9 and the pin electronics control section 61 and the circuit configuration of the pin electronics control section 61 shown in FIG. As shown in FIG.
The I / F unit 9 of the test head bus 200 controls the pin electronics control units 61 to 6n of the test head 30.
Supply data and control signals to the However, as before,
Pin electronics control units 61 to 6n for each channel
Are enabled but omitted.

Next, in the test of the semiconductor test apparatus, D
When the UT fails, the driver output ON / OFF relay is masked (OFF) to prohibit the driver output only for the specific pin where the error occurs, or when the multiple DUTs are measured simultaneously, the specific DUT is used. In the following, a description will be given of a method of performing a test by masking only the input / output of the test channel of the defective DUT when a failure occurs.

As shown in FIG. 4, in the semiconductor test apparatus of the present invention, a channel for pin electronics is divided into blocks and channels to be mask-enabled are designated. For example, if the number of channels of a semiconductor test device is set to 102
Description will be made assuming that there are four channels.

As shown in FIG. 3A, when 32-bit data is represented as data [31: 0], a block is selected by 5 bits of data [12: 8], and data [3: 0] is selected. 4 bits specify one of 16 channels, and 1 bit of data [4] specifies one of channels 1 to 16 or 17 to 32. For example, as shown in FIG. 4A, blocks of channels 1 to 32 are selected by 5-bit data “00000”, and blocks of channels 993 to 1024 are specified by 5-bit data “11111”.

As shown in FIG. 4B, the 5-bit data "00000" is used for channels 1, 33, 6
, 993, and the 5-bit data "11"
111 "and channels 32, 64, 96, ..., 10
Specify 24. Therefore, by specifying a block and a channel, one channel of 1 to 1024 channels can be specified.

Next, the configuration and operation of the pin electronics 60 will be described with reference to FIGS. As shown in FIG. 1, the pin electronics control units 61 to 6n
Are provided for each channel, and independently control the signals of each channel. The test head bus 200 connects between the I / F unit 9 and the pin electronics control units 61 to 6n.

The test head bus 200 is, for example, a 16-bit bus as in the prior art, and is shown in FIGS.
When transferring 32-bit data shown in FIG.
Transfer in multiple times.

As shown in FIG. 2, the pin electronics control section 61 includes registers 71 and 72, a multiplexer 73, and a coincidence detection section in a conventional configuration including a flip-flop register 75, an inverter 76, and an AND gate 77. 74 and an AND gate 78 are additionally provided. However, for simplicity of the figure, the output of the pin electronics control unit 61 only shows a case where a control signal for turning on / off the relay S12 is output.

First, each of the pin electronics control units 61 to 6n shown in FIG. 1 needs to be initialized in advance to recognize which channel it is.

For example, after the semiconductor test apparatus is powered on, the pin electronics control unit 61 is enabled by an enable signal (not shown), and a block is written to the register 71 and a channel is written to the register 72 shown in FIG. Similarly, the pin electronics control units 62 to 1024 are enabled by an enable signal (not shown) for each channel.
Write the block to each register and the channel to each register.

Next, since the pin electronics control unit 61 is set to channel 1 and only the driver output of channel 1 is inhibited, the driver output ON / OFF relay S
A method of performing a test by masking (OFF) 12 will be described. For example, a command signal output from the driver of the test head bus 200 shown in FIG. 2 is taken into the register 51, and a signal for turning on the relay S12 of the driver is output.

The multiplexer 73 selects the channel 1 specified by the register 71 from the 32 bits of the data transferred from the 16 bits twice, and outputs 1 bit.

The coincidence detecting section 74 detects coincidence between the block signal transferred by 5 bits and 5 bits of the register 72, and uses the coincidence signal as a gate signal of the AND gate 78. The clock CLK is supplied to the AND gate 7 by the gate signal.
8 to fetch the channel data of the register 75.

The output of the register 75 is inverted by the inverter 76, and the AND gate 77 masks the relay S 12 of the driver of the register 51 to inhibit only the signal output of the channel 1.

Similarly, a test can be performed by masking only one desired channel or a plurality of channel outputs of the pin electronics control units 62 to 6n.

Therefore, the mask enable signal lines are conventionally provided independently for each channel. However, in the present invention, the pin electronics control units 61 to 6n are controlled by the test head bus 200. The existing mask enable signal line becomes unnecessary.

[0049]

The present invention is embodied in the form described above and has the following effects. That is,
In the semiconductor test apparatus, the distance from the I / F section of the main frame to the pin electronics control section of the test head is usually about 3 m to 5 m. Therefore, there is an effect that cost, maintainability, reliability and the like can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a main block diagram of a main frame and a test head of a semiconductor test apparatus according to the present invention.

FIG. 2 is a main part circuit diagram of a pin electronics control unit of the semiconductor test apparatus of the present invention.

FIG. 3 is an example of data setting of a test head bus of the semiconductor test apparatus of the present invention.

FIG. 4 is a channel setting example of the semiconductor test apparatus of the present invention.

FIG. 5 is an example of a configuration diagram of a semiconductor test apparatus of the present invention.

FIG. 6 is a block diagram of a semiconductor test apparatus.

FIG. 7 is an example of a configuration diagram of a conventional semiconductor test apparatus.

FIG. 8 is a main block diagram of a main frame and a test head of a conventional semiconductor test apparatus.

FIG. 9 is a main part circuit diagram of a pin electronics control section of a conventional semiconductor test apparatus.

FIG. 10 is an example of data setting of a test head bus of a conventional semiconductor test apparatus.

[Explanation of symbols]

 Reference Signs List 3 computer 4 timing generator 5 pattern generator 6 waveform shaper 7 logical comparator 8 DC tester 9 I / F unit 10 workstation 20 mainframe 30 test head 40 pin electronics 41 to 4n pin electronics control unit 51 register 60 pin Electronics 61 to 6n Pin electronics control unit 73 Multiplexer 74 Match detection unit 75 Register 76 Inverter 77, 78 AND gate 80 Performance board 90 IC socket 91 DUT 100 Tester bus 200 Test head bus 301 to 30n Mask enable signal line

Claims (2)

[Claims] 1. A semiconductor test apparatus in which a main frame and a test head are electrically connected by a test head bus and a pin electronics control circuit of each channel of the test head controls a signal of the channel. And a second register capable of receiving a test head bus data and specifying a block composed of a plurality of channels in advance in each pin electronics control circuit. A semiconductor test apparatus characterized in that only channel signals can be masked. 2. A semiconductor test apparatus in which a main frame and a test head are electrically connected by a test head bus, and a pin electronics control circuit of each channel of the test head controls a signal of the channel. A first register that can specify a channel in advance, a multiplexer that selectively outputs channel data of a test head bus using an output of the first register as a selection signal, and a selection output of the multiplexer as data, A register of a flip-flop that outputs a mask signal, a second register that can receive data of the test head bus and can specify a block composed of a plurality of channels, and determines whether the second register matches the block data of the test head bus. A match detection unit for detecting the match, And an AND gate that uses the sum of the output portion and the clock as a clock input of the register of the flip-flop, provided in each pin electronics control circuit, so that only a signal of a predetermined channel can be masked.