JP2002132453A - Disk array system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a disk array having a high internal transfer capacity corresponding to a host computer with a high-speed fiber interface. SOLUTION: This disk array system is equipped with plural upper fiber interfaces 102 that receive/send data from/to a host fiber interface 100, a cache memory 105 connected to the plural upper fiber interfaces, plural disk storage means 107 which data is written on or read from, and a disk drive interface 106 for controlling the storage means, and each of the plural upper fiber interfaces has a cache memory. Moreover, in the disk array system, a data distribution controlling part 103 is provided between the host fiber interface and the upper fiber interfaces.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a storage system for controlling a storage medium such as a magnetic disk device, a magnetic tape device, a semiconductor storage device or an optical disk device connected to a computer system using a fiber interface.

[0002]

2. Description of the Related Art Disk array systems use RAID.
(Redundant Arraysof Inexp
Also referred to as "enhanced disks", a configuration in which a plurality of disk devices are arranged in a row (array) is used, and a read request (data read request) and a write request (data write request) from the host are operated in parallel with the disks. A storage device that performs high-speed processing and adds redundant data to data to improve reliability. Disk array systems are classified into five levels according to the type and configuration of redundant data.
"A Case for Redundant Arr
ays of Inexpensive Disks
(RAID) ", David A. Patterso
n, Garth Gibson, and Rand
yH. Katz, Computer Science
e Division Division of
Electrical Engineering an
d Computer Sciences, Univ
erity of California Berke
eley).

At the time of a write request from the host, data received from the host is divided by a special address conversion inside the disk array, temporarily stored in a cache, and then sequentially written in parallel to a disk device. Is common. Conversely, at the time of a read request from the host, the divided data is read in parallel from the disk device and stored in the cache, and the divided data read from the cache is bundled as the original data and transferred to the host.

FIG. 2 is a configuration diagram of a conventional disk array based on the RAID technology. The disk array system includes a disk array fiber or SCSI upper interface 202 connected to the host interface 200, an MPU unit 204 and a cache controller 2 connected to each other via the interface 202 and the internal bus 203.
05 and the HD connected to the cache controller 205
D interface 207 and HDD group 209.

[0005] In FIG. 2, one upper interface is written, but a plurality may be provided. In this case, in the configuration of FIG. 2, a plurality of upper interfaces are connected to the shared cache memory, and the data bus transfer between the upper interface and the cache memory is performed in order to utilize the transfer capability of the upper interface. It is assumed that the capability is equal to or higher than the upper interface transfer capability. The transfer capability referred to here is the amount of data that can be transmitted per unit time. For example, the capability to transfer 1 gigabyte of data per second is represented by 1 gigabyte per second (GB / s). .

[0006]

In the conventional architecture shown in FIG. 2, in response to a read request from the host, data is sent from the disk to the cache memory, and then data is sent from the cache memory to the host. If the transfer capability of the host interface is 1, the transfer capability of the disk interface is 1, and the transfer capability of the cache memory is 2. Cache memory is
Since there is input and output of data, the transfer capability is twice that of the host interface and the disk interface. To make full use of the transfer capability of the host interface, the transfer capability of the cache memory needs to be twice that of the host interface. Similarly, if the number of upper hosts becomes N times, the transfer capacity of the upper host interface also becomes N times, and the transfer capacity of the cache memory becomes 2N times.

As can be seen from the above, in the conventional disk array architecture, the transfer capability of the internal bus is increased beyond the transfer capability of the upper side, and the transfer capability of the cache memory is also increased with the improvement of the internal bus transfer capability. It is essential to raise.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to simultaneously utilize a plurality of upper fiber interfaces to exchange data with one high-speed host fiber interface. A disk array having an internal bus with a low transfer rate can cope with a host fiber interface having a high transfer rate.

Another object of the present invention is to provide a host for managing a plurality of fiber interfaces when a plurality of higher-level fiber interfaces are provided in a disk array, or a target ID (for each port of a plurality of fibers). This is to provide a means for accessing one fiber interface without applying a load of switching of the target address (when a fiber connection is made after switching the target ID, a load is applied to the host).

[0010]

In order to solve the above problems, the present invention mainly employs the following configuration.

A plurality of upper fiber interfaces for transmitting and receiving data from the host fiber interface; a cache memory connected to the plurality of upper fiber interfaces; a plurality of disk storage means for writing or reading data; and controlling the storage means. A disk array system comprising: a disk drive interface; and a cache memory corresponding to each of the upper fiber interfaces of the plurality of upper fiber interfaces.

A plurality of upper fiber interfaces for transmitting and receiving data from the host fiber interface, a cache memory connected to the plurality of upper fiber interfaces, a plurality of disk storage means for writing or reading data, and the storage means. A disk drive interface to be controlled, comprising: a data distribution control unit provided between the host fiber interface and the higher-level fiber interface; The data from the interface is divided into a plurality of data and supplied to the plurality of upper fiber interfaces, and the divided data is simultaneously transmitted to the plurality of cache memories in parallel through the plurality of upper fiber interfaces. To transfer, and at the time of reading, the data from the plurality of cache memories is transferred in parallel to the data distribution control unit through the plurality of upper fiber interfaces, and the data divided by the data distribution control unit is bundled as original data, A disk array system that returns read data to the host.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A disk array system according to an embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 shows a disk array system according to an embodiment of the present invention. As shown in FIG. 1, the disk array system includes a data distribution control unit 10 connected to a host fiber interface 100 via a fiber cable 101.
3, upper fiber interfaces 102-0 and 102-1 connected to the data distribution control unit 103 via fiber cables 108-0 and 1, and temporarily connected to the upper fiber interfaces 102-0 and 102-1. Cache memory control controller 104 for storing data
−0 and 104-1 and the cache memories 105-0,1 under the cache controllers 104-0,1
, HDD interface 106, disk group HDD
107. Cache controller 1
It is connected by a high-speed data bus 111 so that cache management information and data can be exchanged between 04-0 and 104-1.

In the configuration of the disk array described above,
When the host writes data to the disk array via the fiber interface whose transfer speed is higher than that of the disk array, the data is temporarily received by the data distribution control unit 103 of the disk array, and the upper fiber interface in the disk array is received. The data is divided according to the number of. Further, a write command to the upper fiber interface is generated from the received host command, and the write command is written to the cache memory 105-0,1 via each upper fiber interface 102-0,1.

After the data blocks divided by the cache memory 105 are associated with each other for restoring the host data, the redundancy information is added, and the HDD group 107 is set in the free time.
Write to In response to a read command from the host, the request distribution data is sent to the data distribution control unit 103 from the cache memory 105 when data is present in the cache memory and from the HDD group 107 when data is not present in the cache memory. And the data distribution control unit 103
And returns it to the host (details will be described later).

Next, the data distribution control unit 1 will be described with reference to FIG.
The function or operation of 03 will be described. The configuration shown in FIG. 3 is a detailed structure of the data distribution control unit 103 in FIG. In order to sufficiently absorb the transfer speed difference between the host fiber interface 100 and the upper fiber interface 102, two buffers are provided in each upper fiber interface to make a total of four buffers. The capacity of each buffer is equal. In the host fiber drive control unit 301, four data transfer buffers 304-0, 1, 2, 3 have internal buses 303, 30 having the same speed as the host fiber 301.
5-0, 1, 2, 3 via the buffer bus switch 302, and the four-sided data buffer has an internal data bus 308, 309, 311 having a transfer rate equivalent to that of the upper-level fiber drive control unit 307. −0,1,
These are connected to the upper-level fiber drive controllers 307-0 and 307-1 via the bus switches 306 and 2,3.

The buffer switch 302 causes the host fiber drive control unit 301 to switch to the buffer to be connected, and causes the upper-level fiber drive control units 307-0, 307-1 to use another three-sided buffer not used by 301. Make it possible. By switching the bus switch 306, two of the four buffers can simultaneously transfer data with the fiber drive controllers 307-0 and 307-0. The switching operation of the bus switch is performed based on a transfer list described later. By introducing the bus switch, the data transfer speed between the buffer and the fiber drive control unit can be maximized as well as the bus transfer capability.

The MPU unit 310 has an area for storing commands from the host computer. The address of the access destination and the transfer data length are determined from the command received from the host, and the value obtained by dividing the transfer data length by the number of upper fiber interfaces is the length of the data transferred by each upper fiber drive control unit 307-0,1. Further, a value obtained by dividing the transfer data length by the size of one buffer in the data distribution control unit is set as the number of buffers to be activated by each upper fiber drive control unit 307-0,1. For example, if the number of upper fiber interfaces is N, the buffer size is M, and the length of read or write data from the host is L, the transfer data length by each upper fiber interface is L / N, and The number of buffers activated by the fiber interface is (L / N) / M. A transfer list is generated in the host fiber drive control unit 301 and the upper-level fiber drive control unit 307 using the transfer count.

FIG. 8 shows the upper-level fiber drive control unit 307.
And the control unit of the upper-level fiber drive 307 performs data transfer from the buffer to the cache according to the transfer list. FIG. 8A illustrates a control unit transfer list in the fiber drive control unit 307-0, and FIG. 8B illustrates a fiber drive control unit 307.
1 is a control unit transfer list in FIG.

Further, a copy of the management table of the cache memory on the two sides is provided in the MPU unit 310, and when the management table in the cache memory is updated, the update is transferred to the management table in the MPU unit 310 through the upper fiber interface. Will be reflected. In response to a write command from the host,
By searching the cache management table and showing the free space of the cache memory, it becomes possible to respond to a large-capacity data transfer request from the host at a high speed.

In order to simplify the management of the internal buffer,
Make the buffer have consecutive addresses. Host fiber drive control unit 301 and host fiber drive 307
A flag bit is provided to indicate whether or not the buffer is in use in order to avoid a buffer use conflict between the two. If the buffer is being used, the flag bit of the buffer is set to 0 (indicative of unusable), and after the use is completed (after the data in the buffer is used), the flag bit of the buffer is set to 1 (indicative of usable). And the fiber drive is in a buffer usable state. For example, when data is written from the host fiber drive 301 to the buffer 1 (304-1), the flag of the buffer 1 becomes 0, and the host 1 cannot access the buffer 1 from the upper-level fiber drive control unit 307. If the flag of -2 is 1, reading from the upper fiber drive or writing is possible.

The flow of a write process from the host will be described with reference to FIG. Here, the buffers 604-0, 1, 2,.
Assume the capacity of 3 is 300 KB. The write request from the host is 1.8 MB, and shows a flow when the write request is larger than the total buffer capacity.

The data distribution control unit decodes the write command from the host and writes the write destination address LBA (Logic).
c Block Address) and transfer data length Le
ngth is temporarily stored in the memory of the MPU unit 609. At the same time, the cache capacity is checked, and if the free space is larger than the requested data length, a response of the total transfer is returned to the host, and 1.8 MB of data is received at one time. When the cache capacity is small and 1.8 MB data cannot be received at one time, a request for data transfer corresponding to the cache free space is returned to the host. Also, when there is free space in the cache,
Receive the remaining data. In the example shown in the figure, only a case in which a typical cache free space is sufficient will be introduced.

The 1.8 MB data from the host is transferred to the buffer 0 by the host fiber drive controller 601.
KB, 300KB in buffer 1, 300K in buffer 2
B, 300KB in buffer 3, 300K in buffer 0
B, 300 KB is stored in the buffer 1. FIG. 4 shows a time chat for buffer switching.

When the host fiber drive controller 601 completes data storage in the buffer 0 (604-0),
The flag of the buffer 0 is set to 1 and the buffer 1 (604
-1) Data storage is started. At the same time, a write command including the write address LBA from the host and the transfer data length Length / 2 information by the upper fiber drive 608 is issued to the upper fiber drive 0 (608-0), and a buffer is issued from the upper fiber drive 0 (608-0). 0 (604-0) cache 0
Transfer to (612-0) is started (the flag is set to 0), and after the transfer is completed, the flag bit of the buffer 0 (304-0) is returned to 1 so that another fiber drive control unit can use it.

After the host fiber drive control unit 601 finishes storing data in the buffer 1 (604-1), it continues to store data in the buffer 2 (604-2). 1 (60
8-1), the write command issued to 608-0 is issued, and the buffer 1 is sent from the fiber drive 1 (608-1).
The data of (604-1) is transferred to the cache 1.
The host fiber drive control unit 601 transmits the buffer 2 (6
04-3), the buffer 3 (304)
-3), the upper fiber drive 0 (608-0) simultaneously stores the data in buffer 2 (604-604).
The data of 2) is subsequently transferred to the cache 0. After the transfer to the cache 0 is completed, the flag bit of the buffer 2 (604-2) is set to 1. Concurrently, the host fiber drive control unit starts putting host data into the buffer 0 (604-0). After storing the data in the buffer 3 (604-3) is completed, the host fiber drive controller stores the data in the buffer 3 in the fiber drive 1 (608).
-1) is transferred to the cache 1.

At the same time that the host fiber drive control unit 601 stores the last 300 KB in the buffer 1, the host fiber drive 0 (608-0) stores the last 300 KB in the buffer 0 (604).
−0) is transferred to the cache. After the host fiber drive completes the data storage in the buffer 1, the host fiber drive 1 sends the buffer 1 from the higher-level fiber drive 1 (608-1).
Is stored in the cache 1 repeatedly.

By using a plurality of buffers as described above, host data can be divided into two blocks of 900 KB and stored in the cache without interrupting data transfer from the host. After the cache finishes writing, the write completion report is sent to each upper interface, and when a write end signal is received from each upper interface in the data distribution control unit, the write completion is reported to the host.

The realization of the above method is ensured by the fact that the total transfer capability of the host fiber drive 608 is greater than the transfer capability of the host fiber drive 601. FIG. 5 shows a data transfer time chart between the host and the data distribution control unit ((1) in FIG. 5) and between the data distribution control unit and the upper fiber interface ((2) in FIG. 5). On the left side of the upper and lower parallel lines shown in FIG. 5 (1), the contents of transmission or reception in the host fiber interface are described in order from the top with time, and on the right side, the contents of reception or transmission in the data distribution control unit are the same. It is described in.
In FIG. 5B, the contents of transmission or reception between the data distribution control unit and the higher-level fiber interface unit are described over time, similarly to FIG. 5A.

In FIG. 6, cache 0 (612-0) under the control of the higher-level fiber drive 0 'control unit (610-0).
Are stored in the cache memory 1 (612-1) under the control of the fiber drive 1 'control unit (610-1).
00KB is stored. Here, the upper fiber drive 0 ′ control unit 610-0 and the upper fiber drive 1 ′ control unit 610-1 shown in FIG. 6 correspond to the upper fiber interface 102-0 and the upper fiber interface 102-1 shown in FIG. Things.

In order to simplify the cache management, the current cache control algorithm can be diverted as it is by managing the two-sided cache as a one-sided cache memory with continuous addresses. The cache management tables SGCB0, SGCB0,
1 (Segment Control Block) is provided, the table of cache 0 is used as a master, and cache 0 has a copy of the management table of cache 1. The management unit on the cache is a segment. The 1.8 MB host data divided into blocks 0 and 1 is further divided on the cache in segments and managed by the SGCBs 0 and 1. The segments are not necessarily contiguous in the cache. SGCB
Has the segment address and the LBA (Logic Blo) of the data staged in the cache.
ck Address).

After data is written to the cache, the SGC
The change in B1 is reflected in the copy of SGCB1 in cache 0 via the bus between the caches. Master SG
The segment belonging to SGCB1 in which CB0 has the same LBA is regarded as a part of the host write data,
The CB is reconstructed as shown in FIG. Therefore, the host data is integrated and managed. In the code shown in FIG.
SEG of EGL means segment (Segment), and L of SEGL means left (Left). SEG, which has two caches and is located in cache 0 on the left side, is referred to as SEGL, and cache 1 is located on the right.
Is the SEGR. Also, SEGL or SEG
ADR after R means address.

As shown in FIG. 7, data from the host is divided into left or right caches, and the divided data is managed in each cache in SEG units. When the SEG of the two-sided cache has the relationship shown in FIG. 7, it is possible to manage and use the distributed data as one data in the distributed cache.

The cache controllers 0, 1 (612-
0, 1) is provided with a function of adding data redundancy. In the case of the standard RAID3 or RAID5, when generating a redundancy code for storage in the HDD group in the cache, the cache 0, 1 (612-612) is used. 0, 1) generate redundant codes while maintaining synchronization. Cache 0 (612
After calculating the parity of the block 0 in (−0), the parity and necessary data are passed to the cache 1 (612-1), and the data parity of the block 1 is synthesized by the cache 1. The HDD interface (106 in FIG. 1) transfers data blocks 0 and 1 having redundancy to the HDD group (1 in FIG. 1).
07).

The writing destination of data block 0 to the HDD group (107) is determined based on the LBA of SGCB0 and the data transfer length information. The write destination of the block 1 to the HDD group is determined based on the LBA of the SGCB1 + the LBA as the length of the redundant block 0. When writing data to the HDD group, block 0 is performed first, and then block 1 is performed. In the case of RAID1, data copy is performed between caches, and after reaching a certain state of blocks 0 and 1 in both caches, writing to HDDs under each control is performed from the HDD interface.

Next, when the write request from the host is 200
A flow in the case of KB and smaller than the total buffer capacity will be described. The 200 KB data from the host is transferred from the host fiber drive control unit 601 to the buffer 0 (60
4-0) to 100 KB, buffer 1 (604-1) to 1
Stored at 00 KB each, without using buffers 2 and 3. The host fiber drive control unit 601 sends the buffer 0 (604
After the data storage in (−0) is completed, the flag of the buffer 0 is set to 1 and the buffer 0 (604-0) is set in a state where the other fiber drive control unit can use it.

Thereafter, the upper fiber drive 0 (608) is started simultaneously with the start of data storage in the buffer 1 (604-1).
-0) starts transferring the data of the buffer 0 to the designated cache 0 (612-0), and after the transfer is completed, returns the flag bit of the buffer 0 to 1 so that the other fiber control unit can be used. Host fiber drive control unit 60
After the data storage in the buffer 1 (604-1) is completed, the buffer 1 is made available, and then the upper fiber drive 1 similarly stores the data in the buffer 1 in the cache 1 (612-1). ) To perform data transfer. 1 each under the cache 0, 1 (612-0, 1)
00 KB of host data is stored. Subsequent processing is the same as in the transfer example of 1.8 MB.

Next, read hit / miss determination is performed by SGCB.
This is performed based on the LBA of 0 and the segment information. A read command from the host is sent from the data distribution control unit to the upper fiber interface 0. If the requested LBA and the requested data exist on the cache, it is possible to determine that the hit has occurred and immediately start data transfer. Request LBA
Exists, but a portion of the requested data has already been written to the HDD, the segment used by that data is allocated to other data, and if a portion of the data does not exist in the cache, a cache hit occurs. However, the data transfer is started after reading the missing data from the cache from the HDD. LBA requested by host command
If it does not match the LBA information held by SGCB0, it is determined that a mistake has occurred.

At the request of the host, 1.
A flow when 8 MB data is read from the disk array will be described.

The data distribution control unit interprets the read command from the host, determines the read destination and the required data length, and temporarily stores them. A value obtained by dividing the required read data length by the number of upper fiber channels is set as a data length to be transferred by each upper fiber drive control unit. Then, a read command including a read destination address LBA and transfer data length information is issued to the upper fiber interface 0. Hit / miss is determined by the above rule in the cache 0, and in the case of a hit, data is returned from the caches 0 and 1.

In the case of a mistake, the read address LBA and data transfer length information are sent to the HDD interface 106, and
From 06, block 0, half of the host data, is sent to cache 0. Thereafter, a read command including half of host data, an address LBA for reading block 1 and transmission data length information is issued from the cache 0 to the HDD interface 106 via the cache 1. Block 0
Is completed, the block 1 is transferred to the cache 1 from 106. Read LBA of block 1 is L of block 0
BA + transfer data length.

After the read data is put into the cache, the fiber drive control units 0 and 1 send the transfer list of FIG. 9 regarding the order in which the data from the cache is buffered in order to transfer the data to the data distribution control unit. Generate. In order to return the data from the cache put in the data distribution control unit buffer to the host, the host fiber drive control unit 301 also generates a transfer list in the form shown in FIG.

The fiber drive control units 0 ', 1' (610-0, 1) on the cache side receive the read command from the data distribution control unit and instruct the HDD interfaces 0, 1 on the read destination address and the read data length. Accordingly, the HDD interfaces 0 and 1 transfer block 0 to the cache 0 and block 1 to the cache 1. Then, the data blocks 0 and 1 are transmitted from the fiber drives 0 'and 1' to the data distribution control unit. The data received by the upper fiber drive 0, 1 controller (307-0, 1) is transferred to the data distribution control buffer three times each according to the transfer list in FIG.

In the first transfer by the upper fiber drive controllers 0 and 1, buffers 0 and 1 (304-0, 1) are used.
Is full, the upper fiber drive control units 0, 1
Releases the buffers 0 and 1 and sets the buffer use status flag to 1, then starts the host fiber drive 301 and returns data to the host in the order of buffers 0 and 1. At the same time, the second data transfer from the upper fiber drives 0 and 1 to the buffers 2 and 3 is performed, and after completion, the flag bit of the corresponding buffer is set to 1 and the host fiber drive control unit is enabled. Buffer 0, 1
When the data transfer from the host to the host is completed and the data becomes usable, the last 600 MB is stored in the buffers 0 and 1 again from the higher-level fiber drive controllers 0 and 1. At the same time, the host fiber drive control unit 301 returns data from the buffers 2 and 3 to the host, and the last 600 MB
From the buffers 0 and 1 to the host.

Next, the flow of reading the 200 MB data stored in the above example from the HDD group will be described. The data distribution control unit 203 interprets the read command from the host, determines the read destination and the required data length, and temporarily stores them. The requested read data length is divided by the number of upper fiber interfaces (608-0, 1), and 100 MB is the data length transferred by the upper fiber drive.
Use only one at a time. The data distribution control unit issues a read command to the upper-level fiber interface 0, including a read destination address LBA and transfer data length information.

In the cache 0, hit / miss is determined according to the above rule, and in the case of a hit, data is returned from the cache. In the case of a miss, the read address LBA and the data transfer length information are sent to the HDD interface 106, and the data block 0 of 100 MB from the HDD is stored in the cache 0 and the block 1 is stored in the cache 1 from the HDD. A transfer list for transmitting 100 MB of data in each buffer from the caches 0 and 1 is generated. In order to return data from the cache to the data distribution control unit buffer to the host, a transfer list similar to that shown in FIGS. 9 and 10 is generated in the host fiber control unit and the upper fiber interface control unit.

According to the transfer list, the upper-level fiber drive controllers 0 and 1 simultaneously transfer 100 MB of data to the buffers 0 and 1 for data distribution control. After the buffers 0 and 1 are ready to be used by the host fiber drive controller, 100 MB of data is returned from the buffers 0 and 1 to the host.

The HDD group in this embodiment employs an HDD having a fiber interface, and a fiber drive FPC for controlling the HDD group is used for the HDD interface. Although the parity generation function is provided in the cache controller, it is also possible to provide the HDD interface with a parity generation function instead of the cache controller.

Further, in this embodiment, an example is described in which two upper fiber interfaces are used inside the disk array. However, the number of upper fiber interfaces is not limited to two, but may be plural. Further, in the present embodiment, the data distribution control unit and the cache are connected via the fiber channel. However, similar effects can be obtained when the data distribution control unit and the cache are directly connected via the internal bus.

As described above, the embodiments of the present invention include those having the following structures, functions, and actions. That is, a plurality of upper fiber interfaces for transferring data from the host fiber interface, a cache memory connected to the plurality of upper fiber interfaces, a plurality of disk storage means for writing or reading data, and a disk for controlling the storage means And a drive interface, the data distribution control unit provided between the host fiber interface and the higher-level fiber interface, wherein the data distribution control unit blocks data from the host fiber interface into a plurality of blocks according to the number of higher-level interfaces. And simultaneously transferring the divided data to a plurality of cache memories in parallel through a plurality of upper fiber interfaces connected to a data distribution control unit; and Since a plurality of fiber interfaces have their respective cache memories in the inside of the ray, the transfer speed of the disk array internal bus connected to the upper fiber interface (that is, the transfer speed of each internal bus 109-0 or 109-1 shown in FIG. 1) is increased. An object of the present invention is to make it possible to cope with a host fiber interface having a high transfer speed even if its transfer speed is lower than that of a host fiber interface.

Also, in this embodiment, the data distribution control unit shows the ID of the fiber interface that the data distribution control unit itself has to the host, receives the access request from the host once in the buffer, divides it, and simultaneously transmits the divided access request to the upper interface. By issuing and executing the host, the host does not become aware of the existence of the multiple fiber interfaces in the disk array. In other words, unlike the connection by the fiber loop or the fiber switch, the host fiber interface bites the buffer and connects to a plurality of upper fiber channels, and the host fiber interface is not directly connected to the upper fiber interface.

[0052]

The following is a brief description of the effect obtained by the surface of the invention disclosed in the present application.

By operating a plurality of upper fiber interfaces inside the disk array simultaneously, even a disk array system having an internal bus whose transfer speed is slower than that of the host fiber interface has a host fiber interface whose transfer speed is high. It became possible to execute high-speed access from the host without impairing the speed.

In the buffer of the data distribution control unit, the host write request is answered by the free space of the cache, and a small-capacity buffer having a plurality of planes is reused, so that a small-capacity buffer can be used between the host and the disk array. And large-capacity data transfer.

Further, by centrally managing the multi-level cache, it is possible to divert the current cache control micro without making a large change.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an outline of a configuration of a disk array system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a conventional disk array system in RAID technology.

FIG. 3 is a diagram illustrating a configuration of a data distribution control unit according to the present embodiment.

FIG. 4 is a diagram showing a timing of a buffer operation in a data distribution control unit at the time of writing in the embodiment;

FIG. 5 is a time chart of the operation of the data distribution control unit at the time of writing and the operation between a host or an internal upper fiber interface according to the embodiment;

FIG. 6 is a diagram illustrating a configuration between a data distribution control unit and a cache according to the present embodiment.

FIG. 7 is a cache management table S according to the embodiment;
FIG. 7 is a diagram illustrating storage of GCBs 0 and 1 and a segment in a cache.

FIG. 8 is a diagram showing a transfer list for upper-layer fiber drive transfer at the time of cache write according to the embodiment.

FIG. 9 is a diagram illustrating a transfer list for upper-layer fiber drive transfer at the time of cache read according to the embodiment;

FIG. 10 is a view showing a transfer list for host fiber drive transfer at the time of reading in the embodiment.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 Host fiber interface 101 Fiber cable 102-0-1 Upper fiber interface 103 Data distribution controller 104-0-1 Cache controller 105-0-1 Cache memory 106 HDD interface 107-0-3 HDD drive 108-0-1 Fiber Cables 109-0 to 1 Internal bus 110 Fiber cable 111 Internal cache bus 200 Host interface 201 Fiber / SCSI cable 202 Upper interface 203 Internal bus 204 MPU unit 205 Cache controller 206 Cache memory 207 HDD interface 208 Fiber / SCSI cable 209-0 HDD drive 301 Host fiber drive controller 302 Buffer bus switch 303 internal bus 304-0-3 data buffer 305-0-3 internal bus 306 buffer bus switch 307-0-1 host fiber drive control unit 601 host fiber drive control unit 602 buffer bus switch 603 internal bus 604 0-3 Data buffer 605 Buffer bus switch 606-7 Internal bus 608-0-1 Upper fiber drive 0, 1 controller 609 MPU unit 610-0-1, Upper fiber drive 0 ', 1' controller 611-0 1 Fiber cable 612-0-1 Cache controller and cache memory 613-0-1 Internal bus

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ikuya Yagisawa 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture F-term in Hitachi, Ltd. System Development Laboratory (Reference) 5B005 JJ12 MM12 NN12 5B065 BA01 CA30 CC08 CE12 CE14 CE26

Claims (8)

[Claims] A plurality of upper fiber interfaces for transmitting and receiving data from a host fiber interface;
A disk array system comprising: a cache memory connected to the plurality of higher-level fiber interfaces; a plurality of disk storage units for writing or reading data; and a disk drive interface for controlling the storage units. A disk array system comprising a cache memory corresponding to each upper fiber interface of a fiber interface. 2. The disk array system according to claim 1, wherein a data distribution control unit provided between the host fiber interface and the upper fiber interface includes a plurality of data buffers, , Managing the free space of the cache memory, storing data from the host fiber interface in the data buffer, or transferring buffer data of the data buffer to the cache memory. Disk array system. 3. The disk array system according to claim 2, wherein said data distribution control unit has a copy of a cache management table in a cache memory. 4. The disk array system according to claim 1, further comprising a communication bus for exchanging data and management information between cache memories provided corresponding to each of the upper fiber interfaces. Disk array system. 5. A plurality of upper fiber interfaces for transmitting and receiving data from a host fiber interface;
A disk array system comprising: a cache memory connected to the plurality of upper fiber interfaces; a plurality of disk storage units for writing or reading data; and a disk drive interface for controlling the storage units. A data distribution control unit is provided between the host fiber interface and the host fiber interface. The data distribution control unit divides the data from the host fiber interface into a plurality of data and supplies the data to the plurality of upper fiber interfaces. A disk array system wherein the divided data is simultaneously transferred to a plurality of cache memories in parallel via a fiber interface. 6. The disk array system according to claim 5, wherein the data distribution control unit includes a plurality of data buffers, the data distribution control unit manages a free space of the cache memory, and the host fiber A disk array system having a function of storing data from an interface in the data buffer or transferring buffer data of the data buffer to the cache memory. 7. The disk array system according to claim 5, wherein said data distribution control unit has a copy of a cache management table in a cache memory. 8. The disk array system according to claim 5, further comprising: a communication bus for exchanging data and management information between cache memories installed corresponding to the respective upper fiber interfaces. Disk array system.