JP2002118175A - Semiconductor device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fabricate a MISFET having a low threshold voltage by employing materials having optimal work functions in the metal gate electrode of a p-type MISFET and an n-type MISFET. SOLUTION: The gate electrode of an N type MIS transistor has a first metal film 616 touching a gate insulation film 615 and having a work function ϕf in the range of Vth+3.9<=ϕf<=Vth+4.1, where Vth is a threshold voltage. The gate electrode of a P type MIS transistor has a second metal film 617 touching the gate insulation film 615 and having a work function ϕf in the range of 5.1+Vth<=ϕf<=5.3+Vth, where Vth is the threshold voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an N-type MIS transistor and a P-type MI transistor.
The present invention relates to improvement of a gate electrode of an S transistor.

[0002]

2. Description of the Related Art In order to realize a low threshold value in a fine MISFET, an N-type MISFET, a P-type MISF
It has been practiced to use gate electrodes having different work functions for each ET. Conventionally, polycrystalline silicon has been used for the gate electrode, and N-type MISFET, P-type M
The doping of each polycrystalline silicon (gate electrode) of the ISFET is made n ⁺ and p ⁻ type, and the work function of each polycrystalline silicon is set to a conduction band.
And near the valence band (Valence Band),
A low threshold can be easily achieved.

However, a gate electrode made of polycrystalline silicon has an impurity concentration of 10 ^20, which is the solid solubility limit of conductive impurities.
Even if the doping is performed at a high concentration to the order of cm ⁻³ , the gate capacitance is reduced correspondingly because a depletion layer is formed on the gate electrode side. This becomes a serious problem particularly in the P-type MISFET. P doped with B (boron)
It is known that B diffuses from a ⁺ type polycrystalline silicon through a gate insulating film to a channel region by a thermal process.

[0004] Since restricted by this phenomenon, the p ⁺ -type polysilicon gate electrode can not be doped with B at a high concentration, reduction in the gate capacitance due to depletion of the gate is n ⁺ -type polycrystalline silicon -It is more serious than in the case of a gate electrode.

In order to prevent the gate electrode from being depleted, studies have been made to use a metal for the gate electrode. However, in general, in order to obtain the same effect as n ⁺ and p ⁺ polycrystalline silicon, a metal material having a work function about 0.56 eV above and below the center of the band gap of silicon,
It is very difficult to select a material that is compatible with the LSI process from the viewpoint of heat resistance, oxidation resistance, and the like.

Therefore, a method using one kind of metal having a work function located near the center of the band gap of the substrate is considered to be realistic. However, when a metal gate electrode whose work function is located at the center of the band gap of the substrate is used as described above, it is difficult to obtain a low threshold value. A low threshold value can be realized by doping the surface of the channel with an impurity of the opposite conductivity type (counter doping) and forming a buried channel. However, in the buried channel, a channel is not formed at the interface between the gate insulating film and the silicon substrate, but is formed at a position deep in the substrate from the interface. This means that the effective gate insulating film thickness has increased,
It is difficult to suppress the short channel effect,
There is a problem that the S-factor deteriorates.

[0007]

As described above, a low threshold value can be obtained by using a material whose work function is located at the center of the band gap of the substrate for the metal gate electrodes of the p-type MISFET and the n-type MISFET. There was a problem that it was difficult.

An object of the present invention is to provide a p-type MISFET and an n-type MISFET.
For the metal gate electrode of the MISFET, a material having an optimum work function is used, and a low threshold voltage MI
An object of the present invention is to provide a semiconductor device capable of forming an SFET and a method for manufacturing the same.

[0009]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object.

(1) The present invention (claim 1) provides an N-type MIS
A semiconductor device in which a transistor and a P-type MIS transistor are formed, wherein a gate electrode of the N-type MIS transistor is in contact with a gate insulating film and has a work function φ _f [e
V] is equal to V _th + 3.9 ≦ φ with respect to the threshold voltage V _th [V].
a first metal-containing film that satisfies _f ≦ V _th +4.1, a gate electrode of the P-type MIS transistor is in contact with the gate insulating film, and a work function φ _f [eV] is equal to the threshold voltage V _th [V], 5.1 + V _th ≦ φ _f ≦ 5.3 + V _th
Wherein the second metal-containing film is provided.

(2) The present invention (claim 2) provides an N-type MIS
A method of manufacturing a semiconductor device, wherein a gate electrode of each of a transistor and a P-type MIS transistor is formed in an opening formed in an insulating film on a semiconductor substrate via a gate insulating film, wherein the step of forming the gate electrode includes: N-type MI
First gate forming region for S transistor and P-type MI
The work function φ is formed on the gate insulating film formed in the openings of both regions of the second gate formation region for the S transistor.
_f [eV] is, with respect to the threshold voltage _{V th [V], V t} h +3.
A step of forming a first metal-containing film satisfying a condition of 9 ≦ φ _f ≦ V _th +4.1, a step of removing the first metal-containing film formed in the second gate formation region, On the first metal-containing film in the gate formation region and on the gate insulating film in the second gate formation region, the work function φ _f [eV] is 5.1 + V with respect to the threshold voltage V _th [V]. _th ≦ _{φ f} ≦ 5.
Forming a second metal-containing film satisfying the condition of 3 + V _th .

(3) The present invention (claim 3) provides an N-type MIS
A method for manufacturing a semiconductor device, wherein a gate electrode of each of a transistor and a P-type MIS transistor is formed in an opening formed in an insulating film on a silicon substrate via a gate insulating film, wherein the step of forming the gate electrode comprises: N type M
First gate forming region for IS transistor and P-type M
Forming a first metal-containing film on the gate insulating film formed in the openings of both of the second gate forming regions for the IS transistor; and forming at least one of the first and second gate forming regions. A predetermined process is performed on the first metal-containing film in one region, and the work function φ _{f of} the first metal-containing film is
[EV] with respect to the threshold voltage V _th [V], in the first gate formation region, V _th + 3.9 ≦ φ _f ≦ V _th +4.
And the condition of 5.1 + V _th ≦ φ _f ≦ 5.3 + V _th in the second gate formation region.

[Function] The present invention has the following functions and effects by the above configuration.

The gate electrode of the N-type MIS transistor is
A first metal-containing film which is in contact with the gate insulating film and has a work function φ _f of V _th + 3.9 ≦ φ _f ≦ V _th +4.1 eV with _respect to the threshold voltage V _th ; The gate electrode is in contact with the gate insulating film, and the work function φ _f is
With the provision of the second metal-containing film _satisfying 5.1 + V _th ≦ φ _f ≦ 5.3 + V _th , N-type and P-type MISFETs with low threshold voltages can be obtained. In addition, the N-type and P-type MISFETs can suppress a short channel effect and obtain a good MISFET having a low S-factor value.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] First, the present inventor performed a simulation for a MISFET in order to examine necessary conditions for a low threshold voltage MISFET using a metal gate electrode.

N-type MISFE used for simulation
The structure of T is shown in FIG. FIG. 1 is a schematic diagram illustrating a structure of a transistor used in the simulation.

In FIG. 1, reference numeral 100 denotes a silicon substrate, 1
01 is a source / drain, 102 is an extension region, 103 is a channel region, 104 is a counter doping region, 105 is a gate insulating film, 106 is a gate electrode, and 106 is a gate sidewall insulating film.

The parameters used in the simulation are shown below.

Gate length: L = 95 nm equivalent silicon oxide film thickness of gate insulating film: T _ox = 2.4
nm Gate sidewall insulating film thickness: 70 nm Junction depth: x _j = 35 nm Channel counter doping depth: Dc = 30 nm Average impurity concentration of channel: Np = 5 × 10 ¹⁸ cm ^-3 Gate voltage: Vd = 1.2 V For the N-type MISFET shown in FIG. 1, a simulation of transistor characteristics was performed by changing the work function of the gate electrode. Under the above-mentioned parameters, for the entire range of the work function φ _f = 4.2 to 4.7 eV of the gate electrode,
The channel counter-doped impurity concentration Nc was adjusted so that V _th = 0,395 V. φ _f = 4.6 eV is the band gap center.

FIG. 2 shows the relationship between the work function of the gate electrode and the concentration of the counter channel. In the vertical axis of FIG. 2 (counter channel concentration), the + side indicates that the channel surface is doped with p-type, and the − side indicates that the channel surface is doped with n-type. As the n-type impurity concentration on the channel surface increases, the channel structure operates more buried.

FIG. 3 shows the relationship between the gate length L and the threshold voltage _Vth (short channel effect) when the work function of the gate electrode is changed. It can be seen that the curves almost overlap in the region where the work function (WF) is 4.5 eV or less.

FIG. 4 shows a change amount dV _th of the threshold voltage V _th with respect to a change (± 5%) of the gate length L = 95 nm. It can be seen that dV _th rises sharply when the work function exceeds 4.5 eV, but shows almost the same value below that.

FIG. 5 shows V _g -I _d when the work function is changed.
Show characteristics. Here also, it is confirmed that the characteristics become almost the same when the work function becomes 4.5 eV or less.

FIG. 6 shows the S-factor for the work function.
Indicates the value of r. When the work function is 4.5 eV or more, S-fa
ctor rises sharply, and characteristic deterioration becomes remarkable,
At 4.5 eV or less, the S-factor shows a substantially constant value of about 80.

From these results, it can be seen that the threshold voltage V _th = 0.4
It is understood that, when a transistor having a V function is used, when the work function of the gate electrode is shifted from the center of the band gap by 0.1 eV in the direction of the conduction electron band, the same effect as that obtained by shifting the work function more than that can be obtained. Was. In order to realize a threshold value lower than 0.4 V, (0.
It has been found that the same effect can be obtained by shifting the band gap center to the conduction electron band side by the amount of 5-V _th ).

In order to investigate the reason, the potential of the channel when the work functions are different was examined. FIG.
The potential change in the substrate depth direction at the center of the channel when the work function is changed in steps of 0.1 eV between _f = 4.2 and 4.7 is shown. In FIG. 7, the vertical axis represents the potential, and the horizontal axis represents the substrate depth.

As shown in FIG. 7, Φ _f = 4.6, 4.7
At eV, the slope of the potential at the interface with the gate insulating film is-(downward) or almost zero. On the other hand, Φ
_It is + (upward) at _f ≦ 4.5 and has the characteristics of a typical surface channel. As a result, the short channel effect is suppressed, and the S-factor
r is considered to be improved.

Returning to FIG. 2, the channel concentration will be considered. In the vicinity of φ _f = 4.5 eV, not only the surface channel type operation is performed, but also the channel concentration is low. When the channel concentration is low, there is an advantage that the mobility of the channel is improved and leakage at the junction with the extension region is small. From this viewpoint, the work function of the gate electrode in contact with the gate insulating film is preferably closer to the center of the band gap of the silicon substrate than to the end of the conduction electron band.

It is generally considered that the channel concentration is desirably 1 × 10 ¹⁸ cm ⁻³ or less, and 4.3 eV
It is better to be located near the center of the band gap.

If the work function is set so as to satisfy the above-mentioned condition, for V _th = 0.4 V, 4.3 ≦ φ _f
≦ 4.5 eV is preferred. Also for other thresholds, the same effect can be obtained by setting the range of _{3.9 + V th ≦ φ f ≦} 4.1 + V th.

The P-type MISFET can be considered to be symmetrical to the N-type MISFET with respect to the center of the band gap of the silicon substrate, and 5.1 + V _th ≦ φ _f ≦ 5.3 + V
_th (V _th <0), a similar effect can be obtained.

When polycrystalline silicon is used for the gate electrode, it is necessary to shift the band gap center of the silicon substrate by 0.56 eV. However, as described above, by using a metal material electrode, when the threshold voltage is 0.4 V, it is found that a metal electrode material shifted from the center of the band gap of the silicon substrate by 0.1 eV may be used. Was.

To find a metal electrode material that is shifted from the center of the band gap of the silicon substrate by 0.1 eV is equivalent to 0.1.
It is easier than looking for a material that is shifted by 56 eV.

For example, metal materials shown in Table 1 may be used.

[0036]

[Table 1]

From the metal materials shown in Table 1, NMISF
A material having a small work function may be selected for ET, and a material having a large work function may be selected for PMISFET to form a gate electrode.

Next, a method of forming gate electrodes having different work functions on the same substrate will be described with reference to FIGS.
This will be described using (k). 8 to 11 are process cross-sectional views illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 8A, an element isolation insulating film 602 is formed on a silicon substrate 600 by using the STI technique.
Is formed, a p-well 601 is formed in a region where an NMISFET is formed, and an n-well 605 is formed in a region where a PMISFET is formed. Further, a thin silicon oxide film 603 is formed on the surface of the silicon substrate 600. Then, a dummy gate 604 made of polycrystalline silicon or the like is formed on the silicon oxide film 603 in a region where a gate electrode is to be formed later.

Next, as shown in FIG. 8B, after forming a silicon oxide film 606 and selectively forming a resist on the silicon oxide film 606 in the PMISFET region, the resist and the dummy gate 604 in the NMISFET region are formed. N-type extensions 607 are formed by performing ion implantation on the mask. Further, after a resist 608 is selectively formed on the silicon oxide film 606 in the NMISFET region, ion implantation is performed using the resist 608 and the dummy gate 604 in the PMISFET region as a mask to form a P-type extension 609. In addition,
The silicon oxide film 606 is for preventing the substrate from being contaminated by directly applying a resist to the silicon substrate 600.

Next, as shown in FIG. 8C, an insulating film such as a silicon nitride film is deposited on the surface of the silicon substrate 600, and a known sidewall leaving process is performed to form a gate sidewall insulating film 610.

Next, as shown in FIG.
After a resist is selectively formed on the silicon oxide film 606 in the SFET region, ion implantation is performed using the resist and the dummy gate 604 and the gate side wall insulating film 610 in the NMISFET region as a mask, so that the N-type source / drain 611 is formed. To form Further, after selectively forming a resist 612 on the silicon oxide film 606 in the NMISFET region, ion implantation is performed using the resist 612 and the dummy gate 604 and the gate sidewall insulating film 610 in the PMISFET region as a mask, thereby forming a P-type. A source / drain 613 is formed.

Next, as shown in FIG. 9E, an insulating film 614 made of a silicon oxide film or the like is deposited on the surface of the silicon substrate 600 so as to be thicker than the dummy gate 604.

Next, as shown in FIG.
Using a method or the like, the insulating film 614 is ground flat so that the top of the dummy gate 604 is exposed.

Next, as shown in FIG. 10G, the dummy gate 604 is removed by CDE (Chemical Dry Etching) or etching using a mixed solution of HF and HNO _3, and the exposed portion of the silicon oxide film 603 is further removed. Is removed.

Next, as shown in FIG. 10H, a gate insulating film 615 and a work function of 4.5 e are formed in the trench after the dummy gate 604 and the silicon oxide film 603 are removed.
A metal film 616 smaller than V is deposited. Gate insulating film 6
As 15, a film having a higher dielectric constant than a silicon oxide film such as a silicon oxynitride film, a silicon nitride film, or Ta ₂ O ₅ is preferable. Further, as the metal film 616,
Since it only determines the work function in the NMISFET region, an extremely thin film thickness, for example, 10 nm or less is sufficient.

Next, as shown in FIG.
The metal film 616 on the ISFET side is removed, and the metal film 616 is left only on the NMISFET side. This may be removed by wet etching or the like using a resist as a mask. For example, when W, Mo, TiN, or the like is used for the metal film 616, etching can be performed using an H ₂ O ₂ solution. The solution used for etching is not limited to this,
What is necessary is just to select suitably according to the kind of metal to be etched. As long as the gate insulating film 615 is not damaged, the etching may be performed by RIE or CDE.

Next, as shown in FIG. 11 (j), the second metal film 6 is formed as a metal having a work function larger than 4.7 eV.
17 is formed. This second metal film 617 is made of PMIS
The work function in the FET region is determined, and the resistance value of the gate electrode is determined. Therefore, it is desirable that not only the work function has an appropriate value but also the resistivity is low.

Next, as shown in FIG. 11 (k), the second metal film 617 is removed by a CMP method or the like so that at least the second metal film 617 is completely removed from the surface of the insulating film 614. Grinding. At this time, the gate insulating film 615 on the insulating film 614 may be removed or may be left as necessary.

In the above method, the metal films 615 and 617 are
The materials shown in Table 1 can be selected so that the threshold voltages of the NMISFET and the PMISFET are optimized.
From among the metal materials shown in Table 1, a material having a small work function may be selected for the NMISFET and a material having a large work function may be selected for the PMISFET to form the gate electrode.

A conductive metal compound such as TiN can also be used as a metal electrode, but it has been reported that the work function of about 0.12 to 0.14 eV differs depending on the crystal orientation ( Nakajima et al. 1999 Sym
posium on VLSI TechnologyDigest of Technical Paper
s p.96). By changing the film forming method and conditions, TiN having different work functions can be formed and used as two kinds of electrode materials.

Next, a method of changing the work function of one kind of metal after forming a film to obtain gate electrodes having two kinds of work functions will be described with reference to FIG. FIG. 12 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention. First, the gate insulating film 615 and the first metal film 616 are formed after the dummy gate is removed in exactly the same manner as described with reference to FIGS. 8A to 11K.

Next, as shown in FIG.
After forming a resist mask 710 in the ISFET region,
A third metal film 716 obtained by modifying the first metal film 616 is formed by ion-implanting a metal having a low melting point and a low work function such as In or Ga. The third metal film 716 includes 45
By performing a heat process at about 0 ° C., the third metal film 716 is formed.
A metal having a low work function precipitates at the interface with the gate insulating film 615 through the grain boundary, and a desired threshold value can be obtained.

Next, as shown in FIG.
A low-resistance second metal film 617 made of Al or the like is deposited, and the metal films 616, 716, and 61 are deposited on the insulating film 614 by using a CMP method or the like as shown in FIG.
7 is completely removed.

Although a metal having a lower work function than that of the first metal film 616 is injected into the NMISFET region here,
It is possible to inject a metal having a high work function into the PMISFET region, and it is also possible to inject a different metal into both regions as needed.

In the above example, an example of depositing a metal has been described. However, it is also possible to change the work function by ion-implanting an element such as N to form a compound having a different composition. Wakabayashi et al.,
IEDM Technology Digest p.253 (1999).

The present invention is not limited to the above embodiment, but can be implemented in various modifications without departing from the scope of the invention.

[0058]

As described above, according to the present invention, N
The gate electrode of the type MIS transistor, contact with the gate insulating film, the work function phi _f is, with respect to the threshold voltage V _th, V _th +
A first metal-containing film satisfying 3.9 ≦ φ _f ≦ V _th +4.1 eV, and the gate electrode of the P-type MIS transistor
In contact with the gate insulating film, the work function φ _f is 5.1 + V _th ≦
By providing a second metal-containing film _satisfying φ _f ≦ 5.3 + V _th , N-type and P-type
You can get ET. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a transistor structure used for a simulation.

FIG. 2 is a diagram of channel doping required to adjust the threshold to 0.4 V for various work functions.

FIG. 3 is a diagram illustrating a relationship between a gate length and a threshold for various work functions.

FIG. 4 is a diagram showing a threshold value change with respect to a 10% change in work function and L.

FIG. 5 is a diagram showing Vg-Id for various work functions.

FIG. 6 is a diagram showing a relationship between a work function and an S-factor.

FIG. 7 is a diagram showing the potential at the center of the channel for various work functions.

FIG. 8 is a diagram showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a diagram showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 11 is a view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 12 is a view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 silicon substrate 101 source / drain 102 extension region 103 channel region 104 counter doping region 105 gate insulating film 106 gate electrode 106 gate sidewall insulating film

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 4M104 AA01 BB02 BB16 BB18 BB30 BB39 CC05 DD03 DD04 DD26 DD64 DD75 DD81 EE03 EE16 EE17 FF13 GG09 GG10 HH16 HH20 5F048 AA00 AC03 BA01 BB09 BB10 BB11 BB12 BB11 DA03 BC03 DA30

Claims (3)

[Claims] 1. A semiconductor device in which an N-type MIS transistor and a P-type MIS transistor are formed, wherein a gate electrode of the N-type MIS transistor is in contact with a gate insulating film, and a work function φ _f [eV] is a threshold value. Voltage V
a first metal-containing film that satisfies V _th + 3.9 ≦ φ _f ≦ V _th +4.1 with _respect to _th [V]; a gate electrode of the P-type MIS transistor is in contact with the gate insulating film; The work function φ _f [eV] is 5.1 + V _th ≦ φ _f ≦ 5.3 + V with _respect to the threshold voltage V _th [V].
a semiconductor device comprising a second metal-containing film that is _th . 2. A method for manufacturing a semiconductor device, comprising forming a gate electrode of each of an N-type MIS transistor and a P-type MIS transistor in an opening formed in an insulating film on a semiconductor substrate via a gate insulating film. The step of forming the gate electrode includes: forming a gate insulating film on the gate insulating film formed in the opening of both the first gate forming region for the N-type MIS transistor and the second gate forming region for the P-type MIS transistor; The work function φ _f [eV] is higher than the threshold voltage V _th [V] by V
forming a satisfying first metal-containing film of _{th + 3.9 ≦ φ f ≦ V} th +4.1, and removing the first metal-containing film formed on the second gate forming region On the first metal-containing film in the first gate formation region;
Work function φ on the gate insulating film in the gate formation region of
_f [eV] is 5.1 with respect to the threshold voltage V _th [V].
Forming a second metal-containing film that satisfies the condition of + V _th ≦ φ _f ≦ 5.3 + V _th . 3. A method of manufacturing a semiconductor device, wherein a gate electrode of each of an N-type MIS transistor and a P-type MIS transistor is formed in an opening formed in an insulating film on a silicon substrate via a gate insulating film. The step of forming the gate electrode includes: forming a gate insulating film on the gate insulating film formed in the opening of both the first gate forming region for the N-type MIS transistor and the second gate forming region for the P-type MIS transistor; Forming a first metal-containing film; performing a predetermined process on the first metal-containing film in at least one of the first and second gate formation regions; The function φ _f [eV] is larger than the threshold voltage V _th [V] in the first gate formation region by V _th + 3.9 ≦ φ _f ≦
V _th +4.1, and in the second gate formation region, 5.1 + V _th ≦ φ _f ≦
A method of manufacturing a semiconductor device, wherein a condition of 5.3 + V _th is satisfied.