JP2002108298A - Digital signal processing circuit, its processing method, display device, liquid crystal display device and liquid crystal projector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that parts equivalent to a peak and a valley are viewed as lateral lines on a picture since the operation result of linear interpolation becomes a polygonal line when linear interpolation is performed on a vertical direction, and the inclination of the polygonal line becomes sharp when the correction quantity of color unevenness is large. SOLUTION: Correction data on luminance unevenness in a video, which is displayed on the picture, is stored in RAM 24 at every correction point obtained by dividing the picture in horizontal and vertical directions at prescribed intervals. Then, correction data on the whole display picture is generated in an interpolation operation by three-dimensional non-linear interpolation in the horizontal direction, the vertical direction and a gradation direction in an interpolation operation block 25. Generated correction data is added to digital data after various signals are processed by an adder/subtracter 35 and color unevenness is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal processing circuit and a processing method thereof, and a display device, a liquid crystal display device and a liquid crystal projector using the same.

[0002]

2. Description of the Related Art In recent years, in a display device, for example, a liquid crystal display (LCD), a digital signal processing (DSP) comprising a MOS process of a gate array as a signal processing system.
It is common to use an IC. Digital data that has been subjected to predetermined signal processing by the digital signal processing IC is converted into an analog signal by a D / A (digital / analog) converter, and then supplied to an LCD panel via an LCD driver.

In a liquid crystal display device and a liquid crystal projector, it is known that color unevenness occurs on a display screen due to a variation in manufacturing of an LCD panel and an optical system. In order to correct the color unevenness, conventionally, a color unevenness correction IC has been prepared separately from the digital signal processing IC. Then, a correction signal is generated in the color shading correction IC,
This correction signal is input to an LCD driver, and color unevenness is corrected by changing the brightness level of the video signal.

In the color shading correction IC, a correction signal for the entire screen is generated by interpolation using data set in a built-in RAM. The interpolation method in the color shading correction IC differs between the horizontal direction and the vertical direction. That is, in the horizontal direction, a low-pass filter (LP
F), and a smooth correction signal is created by this analog filter.

[0005]

On the other hand, in the vertical direction, an interpolation operation by linear interpolation is performed inside the IC. The calculation result is a polygonal line connecting the correction points with a straight line, as shown in FIG. However, when the correction amount of the color unevenness is large, since the slope of the broken line becomes steep, a large amount of change in the gradation level at a position corresponding to the peak and the valley of the broken line appears as horizontal streaks on the screen. I will.

Further, the conventional color shading correction IC does not have a function of performing interpolation calculation in the gradation direction. Therefore, if the appearance of color unevenness differs depending on the gradation level to be displayed, perfect interpolation cannot be performed. Here, the following can be considered as factors that cause the appearance of the color unevenness to differ depending on the gradation level to be displayed.

First, a factor relating to the LCD panel is that the V (applied voltage) -T (transmittance) characteristics of the liquid crystal vary. When the VT characteristics of the liquid crystal fluctuate due to manufacturing variations, as shown in FIG. 13A, the inclined portion of the VT curve is shifted by ΔV. However, in some cases, as shown in FIG. 13B, not only the shift but also the slope of the VT curve changes. At this time, the correction amount of the color unevenness changes depending on the gradation level to be displayed.

[0008] Another factor relating to the optical system is that the luminance varies in the screen. As a tendency, the brightness is highest at the center of the screen, and decreases as the position approaches the edge of the screen. Decreasing the luminance means that the gain of the displayed image is reduced. Therefore, also in this case, the correction amount of the color unevenness changes depending on the gradation level to be displayed.

Due to these factors, the appearance of color unevenness differs depending on the gradation level to be displayed. Therefore, as in the conventional color unevenness correction IC, simply correcting color unevenness at a specific gradation level is incomplete in obtaining a better display image. Although the above description has been made on the premise that a color liquid crystal display device is used, in the case of a monochrome liquid crystal display device, brightness unevenness occurs on a display screen due to variations in manufacturing LCD panels and optical systems.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to make it possible to reliably correct color unevenness (luminance unevenness) while suppressing occurrence of horizontal streaks on a screen. Digital signal processing circuit and its processing method,
Another object of the present invention is to provide a display device, a liquid crystal display device, and a liquid crystal projector using the same.

[0011]

A digital signal processing circuit according to the present invention converts an input analog video signal into an A / D signal.
A / D converter for (analog / digital) conversion,
A digital signal processing circuit arranged between the digital data after signal processing and a D / A converter for D / A converting the digital data.
Storage means for storing a screen for each correction point divided at regular intervals in the horizontal and vertical directions, and using the stored correction data to interpolate correction data between correction points by two-dimensional non-linear interpolation in the horizontal and vertical directions The configuration is provided with interpolation calculation means for generating correction data for the entire display screen by calculation and addition means for adding the generated correction data to the digital data. This digital signal processing circuit is used for a signal processing system in a display device such as a liquid crystal display device or a liquid crystal projector.

In the digital signal processing circuit having the above configuration or a display device using the same in a signal processing system, the storage means does not store the correction data for all the pixels of the display system but makes the screen horizontally and vertically. Correction data is stored for each correction point divided at regular intervals. Using these correction data, the interpolation calculation means obtains correction data for the entire display screen by interpolation calculation. At this time, a smooth correction curve is created by interpolation calculation using two-dimensional non-linear interpolation in the horizontal and vertical directions. By adding the correction data thus obtained to the digital data, color unevenness (brightness unevenness) is corrected while suppressing occurrence of horizontal streaks on the screen.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a system configuration example of a color liquid crystal display device according to the present invention.

As shown in FIG. 1, the present system
A / D converters 11R, 11G, 11B provided for (red) G (green) B (blue), PLL (Phase Locked)
Loop) circuit 12, digital signal driver (DSD)
IC13, D / A converters 14R-1, 14R-2,
14G-1, 14G-2, 14B-1, 14B-2, L
CD drivers 15R-1, 15R-2, 15G-1, 1
5G-2, 15B-1, 15B-2 and LCD panels 16R, 16G, 16B.

In this system, the digital input to the digital signal driver IC 13 is 8-bit parallel, the signal processing inside the digital signal driver IC 2 and the digital output thereof are 10-bit parallel, and the LCD drivers 15R-1, 15R-2, 15G- 1,15G-2,
It is assumed that the number of output CHs (channels) of 15B-1 and 15B-2 is 6, and the number of signal lines of the LCD panels 16R, 16G and 16B is 12. However, these numerical values are merely examples, and in particular, the number of signal lines between the LCD driver and the LCD panel, that is, the number of signal lines of the LCD panel is not limited to this.

A / D converters 11R, 11G, 11B
Are analog video signals Rin, Gin, Bin of R, G, B, respectively.
Are subjected to A / D conversion, and are output as digital data of a plurality of systems, for example, two systems. That is, as shown in FIG. 2, the digital data DATA synchronized with the master clock MCLK is demultiplexed into two-system digital data of port 1 and port 2 and output.
Here, in the A / D converters 11R, 11G, and 11B, the digital data DATA is demultiplexed into a plurality of systems, for example, two systems of digital data for the following reason.

That is, when considering a system having a high driving frequency, the A / D converters 11R, 11G, 11B
Can operate at high speed because it is usually formed by a bipolar process. However, the digital signal driver IC2 formed by a MOS process cannot operate if the driving frequency is too high, or noise can be reduced by unnecessary radiation caused by a high-frequency clock. Or increase. For this reason,
A / D conversion of input analog video signals Rin, Gin, Bin
When converting into digital data by the converters 11R, 11G, and 11B, the subsequent drive frequency is reduced by demultiplexing the data into a plurality of systems for each channel.

The PLL circuit 12 is provided with a horizontal synchronizing signal HS which is synchronously separated from an input analog video signal and applied.
A master clock MCLK, a horizontal synchronization signal HSYNC, and a vertical synchronization signal VSYNC used in the present system are generated based on the YNC and the vertical synchronization signal VSYNC,
This is given to the digital signal driver IC13.

The digital signal driver IC 13 includes:
Digital signal processing blocks 21R, 21G, 21B provided for R, G, B, serial I / F (interface) 22, timing generator (TG) 2
3. R as storage means for storing correction data to be described later
The circuit configuration has an AM 24 and an interpolation operation block 25. Digital signal processing block 21R, 21
Specific configurations of the G, 21B, the RAM 24, and the interpolation operation block 25 will be described later.

To the serial I / F 22, various information (coefficients) is given as serial data from a microcomputer (not shown) (not shown) that controls the entire system. And serial I / F22
Receives the serial data, controls the digital signal processing blocks 21R, 21G, and 21B, the RAM 24, and the interpolation calculation block 25, and controls the timing of the timing generator 23.

The timing generator 23 has a PLL
The master clock MCLK, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC generated by the circuit 12 are supplied. The timing generator 23 outputs the master clock MCLK and the synchronization signals HSYNC and VSYNC.
Various timing signals are generated based on C, and all timing control of the present system is performed.

D / A converters 14R-1, 14R-
2.14G-1, 14G-2, 14B-1, 14B-2
Is a digital signal processing block 21R-21G-21B of the digital signal driver IC13, which separately performs digital-to-analog conversion on each of R, G, and B digital data subjected to various types of signal processing, and performs an LCD driver 15R-1. , 15R
-2,15G-1,15G-2,15B-1,15B-
Feed to 2.

The LCD drivers 15R-1, 15R
-2,15G-1,15G-2,15B-1,15B-
2 is a D / A converter 14R-1, 14R-2, 14
Amplification processing, 1H (H is a horizontal scanning period) inversion processing, and sampling for each of two analog video signals of R, G, and B supplied from G-1, 14G-2, 14B-1, and 14B-2. After performing a / hold process and the like, the data is supplied to the LCD panels 16R, 16G, and 16B.

The LCD panels 16R, 16G, 16B are:
LCD panels 16R, 16G, 16B in which pixels (not shown) including liquid crystal cells are arranged in a matrix,
It is driven based on various timing pulses such as a vertical start pulse VST, a vertical display transfer pulse VCK, a horizontal start pulse HST, and a horizontal display transfer pulse HCK generated by the timing generator 23, and is driven in accordance with an input analog video signal. Perform image display.

Subsequently, the digital signal processing blocks 21R, 21G, 21B and the RAM 24, which are characteristic parts of the present invention, are provided.
A specific configuration of the interpolation operation block 25 will be described. Here, the digital signal processing blocks 21R, 2R
1G, 21B, RAM 24 and interpolation operation block 25
Is characterized by LC in addition to the original signal processing.
D panel 16R, 16G, 16B and optical system (not shown)
In that color unevenness that occurs on a display screen due to manufacturing variations is corrected by digital signal processing.

FIG. 3 shows a digital signal processing circuit (digital signal processing blocks 21R and 21R) according to an embodiment of the present invention.
1G, 21B, RAM 24 and interpolation operation block 2
It is a block diagram which shows the example of a structure of 5). Note that R, G,
Digital signal processing blocks 21R, 21 corresponding to B
Since G and 21B have exactly the same configuration, they will be commonly described as a digital signal processing block 21 in the following description.

The digital signal processing block 21 includes a user adjustment block 31 and a white balance adjustment block 3.
2, OSD (On Screen Display) MIX block 33,
A gamma correction block 34, an adder / subtractor 35, and a selector 36 are provided. Each of these processing blocks is provided in two systems corresponding to the digital data of port 1 and port 2.

In the digital signal processing block 21, the user adjustment block 31, the white balance adjustment block 32, the OSD MIX block 33, and the gamma correction block 34 perform normal image quality adjustment, that is, user adjustment, white balance adjustment, and OSD MIX (display screen). (A process of displaying another screen such as a menu screen) and signal processing such as gamma correction. Coefficients used in these signal processes are set through serial I / F 22 (see FIG. 1) by serial data input from an external microcomputer.

As will be described later in detail, the adders / subtractors 32-1 and 32-2 are used to perform three-dimensional color unevenness correction in the horizontal direction, the vertical direction, and the gradation direction. A process of adding or subtracting (adding) the correction data obtained by the interpolation operation block 35 to each digital data is performed.

Here, in order to prevent digital data added for color unevenness correction from being affected by various signal processing, various signal processing in the digital signal processing block 21, particularly, relating to color. It is important to add digital data to digital data after gamma correction processing is completed. The operation of the selector 36 will be described later in detail.

The RAM 24 has an LCD panel 16R, 1
Correction data for correcting color unevenness caused by 6G, 16B and manufacturing variations of the optical system is stored. Here, the correction data stored in the RAM 24 is not the correction data for all the pixels of the display system, but the correction data for the correction points (pixels) that divide the screen at fixed intervals in the horizontal and vertical directions.

FIG. 4 shows an example of setting correction data of correction points obtained by dividing the screen at regular intervals in the horizontal and vertical directions. Here, X of 1024 dots × 768 lines
The figure shows an example in which a video signal of the GA display standard is divided into nine points at 128 dot intervals in the horizontal direction and seven points at 128 line intervals in the vertical direction.

In this case, a total of 63 (= 9 ×
7) The correction data of the correction points are set in the RAM 24. Then, a plurality of the RAMs 24 are provided for each of the RGB colors, and color unevenness correction data of different gradation levels are set for each. Note that RA
Although the number of M24 is not particularly limited, in the following description, it is assumed that five M24s are provided for each color.

On the other hand, the interpolation operation block 25 is
4 is read out, and the correction data of the pixel between each correction point is interpolated,
Creates correction data for the entire display screen. The interpolation calculation block 25 performs three-dimensional interpolation calculation in the horizontal direction, the vertical direction, and the gradation direction, and calculates color unevenness correction data corresponding to the gradation level of the video signal displayed on the pixel to be corrected. Is performed.

The coefficients used in the calculation processing of the interpolation calculation block 25 are the same as those used in the signal processing in the user adjustment block 31, the white balance adjustment block 32, the OSD MIX block 33, and the gamma correction block 34. Is set through the serial I / F 22 (see FIG. 1) according to serial data input from the microcomputer.

By the way, the correction data stored in the RAM 24 is used as a correction data corresponding to each color unevenness, for example, when the color unevenness is adjusted in the production line, for example, the color unevenness of the above-mentioned 63 correction points is measured in advance. Is set. In setting the correction data, a cross hatch signal connecting the coordinates of the correction points is output from the interpolation calculation block 25 so that the position (coordinates) of the correction points on the screen can be easily determined. Then, this cross hatch signal is selected by the selector 36 and inserted into the video signal.

Hereinafter, the interpolation calculation in the interpolation calculation block 25 will be specifically described.

In the present embodiment, in order to perform three-dimensional interpolation calculations in the horizontal direction, the vertical direction, and the gradation direction, as shown in FIG. 000h, 100h, 200h, 300
Correction data for correcting color unevenness of each gradation of h and 3FFh is set in five RAMs 24 (see FIG. 3) of RAMs 1 to 5, respectively. Considering this in terms of the luminance level of the image displayed on the screen, the correction data of each luminance level of 0%, 25%, 50%, 75% and 100% is set.

The correction data set in the five RAMs 1 to 5 perform horizontal and vertical interpolation calculations for each data in each RAM. Then, an interpolation operation in the gradation direction is performed using the operation result, and finally, correction data corresponding to the gradation level of the video signal input to the pixel to be corrected is calculated.

At each gradation level, in order to generate correction data for the entire screen, correction data for 16 correction points in the vicinity of the pixel to be corrected is obtained.
The arithmetic processing is performed as an interpolation sample point. That is, in FIG. 4, when trying to obtain the correction data of the pixel (interpolation point) indicated by ◎, first, the correction data of the 16 sample points indicated by 印 are interpolated in the vertical direction. An operation is performed to obtain data of four points indicated by x marks.

Next, using these four points as sample points, an interpolation operation is performed in the horizontal direction on the obtained four data, and finally, correction data of the pixel (interpolation point) indicated by ◎ is obtained. The correction data calculated for each RAM is, as shown in FIG. 5, interpolated by an interpolation operation block 25 (see FIG. 3).
The gradation level of the video data input to (X in FIG. 5)
Look at the correction data at the four points near the mark (marked with a circle in FIG. 5).
), The interpolation calculation in the gradation direction is performed. Therefore, a total of 64 (= 16 × 4) data is used to obtain the correction data of each pixel.

Next, the algorithm of the interpolation calculation will be described. In the present embodiment, in any of the horizontal direction, the vertical direction, and the gradation direction, a 4-tap interpolation filter using four data, for example, an FIR (finite impulse response).
sponse: Performs non-linear interpolation calculation with a finite-length impulse response) filter.

In the interpolation calculation by the 4-tap interpolation filter, as shown in FIG. 6, four sample point data x (n-1), x (n), x (x) set in the RAM 24 are set. (n
+1) and x (n + 2), certain operation coefficients a ₋₁ , a ₀ , a ₁ ,
The data y (m) of the interpolation points indicated by ◎ are calculated by multiplying by a ₂ and adding them up.

When this is represented by a mathematical expression, the product-sum operation is represented by the following expression (1). _{y (m) = a -1 ×} x (n-1) + a 0 × x (n) + a 1 × x (n + 1) + a 2 × x (n + 2) (m = N × n) ...... ( 1) Here, as in the case of the example shown in FIG. 4, when the interval between the sample points is 128, an interpolation calculation of 128 times is performed, so that N = 128. Then, in equation (1),
The four operation coefficients a-1, a0, a1, and a2 correspond to the transfer function of the filter.

In this embodiment, the transfer function of the filter is C
A function called a ubic function is used. The Cubic function is defined by the following equation (2).

(Equation 1)

In the present embodiment, α =
Substituting -1

(Equation 2) Equation (3) is used for the actual interpolation operation.

The Cubic function when α = −1 is shown in FIG.
A curve as shown in FIG. That is, the sample point (（) and the interpolation point (◎) in the example of FIG.
When the relationship of distance t (0 ≦ t <1) with respect to FIG.
As shown in FIG. 7, four sample points exist on the curve of the Cubic function.

The Cubic at the location where these four sample points are located
Since the value of the function may be used as the operation coefficient of the filter, the expression can be expressed by the following expression (4).

(Equation 3)

In the actual calculation, when the interpolation is performed N times, the distance t is changed in 1 / N steps.
When the interval between correction points is 128 dots (lines) as in the example shown in FIG. 4, the distance t is 0/0 depending on the value of the distance between the sample point and the interpolation point, that is, the value of the number of pixels or the number of lines.
Becomes any value between 128 and 127/128,
Interpolation calculation is performed.

In this embodiment, not only the Cubic function but also Spline (third-order L
(aggregate) function. The Spline function is p-1, p0,
It is defined by the cubic expression of the following expression (5) that always passes through the four sampling points p1 and p2. p (t) = p0 + α × t + β × t ² + γ × t ³ (5)

Since the equation (5) passes through four sample points, the following equation (6) holds.

(Equation 4)

From equations (5) and (6), α, β, and γ are obtained and expanded into the form of equation (1).

(Equation 5) And the coefficient of the interpolation calculation is obtained.

Next, the Cubic function is used as a transfer function.
A specific configuration of the interpolation calculation block 25 when performing an interpolation calculation using a tap FIR filter will be described. FIG. 8 is a block diagram showing an example of a specific configuration of the interpolation operation block 25.

In FIG. 8, the interpolation calculation block 25 according to the present embodiment includes a horizontal synchronization signal HSYNC in order to perform correct interpolation on the pixel (interpolation point) to be corrected.
And a counter 41 that operates based on the vertical synchronization signal VSYNC. The count value of the counter 41 is supplied to the address decoder 42, the interpolation coefficient calculation block 43, and the cross hatch decoder 44, respectively.

The address decoder 42 outputs read addresses to, for example, five RAMs 24-1 to 24-5 provided corresponding to different gradation levels based on the count value of the counter 41. These RAM
24-1 to 24-5 correspond to the RAM 24 (RA
M1 to 5). RAM 24-1 to 2
The data read from 4-5 is data of 16 correction points (sample points) near the pixel to be corrected.

The interpolation coefficient calculation block 43 selects a transfer function to be used in the above-described interpolation operation, calculates the distance t between the sample point and the interpolation point from the count value of the counter 41, and calculates the value (the number of dots and the number of lines). ) To equation (4)
Alternatively, the necessary interpolation coefficient is calculated in the horizontal direction and the vertical direction by substituting into the coefficient t in the equation (7).

The cross hatch decoder 44 includes a counter 4
A cross hatch signal connecting the correction points from the count value of 1 is generated. The cross hatch signal generated by the cross hatch decoder 44 is selected by the selector 36 and inserted into the video signal in the digital signal processing block 21 shown in FIG. In this way, by installing the function of displaying the cross hatch connecting the color unevenness correction points (pixels), it is possible to easily determine the measurement point (pixel) of the color unevenness data at the time of adjusting the color unevenness on the production line. become.

The counter 41 and the address decoder 4
2. In the interpolation coefficient calculation block 43 and the cross hatch decoder 44, and further in the gradation direction interpolation coefficient calculation block 49, which will be described later, the serial I / F 22 (see FIG. Parameters such as points and correction intervals are set.

RA output from address decoder 42
The read addresses of M are stored in the five RAMs 24-1 to 24.
-5. Thereby, these RAMs 24-1
Data is read from the corresponding address of .about.24-5. The read data is input to the vertical interpolation calculation blocks 45-1 to 45-5. The operation coefficients calculated in the interpolation coefficient calculation block 43 are also input to these interpolation operation blocks 45-1 to 45-5.

The interpolation operation blocks 45-1 to 45-5 are:
Based on the data read from the RAMs 24-1 to 24-5 and the vertical operation coefficient calculated by the interpolation coefficient calculation block 43, a vertical interpolation operation is performed using Expression (1). The result of the vertical interpolation calculation is given to the horizontal interpolation calculation blocks 46-1 to 46-5. The operation coefficients calculated in the interpolation coefficient calculation block 43 are also input to these interpolation operation blocks 46-1 to 46-5. The interpolation calculation blocks 46-1 to 46-5 calculate the equation (1) based on the calculation results and data of the interpolation calculation blocks 45-1 to 45-5 and the horizontal calculation coefficients calculated by the interpolation coefficient calculation block 43. Is used to perform horizontal interpolation.

The interpolation operation blocks 45-1 to 45-5
Processing and interpolation calculation blocks 46-1 to 46-
By the calculation processing at 5, the calculation at each gradation level (five gradation levels in this example) is completed. The results of the five interpolation calculations at each gradation level are input to the selector 47. The selector 47 looks at the upper two bits of the digital data (video signal) input to the interpolation operation block 25 and selects four data to be used for the interpolation operation in the gradation direction. Give to 48.

On the other hand, the lower 8 bits of the digital data (video signal) are referred to in the interpolation coefficient calculation block 49 for the gradation direction. That is, the interpolation coefficient calculation block 48 treats the lower 8 bits of data as the distance t between the sample point and the interpolation point, selects a transfer function to be used for the interpolation operation in the gradation direction, and obtains the equation (4) or (7). The interpolation coefficient in the gradation direction is calculated using
Give to. The interpolation calculation block 48 in the gradation direction includes the data selected by the selector 47 and the interpolation coefficient calculation block 49.
Based on the interpolation coefficient calculated in step (1), the interpolation calculation in the gradation direction is performed using equation (1).

The interpolation calculation block 25 having the above-described structure calculates correction data corresponding to the gradation level of the video signal input to the pixel to be corrected by interpolation calculation using nonlinear interpolation in both the horizontal and vertical directions. be able to.

In particular, in the vertical direction, in the prior art in which the linear interpolation operation was performed, the operation result is shown in FIG.
However, the result of the calculation by the non-linear interpolation is a smooth curve as shown in FIG. Here, since the actual variation amount of the VT characteristic of the LCD panel changes linearly in the plane, it is better to correct the color unevenness with a smooth curve as shown in FIG.
A better correction result can be obtained.

As is clear from the above, in the above embodiment, the correction data of the entire display screen is calculated by the interpolation calculation using the three-dimensional non-linear interpolation in the horizontal direction, the vertical direction, and the gradation direction. It is not necessary to perform the three-dimensional interpolation operation, but may be an interpolation operation based on two-dimensional non-linear interpolation in the horizontal and vertical directions excluding the gradation direction.

That is, by performing an interpolation operation by nonlinear interpolation also in the vertical direction, as shown in FIG.
Since each correction point can be connected with a non-linear and smooth curve, it is possible to solve a problem that a horizontal streak appears on a line where a correction point exists on the screen, which has been a problem in the conventional linear interpolation. , Can be achieved.

In the case of the preferred embodiment in which the interpolation calculation is performed by three-dimensional nonlinear interpolation including the gradation direction, it is possible to perform the color unevenness correction for all gradations from the white level to the black level. In addition, it is possible to perform correction including the color unevenness caused by the optical system, which is one of the factors in which the appearance of the color unevenness differs depending on the gradation level to be displayed.

In the interpolation calculation block 25 of the example shown in FIG. 8, the interpolation processing in the interpolation coefficient calculation block 49 calculates the interpolation coefficient in the gradation direction based on the lower 8 bits of the video signal. , Interpolation calculation block 2
5 is not limited to this configuration.

That is, as shown in FIG. 10, instead of the interpolation coefficient calculation block 49, data storage means such as RA
M50 is provided, a preset interpolation coefficient is set in the RAM 50, an appropriate interpolation coefficient is read out from the RAM 50 based on the lower 8 bits of the video signal, and given to the interpolation calculation block 48 in the gradation direction. It is also possible to adopt a configuration. By adopting this configuration, the transfer function of the interpolation filter is changed to the Cubic function or the Spring function.
An arbitrary function (filter coefficient) can be set without being limited to the e-function.

In the above embodiment, the case where the present invention is applied to a color liquid crystal display device is described as an example. However, the present invention is not limited to the application to a color liquid crystal display device. In addition, color unevenness (brightness unevenness) caused by manufacturing variations of display devices and optical systems, such as a display device using a CRT (cathode ray tube) or an organic EL element as a display device, may be provided. The present invention can be applied to all display devices having a correction function.

[Application Example] Further, the digital signal processing block 21 (21R, 21G, 21B) according to the above embodiment.
Can be used as a digital signal processing circuit of a liquid crystal projector. FIG. 11 shows a schematic configuration of a liquid crystal projector.

In FIG. 11, the white light emitted from the light source 51 is transmitted through the first beam splitter 52 so that only a specific color component, for example, only the B (blue) light component having the shortest wavelength is transmitted, and the remaining colors are separated. Light components are reflected. The optical path of the B light component transmitted through the first beam splitter 52 is changed by a mirror 53 and passes through a lens 54 to the B LCD panel 11.
B is irradiated.

As for the light component reflected by the first beam splitter 52, for example, a G (green) light component is reflected by the second beam splitter 55, and an R (red) light component is transmitted. The G light component reflected by the second beam splitter 55 passes through the lens 56 to the G LCD panel 11G.
Is irradiated. The light component of R transmitted through the second beam splitter 55 has its optical path changed by mirrors 57 and 58 and is irradiated on the R LCD panel 11R through the lens 59.

The R, G, and B lights passing through the LCD panels 11 R, 11 G, and 11 B are combined by the cross prism 60. The combined light emitted from the cross prism 60 is projected on a screen 62 by a projection prism 61.

In the liquid crystal projector having the above structure, L
To the CD panels 11R, 11G, and 11B, for example, two-system video signals processed in parallel for each of R, G, and B by the signal processing system shown in FIG. 1 are input.

Here, by using the digital signal processing circuit according to the above-described embodiment as the digital signal processing blocks 21R, 21G and 21B of the digital signal driver 13, the LCD panels 11R, 11G and 11B are used.
And unevenness caused by manufacturing variations of optical systems (light source 51, beam splitters 52 and 55, mirrors 53, 57 and 58, lenses 54, 56 and 59, etc.) Since the correction can be made reliably while suppressing the occurrence, a better image display can be realized.

Although the present invention has been described with reference to a case where the present invention is applied to a color liquid crystal projector, the present invention can be similarly applied to a monochrome liquid crystal projector. In this case, it is needless to say that the signal processing system needs only one channel. Also, the LCD panels 11R, 11G,
The unevenness that occurs due to variations in the optical system 11B and the optical system appears as uneven brightness, and this uneven brightness can be corrected by the same principle.

[0078]

As described above, according to the present invention,
The correction data for the brightness unevenness of the image displayed on the screen is stored for each correction point dividing the screen at fixed intervals in the horizontal and vertical directions, and the correction data between the correction points is stored using the stored correction data. The correction data of the entire display screen is generated by an interpolation operation using two-dimensional non-linear interpolation in the horizontal and vertical directions and added to the digital data, so that the occurrence of horizontal streaks on the screen is suppressed while the color unevenness is suppressed. (Luminance unevenness) can be reliably corrected.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a system configuration example of a color liquid crystal display device according to the present invention.

FIG. 2 is a timing chart for explaining an operation of demultiplexing digital data of port 1 and port 2 by an A / D converter.

FIG. 3 is a block diagram illustrating a configuration example of a digital signal processing circuit according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining color unevenness correction in horizontal and vertical directions.

FIG. 5 is a diagram provided for describing color unevenness correction in a gradation direction.

FIG. 6 is a diagram for explaining the relationship between sample points and interpolation points;

FIG. 7 shows a Cubic function and a distance t between a sample point and an interpolation point.
FIG. 9 is a diagram provided for explaining the relationship with.

FIG. 8 is a block diagram illustrating an example of a configuration of an interpolation operation block.

FIG. 9 is a diagram showing a result of an interpolation operation by nonlinear interpolation.

FIG. 10 is a block diagram illustrating another example of the configuration of the interpolation operation block.

FIG. 11 is a schematic configuration diagram illustrating an example of a liquid crystal projector.

FIG. 12 is a diagram showing a result of an interpolation operation by nonlinear interpolation.

FIG. 13 is a diagram showing an example of variation in VT characteristics.

[Explanation of symbols]

11R, 11G, 11B A / D converter, 13 Digital signal driver, 14R-1, 14R-2, 1
4G-1, 14G-2, 14B-1, 14B-2 ... D /
A converter, 15R-1, 15R-2, 15G-1,
15G-2, 15B-1, 15B-2 ... LCD driver, 16R, 16G, 16B ... LCD panel, 21, 22
1R, 21G, 21B ... digital signal processing block, 2
2. Serial I / F, 23 Timing generator (TG), 24, 24-1 to 24-5 RAM, 25
Interpolation operation block, 35 ... Adder / subtractor, 36 ... Selector

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 680 G09G 3/20 680C H04N 5/16 H04N 5/16 B 5/66 102 5/66 102Z F term (reference) 2H093 NA06 NA53 NC13 NC14 NC24 NC27 NC28 NC65 NC68 ND05 ND09 NG02 NH18 5C006 AA22 AC21 AF03 AF04 AF51 AF52 AF53 AF78 BB11 BC13 BC16 BF02 FA22 5C021 PA80 PA85 PA86 XA01 XA34 XA67 5C06 BB EA06 AA10 BB05 CC03 DD05 EE29 EE30 FF09 GG12 JJ01 JJ02 JJ05 JJ06

Claims (54)

[Claims] 1. A digital signal processing circuit arranged between an A / D converter for A / D converting an input analog video signal and a D / A converter for D / A converting digital data after signal processing. Storage means for storing correction data for uneven brightness of an image displayed on a screen for each correction point obtained by dividing the screen at regular intervals in the horizontal and vertical directions; and correction data stored in the storage means. Interpolation means for generating correction data for the entire display screen by interpolation calculation using two-dimensional non-linear interpolation in the horizontal and vertical directions for the correction data between the correction points, and correction generated by the interpolation calculation means A digital signal processing circuit comprising: an adding unit that adds data to digital data. 2. The digital signal processing circuit according to claim 1, wherein said interpolation calculation means uses a 4-tap interpolation filter for interpolation calculation by nonlinear interpolation. 3. The transfer function of the interpolation filter is Cubi.
3. The digital signal processing circuit according to claim 2, wherein a c function is used. 4. A transfer function of the interpolation filter is Spri.
3. The digital signal processing circuit according to claim 2, wherein an n function is used. 5. The digital signal processing circuit according to claim 2, wherein said interpolation operation means has means for storing a filter coefficient for arbitrarily setting a transfer function of said interpolation filter. 6. The interpolation calculation means generates correction data for the entire display screen by performing an interpolation calculation by three-dimensional non-linear interpolation in which the gradation direction is added to the correction data between each correction point. The digital signal processing circuit according to claim 1. 7. The digital signal processing circuit according to claim 6, wherein said interpolation calculation means uses a 4-tap interpolation filter for interpolation calculation by nonlinear interpolation. 8. The transfer function of the interpolation filter is Cubi.
The digital signal processing circuit according to claim 7, wherein a c function is used. 9. The transfer function of the interpolation filter is Spri.
The digital signal processing circuit according to claim 7, wherein an n function is used. 10. The digital signal processing circuit according to claim 7, wherein said interpolation calculation means has means for storing a filter coefficient for arbitrarily setting a transfer function of said interpolation filter. 11. An input analog video signal is R
(Red) G (green) B (blue) color image signals, a plurality of storage means are provided for each of RGB colors,
2. The digital signal processing circuit according to claim 1, wherein correction data for each gradation level to be displayed is set in each storage means. 12. The digital-to-digital converter according to claim 1, wherein said adding means is an adder / subtracter for adding or subtracting correction data generated by said interpolation calculating means to digital data after signal processing. Signal processing circuit. 13. The digital signal processing circuit according to claim 1, further comprising means for inserting a crosshatch signal connecting the coordinates of a correction point to the video signal at a stage subsequent to said adding means. 14. An analog video signal input to an A / D converter
A digital signal processing method for performing signal processing between an A / D converter for converting and a D / A converter for D / A converting digital data after signal processing, the method comprising: The correction data is stored for each correction point in which the screen is divided at regular intervals in the horizontal and vertical directions, and the stored correction data is used to correct the correction data between the correction points in two-dimensional horizontal and vertical directions. A digital signal processing method, wherein correction data for the entire display screen is generated by interpolation by interpolation and added to digital data. 15. The method according to claim 14, wherein, when generating the correction data for the entire display screen, an interpolation operation is performed on the correction data between the correction points by three-dimensional non-linear interpolation in which the gradation direction is added. The digital signal processing method according to the above. 16. A display unit for displaying an image, an A / D converter for A / D converting an input analog video signal, and a predetermined signal processing for digital data output from the A / D converter. A display device comprising: a digital signal processing circuit for applying the digital signal processing circuit; and a D / A converter for D / A converting digital data output from the digital signal processing circuit and supplying the digital data to the display unit. A storage unit that stores correction data for uneven brightness of an image displayed on a screen for each correction point obtained by dividing the screen at regular intervals in the horizontal and vertical directions, and using correction data stored in the storage unit. Compensation for generating correction data for the entire display screen by interpolation calculation using two-dimensional non-linear interpolation in the horizontal and vertical directions for the correction data between the correction points. A display device comprising: an interpolating unit; and an adding unit that adds correction data generated by the interpolating unit to digital data. 17. The display device according to claim 16, wherein said interpolation calculation means uses a 4-tap interpolation filter for interpolation calculation by nonlinear interpolation. 18. A transfer function of the interpolation filter is Cub.
18. The display device according to claim 17, wherein an ic function is used. 19. A transfer function of the interpolation filter is Spr.
The display device according to claim 17, wherein an in function is used. 20. The display device according to claim 17, wherein said interpolation calculation means includes means for storing a filter coefficient for arbitrarily setting a transfer function of said interpolation filter. 21. An apparatus according to claim 21, wherein said interpolation calculation means generates correction data for the entire display screen by an interpolation calculation based on three-dimensional nonlinear interpolation in which the gradation direction is added to the correction data between each correction point. The display device according to claim 16. 22. The display device according to claim 21, wherein said interpolation calculation means uses a 4-tap interpolation filter for interpolation calculation by nonlinear interpolation. 23. The transfer function of the interpolation filter is Cub.
23. The display device according to claim 22, wherein an ic function is used. 24. The transfer function of the interpolation filter is Spr
23. The display device according to claim 22, wherein an in function is used. 25. The display device according to claim 22, wherein said interpolation calculating means has means for storing a filter coefficient for arbitrarily setting a transfer function of said interpolation filter. 26. An analog video signal to be input is R
(Red) G (green) B (blue) color image signals, a plurality of storage means are provided for each of RGB colors,
17. The display device according to claim 16, wherein correction data for each gradation level to be displayed is set in each storage unit. 27. The display according to claim 16, wherein said adding means is an adder / subtracter for adding or subtracting correction data generated by said interpolation operation means to digital data after signal processing. apparatus. 28. The display device according to claim 16, further comprising means for inserting a crosshatch signal connecting the coordinates of the correction point to the video signal at a stage subsequent to said adding means. 29. A display section in which liquid crystal cells are arranged in a matrix, and an analog video signal input to an A / D converter.
A / D converter for conversion, a digital signal processing circuit for performing predetermined signal processing on digital data output from the A / D converter, and D / A conversion of digital data output from the digital signal processing circuit And a D / A converter for supplying the data to the display unit. Storage means for storing each correction point divided at a constant interval, and interpolation by two-dimensional horizontal and vertical non-linear interpolation of correction data between correction points using the correction data stored in the storage means. Interpolation calculating means for generating correction data for the entire display screen by calculation; and digitally converting the correction data generated by the interpolation calculating means. A liquid crystal display device comprising: an adding unit that adds data to data. 30. The liquid crystal display device according to claim 29, wherein said interpolation calculation means uses a 4-tap interpolation filter for interpolation calculation by nonlinear interpolation. 31. The transfer function of the interpolation filter is Cub
31. The liquid crystal display device according to claim 30, wherein an ic function is used. 32. The transfer function of the interpolation filter is Spr
31. The liquid crystal display device according to claim 30, wherein an in function is used. 33. The liquid crystal display device according to claim 30, wherein said interpolation calculation means has means for storing a filter coefficient for arbitrarily setting a transfer function of said interpolation filter. 34. The interpolation calculating means generates correction data for the entire display screen by performing an interpolation calculation by three-dimensional non-linear interpolation by adding a gradation direction to correction data between correction points. A liquid crystal display device according to claim 29. 35. The liquid crystal display device according to claim 34, wherein said interpolation calculation means uses a 4-tap interpolation filter for interpolation calculation by nonlinear interpolation. 36. The transfer function of the interpolation filter is Cub.
The liquid crystal display device according to claim 35, wherein an ic function is used. 37. The transfer function of the interpolation filter is Spr
The liquid crystal display device according to claim 35, wherein an in function is used. 38. The liquid crystal display device according to claim 35, wherein said interpolation operation means has means for storing a filter coefficient for arbitrarily setting a transfer function of said interpolation filter. 39. An input analog video signal is R
(Red) G (green) B (blue) color image signals, a plurality of storage means are provided for each of RGB colors,
30. The liquid crystal display device according to claim 29, wherein correction data for each gradation level to be displayed is set in each storage means. 40. A liquid crystal display according to claim 29, wherein said adding means is an adder / subtracter for adding or subtracting correction data generated by said interpolation operation means to digital data after signal processing. Display device. 41. The liquid crystal display device according to claim 29, further comprising means for inserting a crosshatch signal connecting the coordinates of the correction point to the video signal at a stage subsequent to said adding means. 42. An LCD panel in which liquid crystal cells are arranged in a matrix, irradiation means for irradiating the LCD panel with light, and projection means for projecting the light passing through the LCD panel onto a screen. An A / D converter for A / D converting an analog video signal, a digital signal processing circuit for performing predetermined signal processing on digital data output from the A / D converter, and an output from the digital signal processing circuit A liquid crystal projector comprising: a digital-to-analog (D / A) converter that converts digital data into digital data and supplies the digital data to the LCD panel; Storage means for storing a screen for each correction point divided at regular intervals in the horizontal and vertical directions, and stored in the storage means Interpolation calculation means for generating correction data for the entire display screen by interpolation calculation using two-dimensional non-linear interpolation in the horizontal and vertical directions for correction data between correction points using the correction data; A liquid crystal projector comprising: an adding unit that adds corrected data to digital data. 43. The liquid crystal projector according to claim 42, wherein said interpolation calculation means uses a 4-tap interpolation filter for interpolation calculation by nonlinear interpolation. 44. The transfer function of the interpolation filter is Cub
The liquid crystal projector according to claim 43, wherein an ic function is used. 45. The transfer function of the interpolation filter is Spr
The liquid crystal projector according to claim 43, wherein an in function is used. 46. The liquid crystal projector according to claim 43, wherein said interpolation calculation means has means for storing a filter coefficient for arbitrarily setting a transfer function of said interpolation filter. 47. The interpolation calculating means generates correction data for the entire display screen by performing an interpolation calculation by three-dimensional non-linear interpolation by adding a gradation direction to the correction data between each correction point. The liquid crystal projector according to claim 42. 48. The liquid crystal projector according to claim 47, wherein said interpolation calculation means uses a 4-tap interpolation filter for interpolation calculation by nonlinear interpolation. 49. The transfer function of the interpolation filter
49. The liquid crystal projector according to claim 48, wherein an ic function is used. 50. The transfer function of the interpolation filter is Spr
49. The liquid crystal projector according to claim 48, wherein an in function is used. 51. The liquid crystal projector according to claim 48, wherein said interpolation calculation means has means for storing a filter coefficient for arbitrarily setting a transfer function of said interpolation filter. 52. An analog video signal inputted is R
When the image signal is a (red) G (green) B (blue) color video signal, a plurality of storage means are provided for each color of RGB, and correction data for each gradation level to be displayed is set in each storage means. 43. The liquid crystal projector according to claim 42, wherein: 53. The liquid crystal device according to claim 42, wherein said adding means is an adder / subtractor for adding or subtracting the correction data generated by said interpolation operation means to or from the digital data after signal processing. projector. 54. The liquid crystal projector according to claim 42, further comprising means for inserting a crosshatch signal connecting the coordinates of the correction point to the video signal at a stage subsequent to said adding means.