JP2002094953A - Method fna device for transmitting receiving data superimposed on video signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmitter-receiver for data superimposed on a video signal that eliminates the need for a phase locked loop and a specific high frequency clock signal phase-locked to a integer multiple of a horizontal scanning period, has a simple configuration and is surely in operation without any adjustment and to provide its method. SOLUTION: After waveform shaping of a synchronizing signal 102 obtained by applying clamping and synchronizing separation to a video signal by a retriggerable MB(multivibrator) circuit A4 and a retriggerable MB circuit B5, an edge pulse 106 is generated and a PS shift register circuit 11 captures superimposed data 10. A gate circuit 12 receiving a gate pulse 107 gates a signal 108 resulting from waveform shaping by an MB circuit A13 to generate a shift pulse 109. The shift pulse 109 allows the PS shift register circuit 11 to make its shift operation and a data superimposing circuit A15 utilized the shift pulse 109 as its superimposing control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to vertical retrace of a video signal, for example, by superimposing and multiplexing various sensor signal data on an image captured by a surveillance camera, or superimposing an illegal copy prevention signal or a falsification prevention signal on a video signal. Erasing period (Vertica)
The present invention relates to an apparatus and a method for superimposing and multiplexing digital data during a plurality of predetermined horizontal scanning periods in a (l Blanking Interval: VBI), and an apparatus and method for detecting data from a video signal on which digital data is superimposed and multiplexed.

[0002]

2. Description of the Related Art As shown in examples of a teletext receiver disclosed in JP-A-59-153389 and a closed-circuit television (CCTV) system disclosed in JP-A-3-114387, a vertical signal of a video signal is obtained. Blanking period (VBI)
A technique for superimposing and multiplexing digital data during a predetermined horizontal scanning period within the device is known.

A more specific example is disclosed in Japanese Patent Application Laid-Open
275127, JP-A-2000-152196, JP-A-10-79925, JP-A-2000-6
No. 9458, Japanese Unexamined Patent Application Publication No. Hei 11-203578, etc., all of which focus on the invention in a method of using superimposed multiplexed data, and a predetermined method within a vertical blanking period (VBI) of a video signal is used. No detailed circuit means is described on how to superimpose and multiplex digital data during the horizontal scanning period and how to detect superimposed and multiplexed digital data.

[0004] Japanese Patent Laid-Open Nos. 2000-13784 and 10-164567 have a counter which counts a synchronizing signal from a synchronizing section of a camera, although there is a part lacking in detailed technical clarity. A signal is output at a timing of a required horizontal scanning period in the vertical blanking period, and the sensor signal and the ID are synthesized and superimposed on the video signal. A blanking signal is generated from a synchronization signal separated from the video signal, and the blanking period is generated. A configuration of a mixer that extracts only a data signal and mixes a data signal derived from a gate circuit with a video signal is described.

A conventional example will be described with reference to the drawings. FIG. 8 is a block diagram of a conventional apparatus for transmitting data by superimposing data on a video signal.
Is a data transmission timing chart of a conventional example.

In FIG. 8, a video signal source A1 is a camera or other video signal output device, and a video signal
Reference numeral 12 indicates that the video signal source A1 includes a circuit portion as a composite video signal in which a chrominance signal, a luminance signal, a burst signal, a vertical synchronization signal, a horizontal synchronization signal, and the like are mixed. Since the video signal source A1 and the clamp circuit 2 are AC-coupled for
Although not shown in the figure, the composite video signal has lost the DC component.

The video signal 112 is passed through the clamp circuit 2 so that the DC component is reproduced and the clamped video signal 1
01 is obtained. For example, the waveform near the vertical blanking period at the end of the even-numbered field is as shown in FIG. 9A.

In FIG. 9, P24 represents the last horizontal scanning video in the even field, P11 represents the first horizontal scanning video in the odd field, tH represents one horizontal scanning period, and time TPF2.
From time TV1 to time TP is a vertical synchronization period consisting of a vertical synchronization signal and an equivalent pulse.
The period tBL1 up to S1 is a period during which the contents are not normally displayed on a video display such as a cathode ray tube or a liquid crystal monitor even if data and test signals are superimposed during this period.

The video signal 101 after clamping shown in FIG. 8 is passed through the sync separation circuit 3 to remove the video signal component to obtain a sync signal 102, whose waveform is shown in FIG. 9B.

The vertical synchronizing signal 131 is generated from the synchronizing signal 102 by the vertical synchronizing separation circuit 31 and is derived to the timing generating circuit 38.
The waveform 31 is shown in FIG.

Further, the synchronization signal 102 is connected to a phase comparator 32, where the phase comparator 32 and the LPF circuit 3
3. A phase-locked loop (PLL) composed of a VCO 34 (voltage-controlled oscillator) and a frequency divider A35 is formed, and a horizontal synchronization signal 132 output from the frequency divider A35 is a synchronization signal as shown in FIG. The pulse waveform is phase-locked to 102. Here, the free-running frequency of the VCO 34 is finely adjusted by the adjusting means 37 of FIG. 8 to ensure that the phase-locked loop is phase-synchronized with the synchronization signal 102. The typical adjusting means 37 is a semi-fixed resistor or a trimmer capacitor added to the VCO 34.

In order to superimpose data, it is necessary to generate data superimposition and data fetch timing. In order to generate these timing signals in a digital circuit, generally, an integral multiple of the horizontal scanning period of the synchronization signal 102 is used. In the example shown in FIG. 8, the output signal of the VCO 34 is used as a clock signal 138 via a frequency divider B36 to generate a clock signal 138.
Is derived.

The timing generation circuit 38 can know the absolute time relationship from the vertical synchronizing signal 131, the horizontal synchronizing signal 132, and the clock signal 138. Signal 133, data read timing signal 13
5. The superimposition data 39 can be read and the memory circuit 40 can be controlled by signals such as a memory read / write control signal 136 and a memory address control signal 137.

Data to be superimposed, ie, memory circuit 40
Is converted to a video level to be superimposed by the level conversion circuit 41, and the data is superimposed by the data superimposition circuit B42 at the timing of the data superimposition timing signal 133 as shown in FIG. Da, Db, Dc, Dd, De, Df, shown in FIG.
Dg is obtained in the form of, and the value of the data is 1 (or H)
Whether it is 0 (or L) can be determined based on the video luminance level of the superimposed data.

Although not shown here, in the case of such a conventional example, the data amount that can be superimposed in one horizontal scanning period, that is, the number of bits of each of Da, Db, Dc, Dd, De, Df, and Dg is determined by JEOL. Industry Association (EIAJ) Standard "VBI
As shown in “Video signal transmission method using CPR-1204”, about 20 bits can be superimposed, and in the case of the example shown in FIG. Superimposed transmission is possible.

As described above, in the data superimposition on the conventional video signal, the synchronizing signal is separated from the video signal to form a phase-locked loop for performing phase synchronization to an integral multiple of the horizontal synchronizing signal. Since it is possible to superimpose 20-bit data, the amount of data to be superimposed and transmitted can be secured, and if phase synchronization is established, stable operation is possible. For example, the vertical blanking period (VBI) ) Is applied to various fields such as text multiplex broadcasting and data broadcasting.

[0017]

However, the prior art has the following disadvantages. That is, as a first point, the conventional example is optimal when superimposing a considerable amount of data as in the case of teletext broadcasting. However, for example, data superimposition of about several bits is sufficient as in sensor information transmission of a surveillance camera. In addition, in the case of small-volume production, the provision of a new timing generation circuit and memory circuit as shown in the conventional example is complicated and the circuit scale is large, so that the price increase associated with data superimposition cannot be ignored.

Second, since it is necessary to generate a specific high-frequency clock signal for synchronizing the phase with the synchronizing signal, a phase-locked loop is formed and a VCO is provided. Therefore, the specific high-frequency clock signal, the VCO signal, and the VCO divided signal are generated. The point is that leaks such as these may interfere with the video signal.

As a third point, in order to establish accurate and stable phase synchronization, the VCO needs to be finely adjusted by some kind of adjusting means. There is also a risk of quality deterioration due to the above.

A fourth point is that when a video signal on which data is superimposed is transmitted through a transmission path such as a coaxial cable or a radio wave, the receiving side for detecting the superimposed data is also provided with a complicated timing generation circuit as shown in the conventional example. In addition, it is necessary to provide a memory circuit and the like, and the price increase cannot be ignored.

In view of the above-described disadvantages, the object of the present invention is to eliminate the need for a phase-locked loop or a specific high-frequency clock signal phase-locked to an integral multiple of the horizontal scanning period, and to ensure a simple, unadjusted configuration. An object of the present invention is to provide an inexpensive method and apparatus for transmitting and receiving data superimposed on an operating video signal.

[0022]

The present invention employs the following characteristic constitution means in order to solve the above-mentioned problems. That is,
A first feature of the present invention is that a synchronization signal obtained by clamping and separating a video signal is waveform-shaped by a first retrigger type monostable multivibrator circuit and a second retrigger type monostable multivibrator circuit, An edge pulse is generated by detecting an edge of the waveform shaping signal with a delay caused by a synchronization signal, and the set of a set / reset flip-flop circuit and the output signal of the first retrigger type monostable multivibrator circuit are counted by the edge pulse. And resetting the set-reset flip-flop circuit at a predetermined count value by taking the parallel superimposed data into a parallel / serial shift register to which the parallel superimposed data is input. The reset signal so that the reset signal A gate signal which is an output signal of the set / reset flip-flop circuit, and further outputs the first retrigger type monostable multivibrator circuit output signal by the gate signal. A shift pulse, which is an output of the gate circuit, is generated by controlling a gate circuit to which a signal whose waveform has been shaped by a monostable multivibrator is input, and the shift pulse causes the parallel / serial shift register circuit to perform a shift operation. By generating a specific high-frequency clock signal to be phase-synchronized with a synchronization signal, the pulse is also used as a superimposition control signal of a data superimposition circuit that superimposes the level of an output signal of the parallel-serial shift register circuit on a post-clamp video signal after the conversion. Cameras or screens characterized by no need for Vertical blanking period of the video output signal outputted from such an output device (VBI)
And a data superimposing transmission method for superimposing digital data in a predetermined plurality of horizontal scanning periods to obtain a data superimposed video signal.

A second feature of the present invention is that a synchronizing signal obtained by clamping and separating a video signal is waveform-converted by a first retrigger type monostable multivibrator circuit and a second retrigger type monostable multivibrator circuit. By shaping and detecting the edge of this waveform shaping signal with the delay due to the synchronization signal,
An edge pulse is generated, and the set of the set / reset flip-flop circuit and the first
The reset value of the counter circuit that counts the output signal of the retrigger type monostable multivibrator circuit of
The counter circuit is configured to output a reset signal to the set / reset flip-flop circuit so as to reset the set / reset flip-flop circuit at a predetermined count time, thereby providing an output signal of the set / reset flip-flop circuit. Generate a gate signal,
The gate signal is used to control a gate circuit to which a signal obtained by shaping the waveform of the first retrigger type monostable multivibrator circuit output signal with a second monostable multivibrator is input, thereby shifting the gate circuit output. A pulse is generated, and the serial-parallel shift register circuit to which the post-clamped video signal after the level conversion is input is shifted by the shift pulse, and the serial-parallel shift register circuit output signal is latched at the end of the gate signal. With such a configuration, it is not necessary to generate a specific high-frequency clock signal for synchronizing the phase with the synchronization signal. A predetermined plurality of horizontal lines within a vertical blanking period (VBI) of a video signal such as a camera or a video output device are not required. Data superimposition to detect digital data superimposed during the scanning period and obtain parallel detection data A signal method and apparatus.

According to a third feature of the present invention, an edge pulse is generated by detecting an edge of a vertical synchronizing signal output from a video signal source with a delay caused by a horizontal synchronizing signal output from the video signal source. The set of the set / reset flip-flop circuit according to the first aspect and the count value reset of a counter circuit that counts the horizontal synchronization signal are performed by a pulse, and the counter circuit that counts the horizontal synchronization signal is reset at a predetermined count value time by the counter circuit. A reset signal is output to the set / reset flip-flop circuit so as to reset the set / reset flip-flop circuit, and the horizontal synchronizing signal is output by a third monostable multivibrator circuit and a fourth multivibrator circuit. Inputting the shaped signal to the gate circuit according to the first aspect; By forming was characterized by a specific high-frequency clock signal generator for phase synchronization with the synchronizing signal is not required, the data superimposing transmission method according to the first aspect.

According to a fourth feature of the present invention, the edge pulse described in the first feature is shaped by a fifth multivibrator circuit to generate a signal equivalent to the gate signal described in the first feature. The data superimposed transmission method according to the first aspect, characterized in that it is not necessary to generate a specific high-frequency clock signal for synchronizing the phase with the synchronization signal.

According to a fifth feature of the present invention, the edge pulse described in the second feature is shaped by a fifth multivibrator circuit to generate a signal equivalent to the gate signal described in the second feature. The data superimposition receiving method according to the second aspect is characterized in that the configuration does not require generation of a specific high-frequency clock signal for synchronizing the phase with the synchronization signal.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of a device for superimposing data on a video signal according to the present invention, FIG. 2 is a block diagram of a first embodiment of a device for superimposing data on a video signal of the present invention, and FIG. 3 is a video signal of the present invention. FIG. 4 is a partial block diagram of a third embodiment of a device for superimposing and transmitting data to a video signal according to the present invention, and FIG. 5 is a first data transmission timing diagram of the present invention. 6 is a second data transmission timing chart of the present invention, and FIG. 7 is a data reception timing chart of the present invention.

In FIG. 1, a video signal source A1 is a camera or other video signal output device, and a video signal
Reference numeral 12 denotes a composite video signal in which a chrominance signal, a luminance signal, a burst signal, a vertical synchronization signal, a horizontal synchronization signal, and the like are mixed, and although not shown, the video signal 112 is a composite video signal in which a DC component has been lost. Is the same as in the conventional example.

The video signal 112 is passed through the clamp circuit 2 shown in FIG. 1 so that a DC component is reproduced to obtain a clamped video signal 101. The waveform is not shown in FIGS. This is the same as FIG. 9A of the example.

The clamped video signal 101 is passed through the sync separation circuit 3 so that the video signal component is removed to obtain a sync signal 102, as in the prior art. However, as an example, the vertical retrace at the end of the odd field is performed. The waveform near the erase period is shown in FIG. 5A, and the waveform near the vertical blanking period at the end of the even field is shown in FIG. 6A. The operation of the present invention will be described with reference to FIG.

In FIG. 5, P14 represents the last horizontal scanning video in the odd field, P21 represents the first horizontal scanning video in the even field, tH is one horizontal scanning period, and time TPF1.
Is a vertical synchronization period including a vertical synchronization signal and an equivalent pulse, and a period tV2 from time TV2 to time TP.
The period tBL2 up to S2 is a period in which even if data and test signals are superimposed during this period, the contents are not normally displayed on a video display such as a CRT or a liquid crystal monitor.

Next, due to the fall of the synchronization signal 102, the cycle until the retrigger is shorter than one horizontal scanning period tH and longer than one half cycle tH as shown in FIG.
By driving the retrigger-type MB circuit A4 (retriggerable monostable multivibrator) set to 1, a first waveform-shaped synchronization signal 103, which is the output of the retrigger-type MB circuit A4, is obtained. As shown in FIG. 5B, a pulse wave whose level is at an H level during a vertical synchronization period and whose level is inverted in a horizontal scanning period during other periods is a pulse wave.

Further, when the first waveform-shaped synchronizing signal 103 rises, the re-triggering period is set to a time t2 longer than one horizontal scanning period tH and shorter than two periods tH as shown in FIG. By driving the type MB circuit B5 (re-trigger type monostable multivibrator), a second post-waveform-shaped synchronization signal 104 which is the output of the re-trigger type MB circuit B5 is obtained, and this waveform is shown in FIG. Shown in

The second waveform-shaped synchronization signal 104 is
A delay signal 105 is obtained by the delay circuit 6 configured to output an inverted signal after being delayed at the rising edge of the synchronization signal 102, and this waveform is shown in FIG.

Then, the second waveform-shaped synchronization signal 104
And logical operation of the delay signal 105 (in this embodiment, NAN
The edge pulse 1 is output by the edge detection circuit 7 that performs D).
06, the waveform of the edge pulse 106 is shown in FIG.
As shown in (E), the second post-waveform-shaped synchronization signal 104
Is a very short pulse signal which becomes L level only during one horizontal synchronizing signal period in synchronization with the rising edge of TS1.

With this edge pulse 106, the RSFF
When the circuit 8 (set / reset flip-flop circuit) is set, the gate signal 1 which is the output of the RSFF circuit 8 is output.
At 07, the H level is set at time TS1, and FIG. 5F shows the state of this waveform.

The edge pulse 106 is also connected to the reset terminal of the counter circuit 9, whereby the count value of the counter circuit 9 is reset to zero at the time TS1. FIG. 5 (G) schematically shows this.

Further, the edge pulse 106 is also connected to the load terminal of the PS shift register circuit 11 (parallel serial shift register circuit), and the superimposed data 10 is similarly transmitted via the parallel superimposed data 111 which is a data connection line. At time TS1, superimposed data 10 is stored in PS shift register circuit 11.
Captured inside.

Next, the counter circuit 9 advances the counting at the rising edge of the first waveform-shaped synchronization signal 103 as shown in FIG. 5 (G). For example, if the counter circuit 9 is a binary counter, The third power flag, ie, 8 in decimal
Since the signal which changes from the H level to the L level at the point of time, that is, the reset pulse 113 of FIG. 5 (H) is connected to the RSFF circuit 8, as shown in FIG.
The FF circuit 8 is reset, and as a result, the gate signal 107 is reset to the L level at the time TR1 as shown in FIG.

The first synchronized signal 103 after waveform shaping drives the MB circuit A13 (monostable multivibrator circuit) at its fall, and the trigger period of the MB circuit A13 is shown in FIG. The period t3 for masking the horizontal synchronizing signal is set as described above, so that the MB circuit A1
The third synchronized signal 108 after waveform shaping, which is the output of the third waveform shaping circuit 3, is shown in FIG.
As shown in (I), all the synchronization signals 102 except for the period of tV2 become pulse waves that are at the L level during the L level.

Then, the third waveform-shaped synchronization signal 108
Is connected to the gate circuit 12, and a gate signal 10 which is an output of the RSFF circuit 8 as a gate signal of the gate circuit 12.
7 is connected, the shift pulse 109, which is the output of the gate circuit 12, is output at time TS as shown in FIG.
From the L level to the H level only eight times during the period from 1 to the time TR1
An intermittent shift pulse rising to the level can be obtained.

Further, the PS shift register circuit 11 is sequentially shifted eight times by the shift pulse 109, and at the same time, the shift pulse 109 is used as a superimposition control signal of a data superimposition circuit A15 to which data passed through the level conversion circuit A14 is input. It is constituted so that.

As a result, as shown in FIG.
In the period of g, tf, te, td, tc, tb, ta, ts, data D1, D2, D3, D4, D5, D6,
Although it is possible to superimpose 8-bit data of D7 and D8, it is determined whether the data value is 1 (or H) or 0 (or L) based on the video luminance level of the superimposed data as in the conventional example. Repeats the same operation cyclically for each field.

The television video signal system (NTSC system) in Japan employs an interlace (interlaced scanning) system. At the end of an odd field and at the end of an even field, the video signal is synchronized with the vertical synchronizing signal period in the vertical blanking period. Although the temporal relationship between the pulse and the effective screen period is slightly different, according to the present invention, it is possible to superimpose data in a specific horizontal scanning period of the vertical blanking period in any case. FIG. 6 shows the operation timing at the end of the even field as a second data transmission timing diagram.

The operation of the first embodiment of the apparatus for superimposing data on a video signal according to the present invention has been described above. Next, the operation of the receiving apparatus will be described with reference to FIGS. In the present invention,
The operation on the receiving device side is almost the same as the operation on the transmitting device side described above. In FIG. 2, circuit portions performing the same operation as the transmitting side operation are denoted by the same reference numerals as those in FIG. 7 shows a timing chart of only the data superimposed portion.

First, in FIG. 2, a DC component of the data superimposed video signal 110, which is an input video signal, is reproduced by the clamp circuit 2 to become a post-clamped data superimposed video signal 119 shown in FIG. The image content is displayed on an image display 25 such as a CRT or a liquid crystal monitor, but as described above, data that is normally superimposed and multiplexed during the vertical blanking period is visible on the display screen of the image display 25. Never.

Hereinafter, the synchronization separation circuit 3 to the RSFF circuit 8
The operation up to the generation of the gate signal 107, which is the output of the first signal, is completely the same as the operation on the transmitting device side, and the description is omitted.
The B circuit E24 (monostable multivibrator circuit) is driven, and the trigger period of the MB circuit E24 is set to a period t4 longer than the trigger period t3 of the previous transmission side MB circuit A13 as shown in FIG. 7C. , So M
The fourth synchronized signal 1 after the waveform shaping which is the output of the B circuit E24
Reference numeral 17 denotes a pulse waveform whose rising time is later in time than the third waveform-shaped synchronization signal 108 as shown in FIG. 7C.

The setting of t4 is such that the shift pulse 116 generated by the operation of the gate circuit 12 by the gate signal 107 shown in FIG. 7B is applied during the data period of the superimposition data D1 to D8 as shown in FIG. It is configured to stand almost at the center of the.

Then, the SP shift register circuit 2 shown in FIG.
2 (serial / parallel shift register circuit)
6, the data D1 to D8 can be sequentially shifted substantially at the center of the data period as shown in FIGS. 7 (E) to 7 (L).

Here, by fetching data by latching at the falling edge which is the end of the gate signal 107, the value of the data becomes 1 (or 8) according to the video luminance level of the superimposed data as 8-bit parallel detection data 118. H) or 0 (or L) is detected, and the detection data 23 can be detected.

In addition, this superimposed data detection operation is repeated cyclically for each field, and it is possible to operate without any trouble even at the end of the even field and at the end of the odd field. The same is true.

Next, a second embodiment of the apparatus for superimposing data on a video signal according to the present invention will be described with reference to FIG. In FIG. 3, a video signal source 17 is a camera or the like, and a horizontal synchronization signal 114 and a vertical synchronization signal 115 can be easily derived.

In the case of the second embodiment of the data superimposition transmitting apparatus, the circuit can be further simplified as shown in FIG.
The edge pulse 106 is generated by delaying the vertical synchronizing signal 115 by the horizontal synchronizing signal 114, and the MB circuit B18 (monostable multivibrator circuit) and the MB circuit C19 (monostable multivibrator circuit) are synchronized after the third waveform shaping. For generating a pulse signal equivalent to the signal 108, the counter circuit 9 counts the horizontal synchronizing signal 114 to obtain the same effect as in the first embodiment.

FIG. 4 is a partial block diagram of a third embodiment of the apparatus for transmitting / receiving data to a video signal according to the present invention.
In this embodiment, an MB circuit D is used to obtain the gate signal 107.
20 (monostable multivibrator circuit) is used, and the circuit can be simplified on both the transmitting device side and the receiving device side as compared with the first embodiment.

In the above description of the present invention, the rising and falling of the pulse, the H level and the L level of the signal have been described as if they were fixed. This is for reasons such as ease of understanding and the like. Even if the rise / fall or the logic level is inverted in whole or in part if the logic is consistent,
It goes without saying that the effects of the present invention are not affected at all.

Further, as is apparent from the above-described operation, the present invention provides a PAL system other than the Japanese television video signal system (NTSC system) by appropriately setting the trigger period of the monostable multivibrator or the like. In addition to the composite video signal in which all the signals are mixed, the present invention can be easily applied to an S video having two sequences of a color signal and a luminance / synchronization signal.

As described above, according to the present invention, the retrigger type monostable multivibrator circuit, monostable multivibrator circuit, delay circuit, edge detection circuit,
By driving the shift register circuit with a simple configuration including simple logic circuits such as a set-reset flip-flop circuit, a gate circuit, and a counter circuit, it is possible to superimpose and detect data in a video signal vertical blanking period. .

[0058]

As described above, the following advantages can be obtained by the apparatus and method for transmitting / receiving data to a video signal according to the present invention. Firstly, the first point is that since it has a simple configuration consisting of a simple logic circuit, it is sufficient to superimpose several bits of data, for example, as in sensor information transmission of a surveillance camera. It is possible to realize it.

Second, since it is not necessary to generate a specific high-frequency clock signal for synchronizing the phase with the synchronizing signal, there is no need to provide a phase locked loop or a VCO. For this purpose, since each signal operates in synchronization with the synchronizing signal of the video signal, there is no element that interferes with the video signal including leakage of the specific high-frequency clock signal, the VCO signal, and the VCO frequency-divided signal.

The third point is that there is no need to equip a synchronous loop or a VCO, and as is clear from the description so far, there is no portion to be adjusted and no adjustment is possible.

Further, as a fourth point, according to the present invention, the receiving side for detecting superimposed data has a simple configuration comprising a simple logic circuit substantially similar to the transmitting side, so that the receiving side can be realized at very low cost. is there.

[Brief description of the drawings]

FIG. 1 is a first transmission apparatus for superimposing data on a video signal according to the present invention.
Example block diagram.

FIG. 2 is a first apparatus for receiving data superimposed on a video signal according to the present invention;
Example block diagram.

FIG. 3 is a second transmission apparatus for superimposing data on a video signal according to the present invention.
Example block diagram.

FIG. 4 is a partial block diagram of a third embodiment of a device for transmitting and receiving data to a video signal according to the present invention.

FIG. 5 is a first data transmission timing chart of the present invention.

FIG. 6 is a second data transmission timing chart of the present invention.

FIG. 7 is a data reception timing chart of the present invention.

FIG. 8 is a block diagram of a conventional apparatus for superimposing and transmitting data on a video signal.

FIG. 9 is a data transmission timing chart of a conventional example.

[Brief description of reference numerals]

Reference Signs List 1 video signal source A 2 clamp circuit 3 sync separation circuit 4 retrigger MB circuit A (retrigger monostable multivibrator circuit) 5 retrigger MB circuit B (retrigger monostable multivibrator circuit) 6 delay circuit 7 Edge detection circuit 8 RSFF circuit (set / reset flip-flop circuit) 9 counter circuit 10 superimposed data 11 PS shift register circuit (parallel serial shift register circuit) 12 gate circuit 13 MB circuit A (monostable multivibrator circuit) 14 level conversion circuit A 15 Data superposition circuit A 17 Video signal source B 18 MB circuit B (monostable multivibrator circuit) 19 MB circuit C (monostable multivibrator circuit) 20 MB circuit D (monostable multivibrator circuit) 21 Level conversion circuit B 22 SP Shift register circuit (series Column shift register circuit) 23 detection data 24 MB circuit E (monostable multivibrator circuit) 25 video display 31 vertical sync separation circuit 32 phase comparator 33 LPF circuit 34 VCO (voltage controlled oscillator) 35 frequency divider A 36 frequency division Device B 37 adjusting means 38 timing generation circuit 39 superimposition data 40 memory circuit 41 level conversion circuit B 42 data superposition circuit B 101 video signal after clamp 102 synchronization signal 103 first synchronization signal after waveform shaping 104 second synchronization after waveform shaping Signal 105 Delay signal 106 Edge pulse 107 Gate signal 108 Third waveform-shaped synchronization signal 109 Shift pulse 110 Data superimposed video signal 111 Parallel superimposed data 112 Video signal 113 Reset pulse 114 Horizontal synchronization signal 115 Vertical synchronization signal 116 Shift pulse 117 Fourth waveform-shaped synchronization signal 118 Parallel detection data 119 Clamped data superimposed video signal 131 Vertical synchronization signal 132 Horizontal synchronization signal 133 Data superimposition timing signal 134 Data superimposed video signal 135 Data read timing signal 136 Memory read / write control signal 137 Memory Address control signal 138 Clock signal

Claims (7)

[Claims] 1. A synchronizing signal obtained by clamping and separating a video signal within a vertical blanking period and a plurality of horizontal scanning periods of a video signal output from a video device, to a first retrigger type monostable multi-unit. Waveform shaping by a vibrator circuit and a second retrigger type monostable multivibrator circuit;
The waveform shaping signal is used to generate an edge pulse from a delay circuit and an edge detection circuit based on a synchronization signal, and the set of the set / reset flip-flop circuit and the output signal of the first retrigger type monostable multivibrator circuit are counted by the edge pulse. The counter circuit resets the count value, takes in the parallel superimposed data into the parallel serial shift register to which the parallel superimposed data is input, and resets the set reset flip-flop circuit at a predetermined count value at the counter circuit. A gate signal is generated by an output signal of the set / reset flip-flop circuit by outputting a reset signal to the set / reset flip-flop circuit so that the first retrigger type monostable is generated by the gate signal. Multivibrator circuit output A shift pulse is generated by controlling a gate circuit to which a signal obtained by shaping the signal with a first monostable multivibrator circuit is input, and the parallel serial shift register circuit performs a shift operation. A method for superimposing data on a video signal, wherein the method is used as a superimposition control signal for a data superimposing circuit that superimposes a clamped video signal after level conversion of a parallel serial shift register circuit output signal. 2. A clamp circuit for synchronizing and separating a video signal during a vertical blanking period and a plurality of horizontal scanning periods of a video signal output from a video device, a synchronization separation circuit, and a synchronization obtained from the synchronization separation circuit. First and second retrigger-type monostable multivibrator circuits for shaping a signal, a delay circuit and an edge detection circuit for generating an edge pulse from the waveform shaping signal by using a synchronization signal, A first reset trigger type monostable multivibrator circuit, a set / reset flip-flop circuit for resetting a count value of a counter circuit for counting an output signal, and a parallel superimposed data which is connected to the edge detection circuit and the counter circuit to acquire data. The input parallel / serial shift register and the counter circuit are synchronized with a predetermined count value. A gate circuit for generating a gate signal with an output signal of the set / reset flip-flop circuit by outputting a reset signal to the set / reset flip-flop circuit so as to reset the set / reset flip-flop circuit; A shift pulse is generated at the gate circuit output by controlling a gate circuit to which a signal obtained by shaping the output signal of the first retrigger type monostable multivibrator circuit by the monostable multivibrator circuit is further input by a gate signal of the gate circuit. And a data superimposing circuit that superimposes the shift pulse on the post-clamp video signal after converting the level of the parallel serial shift register circuit output signal while performing the shift operation of the parallel serial shift register circuit with the shift pulse. Featured video Data superimposing transmission apparatus to issue. 3. A mono-stable multi-stable signal obtained by clamping and separating a video signal within a vertical blanking period and a plurality of horizontal scanning periods of a video signal output from a video device. Waveform shaping by a vibrator circuit and a second retrigger type monostable multivibrator circuit;
An edge pulse is generated from the delay circuit and the edge detection circuit by using the waveform shaping signal and the synchronization signal, and the set pulse of the set / reset flip-flop circuit and the output signal of the first retrigger type monostable multivibrator circuit are generated by the edge pulse. A count signal of the counter circuit for counting is reset, and a reset signal is generated so that the counter circuit resets the set-reset flip-flop circuit at a predetermined count value. The gate signal is used to control a gate circuit to which a signal obtained by shaping the output signal of the first retrigger-type monostable multivibrator circuit with a second monostable multivibrator circuit is input, thereby controlling the gate circuit. Generates a shift pulse at the output, And a shift operation of the serial / parallel shift register circuit to which the post-clamped video signal after the level conversion is input by the trigger pulse, and latching the output signal of the serial / parallel shift register circuit at the end of the gate signal. A method of receiving data superimposed on a video signal. 4. A clamp circuit for synchronizing and separating a video signal within a vertical blanking period and a plurality of horizontal scanning periods of a video signal output from a video device, a synchronization separation circuit, and a synchronization obtained from the synchronization separation circuit. First and second retrigger-type monostable multivibrator circuits for shaping a signal, a delay circuit and an edge detection circuit for generating an edge pulse from the waveform shaping signal by using a synchronizing signal, A set-reset flip-flop circuit for resetting a count value of a counter circuit for counting an output signal of a first retrigger type monostable multivibrator circuit; and a reset circuit for resetting the set-reset flip-flop circuit at a predetermined count value at the counter circuit. And outputs a reset signal to the set-reset flip-flop circuit. Wherein by configuring urchin set-reset flip-flop and a gate circuit for generating a gate signal by the output signal of the circuit, further a second said first retriggerable type monostable multivibrator circuit output signal by the gate signal of the gate circuit
By controlling a gate circuit to which a signal whose waveform has been shaped by the monostable multivibrator circuit is input, a shift pulse is generated at the output of the gate circuit, and a level-converted video signal after the level conversion is input by the shift pulse. A serial-parallel shift register circuit for performing a shift operation, wherein the output signal of the serial-parallel shift register circuit is latched at the end of the gate signal. 5. An edge pulse is generated by detecting an edge of a vertical synchronization signal output from a video signal source with a delay by a horizontal synchronization signal output from the video signal source, and the set / reset flip-flop is generated by the edge pulse. A circuit for setting and resetting a count value of a counter circuit for counting the horizontal synchronizing signal, a counter circuit for counting the horizontal synchronizing signal is supplied with a reset signal so as to reset the set / reset flip-flop circuit at a predetermined count value. The horizontal reset signal is configured to be output to the set-reset flip-flop circuit, and a signal obtained by shaping the horizontal synchronizing signal by a third monostable multivibrator circuit and a fourth multivibrator circuit is input to the gate circuit. The data to a video signal according to claim 1, wherein Superimposed transmission method. 6. The video signal according to claim 1, wherein the edge pulse is shaped by a fifth monostable multivibrator circuit to generate a signal equivalent to the gate signal. Data overlay transmission method. 7. The data superimposition on a video signal according to claim 3, wherein the edge pulse is shaped by a fifth multivibrator circuit to generate a signal equivalent to the gate signal. Receiving method.