JP2002094511A - Atm switch device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM switch device of an output buffer type that can reduce the probability of aborted input data and effectively utilize a memory resource. SOLUTION: In the ATM switch device of an output buffer type that is provided with N-sets (N is an integer, 2 or over) of data output ports (out 0, out 1) and N-sets of output buffers (SB0, SB1) and writes input data (WD0, WD1) whose output destination is a k-th (k is an optional integer from 1 to N) data output port to a k-th output buffer, the residual memory capacity of the respective output buffers is detected and when the residual memory capacity of the k-th output buffer is deficient, the output buffer to which the input data outputted from the k-th output buffer are written is changed from the k-th output buffer into other output buffer whose residual memory capacity is not deficient.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer type ATM (Asynchronous Transfer Mode) switch device.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram of a conventional output buffer type ATM switch. The ATM switch of FIG. 11 includes an input unit MUX and a FIFO type output buffer BU.
AT of 2 × 2 switch configuration including F0 and BUF1
This is an M switch, and has a configuration in which input data WD0 and WD1 are time-multiplexed in the input unit MUX to avoid collision in the data path due to simultaneous writing. Such an output buffer type ATM switch has an output buffer BUF.
When the memory amount of 0, BUF1 is infinite, the maximum throughput can be realized at 100 [%], and there is an advantage that the structure is simple.

[0003]

However, in the conventional output buffer type ATM switch, data output from the same data output port is written to the same output buffer, so that writing of input data to one output buffer is concentrated. Then, the output buffer runs out of space, and the input data must be discarded. To reduce the probability that the input data is discarded, it is necessary to increase the memory of each output buffer. However, when an output buffer is full, the memory of another output buffer is often sparse, and the sparse memory is wasted. For this reason, it has been difficult to say that the above conventional output buffer type ATM switch effectively utilizes the memory resources.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an output buffer type ATM switch device which can reduce the probability of input data being discarded and can effectively utilize memory resources. It is intended to provide.

[0005]

In order to achieve the above object, an ATM switch according to claim 1 of the present invention comprises:
N (N is an integer of 2 or more) data output ports and N
An output buffer type ATM switch device which includes a plurality of output buffer devices and writes input data whose output destination is a k-th (k is an arbitrary integer from 1 to N) data output port to a k-th output buffer device. Determining the remaining memory capacity of each output buffer device, and writing the input data to be output from the k-th data output port when the remaining memory capacity of the k-th output buffer device is insufficient. From the output buffer device of (1) to another output buffer device having sufficient memory capacity.

According to a second aspect of the present invention, there is provided an ATM switch device according to the first aspect, further comprising means for assigning an identifier to each output buffer device, and the k-th output buffer device is configured to write input data. A memory for initializing a write identifier of the own device to an identifier of the own device, a unit for writing input data assigned an address corresponding to the write identifier of the own device to the data memory, and a memory of the own device. Means for detecting the remaining capacity and notifying the other output buffer apparatus of the remaining memory capacity, and writing the remaining memory capacity of the own apparatus to another output buffer apparatus having the sufficient remaining memory capacity when the remaining memory capacity is insufficient. Means for outputting an identifier replacement signal, and changing the write identifier of the own device from the identifier of the own device to the identifier of the other output buffer device; and Means for changing the write identifier of the own device from the identifier of the own device to the identifier of the other output buffer device when a write identifier exchange signal is input from another output buffer device. is there.

According to a third aspect of the present invention, in the ATM switch device according to the second aspect, the k-th output buffer device transmits the input data provided with an address corresponding to the identifier of the device. Either read from the memory and output to the k-th data output port, or read the input data with the address corresponding to the identifier of the other output buffer device from the data memory and transfer it to the other output buffer device Output the input data with the address corresponding to the identifier of the own device transferred from the other output buffer device to the k-th data output port, or correspond to the identifier of the other output buffer device. Input data to which the address to be assigned is read from the data memory and transferred to the other output buffer device Or is characterized in that it further comprises a means for outputting the input data to the corresponding address is attached to the identifier of the device that has been transferred from said other output buffer device to the data output port of the first k.

According to a fourth aspect of the present invention, there is provided an ATM switch device according to the first aspect, wherein each of the output buffer devices has an identifier, and the write identifier of the k-th output buffer device is a k-th output buffer device. Means for initially setting the identifier of the buffer device, and another output buffer device having a memory capacity sufficient for the write identifier of the k-th output buffer device when the remaining memory capacity of the k-th output buffer device is insufficient. And an identifier changing means for changing the write identifier of the other output buffer to the identifier of the k-th output buffer device, wherein the k-th output buffer device has a data memory in which input data is written. Means for writing, to the data memory, input data assigned an address corresponding to the write identifier of the own device; Detecting the re remaining, the remaining memory capacity is characterized in that it has a means for notifying to the identifier change means.

According to a fifth aspect of the present invention, in the ATM switch device, the input data to which the address corresponding to the identifier of the k-th output buffer device is added from the k-th data output port. Means for generating a control signal for output for each output buffer device, and outputting these control signals to each output buffer device, wherein the k-th output buffer device outputs the data signal according to the control signal. The input data written to the memory is read and output to the k-th data output port, or the input data written to the data memory is read and transferred to another output buffer device and the other output buffer device is read out. Output the input data transferred from to the k-th data output port,
Alternatively, a means for reading the input data written in the data memory and transferring the read data to another output buffer device or outputting the input data transferred from the other output buffer device to the k-th data output port is further provided. It is characterized by having.

[0010]

FIG. 1 is a block diagram of an output buffer type ATM switch according to a first embodiment of the present invention. FIG. 2 is an internal configuration diagram of the switch blocks SB0 and SB1 of FIG. The internal configuration of switch blocks SB0 and SB1 is the same.

The ATM switch according to the first embodiment includes switch blocks (output buffers) SB0 and SB1, an input unit IU, data input ports in0 and in1, and data output ports out0 and out1.

The ATM switch according to the first embodiment has two switches.
× 2 switch configuration, and the data input port i
Input data (input cell) WD0 input from n0 is
According to the output destination (destination) address included in the header portion of this input data WD0, data output port out
Output data RD0 from 0 or output data RD1 from the data output port out1 and input data (input cell) WD1 input from the data input port in1 are included in the header of the input data WD1. The data is output from the data output port out0 as output data RD0 or from the data output port out1 as output data RD1 according to the output destination (destination) address.

[Input Unit IU] The input unit IU transfers the input data WD0 to the switch blocks SB0 and SB1 and also transfers the input data WD1 to the switch block SB.
0 and transferred to SB1.

Further, the input section IU receives an address signal WA of the input data WD0 based on the header section of the input data WD0.
0, and sends the address signal WA0 to the switch blocks SB0 and SB1 and the input data WD
The address signal WA1 of the input data WD1 is generated based on the header portion of the data block No. 1 and the address signal WA0 is sent to the switch blocks SB0 and SB1.

The address signal WA0 is a signal for identifying the data output port for outputting the input data WD0 by the switch blocks SB0 and SB1, and the address signal WA1 is a data output port for outputting the input data WD1. Is a signal for identifying by the switch blocks SB0 and SB1. Here, the data output port o
The value of the address signal of the input data output from ut0 is set to "
00 ", and the value of the address signal of the input data output from the data output port out1 is" 01 ". In the following description, the input data output from the data output port out0 is referred to as the 0-system data, and the data output port ou.
The input data output from t1 is referred to as 1-system data.

The input unit IU is connected to a data input port i.
An input enable signal WE0 is generated in accordance with whether or not input data WD0 is input to n0. This input enable signal WE0 is sent to switch blocks SB0 and SB1, and input data WD is input to data input port in1.
1 according to whether or not 1 has been input.
1 and sends the input enable signal WE1 to the switch blocks SB0 and SB1.

The input enable signal WE0 is a signal for the switch blocks SB0 and SB1 to identify whether or not the input data WD0 has been input to the data input port in0, and the input enable signal WE1 is the data input signal WE1. This signal is used by the switch blocks SB0 and SB1 to identify whether the input data WD1 has been input to the port in1. In other words, the input enable signal W
E0 is a signal for permitting the switch blocks SB0 and SB1 to write the input data WD0, and the input enable signal WE1 is a signal for permitting the switch blocks SB0 and SB1 to write the input data WD1.

The input unit IU generates a frame signal FR0 based on the input timing of the input data WD0,
The frame signal FR0 is sent to the switch blocks SB0 and SB1, and a frame signal FR1 is generated based on the input timing of the input data WD1, and the frame signal FR1 is sent to the switch blocks SB0 and SB1.
Send to

The above-mentioned frame signal FR0 is a signal for the switch blocks SB0 and SB1 to identify the timing such as the head position of the input data WD0, and the above-described frame signal FR1 is the timing such as the head position of the input data WD1. Is a signal for identifying by the switch blocks SB0 and SB1.

The input unit IU includes a switch block S
Identifier BID0 of B0 and switch block SB1
Is generated. And the identifier BID0
Is sent to the switch block SB0 as an identifier of the own block, and is sent to the switch block SB1 as an identifier of another block. The identifier BID1 is sent to the switch block SB1 as an identifier of the own block, and is sent to the switch block SB0 as an identifier of another block.

The input unit IU generates a remaining memory threshold RT, and sends the remaining memory threshold RT to the switch blocks SB0 and SB1. The memory remaining threshold RT is used as a threshold when determining the remaining memory of the switch blocks SB0 and SB1 as described later.

The ATM switch according to the first embodiment detects the remaining memory capacity of the switch blocks SB0 and SB1,
When both the remaining memory amounts of the switch blocks SB0 and SB1 are not insufficient, the 0-system data is written into the switch block SB0, and the 1-system data is written into the switch block SB1.
If the remaining memory capacity of one of B1 is insufficient and the remaining memory capacity is not insufficient, the switch block for writing the 0-system data is changed from the switch block SB0 to the switch block SB1, and A switch block for writing data is called a switch block SB.
It is characterized by changing from 1 to the switch block SB0 (replace the write block).

After the replacement of the write blocks is performed, when the remaining memory capacity of the switch block having the insufficient remaining memory is recovered, the replacement of the write blocks is restored.

When the remaining memory capacity of both the switch blocks SB0 and SB1 is insufficient, it is optional whether or not to replace the write block (if the replacement has already been performed, release the replacement).
Here, it is assumed that when the remaining memory capacity of both the switch blocks SB0 and SB1 is insufficient, the writing blocks are not replaced (if the replacement has already been performed, the replacement is canceled).

The replacement of the write block is performed by a write identifier (hereinafter, WID0) of the switch block SB0.
This is performed by exchanging the value of the write identifier (hereinafter referred to as WID1) of the switch block SB1.

In order to realize the replacement of the write block, the switch block SB0 is provided with the write identifier W of its own block, separately from the identifier BID0 of its own block.
The switch block SB1 has the write identifier WID1 of its own block, separately from the identifier BID1 of its own block. The value of the identifier BID0 of the switch block SB0 and the value of the identifier BID1 of the switch block SB1 are not changed on the way. Here, the value of the identifier BID0 is set to “00” and the identifier BID
The value of 1 is “01”. The switch block SB0 with the identifier BID0 = "00" is connected to the data output port out0.
Is a switch block that outputs data to the
The switch block SB1 with ID1 = "01" is a switch block that outputs data to the data output port out1. The switch block that outputs data to the data output port out0 and the switch block that outputs data to the data output port out1 are not interchanged on the way, due to the structure of the output buffer type ATM switch.

On the other hand, the value of the write identifier WID0 of the switch block SB0 and the value of the switch block SB0
The value of the write identifier WID1 of B1 is changed when the write block is replaced and when the replacement of the write block is restored. The value of the write identifier WID0 of the switch block SB0 is the identifier BID0 of the own block when the write block is not replaced, and is changed to the identifier BID1 of the other block when the write block is replaced. The value of the write identifier WID1 of the switch block SB1 is the identifier BID1 of the own block when the write block is not replaced, and is changed to the identifier BID0 of the other block when the write block is replaced. . Therefore, the write identifier WID (WID0 or WID1) is BID0
The switch block of “00” is a switch block for writing system 0 data (data to be output to the data output port out0), and has a write identifier WID (WI
The switch block whose DID or WID1) is BID1 = "01" is the first system data (data output port out).
1 is a switch block for writing data (data to be output to 1).

When the remaining memory capacity of the switch blocks SB0 and SB1 is not insufficient, the write identifier WID0 of the switch block SB0 is the identifier BID0 of the own block, and the write identifier WID1 of the switch block SB1 is the identifier of the own block. BID1. When the remaining memory capacity of the switch block SB0 or SB1 becomes insufficient, the write identifier WID0
Is replaced with the value of the write identifier WID1, the write identifier WID0 of the switch block SB0 is changed to the identifier BID1 of the switch block SB1, and the write identifier WID1 of the switch block SB1 is changed to the identifier BID0 of the switch block SB1. .

In the ATM switch according to the first embodiment, the 0 written in the switch block SB1 is set to 0.
The system data is transferred from the switch block SB1 to the switch block SB0, and is output from the switch block SB0 to the data output port out0. Similarly, the 1-system data written in the switch block SB0 is transferred from the switch block SB0 to the switch block SB1, and is output from the switch block SB1 to the data output port out1.

[Switch Blocks SB0 and SB1] FIG.
The switch blocks SB0 and SB1 respectively include an input data identification circuit IDC, a spatial cross switch SW, data memories DMA and DMB, a management memory CM, an output selector OS, and a write / read controller WRC. , A memory controller MMC.

In the following description, the switch block S
B0 spatial cross switch SW, write / read controller WRC, data memories DMA, DMB, management memory CM, output selector OS, memory controller MM
C as SW0, WRC0, DMA0, DMB
0, CM0, OS0, MMC0, the spatial cross switch SW of the switch block SB1, the write / read controller WRC, the data memories DMA, DMB,
The management memory CM, the output selector OS, and the memory controller MMC are connected to SW1, WRC1, DMA1, and D1, respectively.
MB1, CM1, OS1, and MMC1.

Further, the write identifier exchange signal CI generated by the switch block SB0, the memory data selection signal MS generated by the switch block SB0, the remaining memory ZAN of the switch block SB0, the memory data MQA and MQB of the switch block SB0, Write identifier WID of switch block SB0, and input data identification signal DC generated in switch block SB0
To CI0, MS0, ZAN0, MQA0, M
QB0, WID0, DC0, the write identifier exchange signal CI generated by the switch block SB1,
Memory data selection signal MS generated in switch block SB1, remaining memory capacity ZA of switch block SB1
N, memory data MQA, M of switch block SB1
QB, write identifier WI of switch block SB1
D and the input data identification signal DC generated by the switch block SB1 are respectively CI1, MS1, ZAN
1, MQA1, MQB1, WID1, and DC1.

In FIG. 2, an input data identification circuit IDC, a spatial cross switch SW, a write / read controller WRC, data memories DMA and DMB, a management memory CM, an output selector OS, and a memory controller M
MC, identifier BID of own block, identifier BIDT of other block, write identifier exchange signal CI output to other block, write identifier exchange signal CIT input from other block, memory data selection signal MS output to other block, other block Data selection signal MST input from the memory, the remaining memory ZAN of the own block, the remaining memory ZANT of the other block, the memory data MQA and MQB of the own block, the memory data MQA of the other block
The parentheses of T, MQBT, the write identifier WID of the own block, and the input data identification signal DC are as described above when the switch block in FIG. 2 is the switch block SB0.

The switch blocks SB0, SB1
Are input terminals fr0 and fr1 for frame signals FR0 and FR1, input terminals wd0 and wd1 for input data WD0 and WD1, input terminals wa0 and wa1 for address signals WA0 and WA1, and input enable signals WE0 and wa1, respectively.
Input terminals we0 and we1 of WE1, an input terminal bid of an identifier BID of its own block (identifier BID0 or BID1), and an identifier BIDT of another block (identifier BID)
1 or BID0), an input terminal rt for the remaining memory threshold RT, and output data RD (RD
0 or RD1) output terminal rd.

The input terminal bi of the switch block SB0
d, and the input terminal bidt of the switch block SB1
, The identifier BID0 is input, and the identifier BID1 is input to the input terminal bid of the switch block SB1 and the input terminal bidt of the switch block SB0.

In the switch block SB0, FIG.
The identifier BID of its own block is the identifier BID0, the identifier BIDT of the other block in FIG. 2 is the identifier BID1,
In the switch block SB1, the identifier BID of the own block in FIG. 2 is the identifier BID1, and the identifier BIDT of the other blocks in FIG. 2 is the identifier BID0.

The output data RD in FIG. 2 is the output data RD0 output to the data output port out1 in the switch block SB0, and the switch block SB1
Is output data RD1 output to the data output port out2.

The switch blocks SB0 and SB1
Is a write identifier replacement signal CI (C
I0 or CI1) and a write identifier exchange signal CIT (CI1 or CI1) of another block.
0) and the output terminal mso of the memory data selection signal MS (MS0 or MS1) of the own block.
And a memory data selection signal MST (MS1
Or MS0) and an output terminal z of the remaining memory ZAN (ZAN0 or ZAN1) of the own block.
nano and the remaining memory ZANT (ZAN1
Or ZAN0) and output terminals mqao, mqbo of the memory data MQA, MQB (MQA0, MQB0 or MQA1, MQB1) of the own block.
And memory data MQAT, MQBT (M
QA1 and MQB1 or MQA0 and MQB0) input terminals mqai and mqbi.

Output terminal ci of switch block SB0
From o, mso, zano, mqao, and mqbo, a write identifier exchange signal CI0, a memory data selection signal MS0, a remaining memory capacity ZAN0, and memory data MQA0, MQB0 are output, respectively, and a switch block SB is output.
0 input terminals cii, msi, zani, mqai, m
qbi includes a write identifier exchange signal CI
1, memory data selection signal MS1, remaining memory capacity ZAN
1. Memory data MQA1 and MQB1 are input. Also, the output terminals cio, ms of the switch block SB1
From o, zano, mqao, and mqbo, the write identifier exchange signal CI1, the memory data selection signal MS1, the remaining memory capacity ZAN1, and the memory data MQA, respectively.
1, MQB1 is output, and the input terminals cii, msi, zani, mqai, mqbi of the switch block SB1 are output.
Are respectively input with a write identifier exchange signal CI0, a memory data selection signal MS0, a remaining memory ZAN0, and memory data MQA0 and MQB0.

In the switch block SB0, FIG.
The write identifier replacement signal CIT, the memory data selection signal MST, and the memory data MQAT and MQBT are CI1, MS1, MQA1, and MQB1, respectively. In the switch block SB1, the write identifier replacement signal CIT and the memory data selection signal shown in FIG. MST,
The memory data MQAT and MQBT are respectively CI0,
MS0, MQA0, and MQB0.

The input data WD0 and WD1 are input to the spatial cross switches SW of the switch blocks SB0 and SB1. The address signals WA0 and WA1 are input to the input data identification circuit IDC. Further, the input enable signals WE0, WE1 and the frame signals FR0, WE1
FR1 includes an input data identification circuit IDC, a write / read controller WRC, and a memory controller MMC.
Is input to Further, the remaining memory threshold RT is input to the memory controller MMC.

The memory data MQA of another block
T, MQBT (MQA0, MQB0, or MQA1,
MQB1) are input terminals opc, o of the output selector OS.
pd. Also, the write identifier exchange signal CIT, the memory data selection signal MST input from another block, and the remaining memory capacity ZA of the other block.
NT (CI1, MS1, ZAN1, or CI0, MS
0, ZAN0) is input to the memory controller MMC.

[Input data discrimination circuit IDC] The input data discrimination circuit IDC includes input enable signals WE0 and WE.
1. In accordance with the address signals WA0, WA1 and the write identifier WID of the own block input from the memory controller MMC, it is determined whether or not the input data WD0, WD1 is data to be written to the data memories DMA, DMB of the own block. , An input data identification signal DC to the memory controller MMC and the write / read controller WRC.

As described above, the switch block S
When both the remaining memory amounts of B0 and SB1 are not insufficient, the write identifier WID of the switch block SB0
Since 0 = BID0 = “00”, the switch block SB0 is a block for writing 0-system data, and the write identifier WID1 = BID1 of the switch block SB1.
= "01", the switch block SB1 is a switch block for writing the 1-system data. When the remaining memory capacity of one of the switch blocks SB0 and SB1 is insufficient, the write identifier WID0 of the switch block SB0 is changed to BID1, so that the switch block SB0 becomes a switch block for writing the 1-system data, and the switch block SB1 Write identifier W
Since ID1 is changed to BID0, the switch block SB1 is a switch block for writing 0-system data. The value of the address signals WA0 and WA1 of the 0-system data is “00”, and the address signal WA of the 1-system data.
The values of 0 and WA1 are “01”.

The input data identification circuit IDC0 of the switch block SB0 has its own block write identifier WID0.
= BID0 = “00”, the address signal WA0
If "00", the input data WD0 is identified as data to be written into its own block, and the address signal WA0
If "01", the input data WD0 is identified as data to be written into another block, and the address signal WA1 is determined.
If "00", the input data WD1 is identified as the data to be written to the own block, and the address signal WA1 is determined.
If "01", the input data WD1 is identified as data to be written to another block. When the write identifier WID0 = BID1 = "01" of the own block, if the address signal WA0 = "00", the input data WD0 is identified as data to be written to another block, and the address signal WA0 = "01". If so, the input data WD0 is identified as data to be written to the own block. If the address signal WA1 = "00", the input data WD1 is identified as data to be written into another block, and the address signal WA1 = "". If "01", the input data WD1 is identified as data to be written to the own block.

Similarly, when the write identifier WID1 = BID1 = "01" of the own block, the input data identification circuit IDC1 of the switch block SB1 transfers the input data WD0 to the own block if the address signal WA0 = "01". When the address signal WA0 = “00”, the input data WD0 is identified as data to be written to another block. When the address signal WA1 = “01”, the input data WD1 is determined. The input data WD1 is identified as data to be written into another block if the address signal WA1 = "00" is identified as data to be written into the own block. When the write identifier WID1 = BID0 = “00” of the own block, if the address signal WA0 = “01”, the input data WD0 is identified as data to be written to another block, and the address signal WA0 = “00”. If it is, the input data WD0 is identified as data to be written into the own block, and if the address signal WA1 = "01", the input data WD1 is identified as data to be written into another block, and the address signal WA1 = "". If "00", the input data WD1 is identified as data to be written in the own block.

The input data identification signal DC is a signal for notifying the memory controller MMC and the write / read controller WRC whether or not the input data WD0, WD1 is data to be written to the own block.
Here, the value of the input data identification signal DC is “00” when both the input data WD0 and WD1 are not data to be written into the own block, and “01” when only the input data WD0 is data to be written into the own block. ,
"10" when only the input data WD1 is data to be written to the own block, "1" when both the input data WD0 and WD1 are data to be written to the own block.
1 ".

[Space-type cross switch SW] The space-type cross switch SW is composed of a selector, a transistor switch, etc., and has a write / read controller WR.
The data memory which is controlled by C and transfers the input data WD0 and WD1 is switched. The spatial cross switch SW transfers the input data WD0 to the data memory DMA as the data SQA and transfers the input data WD1 to the data memory DMB as the data SQB, or conversely, transfers the input data WD0 to the data
The input data WD1 is transferred to the data memory DMB as data SQA while being transferred to the data memory DMB as QB.
Transfer to A.

[Data Memory DMA, DMB] The data memory DMA, DMB is a write / read controller W
This is a FIFO type memory in which writing and reading of data are controlled by the RC. The data SQA (input data WD0 or WD1) is written to the data memory DMA as memory data MQA, and the memory data MQA is output to the output terminal mqao and the data input terminal opa of the output selector OS. Also, the data SQ
B (input data WD1 or WD0) is written to the data memory DMB as memory data MQB, and this memory data MQB is output to the output terminal mqbo and the data input terminal opb of the output selector OS.

The input data WD1 and WD0 are written
The following procedure is used. Input data is stored in the data memory DM
A and DMB are written alternately. In the data memories DMA and DMB, input data is written in order from a vacant address having a higher read order, and when the input data written in the address of the read order 1 is read as memory data MQA or MQB, the read order is increased. The input data written in the second and subsequent addresses is shifted to the next higher address in the reading order.

In the data memories DMA and DMB, assuming that the empty address having the highest read order is a write empty address, the input data is written to the empty write address of the data memory DMA or DMB. When the read order of the write free addresses of the data memory DMA and the DMB is the same, the data memory DMA
The write free address of the data memory DMB is set to the write order 1, and the free write address of the data memory DMB is set to the write order 2.
And When the read order of the free write address of the data memory DMA is one higher than the read order of the free write address of the data memory DMB,
The free write address of the data memory DMB is set to the write order 1, and the free write address of the data memory DMA is set to the write order 2.

Input data WD0, WD input simultaneously
When both 1 are data to be written to the own block, the input data WD0 is written to a free write address of write order 1 and the input data WD1 is written to a free write address of write order 2. When any one of the input data WD0 and WD1 is data to be written to the own block, the input data is written to a write free address of the write order 1.

[Output Selector OS] Output Selector OS
Are controlled by the memory controller MMC. The output selector OS outputs the memory data MQA of the own block input to the data input terminal opa, the memory data MQB of the own block input to the data input terminal opb, and the data input terminal op at each data output timing.
c, the memory data MQAT of the other block input to the data input terminal opd and the memory data MQAT of the other block input to the data input terminal opd are output to the output data RD (RD
0 or RD1) to the output terminal rd (data output port out0 or out1).

[Write / Read Controller WRC] The write / read controller WRC operates according to the input data identification signal DC and the write procedure of the input data.
The switching operation of the spatial cross switch SW and the writing operation of the data memories DMA and DMB are controlled, and the writing of the input data WD0 and WD1 is controlled.

The write / read controller WRC
Detects the remaining memory capacity ZAN of the data memories DMA and DMB, outputs the remaining memory capacity ZAN to the memory controller MMC, and outputs the remaining memory capacity ZAN to another block from the output terminal zano.

The write / read controller WRC
Controls the read operation of the data memories DMA and DMB and controls the read of the memory data MQA and MQB in accordance with an instruction from the main memory MMC.

[Management Memory CM] In the management memory CM,
The read / output management data for controlling the reading of the memory data MQA and MQB and the output of the read memory data MQA and MQB are stored in the memory controller MM.
Recorded by C. The read / output management data includes the read order and read address of the data memories DMA and DMB, and the memory data MQA and M
It is composed of a QB output destination and the like.

The above-mentioned read / output management data is created for each memory data and is made up of 2-bit data. The MSB of the read / output management data indicates that the memory data is
LSB of read / output management data, which is used to determine whether data has been written to data memory DMA (whether MQA) or data memory DMB (whether MQB) when reading and outputting.
Is the output destination of the memory data (the memory data is
0 data or 1 data) at the time of reading and outputting. Here, the value of the read / output management data is “00” when the memory data is the 0-system data written in the data memory DMA, and “10” when the memory data is the 0-system data written in the data memory DMB. Data memory D
The value is set to "01" for the first-system data written in the MA, and set to "11" for the first-system data written in the data memory DMB.

[Memory Controller MMC] The memory controller MMC stores the write identifier WID of its own block at the initial stage such as when turning on the power of the ATM switch.
Identifier BID of own block (identifier BID0 or BI
D1), input data output from the own block is written in the own block,
By comparing the remaining memory ZAN of the own block and the remaining memory ZANT of the other blocks with the remaining memory threshold RT, respectively, the remaining memory ZAN of the own block is obtained.
It is determined whether or not the remaining memory capacity ZANT of the other block is insufficient, and if the remaining memory capacity ZANT of the own block is insufficient, the remaining memory capacity ZANT of the other block is insufficient. If not, a write identifier exchange signal CI is sent to the other block to replace the write identifier of the other block with the identifier BID of the own block.
(= BID0 or BID1),
By changing the write identifier WID of the own block to the identifier BIDT (= BID1 or BID0) of the other block, the values of the write identifiers of the own block and the other block are exchanged, and the output of the own block is performed by exchanging the write identifier. The switch block to which the input data is written is changed to the other block, and the switch block to which the input data output from the other block is written is changed to the own block (the write block is replaced).

Therefore, when the write identifier replacement signal CIT is input from the other block, the memory controller MMC conversely writes the write identifier W of its own block.
By changing the ID to the identifier BIDT of the other block, input data to be written to the own block is changed to input data to be output from the other block.

The memory controller MMC which has exchanged the write block by sending the write identifier exchange signal CI has the remaining memory capacity ZAN of its own block.
Is restored, the replacement of the write block is restored. Further, when the remaining memory ZAN of the own block is insufficient and the remaining memory ZANT of the other block is also insufficient, the memory controller MMC does not replace the write block.

The value of the write identifier replacement signal CI is “0” when the write block is not replaced, and becomes “1” when the remaining memory ZAN is insufficient and the write block is replaced. It changes to "0" when the replacement of the write block is undone.

In the initial stage of the ATM switch, the memory controller MMC0 of the switch block SB0 sets the write identifier WID0 of the own block to the identifier BID0 of the own block, and the memory controller MMC1 of the switch block SB1 sets the write identifier WID1 of the own block. Is set as the identifier BID1 of the own block.

During the operation of the ATM switch,
The memory controller MMC0 transmits the remaining memory ZAN0 of its own block and another block (switch block SB).
The memory controller MMC1 determines whether or not the remaining memory capacity of the own block and the other blocks is insufficient based on whether or not the remaining memory capacity ZAN1 of 1) is equal to or smaller than the memory remaining capacity threshold RT. Remaining memory ZAN1 and other blocks (switch block SB0)
It is determined whether or not the remaining memory capacity of the own block and the other blocks is insufficient based on whether or not the remaining memory capacity ZAN0 is equal to or smaller than the remaining memory threshold RT.

When the remaining memory amounts ZAN0 and ZAN1 of the switch blocks SB0 and SB1 are not insufficient (when ZAN0> RT and ZAN1> RT),
The memory controller MMC0 outputs the write identifier exchange signal CI0 = "0" to the memory controller MMC1 of the switch block SB1, and the memory controller MMC1 outputs the write identifier exchange signal CI1 = "".
0 ”is set to the memory controller M of the switch block SB0.
Output to MC0. Therefore, the write blocks are not replaced, the 0-system data is written to the data memories DMA0 and DMB0 of the switch block SB0, and the 1-system data is stored in the data memory DMA of the switch block SB1.
1, written to DMB1.

Then, for example, the switch block SB0
(ZAN1> R)
T and ZAN0 ≦ RT), the memory controller MMC0 sends the write identifier exchange signal CI0
Is changed to "1", and the write identifier WID0 of the own block is changed from the identifier BID0 of the own block to the identifier BID1 of the switch block SB1. The memory controller MMC1 is a memory controller MMC
When the write identifier exchange signal CI0 = "1" is input from 0, the write identifier WID1 of the own block is changed to
Switch block SB from own block identifier BID1
Change to the identifier BID0 of 0. With the exchange of the write identifier, the exchange of the write block is performed, and the 0-system data is written into the data memories DMA1 and DMB1 of the switch block SB1.
The system data is stored in the data memory D of the switch block SB0.
The data is written to MA0 and DMB0.

After the write block is replaced by the memory controller MMC0, when the remaining memory ZAN0 of the switch block SB0 recovers (ZA
When N0> RT), the memory controller MMC0
Returns the write identifier exchange signal CI0 to "0" and returns the write identifier WID0 of the own block to the identifier BID0 of the own block. When the write identifier exchange signal CI0 = "1" is input from the memory controller MMC0, the memory controller MMC1 returns the write identifier WID1 of its own block to the identifier BID1 of its own block. By returning the exchange of the write identifier, the exchange of the write block is returned to the original, and the 0-system data is again written to the data memories DMA0 and DMB0 of the switch block SB0. The data is written to the data memories DMA1 and DMB1 of the block SB1.

The memory controller MMC controls the read of the memory data MQA and MQB by controlling the write / read controller WRC, and also controls the output selector OS by controlling the output selector OS.
The output of the read memory data MQA, MQB and the memory data MQAT, MQBT transferred from another block is controlled.

When input data is written, the memory controller MMC stores the read / output management data in accordance with the input data identification signal DC in the management memory CM.
To record.

The memory controller MMC reads the memory data and outputs the data in accordance with the read / output management data described above.
Memory data MQA or MQB from MA or DMB
And sends the memory data MQA or MQB to the output selector OS of the own block and the other block, and according to the identifier BID of the own block, the identifier BIDT of the other block, and the read / output management data, a memory data selection signal MS And sends this memory data selection signal MS to another block.

The memory data selection signal MS indicates whether the read memory data is the memory data MQA of the data memory DMA, the memory data MQB of the data memory DMB, and the data output from the own block. , Is a signal for notifying another block whether the data is output from another block. The memory data selection signal MS is 2-bit data, and the MSB of the memory data selection signal MS is the read memory data.
The LSB of the memory data selection signal MS indicates the output destination of the read memory data (the read memory data is the 0-system data or the 1-system data). ). Here, the value of the memory data selection signal MS is such that the read memory data is M
"00" for QA and 0 system data, "10" for MQB and 0 system data, "01" for MQA and 1 system data, and "01" for MQB and 1 system data.
11 ".

Further, at the time of reading and outputting the memory data, the memory controller MMC according to the memory data selection signal MST input from another block and the above-mentioned read / output management data, the memory data MQA, MQB, MQAT, One of the MQBTs is output from the output selector OS as output data RD (RO0 or RD1).

The memory data MQA and MQB are alternately read at each data output timing in the order of writing. Therefore, the memory data MQAT,
In the MQB, also in the other blocks,
The data is alternately read at each data output timing.

At the data output timing, the output destination of the memory data MQA or MQB of the own block (data output port out0 or out1) differs from the output destination of the memory data MQAT or MQBT of the other block. Data MQA or MQB
And memory data MQAT or MQBT of another block
Are the data written when the write blocks have not been exchanged (or when the exchange has been reversed), or both have been written when the write blocks have been exchanged. This is the case for data. As described above, at the data output timing where the output destination of the memory data of the own block and the output destination of the memory data of the other block are different, the memory data of the own block is output from the own block, and the memory data of the other block is output. By outputting from the block or outputting the memory data of the own block from the other block and outputting the memory data of the other block from the own block, the memory data MQA or MQB of the own block and the memory data of the other block are output. Connect MQAT or MQBT to data output port ou
It is possible to output simultaneously from t1 and out2.

However, when a switch block is replaced or replaced, the timing at which the output destination of the memory data of the own block changes and the timing at which the output destination of the memory data of another block changes. Does not always match. For this reason, at the data output timing, the output destination of the memory data of the own block matches the output destination of the memory data of the other block, and the memory data of the own block and the memory data of the other block are output to the data output ports out1 and out1. out
2 cannot be output simultaneously. At such data output timing, the memory data having the earlier write timing (input timing) of the memory data of the own block and the memory data of the other block is output to the corresponding data output port.

Therefore, when the memory data MQAT or MQBT transferred from the other block is output from the own block at the data output timing at which the output destination of the memory data of the own block matches the output destination of the memory data of the other block. , Memory data MQ of the own block
A or MQB is not read. Further, at the data output timing when the output destination of the memory data of the own block and the output destination of the memory data of the other block match,
When the memory data MQA or MQB of the own block is transferred to another block and output from the other block to the data output port, the data input terminal o of the output selector OS
It does not output any of the data input to pa, opb, opc, and opd.

As described above, the memory controller MMC
Controls the write / read controller WRC and the output selector OS at each timing of memory data read and data output, reads memory data MQA or MQB output from its own block from the data memory DMA or DMB, and outputs it from its own block. Memory data MQ output from another block
A or MQB is read from the data memory DMA or DMB and transferred to the other block, and the memory data MQAT or MQBT transferred from the other block is output from the own block, or the memory data MQA or The MQB is read from the data memory DMA or DMB and is transferred to the other block (at this time, no data is output from the own block), or the memory data MQAT or MQBT transferred from the other block is output from the own block ( At this time, no data is output from other blocks.)

For example, the value of the read / output management data of the memory data read from the data memory DMA0 or DMB0 of the switch block SB0 is “10”,
When the value of the read / output management data of the memory data read from the data memory DMA1 or DMB1 of the switch block SB1 is “01” (in this case, the memory data read from the data memories of both blocks is
In both cases, the data is written when the write blocks are not replaced.) The memory controller MMC0 of the switch block SB0 reads the memory data MQB0 and outputs it as the output data RDO, and the memory data selection signal MS0 = "10" is sent to the switch block SB1, and the switch block SB
1 of the memory controller MMC1
A1 is read and output as output data RD1, and a memory data selection signal MS1 = "01" is sent to the switch block SB1.

Further, for example, the value of the read / output management data of the memory data read from the data memory DMA0 or DMB0 of the switch block SB0 is “11” and the data memory DMA1 of the switch block SB1 is
Or read / write of memory data read from DMB1
When the value of the output management data is “00” (in this case, the memory data read from the data memories of both blocks is data written when the write blocks are exchanged). The memory controller MMC0 of the switch block SB0 reads the memory data MQB0 and outputs the memory data selection signal MS0
= “11” to the switch block SB1, and the memory controller MMC1 of the switch block SB1 reads the memory data MQA1 and outputs the memory data selection signal M
S1 = "00" is sent to the switch block SB0. The memory controller MMC0 outputs a memory data selection signal MS
Since 1 = “00”, the memory data MQA1 transferred from the switch block SB1 to the data input terminal opc of the output selector OS0 is output as output data RD0, and the memory controller MMC1 has the memory data selection signal MS0 = “11”. Switch block SB0
Outputs the memory data MQB0 transferred to the data input terminal opd of the output selector OS1 as output data RD1.

Further, for example, the value of the read / output management data of the memory data read from the data memory DMA0 or DMB0 of the switch block SB0 is “10” and the data memory DMA1 of the switch block SB1 is
Or read / write of memory data read from DMB1
When the value of the output management data is “00”, the memory controller MMC0 of the switch block SB0 reads the memory data MQB0 and outputs the memory data selection signal M
S0 = “10” is sent to the switch block SB1, and the memory controller MMC1 of the switch block SB1 sends
The memory data MQA1 is read, and a memory data selection signal MS1 = "00" is sent to the switch block SB1.

As described above, the reason why the output destinations of the memory data of the switch block SB0 and the memory data of the switch block SB1 match (the values of the LSBs of the memory data selection signals MS0 and MS1 match) is that the switch block SB0 Is the data written before the replacement of the write block, and the memory data of the switch block SB1 is the data written after the replacement of the write block, or the memory data of the switch block SB0. Is the data written after the replacement of the write block is returned, and the memory data of the switch block SB1 is the data written before the replacement of the write block is returned.

Memory Controllers MMC0 and MMC
1 are memory data selection signals MS0 and MS
1 and the number of times the LSB value of the memory data selection signals MS0 and MS1 has changed, when the output destinations of both memory data match as described above. Then, the memory data with the faster write timing is determined and output.

Memory data M of switch block SB0
When QB0 is the data written before the replacement of the write block and the memory data MQA1 of the switch block SB1 is the data written after the replacement of the write block, the memory controllers MMC0 and MMC1 , Memory data selection signal MS1 = "10", memory data selection signal MS1 = ""
00 "and memory data selection signals MS0 and MS
1 that the output destinations of both memory data coincide with each other, and that the memory data MQB
It recognizes that the write timing of 0 is earlier than the memory data MQA1. And the memory controller MM
C0 outputs the memory data MQB0 from the data input terminal opb of the output selector OS0 as output data RD0. At this time, the memory controller MMC1 does not output the output data RD1 and the memory data MQA
1 is invalidated, and the memory data MQA1 is read again at the next read and output timing.

The memory data MQB0 of the switch block SB0 is data written after the replacement of the write block is restored, and the memory data MQA1 of the switch block SB1 is changed based on the replacement of the write block. In the case of data written before returning, the memory controllers MMC0 and MMC1
Means that the output destinations of both memory data coincide with each other according to the memory data selection signal MS1 = "10", the memory data selection signal MS1 = "00", and the number of times the LSB value of the memory data selection signals MS0 and MS1 has changed. , And that the write timing of the memory data MQA1 is earlier than that of the memory data MQB0. And
The memory controller MMC0 stores the memory data MQA transferred to the data input terminal opc of the output selector OS0.
1 is output as output data RD0. At this time, the memory controller MMC0 transmits the memory data MQ
The reading of B0 is invalidated, and the memory data MQB0 is read again at the next reading and output timing. Further, the memory controller MMC1 does not output the output data RD1.

As described above, in the ATM switch according to the first embodiment, the input unit IU corresponds to a unit for assigning an identifier to each output buffer device (switch block). Further, in the switch blocks SB0 and SB1 of the ATM switch according to the first embodiment, the data memories DMA,
DMB corresponds to a data memory in which input data WD0 and WD1 are written.

The memory controller MMC corresponds to a means for initially setting the write identifier WID of its own device to the identifier BID of its own device.

The input data identification circuit IDC, the write / read controller WRC, and the spatial cross switch SW store the input data WD0, WD1 assigned with the address corresponding to the write identifier WID of the own device in the data memories DMA, DMB. The means for writing to is configured.
Note that, in the first embodiment, the above address corresponds to the output destination address included in the header portion of the input data WD0 and WD1, or the address signals WA0 and WA1.

The write / read controller WRC
Corresponds to a unit that detects the remaining memory ZAN of the own apparatus and notifies the other output buffer apparatus of the remaining memory.
In addition, when the remaining memory capacity (remaining data memory capacity) of the memory controller MMC is insufficient, the memory controller MMC outputs the write identifier replacement signal CI to another output buffer device having the sufficient remaining memory capacity, The write identifier WID of the own device is replaced with the identifier BID (BID0
Alternatively, it corresponds to a means for changing the identifier BIDT (BID1 or BID0) of the other output buffer device from BID1).

The memory controller MMC receives a write identifier exchange signal CI from another output buffer device.
When T is input, the write identifier WID of the own device
Is changed from the identifier BID of the own device to the identifier BIDT of the other output buffer device.

Further, the memory controller MMC, the management memory CM, and the output selector OS send the input data (WD) to which the address corresponding to the identifier BID of the own device is attached.
0 or WD1) from its own data memory DMA or DMB and read out its own data output port (ou).
t0 or out1), or read out input data with an address corresponding to the identifier BIDT of another output buffer device from its own data memory DMA or DMB and transfer it to the other output buffer device. Either output the input data attached with the address corresponding to the identifier BID of the own device transferred from the other output buffer device to the data output port of the own device, or input the address corresponding to the identifier BIDT of the other output buffer device Is read from the data memory DMA or DMB of the own device and transferred to the other output buffer device (at this time, no data is output to the data output port of the own device) or another output An address corresponding to the identifier BID of the own device transferred from the buffer device is added. And it outputs the input data to the output port of the apparatus (this time, the data memory DMA of the self apparatus
Alternatively, data read from the DMB is invalidated).

Next, the operation of the ATM switch according to the first embodiment will be described below. First, switch block S
The data write operation when the remaining memory amounts of B0 and SB1 are not both short and the write blocks are not replaced will be described. FIG. 3 is a timing chart illustrating a data write operation in the case where write blocks are not exchanged in the ATM switch according to the first embodiment of the present invention. FIG. 4 shows the data memories DMA0, DMB0,
FIG. 3 is a diagram for explaining the written contents of DMA1, DMB1 and management memories CM0, CM1. In FIG.
(A) shows the contents of the data memories DMA0 and DMB0,
(B) shows the contents of the data memories DMA1 and DMB1,
(C) shows the contents of the management memory CM0, and (d) shows the contents of the management memory CM1.

In FIG. 3, input data WD0, WD1
Are valid data, and the input enable signals WE0 and WE1 are "Vaild" in all periods.
(Valid, write-enabled).

In FIG. 3, the remaining memory capacity ZAN
0, ZAN1 is larger than the remaining memory threshold RT (= 4) in all periods (ZAN0> RT, ZAN1).
> RT), not shortage. For this reason, the memory controllers MMC0 and MMC1 set the write identifier exchange signals CI0 and CI1 to “0” during the entire period, and change the write identifiers WID0 and WID1 to W0 during the entire period.
ID0 = BID0 = “00”, WID1 = BID1 = ”
01 ".

Therefore, in the entire period, the address signal W
The input data WD0 with A0 = “00” and the input data WD1 with address signal WA1 = “00” are written into the data memories DMA0 and DMB0, and the input data WD0 and address signal WA1 with the address signal WA0 = “01”. = 01, the input data WD1
The data is written to the data memories DMA1 and DMB1.

First, at a timing T1, the input data WD0 = "" is applied to the switch blocks SB0 and SB1.
d00 ", WD1 =" d10 ", and the address signal W
A0 = “01” and WA1 = “00” are input.

At the timing T1, since the remaining memory capacity ZAN0 = m> RT = 4, the memory controller MMC0 changes the write identifier replacement signal CI0 to "
0 ”and the switch block SB0
The write identifier WID0 of the switch block SB0 is maintained as the identifier BID0 = “00”.

Similarly, the remaining memory capacity ZAN1 = m> R
Since T = 4, the memory controller MMC1 keeps the write identifier exchange signal CI1 at “0” and also writes the write identifier WI of the switch block SB1.
D1 is the identifier BID1 of the switch block SB1 = "0"
1 ”is maintained.

Next, at a timing T2, the input data identification circuit IDC0 outputs the address signal WA0 = "0".
1 ", WA1 =" 00 "and the write identifier WID
Since 0 = "00", only the input data WD1 = "d10" is identified as data to be written into the data memories DMA0 and DMB0, and the input data identification signal DC0 = "10".
To the memory controller MMC0 and the write / read controller WRC0.

Similarly, the input data identification circuit IDC1
Are the address signals WA0 = “01” and WA1 = “00”
Since the write identifier WID1 = "01", only the input data WD0 = "d00" is stored in the data memory DMA.
1, the data to be written to DMB1 is identified, and the input data identification signal DC1 = "01" is supplied to the memory controller M
Send to MC1 and write / read controller WRC1.

Next, at the timing T3, the write /
Read controller WRC0 receives input data identification signal D
According to C0 = "10", the spatial type cross switch SW0
And control the data memories DMA0 and DMB0 to write the input data WD1 = "d10" to the address ADD = 0 of the data memory DMA0 (see FIG. 4A). Then, the write / read controller WRC0 reduces the remaining memory ZAN0 from m to m-1.

Similarly, the write / read controller WRC1 controls the spatial cross switch SW1 and the data memories DMA1 and DMB1 according to the input data identification signal DC1 = "01", and the input data WD0 = "d".
00 "is written to the address ADD = 0 of the data memory DMA1 (see FIG. 4B). Then, the write / read controller WRC1 reduces the remaining memory ZAN1 from m to m-1.

At the timing T3, the memory controller MMC0 sets the input data identification signal DC0 = ”
Based on 10 "and the write identifier WID0 =" 00 ", the number (one) of input data written and the output destination (data output port out0) are determined, and the input data WD1 =""written in the data memory DMA0. d10 "
The read / output management data = "00" is created, and this read / output management data is recorded in the address ADC = 0 of the management memory CM0 (see FIG. 4C).

Similarly, the memory controller MMC1
Determines the number (one) of input data written and the output destination (data output port out1) based on the input data identification signal DC1 = "01" and the write identifier WID1 = "01", and The read / output management data = "01" of the input data WD0 = "d00" written in the DMA1 is created, and the read / output management data is recorded at the address ADC = 0 of the management memory CM1 (see FIG. 4D). ).

Next, at timing T4, the input data WD0 = "" is applied to the switch blocks SB0 and SB1.
d01 ", WD1 =" d11 ", and the address signal W
A0 = “01” and WA1 = “01” are input.

Next, at timing T5, the input data identification circuit IDC0 outputs the address signal WA0 = "0".
1 ", WA1 =" 01 "and the write identifier WID
Since 0 = “00”, the input data WD0 and WD1 are both identified as not data to be written to the data memories DMA0 and DMB0, and the input data identification signal DC0 = “00” is sent to the memory controller MMC0 and the write / read controller WRC0.

Similarly, input data identification circuit IDC1
Are the address signals WA0 = “01”, WA1 = “01”
Since the write identifier WID1 = "01", the input data WD0 = "d01" and WD1 = "d11" are both identified as data to be written into the data memories DMA1 and DMB1, and the input data identification signal DC1 = "11".
To the memory controller MMC1 and the write / read controller WRC1.

Next, at timing T6, the write /
Read controller WRC0 receives input data identification signal D
Since C0 = "00", the data memories DMA0 and DMB
Do not write input data to 0. For this reason, the remaining memory ZAN0 = m-1.

On the other hand, the write / read controller WRC1 controls the spatial cross switch SW1 and the data memories DMA1 and DMB1 according to the input data identification signal DC1 = “11”, and the input data WD0 = “d”.
01 "is written to the address ADD = 0 of the data memory DMB1, and the input data WD1 =" d11 "is written to the address ADD = 1 of the data memory DMA1 (FIG. 4).
(B)). And the write / read controller W
RC1 reduces the remaining memory ZAN1 from m-1 to m-3.

At the timing T6, the memory controller MMC0 sets the input data identification signal DC0 = ”
00 ”, it is determined that there is no written input data, and no read / output management data is created.

On the other hand, the memory controller MMC1
Determines the number (2) of input data written and the output destination (data output port out1) based on the input data identification signal DC1 = "11" and the write identifier WID1 = "01", The input data WD0 written to the DMB1 = read / output management data of "d01" = "11", and the input data WD1 written to the data memory DMA1 = read / output management data of "d11" = "01", These read /
The output management data is stored in the address ADC of the management memory CM1 =
1 and 2 (see FIG. 4D).

Next, at timing T7, the input data WD0 = "" is applied to the switch blocks SB0 and SB1.
d02 ", WD1 =" d12 ", and the address signal W
A0 = “00” and WA1 = “00” are input.

Next, at a timing T8, the input data identification circuit IDC0 outputs the address signal WA0 = "0".
0 ", WA1 =" 00 "and the write identifier WID
Since 0 = “00”, the input data WD0 = “d02”,
WD1 = “d12” for both data memories DMA0, DMA
The input data identification signal DC0 = "11" is identified as data to be written to MB0, and the memory controller MMC0
And write / read controller WRC0.

On the other hand, the input data identification circuit IDC1
Are the address signals WA0 = "00" and WA1 = "00"
Since the write identifier WID1 = "01", both the input data WD0 and WD1 are in the data memory DMA.
1, it is determined that the data is not data to be written to DMB1, and the input data identification signal DC1 = "00" is supplied to the memory controller M
Send to MC1 and write / read controller WRC1.

Next, at timing T9, the write /
Read controller WRC0 receives input data identification signal D
According to C0 = “11”, the spatial cross switch SW0
And control the data memories DMA0 and DMB0, and write the input data WD0 = "d02" to the address ADD = 0 of the data memory DMB0, and input data WD1 = "d".
12 "is written to the address ADD = 1 of the data memory DMA0 (see FIG. 4A). Then, the write / read controller WRC0 sets the remaining memory ZAN0 to m-1.
From m to m-3.

On the other hand, the write / read controller WRC1 does not write the input data to the data memories DMA1 and DMB1 because the input data identification signal DC1 = "00". For this reason, the remaining memory capacity ZAN1 = m-3.

At the timing T6, the memory controller MMC0 sets the input data identification signal DC0 = ”
11 "and the write identifier WID0 =" 00 ", the number (two) of input data written and the output destination (data output port out0) are determined, and the input data WD0 =""written to the data memory DMB0. d02 "
Read / output management data = "10", and input data WD1 written to data memory DMA0 = "d1".
2 "read / output management data =" 00 "is created,
These read / output management data are stored in the management memory CM0.
At the address ADC = 1, 2 (see FIG. 4C).

On the other hand, the memory controller MMC1
Since the input data identification signal DC1 = "00", it is determined that no input data has been written, and no read / output management data is created.

Next, a read operation of data written by the data write operation of FIG. 3 will be described.
FIG. 5 is a timing chart illustrating a read operation of data written by the data write operation of FIG.

At the timing T11 in FIG. 5, the write contents of the data memories DMA0, DMB0, DMA1, DMB1 and the management memories CM0, CM1 are as shown in FIGS. 4A to 4D, respectively. I do. Further, the data memories DMA0, DMB0, DMA1, and DM
The data written at the address ADD = 0 (the address of the reading order 1) of B1 is the memory data MQA0, MQB0, MQA1, MQB1, respectively, and these memory data MQA0, MQB0, MQA1, M
QB1 is the data memory DMA0, DMB0, DMA
1, it is assumed that the signal is always output from DMB1.

First, at timing T11, the memory controller MMC0 reads the memory data selection signal MS0 according to the read / output management data at the address ADC = 0 of the management memory CM0 = "00" (see FIG. 4C).
= “00” and sends it to the memory controller MMC1.

Similarly, the memory controller MMC1
Generates the memory data selection signal MS1 = "01" according to the read / output management data at the address ADC = 0 of the management memory CM1 = "01" (see FIG. 4D);
To the memory controller MMC0.

Next, at timing T12, the memory controller MMC0 sets the identifier BID0 of the switch block SB0 = “00”, the read / output management data at the address ADC = 0 of the management memory CM0 = “00”, and the memory data selection signal. Based on MS1 = "01"
It is determined that the data output from the output selector OS0 is the memory data MQA0 = "d10" of the data memory DMA0, and this memory data MQA0 = "d10" is output from the output selector OS0 as the output data RD0. Note that the output data RD0 = "d10" is output until timing T14.

Similarly, the memory controller MMC1
Is the identifier BID1 of the switch block SB1 = "0"
1 ", read / output management data of address ADC = 0 of management memory CM1 =" 01 ", and output selector OS1 based on memory data selection signal MS0 =" 00 ".
Is determined that the memory data MQA1 of the data memory DMA1 = "d00", and the memory data MQA1 = "d00" is output from the output selector OS1 as the output data RD1. The output data RD1 = "d00" is output until timing T14.

Next, at timing T13, the memory controller MMC0 shifts the read / output management data of the address ADC = 1, 2,... Of the management memory CM0 to the address ADC = 0, 1,. It is assumed that read / output management data of 0 = "10". Further, the memory controller MMC0 and the write / read controller WRC0 are connected to the data memory DMA
The data of the address ADD = 1, 2,... Is shifted to the address ADD = 0, 1,..., Respectively, so that the memory data MQA0 = "d12".

Similarly, the memory controller MMC1
.. Read / output management data at addresses ADC = 1, 2,...
., And the read / output management data at the address ADC = 0 is set to “11”. Further, the memory controller MMC1 and the write / read controller WRC1 provide the address ADD =
The data of 1, 2,...
.., And the memory data MQA1 = “d1”
1 ".

Next, at timing T14, the memory controller MMC0 generates a memory data selection signal MS0 = "10" according to the read / output management data = "10" of the address ADC = 0 of the management memory CM0, and Send to MMC1.

Similarly, the memory controller MMC1
Generates the memory data selection signal MS1 = "11" according to the read / output management data = "11" of the address ADC = 0 of the management memory CM1, and sends it to the memory controller MMC0.

Next, at timing T15, the memory controller MMC0 sets the identifier BID0 of the switch block SB0 = “00”, the read / output management data at the address ADC = 0 of the management memory CM0 = “10”, and the memory data selection signal. Based on MS1 = "11"
It is determined that the data output from the output selector OS0 is the memory data MQB0 = "d02" of the data memory DMB0, and the memory data MQB0 = "d02" is output from the output selector OS0 as the output data RD0.

Similarly, the memory controller MMC1
Is the identifier BID0 of the switch block SB1 = "0"
1 ", read / output management data of address ADC = 0 of management memory CM1 =" 11 ", and output selector OS1 based on memory data selection signal MS0 =" 10 ".
Is determined that the memory data MQB1 = "d01" of the data memory DMB1, and this memory data MQB1 = "d01" is output from the output selector OS1 as the output data RD1.

Next, at timing T16, the memory controller MMC0 shifts the read / output management data of the address ADC = 1, 2,... Of the management memory CM0 to the address ADC = 0, 1,. It is assumed that the read / output management data of 0 = "00". Further, the memory controller MMC0 and the write / read controller WRC0 are connected to the data memory DMB.
The data of the address ADD = 1, 2,... Is shifted to the address ADD = 0, 1,.

Similarly, the memory controller MMC1
.. Read / output management data at addresses ADC = 1, 2,...
., And the read / output management data at the address ADC = 0 is set to “01”. In addition, the memory controller MMC1 and the write / read controller WRC1 provide an address ADD =
The data of 1, 2,...
Shift to 1, ...

Next, at timing T17, the memory controller MMC0 generates a memory data selection signal MS0 = "00" in accordance with the read / output management data at the address ADC = 0 of the management memory CM0 = "00". Send to MMC1.

Similarly, the memory controller MMC1
Generates the memory data selection signal MS1 = "01" in accordance with the read / output management data = "01" of the address ADC = 0 of the management memory CM1, and sends it to the memory controller MMC0.

Next, at timing T18, the memory controller MMC0 sets the identifier BID0 of the switch block SB0 = “00”, the read / output management data at the address ADC = 0 of the management memory CM0 = “00”, and the memory data selection signal. Based on MS1 = "01"
It is determined that the data output from the output selector OS0 is the memory data MQA0 = "d12" of the data memory DMA0, and the memory data MQA0 = "d12" is output from the output selector OS0 as the output data RD0.

Similarly, the memory controller MMC1
Is the identifier BID1 of the switch block SB1 = "0"
1 ", read / output management data of address ADC = 0 of management memory CM1 =" 01 ", and output selector OS1 based on memory data selection signal MS0 =" 00 ".
Is determined that the memory data MQA1 of the data memory DMA1 = "d11", and the memory data MQA1 = "d11" is output from the output selector OS1 as the output data RD1.

Next, at timing T19, the memory controller MMC0 shifts the read / output management data of the address ADC = 1, 2,... Of the management memory CM0 to the address ADC = 0, 1,. Further, the memory controller MMC0 and the write / read controller WRC0 transfer the data of the address ADD = 1, 2,.
DD = 0, 1,...

Similarly, the memory controller MMC1
.. Read / output management data at addresses ADC = 1, 2,...
Shift to 0, 1, .... Further, the memory controller MMC1 and the write / read controller WRC1
Are the addresses ADD = 1, 2, 2 of the data memory DMA1.
.. Are shifted to addresses ADD = 0, 1,.

Next, the switch block SB0 or SB
The data write operation in the case where the remaining memory of 1 is insufficient and the write block is replaced will be described. FIG. 6 is a timing chart illustrating a data write operation when a write block is exchanged in the ATM switch according to the first embodiment of the present invention. FIG.
Is a data memory DMA by the data write operation of FIG.
0, DMB0, DMA1, DMB1 and management memory C
FIG. 7 is a diagram for explaining the written contents of M0 and CM1. FIG.
In (a), the contents of the data memories DMA0 and DMB0, (b) the contents of the data memories DMA1 and DMB1, (c) the contents of the management memory CM0, and (d) the contents of the management memory CM1.

In FIG. 6, input data WD0, WD1
Are valid data, and the input enable signals WE0 and WE1 are "Vaild" in all periods.
(Valid, write-enabled).

In FIG. 6, after timing T23, the remaining memory ZAN1 of the switch block SB1 becomes insufficient, and after timing T24, the write blocks are replaced.

First, at timing T21, the input data WD0 is applied to the switch blocks SB0 and SB1.
= "D00", WD1 = "d10", and the address signals WA0 = "00", WA1 = "01".

At timing T21, since the remaining memory capacity ZAN0 = 12> RT = 4, the memory controller MMC0 sends the write identifier replacement signal CI0
= “0” and the switch block S
The write block identifier WID0 of B0 is held as the identifier BID0 = "00" of the switch block SB0.

Similarly, the remaining memory capacity ZAN1 = 5> R
Since T = 4, the memory controller MMC1 keeps the write identifier exchange signal CI1 at “0” and sets the write block identifier WID1 of the switch block SB0 to the identifier BID of the switch block SB1.
1 is kept as "01".

Next, at a timing T22, the input data identification circuit IDC0 outputs the address signal WA0 = "0".
0 ", WA1 =" 01 "and the write identifier WID
Since 0 = “00”, only the input data WD0 = “d00” is identified as the data to be written to the data memories DMA0 and DMB0, and the input data identification signal DC0 = “01”.
To the memory controller MMC0 and the write / read controller WRC0.

Similarly, input data identification circuit IDC1
Are the address signals WA0 = “00” and WA1 = “01”
Since the write identifier WID1 = "01", only the input data WD1 = "d01" is stored in the data memory DMA.
1, the data to be written to DMB1 is identified, and the input data identification signal DC1 = "10"
Send to MC1 and write / read controller WRC1.

Next, at timing T23, the write / read controller WRC0 responds to the input data identification signal DC0 = "01" by using the spatial cross switch SW
0 and the data memories DMA0 and DMB0 and input data WD0 = "d00" to the data memory DMA0.
(ADD free address) (see FIG. 7A). Then, the write / read controller WRC0 reduces the remaining memory ZAN0 from 12 to 11.

Similarly, the write / read controller WRC1 controls the spatial cross switch SW1 and the data memories DMA1 and DMB1 according to the input data identification signal DC1 = “10”, and the input data WD1 = “d”.
10 "is the address ADD of the data memory DMB1 = n-
2 (write free address) (see FIG. 7B). Then, the write / read controller WRC1
Reduces the remaining memory ZAN1 from 5 to 4.

At timing T23, memory controller MMC0 outputs input data identification signal DC0.
= “01” and the write identifier WID0 = “00”, the number (one) of the input data written and the output destination (data output port out0) are determined, and the input data WD0 written to the data memory DMA0 is determined. = "D0
Create read / output management data of “0” = “00”,
This read / output management data is recorded at the address ADC = m-11 in the management memory CM0 (see FIG. 7C).

Similarly, the memory controller MMC1
Determines the number (one) of input data written and the output destination (data output port out1) based on the input data identification signal DC1 = "10" and the write identifier WID1 = "01", The read / output management data = "01" of the input data WD1 = "d10" written in the DMA1 is created, and this read / output management data is recorded in the address ADC = m-4 of the management memory CM1 (FIG. 7 (d) )reference).

Next, at timing T24, the input data WD0 is applied to the switch blocks SB0 and SB1.
= “D01”, WD1 = “d11”, and the address signals WA0 = “01”, WA1 = “01”.

At timing T24, since the remaining memory capacity ZAN0 = 11> RT = 4, the memory controller MMC0 sends the write identifier exchange signal CI0
Is maintained as “0”.

On the other hand, since the remaining memory capacity ZAN1 = 4 and ZAN1 ≦ RT = 4, the memory controller MMC1 determines that the remaining memory capacity ZAN1 of the switch block SB1 is insufficient. Then, after confirming that the remaining memory ZAN0 of the switch block SB0 is not insufficient (at this time, the remaining memory ZAN0 <RT), the memory controller MMC1 changes the write identifier replacement signal CI1 to “1”. And the write identifier WI of the switch block SB1.
D1 is the identifier BID0 of the switch block SB0 = "
00 ”.

The memory controller MMC0 receives the write identifier exchange signal C from the memory controller MMC1.
When I1 = "1" is input, the switch block SB0
Write identifier WID0 of switch block SB1
Identifier BID1 = “01”.

Therefore, after the timing T24, the write blocks are exchanged, and the address signals WA0 and WA1 are changed.
Are written to the switch block SB1, and the input data WA0 and WA1 whose address signals WA0 and WA1 are "01" are written to the switch block SB0. Will be able to

Next, at timing T25, the input data identification circuit IDC0 outputs the address signal WA0 = "0".
1 ", WA1 =" 01 "and the write identifier WID
Since 0 = BID1 = “01”, the input data WD0 = ”
Both d01 "and WD1 =" d11 "are stored in the data memory D
It identifies that it is data to be written to MA0 and DMB0, and sends an input data identification signal DC = "11" to the memory controller MMC0 and the write / read controller WRC0.

Similarly, input data identification circuit IDC1
Are the address signals WA0 = “01”, WA1 = “01”
And the write identifier WID1 = BID0 = “00”
Therefore, the input data WD0 and WD1 are both identified as not data to be written to the data memories DMA1 and DMB1, and the input data identification signal DC1 = "00" is set to the memory controller MMC1 and the write / read controller WR.
Send to C1.

Next, at a timing T26, the write / read controller WRC0 responds to the input data identification signal DC0 = "11" by using the spatial cross switch SW.
0 and the data memories DMA0 and DMB0, and the input data WD0 = "d01" is written to the address ADD = n-5 of the data memory DMB1, and the input data WD1
= “D11” is the address ADD of the data memory DMA1
= N-4 (see FIG. 7A). Then, the write / read controller WRC0 sends the remaining memory ZAN
1 is reduced from 11 to 9.

On the other hand, the write / read controller WRC1 does not write the input data to the data memories DMA1 and DMB1 because the input data identification signal DC1 = "00". Therefore, the remaining memory capacity ZAN0 = 4.

Next, at timing T27, input data WD0 is applied to switch blocks SB0 and SB1.
= "D02", WD1 = "d12", and address signals WA0 = "01", WA1 = "00".

At the timing T27, since the remaining memory capacity ZAN1 = 4 ≦ RT, the memory controller M
MC1 sets the write identifier exchange signal CI1 to "1".
Keep as is.

Next, at timing T28, the input data identification circuit IDC0 sets the address signal WA0 = “0”.
1 ", WA1 =" 00 "and the write identifier WID
Since 0 = BID1 = “01”, the input data WD0 = ”
d02 "alone is identified as data to be written to the data memories DMA0 and DMB0, and the input data identification signal DC
= “01” to the memory controller MMC0 and the write / read controller WRC0.

Similarly, input data identification circuit IDC1
Are the address signals WA0 = “01” and WA1 = “00”
And the write identifier WID1 = BID0 = “00”
Therefore, only the input data WD1 = “d12” is identified as the data to be written to the data memories DMA1 and DMB1, and the input data identification signal DC1 = “10” is identified by the memory controller MMC1 and the write / read controller WR.
Send to C1.

Next, at timing T29, the write / read controller WRC0 sets the spatial cross switch SW in accordance with the input data identification signal DC0 = "01".
0 and the data memories DMA0 and DMB0 and input data WD0 = "d02" to the data memory DMB0.
(ADD free address) (see FIG. 7A). Then, the write / read controller WRC0 reduces the remaining memory ZAN0 from 9 to 8.

Similarly, the write / read controller WRC1 controls the spatial cross switch SW1 and the data memories DMA1 and DMB1 according to the input data identification signal DC1 = "10", and the input data WD1 = "d".
12 "is the address ADD of the data memory DMA1 = n-
1 (write free address) (see FIG. 7B). Then, the write / read controller WRC1
Reduces the remaining memory ZAN1 from 4 to 3.

Remaining memory capacity ZA of switch block SB1
N1 is insufficient when the input of the 1-system data is concentrated. At this time, the input of the 0-system data is sparse, and therefore, the data memory of the switch block SB1 is sparse.
In the conventional ATM switch, even if the remaining memory ZAN1 of the switch block SB1 is insufficient, the timing T25,
In the writing of T28, three 1-system data WD0
= "D01", WD1 = "d11", WD0 = "d0"
2 "is written in the switch block SB1, and the remaining memory ZAN1 of the switch block SB1 becomes 1. Therefore, if one more system 1 data is written in the switch block SB1, the remaining memory ZAN1 = 0,
Subsequent 1-system data will be discarded.

On the other hand, in the ATM switch according to the first embodiment, the remaining memory ZA of the switch block SB1 is set.
If N1 is insufficient, the write block is replaced at timing T24, so that timings T25 and T28
In the writing of three, the first system data WD0 = “d0”
1 ", WD1 =" d11 ", WD0 =" d02 "are the switch blocks SB in which the remaining memory ZAN0 is not insufficient.
0, and one 0-system data WD1 = “d12”
Is written into the switch block SB1, and the remaining memory ZAN1 of the switch block SB1 becomes 3. For this reason, there is room for writing three 0-system data before the remaining memory ZAN1 = 0 and the 0-system data is discarded.

As described above, in the ATM switch according to the first embodiment, when the remaining memory ZAN1 is insufficient, the write block is replaced at the timing T24 to write the first system data into the switch block SB0. It is possible to suppress a further decrease in the remaining memory remaining amount ZAN1 and prevent the first system data from being discarded.

Next, a read operation of data written by the data write operation of FIG. 6 will be described.
FIG. 8 is a timing chart illustrating a read operation of data written by the data write operation of FIG.

At the time T31 in FIG. 8, the contents of the data memory DMA0 are the data of the address ADD = n-4, n-3,. ., And the contents of the data memory DMB0 are the data of the addresses ADD = n−5, n−4,.
The addresses are shifted to ADD = 0, 1,..., Respectively.
7B, the data at the address ADD = n−1, n is shifted to the address ADD = 0, 1, respectively. The contents of the data memory DMB1 are as shown in FIG.
In (b), the address ADD = n−2, n−1,.
Are shifted to addresses ADD = 0, 1,..., Respectively.

At the time T31 in FIG.
The contents of the management memory CM0 are obtained by shifting the data of the address ADC = m-10, m-9,... To the address ADC = 0, 1,. 7D, the data of the address ADC = m−4, m−5,.
It is assumed that the addresses are shifted to ADC = 0, 1,.

That is, at the timing T31 in FIG. 8, in FIG. 7A, the data of the addresses ADD = 0 to n-5 of the data memory DMA0 and the data of the addresses ADD = 0 to n-6 of the data memory DMB0 in FIG. The data has already been output, and in FIG. 7B, the data of the address ADD = 0 to n-2 of the data memory DMA1 and the address ADD = 0 to n-3 of the data memory DMB1.
It is assumed that the data has already been output.

Therefore, at the timing T31 in FIG. 8, the memory data MQA0 = “d11”, the memory data MQB0 = “d01”, and the memory data MQA
A1 = “d12” and the memory data MQB1 = “d
10 ".

The data memories DMA0, DMB0,
The data written to the address ADD = 0 (the address of the reading order 1) of the DMA1 and DMB1 are the memory data MQA0, MQB0, MQA1, and MQB, respectively.
1 and these memory data MQA0, MQB0,
MQA1 and MQB1 are data memories DMA0 and DMB
0, DMA1, and DMB1 are always output.

First, at the timing T31, the memory controller MMC0 reads out / outputs the management data of the address ADC = 0 of the management memory CM0 = “11” (in FIG. 7C, the read / output of the address ADC = m−10). The memory controller MM generates a memory data selection signal MS0 = "11" according to the output management data).
Send to C1.

Similarly, the memory controller MMC1
Is read / output management data at address ADC = 0 in management memory CM1 = “11” (in FIG. 7D,
Read / output management data at address ADC = m-4)
Generates a memory data selection signal MS1 = "11" and sends it to the memory controller MMC0.

Next, at timing T32, the memory controller MMC0 sets the identifier BID0 of the switch block SB0 = “00”, the read / output management data at the address ADC = 0 of the management memory CM0 = “11”, and the memory data selection signal. Based on MS1 = “11” and the like, both the memory data MQB0 = “d01” and the memory data MQB1 = “d10” of the switch block SB1 are data output from the output selector OS1 of the switch block SB1, and output at this timing. The selector OS1 preferentially outputs the memory data M written before the replacement of the write block.
It is determined that QB1 = "d10" and the output selector OS
From 0, no memory data is output.

Similarly, the memory controller MMC1
Is the identifier BID1 of the switch block SB1 = "0"
1 ", read / output management data at address ADC = 0 in management memory CM1 =" 11 ", and memory data selection signal MS0 =" 11 ".
QB1 = “d10” and the memory data MQB0 = “d01” of the switch block SB0 are both data output from the output selector OS1, and the output from the output selector OS1 with priority at this timing is before the replacement of the write block. It is determined that the memory data MQB1 = “d10” written in the memory is written, and this memory data MQB1 = “d10” is output from the output selector OS1 as the output data RD1. Note that the output data RD1 = "d10" is output until timing T34.

Next, at timing T33, the memory controller MMC1 shifts the read / output management data of the address ADC = 1, 2,... Of the management memory CM1 to the address ADC = 0, 1,. 0 read / output management data = "00"
(In FIG. 7D, the read / output management data of the address ADC = m−3). Further, the memory controller MMC1 and the write / read controller WR
C1 is the address ADD = 1 of the data memory DMA1,
The data ADD = 0, 1,.
And the memory data MQA1 = “d04”.

On the other hand, memory controller MMC0
Indicates that the memory data MQ
Since B0 = “d01” was not output from the output selector OS1, the reading of the memory data MQB0 = “d01” is determined to be invalid, and the read / output management data of the management memory CM0 is not shifted. Further, the memory controller MMC0 and the write / read controller W
RC0 does not shift the data in data memory DMB0. Therefore, the memory data MQB0 is held as “d01”.

Next, at timing T34, the memory controller MMC0 generates the memory data selection signal MS0 = "11" in accordance with the read / output management data = "11" of the address ADC = 0 of the management memory CM0, and Send to MMC1.

Similarly, the memory controller MMC1
Generates the memory data selection signal MS1 = "00" according to the read / output management data = "00" of the address ADC = 0 of the management memory CM1 and sends it to the memory controller MMC0.

Next, at timing T35, the memory controller MMC0 sets the identifier BID0 of the switch block SB0 = “00”, the read / output management data at the address ADC = 0 of the management memory CM0 = “11”, and the memory data selection signal. Based on MS1 = "00"
The data output from the output selector OS0 is the memory data MQA1 = "" transferred from the switch block SB1.
d12 ", and the memory data MQA1
= “D12” is output from the output selector OS0 to the output data RD
Output as 0.

Similarly, the memory controller MMC1
Is the identifier BID0 of the switch block SB1 = "0"
1 ", read / output management data of address ADC = 0 of management memory CM1 =" 00 ", and output selector OS1 based on memory data selection signal MS0 =" 11 ".
It is determined that the memory data MQB0 = “d01” transferred from the switch block SB0 is output from the switch block SB0, and this memory data MQB0 = “d01” is output from the output selector OS1 as output data RD1.

Next, at timing T36, the memory controller MMC0 shifts the read / output management data of the address ADC = 1, 2,... Of the management memory CM0 to the address ADC = 0, 1,. 0 read / output management data = "01"
(In FIG. 7C, the read / output management data at the address ADC = m−9). Further, the memory controller MMC0 and the write / read controller WR
C0 is the address ADD = 1 of the data memory DMB0,
The data ADD = 0, 1,.
And the data memory DMB0 = “d02”.

Similarly, the memory controller MMC1
.. Read / output management data at addresses ADC = 1, 2,...
., And the read / output management data at the address ADC = 0 = “10” (in FIG. 7D, the read / output management data at the address ADC = m−2). Further, the memory controller MMC1 and the write / read controller WRC1 shift the data of the address ADD = 1, 2,... Of the data memory DMA1 to the address ADD = 0, 1,.

Next, at timing T37, the memory controller MMC0 generates the memory data selection signal MS0 = "01" in accordance with the read / output management data = "01" of the address ADC = 0 of the management memory CM0, and Send to MMC1.

Similarly, the memory controller MMC1
Generates the memory data selection signal MS1 = "10" according to the read / output management data = "10" of the address ADC = 0 of the management memory CM1, and sends it to the memory controller MMC0.

Next, at timing T38, the memory controller MMC0 sets the identifier BID0 of the switch block SB0 = “00”, the read / output management data at the address ADC = 0 of the management memory CM0 = “01”, and the memory data selection signal. Based on MS1 = "10"
The data output from the output selector OS0 is the memory data MQB1 = "" transferred from the switch block SB1.
d04 ", and the memory data MQB1
= “D04” is output from the output selector OS0 to the output data RD
Output as 0.

Similarly, the memory controller MMC1
Is the identifier BID1 of the switch block SB1 = "0"
1 ", read / output management data of address ADC = 0 of management memory CM1 =" 10 ", and memory selector signal MS0 =" 01 ", output selector OS1
It is determined that the memory data MQA0 = “d11” transferred from the switch block SB0 is output from the switch block SB0, and this memory data MQA0 = “d11” is output from the output selector OS1 as the output data RD1.

Next, at timing T39, the memory controller MMC0 shifts the read / output management data of the address ADC = 1, 2,... Of the management memory CM0 to the address ADC = 0, 1,. 0 read / output management data = "11"
(In FIG. 7C, the read / output management data at the address ADC = m−8). Further, the memory controller MMC0 and the write / read controller WR
C0 is an address ADD = 1 of the data memory DMA0,
The data ADD = 0, 1,.
To make the data memory DMA0 = "d03".

Similarly, the memory controller MMC1
.. Read / output management data at addresses ADC = 1, 2,...
Shift to 0, 1, .... Further, the memory controller MMC1 and the write / read controller WRC1
Are the addresses ADD = 1,2,2 of the data memory DMB1.
.. Are shifted to addresses ADD = 0, 1,.

As described above, according to the first embodiment, the remaining memory ZAN0 of switch block SB0 is detected by write / read controller WRC0 of switch block SB0, and the remaining memory ZAN1 of switch block SB1 is detected by switch block SB1. Detected by the write / read controller WRC1, when either the remaining memory ZAN0 or ZAN1 of the switch block SB0 or SB1 becomes insufficient, the 0-system data is output by the memory controller MMC0 of the switch block SB0 and the memory controller MMC1 of the switch block SB1. Is changed from the switch block SB0 to the switch block SB1, and the switch block for writing the 1-system data is changed to the switch block SB. By the change in the switch block SB0 (replacing the write block),
When the memory capacity is the same as that of the conventional ATM switch, the probability that input data is discarded can be reduced, and the memory resources can be effectively used.

The switch blocks SB0 and SB1
Need not be provided in the same LSI (separate LS
I), so large ATMs
It is possible to configure switches.

Embodiment 2 FIG. 9 is a block diagram of an output buffer type ATM switch according to Embodiment 2 of the present invention. FIG. 10 is an internal configuration diagram of the switch blocks SB0 and SB1 in FIG.
The internal configuration of switch blocks SB0 and SB1 is the same.

The ATM switch according to the second embodiment includes switch blocks (output buffers) SB0 and SB1, an input / output control unit IOC, data input ports in0 and in1,
Data output ports out0 and out1 are provided.

The ATM switch according to the second embodiment has two switches.
× 2 switch configuration, and the data input port i
Input data (input cell) WD0 input from n0 is
According to the output destination (destination) address included in the header portion of this input data WD0, data output port out
Output data RD0 from 0 or output data RD1 from the data output port out1 and input data (input cell) WD1 input from the data input port in1 are included in the header of the input data WD1. The data is output from the data output port out0 as output data RD0 or from the data output port out1 as output data RD1 according to the output destination (destination) address.

[Switch Blocks SB0 and SB1] FIG.
Like 0, the switch blocks SB0 and SB1 each include an input data identification circuit IDC, a spatial cross switch SW, data memories DMA and DMB, an output selector OS, and a write / read controller WRC. .

In the following description, the switch block S
The spatial cross switch SW of B0, the write / read controller WRC, the data memories DMA and DMB, and the output selector OS are set to SW0, WRC0, DMA0,
DMB0 and OS0, the spatial cross switch SW, write / read controller WRC, data memories DMA and DMB, and output selector OS of the switch block SB1 are denoted by SW1, WRC1, DMA1, and DMB, respectively.
1, OS1.

Further, the remaining memory capacity ZAN of the switch block SB0 and the memory data M of the switch block SB0
QA, MQB, the write identifier WID of the switch block SB0, the input data identification signal DC of the switch block SB0, the read control signal MCA input to the switch block SB0, and the output control signal MCB input to the switch block SB0 are respectively ZAN0. , MQ
A0, MQB0, WID0, DC0, MCA0, MCB
0 and the remaining memory capacity ZA of the switch block SB1
N, memory data MQA, M of switch block SB1
QB, write identifier WI of switch block SB1
D, input data identification signal D of switch block SB1
C, the read control signal MCA input to the switch block SB1 and the output control signal MCB input to the switch block SB1 are respectively ZAN1 and MQA.
1, MQB1, WID1, DC1, MCA1, MCB1
Notation.

In FIG. 10, the input data identification circuit IDC, the spatial cross switch SW, the write / read controller WRC, the data memories DMA and DMB, the output selector OS, the remaining memory ZAN of the own block, the memory data of the own block In the parentheses of the MQA, MQB, the memory data MQAT, MQBT of the other block, the write identifier WID of the own block, and the input data identification signal DC, the switch block in FIG.
The above description is for B0.

The switch blocks SB0 and SB1 shown in FIG.
Are the switch blocks SB0, SB of the first embodiment.
1 (see FIG. 2), the memory controller MMC and the management memory CM are not provided.
The functions of the input data identification circuit IDC, the spatial cross switch SW, the data memories DMA and DMB, the output selector OS, and the write / read controller WRC of the switch blocks SB0 and SB1 of FIG. 10 are the same as those of the switch block SB0 of the first embodiment. , SB1 have the same functions as the input data identification circuit IDC, the spatial cross switch SW, the data memories DMA and DMB, the output selector OS, and the write / read controller WRC.

However, the switch block SB shown in FIG.
0, SB1, the write identifier W of the own block
ID (WID0 or WID1) is input / output control unit IO
Input from C. As in the first embodiment, the write identifier WID0 of the switch block SB0 is the identifier BID0 of the switch block SB0 = "00" when the write block is not replaced, and
When the write block is replaced, the identifier BID1 of the switch block SB1 is changed to "01". Also, the write identifier W of the switch block SB1
ID1 is the identifier BID1 of the switch block SB1 = "0" when the write block is not replaced.
1 ", the identifier BID0 of the switch block SB0 =" 0 "when the write block is replaced.
It is changed to "0".

Furthermore, the switch block SB shown in FIG.
0, SB1, the write / read controller W
RC is a read control signal MCA (M) input from the input / output control unit IOC when reading memory data.
CA0 or MCA1). The output selector OS is controlled by an output control signal MCB (MCB0 or MCB1) input from the input / output control unit IOC.

The switch blocks SB0, SB0 in FIG.
SB1 includes input terminals fr0 and fr1 for frame signals FR0 and FR1, input terminals wd0 and wd1 for input data WD0 and WD1, and address signals WA0 and WA, respectively.
1 input terminals wa0 and wa1 and an input enable signal W
The input terminals we0 and we1 of E0 and WE1, the input terminal wid of the write identifier WID (WID0 or WID1) of the own block, the output terminal dc of the input data identification signal DC (DC0 or DC1), and the remaining memory ZAN (Z
AN0 or ZAN1), an input terminal mca of a read control signal MCA (MCA0 or MCA1), and an output control signal MCB (MCB0 or MCB).
1) The input terminal mcb and the memory data M of the own block
QA, MQB (MQA0, MQB0 or MQA1, M
QB1) and the memory data MQAT, MQBT (MQA1, MQB1) of another block.
1 or MQA0, MQB0) input terminal mqai, m
qbi and an output terminal rd for output data RD (RD0 or RD1).

The ATM switch of the second embodiment is different from the ATM switch of the first embodiment in that the memory controllers MMC0 and MMC0 of the switch blocks SB0 and SB1
The replacement of the write blocks controlled by the MMC0, and the reading and data output of the memory data are controlled by the input / output control unit IOC.

Therefore, the ATM switch according to the second embodiment is similar to the ATM switch according to the first embodiment,
The remaining memory capacity of the switch blocks SB0 and SB1 is detected, and when the remaining memory capacity of both the switch blocks SB0 and SB1 is not insufficient, the 0-system data is written to the switch block SB0 and the 1-system data is written to the switch block SB1. , Switch block SB
0, SB1 when one of the remaining memory is insufficient,
If the remaining memory capacity is not insufficient, the write block is replaced.

After the replacement of the write blocks is performed, when the remaining memory capacity of the switch block having the insufficient remaining memory is recovered, the replacement of the write blocks is restored.

When the remaining memory capacity of the switch blocks SB0 and SB1 is insufficient, the write block is replaced (when the replacement is already performed,
Whether or not to perform this exchange is optional. Here, it is assumed that when the remaining memory amounts of the switch blocks SB0 and SB1 are both insufficient, the write blocks are not replaced (if the replacement has already been performed, the replacement is canceled).

[0209] The replacement of the write block is performed by changing the value of the write identifier WID0 of the switch block SB0,
This is performed by exchanging the value of the write identifier WID1 of the switch block SB1 with the input / output control unit IOC.

In order to realize the replacement of the write block, the switch block SB0 is provided with the write identifier W of its own block separately from the identifier BID0 of its own block.
The switch block SB1 has the write identifier WID1 of its own block, separately from the identifier BID1 of its own block. However, in the second embodiment, the switch blocks SB0 and SB are controlled by the input / output control unit IOC in order to control the replacement of the write blocks and the control of reading and outputting the memory data.
1, the write identifiers WID0 and WID1 are notified, but the identifiers BID0 and BID1 are not notified.

Identifier BID0 of switch block SB0
And the identifier BID1 of the switch block SB1
Is not changed on the way. Here, the value of the identifier BID0 is “00”, and the value of the identifier BID1 is “01”. The switch block SB0 with the identifier BID0 = "00" is a switch block that outputs data to the data output port out0, and the identifier BID1
The switch block SB1 of “01” is a switch block that outputs data to the data output port out1.

In contrast, the value of the write identifier WID0 of the switch block SB0 and the value of the switch block SB0
The value of the write identifier WID1 of B1 is changed by the input / output control unit IOC when the write block is replaced and when the replacement of the write block is restored. The value of the write identifier WID0 of the switch block SB0 is the identifier BID0 of the own block when the write block is not replaced, and is changed to the identifier BID1 of the other block when the write block is replaced. The value of the write identifier WID1 of the switch block SB1 is the identifier BID1 of the own block when the write block is not replaced, and is changed to the identifier BID0 of the other block when the write block is replaced. . Therefore, a switch block in which the write identifier WID (WID0 or WID1) is BID0 = "00" is a switch block that writes system 0 data (data to be output to the data output port out0), and the write identifier WID (WID0 or WID1). Is BI
The switch block in which D1 = "01" is a switch block for writing the first system data (data to be output to the data output port out1).

When the remaining memory amounts of the switch blocks SB0 and SB1 are not insufficient, the write identifier WID0 of the switch block SB0 is the identifier BID0 of the own block, and the write identifier WID1 of the switch block SB1 is the identifier of the own block. BID1. When the remaining memory capacity of the switch block SB0 or SB1 becomes insufficient, the write identifier WID0
Is replaced with the value of the write identifier WID1, the write identifier WID0 of the switch block SB0 is changed to the identifier BID1 of the switch block SB1, and the write identifier WID1 of the switch block SB1 is changed to the identifier BID0 of the switch block SB1. .

In the ATM switch according to the second embodiment, the 0 written in the switch block SB1 is
The system data is transferred from the switch block SB1 to the switch block SB0, and is output from the switch block SB0 to the data output port out0. Similarly, the 1-system data written in the switch block SB0 is transferred from the switch block SB0 to the switch block SB1, and is output from the switch block SB1 to the data output port out1.

[Input / output control unit IOC] Input / output control unit IO
C denotes all functions of the input unit IU of the first embodiment, and the memory controllers MMC0 and MMC of the first embodiment.
And the management memory C according to the first embodiment.
It has all the functions of M0 and CM1.

The input / output control unit IOC detects the switch block SB at an initial stage such as when the power of the ATM switch is turned on.
0 write identifier WID0 to the switch block SB0
And the switch block S
Write identifier WID1 of B1 to switch block SB
By setting the identifier BID1 to 1, the data (0-system data) output from the switch block SB0 is written to the switch block SB0, and the data (1-system data) output from the switch block SB1 is written to the switch block SB1. By comparing the remaining memory ZAN0 of the switch block SB0 and the remaining memory ZAN1 of the switch block SB1 with the remaining memory threshold RT, respectively, it is determined whether the remaining memory ZAN0 is insufficient and whether the remaining memory ZAN0 is insufficient. Quantity Z
It is determined whether or not AN1 is insufficient, and if the remaining memory ZAN1 is not insufficient when the remaining memory ZAN0 is insufficient (ZAN1> RT and ZAN0
≤RT), or conversely, if the remaining memory ZAN1 is insufficient and the remaining memory ZAN0 is not insufficient (ZAN0> RT and ZAN1≤RT), the write identifier WID of the switch block SB0 is written.
0 is changed to the identifier BID1 of the switch block SB1, and the write identifier WID1 of the switch block SB1 is changed to the identifier BID1 of the switch block SB0.
By exchanging the value of D1 and exchanging the write identifier, the switch block to which the 0-system data is written is changed to the switch block SB1 and the switch block to which the 1-system data is written is changed to the switch block SB0 (the write block is exchanged). ).

The input / output control unit IOC operates when the remaining memory capacity of the switch block, which had become insufficient when the write block was replaced, is restored,
Undo the replacement of the write block. Further, the input / output control unit IOC does not replace the write block when the remaining memory of both blocks is insufficient simultaneously.

The input / output control unit IOC controls the write / read controller WRC0 of the switch block SB0 with the read control signal MCA0 to control the reading of the memory data MQA0 and MQB0 of the switch block SB0, and the control of the switch block SB1. Reads the write / read controller WRC1 and the read control signal MCA1
To control the reading of the memory data MQA1 and MQB1 of the switch block SB1, and the output selector OS0 of the switch block SB0 by the output control signal MCB0 to control the read memory data MQA0 and MQB0 and the switch block S1.
The output of the memory data MQA1 and MQB1 transferred from B1 is controlled, the output selector OS1 of the switch block SB1 is controlled by the output control signal MCB1, and the read memory data MQA1 and MQB1 and the memory data transferred from the switch block SB0. MQA0,
Controls the output of MQB0.

At the time of input data writing, the input / output control unit IOC creates read / output management data of the switch block SB0 according to the input data identification signal DC0 from the switch block SB0. According to the data identification signal DC1, read / output management data of the switch block SB1 is created, and these read / output management data are
The information is recorded in a management memory CM0 (management memory for managing the switch block SB0) and CM1 (management memory for managing the switch block SB1) provided inside the input / output control unit IOC. The configuration of the read / output management data is the same as the read / output management data (data recorded in the management memory CM) described in the first embodiment.

[0220] The input / output control unit IOC generates a read control signal MCA0 and sends it to the write / read controller WRC0 according to the read / output management data of the switch block SB0 when reading and outputting the memory data. , Data memory DMA0
Or memory data MQA0 or MQB from DMB0
0, and the memory data MQA0 or MQA
B0 is the output selector OS0 and switch block SB
1 and generates a read control signal MCA1 in accordance with the read / output management data of the switch block SB1 to generate a write / read controller WRC.
1 to read out the memory data MQA1 or MQB1 from the data memory DMA1 or DMB1, and output the memory data MQA1 or MQB1 to the output selector O.
S1 and the switch block SB0 are sent.

Further, the input / output control unit IOC generates an output control signal MCB0 according to the read / output management data of the switch blocks SB0 and SB1 and sends it to the output selector OS0 at the time of reading and outputting the memory data. Memory data MQA0, MQB0, M
Either QA1 or MQB1 is output from the output selector OS0 as output data RO0, and in accordance with the read / output management data of the switch blocks SB0 and SB1, an output control signal MCB1 is generated and sent to the output selector OS1, and the memory data MQA1 is output. , MQB
1, MQA0, or MQB0 to output selector O
S1 is output as output data RO1.

The memory data MQA0, MQA including the case where the output destination of the memory data of the switch block SB0 matches the output destination of the memory data of the switch block SB1.
1, MQB0, and MQB1 are read and output in the same order and procedure as in the first embodiment.

As described above, in the ATM switch according to the second embodiment, the input / output control unit IOC corresponds to means for assigning an identifier to each output buffer device (switch block).

The input / output control unit IOC determines the write identifier WID of the k-th output buffer device (k is an arbitrary integer from 1 to N, N is the number of output buffer devices, N = 2 in this case). Is the identifier B of the k-th output buffer device.
This corresponds to means for initial setting to an ID.

Further, the input / output control unit IOC determines whether the remaining memory ZAN (ZAN0 or ZA0) of the k-th output buffer device is present.
When N1) is insufficient, the write identifier WID (WID0 or WID1) of the k-th output buffer device is changed to an identifier (BID1 or BID0) of another output buffer device having sufficient memory capacity, and Write identifier (WID1 or WID1) of another output buffer
ID0) is replaced with the identifier BID (B
ID0 or BID1).

In the switch blocks SB0 and SB1 of the ATM switch according to the second embodiment, the data memories DMA and DMB correspond to data memories in which input data WD0 and WD1 are written.

The input data identification circuit IDC, the write / read controller WRC, and the spatial cross switch SW store the input data WD0, WD1 assigned with the address corresponding to the write identifier WID of the own device in the data memories DMA, DMB. The means for writing to is configured.
In the second embodiment, the above-mentioned address corresponds to the output destination address included in the header portion of the input data WD0, WD1, or the address signals WA0, WA1.

A write / read controller WRC
Corresponds to a unit that detects the remaining memory ZAN of the own apparatus and notifies the identifier changing unit of the remaining memory.

Further, the input / output control unit IOC outputs a control signal for outputting input data assigned an address corresponding to the identifier BID of the k-th output buffer device from the k-th data output port to each output buffer. It is equivalent to a means for generating a device and outputting these control signals to respective output buffer devices. Note that, in the second embodiment, the control signal is a read control signal MCA.
And the output control signal MCB.

Further, in the switch blocks SB0 and SB1, the memory controller MMC, the management memory CM,
And the output selector OS inputs the input data (WD0 or WD) to which an address corresponding to the identifier BID (BID0 or BID1) of its own device is attached in accordance with the control signal.
1) is read out from the data memory DMA or DMB of the own device, and the k-th data output port (out0 or out) is read out.
t1), or read out input data to which an address corresponding to an identifier (BID1 or BID0) of another output buffer device is attached from its own data memory DMA or DMB and transfer it to the other output buffer device. Output the input data to which the address corresponding to the identifier BID of the own device transferred from the other output buffer device is added to the k-th data output port,
Alternatively, input data to which an address corresponding to the identifier of another output buffer device is assigned can be stored in its own data memory DM.
The data is read from A or DMB and transferred to the other output buffer device (at this time, no data is output to the kth data output port), or the identifier BID of the own device transferred from the other output buffer device is used. The input data to which the corresponding address is assigned is output to the output port of the own device (at this time, the data memory DMA or D of the own device is output).
The data read from the MB is invalidated).

The data write operation, the data read operation, and the data output operation of the ATM switch according to the second embodiment are the same as those of the ATM switch according to the first embodiment, and a description thereof will be omitted.

According to the second embodiment, the remaining memory ZAN0 of the switch block SB0 is detected by the write / read controller WRC0 of the switch block SB0, and the remaining memory ZAN1 of the switch block SB1 is detected by the switch block SB1. Detected by the write / read controller WRC1, and when either the remaining memory ZAN0 or ZAN1 of the switch block SB0 or SB1 becomes insufficient, the input / output control unit I
The switch block for writing the 0-system data is changed from the switch block SB0 to the switch block SB1 by the OC.
And the switch block for writing the 1-system data is changed from the switch block SB1 to the switch block SB0 (the write block is replaced), so that the input data is discarded in the case of the same memory capacity as the conventional ATM switch. While reducing the probability,
Memory resources can be used effectively.

The output buffer type ATM switch according to the first and second embodiments is described in order to simplify the description.
Although a 2 × 2 switch configuration is used, the present invention is applied to a 3 × 3 switch.
The present invention can also be applied to the output buffer type ATM switch having the above switch configuration. In a 3 × 3 or more switch configuration, the number of switch blocks is set to three or more, the number of data memories in each switch block is set to three or more, and an output destination is identified in read / output management data. By increasing the number of bits of the data (1 bit data of LSB) to 2 bits or more, it is possible to increase the scale. For example, in the case of an 8 × 8 switch configuration, eight switch blocks are provided, eight data memories are provided in each switch block, and data for identifying an output destination is three bits. Furthermore, when there is a shortage of remaining memory in a certain switch block and there are a plurality of switch blocks in which the remaining memory is not insufficient, for example, the write block may be replaced with a switch block having the largest remaining memory. To

In the first and second embodiments, when the output destinations of the memory data of the switch block SB0 and the memory data of the SB1 coincide with each other in the data output, the memory data with the earlier write timing is preferentially output. However, when the output destination of the memory data matches as described above, the memory data of the switch block with the smaller remaining memory is preferentially output,
Alternatively, the memory data of the own block and the memory data transferred from another block may be alternately output.

In the first and second embodiments, whether or not to replace a write block is determined by referring only to the remaining memory capacity. In addition to the remaining memory capacity, prediction of traffic characteristics and the like are performed. It is also possible to determine whether or not to replace the write block by referring to it.

[0236]

As described above, according to the ATM switch device of the present invention, the remaining memory capacity of each output buffer device is detected, and when the remaining memory capacity of the k-th output buffer device becomes insufficient, By changing the output buffer device for writing input data to be output from the k data output port from the k-th output buffer device to another output buffer device having sufficient memory capacity, the conventional ATM
When the memory capacity is the same as that of the switch, there is an effect that the probability that input data is discarded is reduced and the memory resources can be effectively used.

[Brief description of the drawings]

FIG. 1 is an output buffer type ATM according to a first embodiment of the present invention.
It is a block diagram of a switch.

FIG. 2 is an internal configuration diagram of a switch block constituting the ATM switch of FIG. 1;

FIG. 3 is a timing chart for explaining a data write operation when a write block is not replaced in the ATM switch of FIG. 1;

FIG. 4 is a diagram for explaining the write contents of a data memory and a management memory by the data write operation of FIG. 3;

FIG. 5 is a timing chart illustrating a read and output operation of data written by the data write operation of FIG. 3;

FIG. 6 is a timing chart illustrating a data write operation when a write block is replaced in the ATM switch of FIG. 1;

FIG. 7 is a diagram for explaining the write contents of a data memory and a management memory by the data write operation of FIG. 6;

FIG. 8 is a timing chart illustrating a read and output operation of data written by the data write operation of FIG. 6;

FIG. 9 is an output buffer type ATM according to the second embodiment of the present invention;
It is a block diagram of a switch.

FIG. 10 is an internal configuration diagram of a switch block constituting the ATM switch of FIG. 9;

FIG. 11 is a block diagram of a conventional output buffer type ATM switch.

[Explanation of symbols]

in0, in1 data input port, out0, ou
t1 data output port, IU input part, IC input control part, OC output control part, SB0, SB1 switch block, CM management memory, CM0 management memory of switch block SB0, DMA, DMB
Data memory, data memory of DMA0, DMB0 switch block SB0, IDC input data identification circuit, input data identification circuit of IDC0 switch block SB0, OS output selector, output selector of OS0 switch block SB0, SW spatial cross switch, SW0 switch block SB0 spatial cross switch, WRC write / read controller, WRC0 switch block SB0 write / read controller, MMC memory controller,
MMC0 Memory controller of switch block SB0, BID Identifier of own block, BIDT Identifier of other block, BID0 Switch block SB0
ID, BID1 Identifier of switch block SB1, CI Write identifier exchange signal of own block, CIT Write identifier exchange signal of other blocks, CI0 Write identifier exchange signal output by switch block SB0, CI1 Write identifier exchange signal output by switch block SB1 Signal, DC
Input data identification signal, DC0 switch block SB
0 input data identification signal, FR0, FR1 frame signal, MQA, MQB, memory data of own block, MQAT, MQBT memory data of other blocks, MQA0, MQB0 memory data of switch block SB0, MQA1, MQB1 memory of switch block SB1 Data, MS Memory data selection signal of own block, MST Memory data selection signal of other blocks, MS0 Memory data selection signal output from switch block SB0, MS1 Memory data selection signal output from switch block SB1, RD output data, RD0 switch Output data of the block SB0, RD1 output data of the switch block SB1,
RT memory remaining threshold, SQA, SQB switched input data, WA0, WA1 address signal,
WD0, WD1 input data, WE0, WE1 input enable signal, WID own block identifier,
WID0 Identifier of switch block SB0, WID
1 Identifier of switch block SB1, ZAN Remaining memory of own block, ZANT Remaining memory of other block, ZAN0 Remaining memory of switch block SB1,
ZAN1 The remaining memory capacity of the switch block SB1.

Claims (5)

[Claims] 1. A data output port comprising N (N is an integer of 2 or more) data output ports and N output buffer devices, and whose output destination is a k-th (k is an arbitrary integer from 1 to N). In the output buffer type ATM switch device which writes input data into the k-th output buffer device, the remaining memory capacity of each output buffer device is detected, and when the remaining memory capacity of the k-th output buffer device becomes insufficient. An ATM switch for changing an output buffer device for writing input data to be output from a k-th data output port from the k-th output buffer device to another output buffer device having sufficient memory capacity. apparatus. 2. An output buffer device, comprising: means for assigning an identifier to each output buffer device, wherein the k-th output buffer device initializes a data memory in which input data is written, and a write identifier of the device to an identifier of the device. Means, means for writing input data assigned an address corresponding to the write identifier of the own device to the data memory, detecting the remaining memory of the own device, and notifying the remaining memory to another output buffer device Means for outputting a write identifier replacement signal to another output buffer device in which the remaining memory capacity is not insufficient when the remaining memory capacity of the own device is insufficient, and changing the write identifier of the own device from the identifier of the own device. Means for changing to the identifier of the other output buffer device; and a write identifier exchange signal is input from the other output buffer device. To come, ATM switching device according to claim 1, characterized in that a means for changing the write identifier of the device from the identifier of the device to an identifier of said other output buffer device. 3. The k-th output buffer device reads, from the data memory, input data to which an address corresponding to an identifier of the k-th output buffer device is output, and outputs the input data to the k-th data output port. The input data with the address corresponding to the identifier of the output buffer device is read from the data memory and transferred to the other output buffer device, and also corresponds to the identifier of the own device transferred from the other output buffer device. The input data with the address is output to the k-th data output port, or the input data with the address corresponding to the identifier of the other output buffer device is read from the data memory and the other output is performed. To the buffer device, or to the own device identifier transferred from the other output buffer device. ATM switching device according to the input data address is attached to claim 2, further comprising means for outputting the data output port of the first k that. Means for assigning an identifier to each output buffer device; means for initializing the write identifier of the k-th output buffer device to the identifier of the k-th output buffer device; and memory for the k-th output buffer device. When the remaining amount is insufficient, the write identifier of the k-th output buffer device is changed to the identifier of another output buffer device having the insufficient memory amount, and the write identifier of the other output buffer is changed to the k-th output buffer device. An identifier changing means for changing the identifier to an output buffer device, wherein the k-th output buffer device includes a data memory in which input data is written, and input data provided with an address corresponding to a write identifier of its own device. Means for writing to the data memory; means for detecting the remaining memory capacity of the own device and notifying the identifier changing means of the remaining memory capacity 2. The ATM switch device according to claim 1, comprising: 5. A control signal for outputting from the k-th data output port input data to which an address corresponding to the identifier of the k-th output buffer device is generated for each of the output buffer devices, and the control signals are generated. Means for outputting a signal to each output buffer device, wherein the k-th output buffer device reads input data written in the data memory and outputs the input data to the k-th data output port according to the control signal. Or read the input data written in the data memory and transfer it to another output buffer device and output the input data transferred from the other output buffer device to the k-th data output port. Alternatively, the input data written in the above data memory is read and transferred to another output buffer device. Or feed, or ATM according to claim 4, further comprising means for outputting the input data transferred from said other output buffer device to the data output port of the first k
Switch device.