JP2002093178A - Semiconductor memory and operarting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a bit cost of a CAM cell by decreasing the number of elements and dispersing with wiring supplying fixed voltage. SOLUTION: This device has a first write-in transistor Mw1 of which a gate is connected to a word line WL and a drain is connected to a first bit line BL, a second bit line /BL of which a gate is connected to the word line WL and a drain is connected to a second bit line /BL, a first retrieving transistor Ms1 connected between the first bit line BL and a match line ML and of which a gate is connected to a storage node SN1, a second retrieving transistor Ms2 connected between the second bit line /BL and a match line ML and of which a gate is connected to a storage node SN2, and first and second capacitors C1, C2 connected between gates of the first and the second retrieving transistors Ms1, Ms2 and the match line ML.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called gain cell in which stored data is amplified by a transistor and read out to a bit line. Based on a so-called gain cell, match / mismatch with stored data is determined by applying search data to a bit line. The present invention relates to a semiconductor memory device realizing a CAM cell having a function of being able to determine from a voltage fluctuation of the semiconductor memory device and an operation method thereof.

[0002]

2. Description of the Related Art Content address memory (CAM; Content A)
The ddressable memory has a function of performing a search for a match / mismatch between search data and storage data in parallel with respect to a plurality of bits representing an address, and outputting a storage address of the matched data.

FIG. 9 shows one type of a conventional CAM cell.
For example, “A 288-kb Fully Parallel Content Addressa
ble Memory Using a Stacked-Capacitor Cell Structur
e, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.27, NO.1
2, DECEMBER 1992, pp1927-1933 "General purpose DR
It is a circuit diagram of a CAM cell based on AM (Dynamic Random Access Memory). This conventional CAM cell is a general-purpose DR
Two AM cells are integrated in one cell, and EXCLU
A SIVE-NOR circuit is added. That is, the capacitor C1 and the write transistor Mw1, which are connected in series between the common voltage plate supplying the plate voltage Vcp and the bit line BL, the common voltage plate and the bit auxiliary line / B
L and a capacitor C2 and a write transistor Mw2 connected in series. Write transistor Mw
The gates of 1 and Mw2 are connected to one word line WL. Further, search transistors Ms1 and Ms2 are connected in series between the bit line BL and the bit supplementary line / BL,
A diode connection transistor (hereinafter, referred to as a diode) Md whose drain and gate are short-circuited is connected between the connection midpoint and the match line ML. An EXCLUSIVE-NOR circuit is formed by the diode Md and the two search transistors Ms1 and Ms2. The search transistor is used not only during a search operation but also as a read transistor.

At the time of writing, the word line WL is activated to turn on the write transistors Mw1 and Mw2, and the pair of bit lines BL and / BL are driven according to the write data.
After that, the word line WL is returned to the inactive state. As a result, one of the storage nodes SN1 and SN2 holds high-level storage data and the other stores low-level storage data in accordance with the write data.

At the time of reading, a bit line pair BL, / BL
, The match line ML is driven to a high level. The storage data is "1", that is, the storage node S
When N1 is at a high level and storage node SN2 is at a low level, search transistor Ms1 turns on, bit line BL is charged through diode Md and search transistor Ms1, and its potential rises. On the other hand, since the search transistor Ms2 does not turn on, the bit auxiliary line / BL maintains a low level (ground potential). Conversely, when the stored data is "0", the search transistor Ms2 is turned on and the search transistor Ms1 is not turned on.
The potential of BL rises, and the potential of bit line BL maintains a low level. The potential difference between the bit line pair is amplified by a sense amplifier and read.

At the time of retrieval, after precharging the pair of bit lines BL and / BL and the match line ML to high level, one of the pair of bit lines BL and / BL falls to low level according to the content of the retrieval data. At this time, if the search data and the storage data match, the storage node SN1 on the bit line BL or bit auxiliary line / BL side lowered to the low level
Alternatively, SN2 is at low level, and the search transistor Ms1 or Ms2 whose source is at low level does not turn on. The other search transistors are not turned on because no voltage is applied between the source and the drain. On the other hand, when the search data and the storage data do not match, since the bit line BL lowered to the low level or the storage node SN1 or SN2 on the bit auxiliary line / BL side is at the high level, the source is set to the low level. Search transistor M
S1 or Ms2 turns on, and the precharge voltage of the match line ML decreases. In other words, the search data and the stored data can be collated as “non-match” when the match line voltage decreases and “match” when the match line voltage does not decrease.

Usually, this search operation is performed simultaneously among a plurality of cells. For example, after all or a plurality of bit line pairs BL, / BL and a plurality of match lines ML within a search target range are simultaneously precharged to a high level, a plurality of bit line pairs are searched for one page or as search data. A bit string of a specific length such as one word is set. At this time, 1
If a mismatch also occurs in the bits, the voltage of the match line ML decreases. However, only in the specific word line WL whose address matches, the storage content (storage bit string) of the same row completely matches the search content, so that the match line ML is Voltage does not change. In this way, an address where the bit string of the search data completely matches the storage content can be detected.

[0008]

The conventional general-purpose DRA
In an M-based CAM cell, when the search operation is performed simultaneously among a plurality of cells as described above, the same bit line pair BL,
If there are many match lines ML simultaneously discharged to / BL,
This causes a large load on the bit line pair BL, / BL. In addition, since a large current flows, the potential of the bit line (BL, / BL), which has been the ground potential, temporarily rises. Therefore, the potential change of the match line ML is not sharp, and it takes time until the potential is stabilized. Furthermore, there is much wasteful power consumption.
The diode Md is provided to prevent such a problem. In a conventional CAM cell, a diode Md
Therefore, the match line ML does not become lower than the forward voltage of the diode from 0.6 V to 0.7 V. Therefore, the current flowing into bit line BL or bit auxiliary line / BL is limited, and as a result, the potential of match line ML changes quickly, and power consumption does not increase more than necessary.

However, this conventional DRAM-based C
In the AM cell, the diode-connected transistor Md is
It is provided only for this search operation. Therefore, the conventional CAM cell has a problem that the number of transistors constituting the cell is large and the cell area is large.

That is, a CAM cell based on a general-purpose one-capacitor-one-transistor DRAM requires five transistors in addition to two capacitors, and has a large cell area because it includes many elements. In addition, since a supply line of a constant voltage (Vcp) is required,
The cell area increases and the number of manufacturing steps increases. As described above, the semiconductor device using the conventional CAM cell has a disadvantage that the bit cost is high.

An object of the present invention is to propose a semiconductor memory device having a content address memory function with a smaller number of elements and no wiring for supplying a constant voltage, thereby reducing bit cost, and an operation method thereof. Is to do.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor memory device in which a gate is connected to a word line, and one of a source and a drain is connected to a first bit line.
A write transistor, a gate connected to the word line, one of a source and a drain connected to the second bit line, a second write transistor connected between the first bit line and the match line, and a gate connected to the word line. A first write transistor connected to the other of the source and the drain of the first write transistor
A search transistor, a second search transistor connected between the second bit line and the match line, a gate connected to the other of the source and the drain of the second write transistor, and a gate of the first search transistor And a second capacitor connected between the gate of the second search transistor and the match line. Preferably, the first
And a second search transistor, when a high-level voltage is applied to the match line, a gate voltage that increases from a high-level storage voltage of the first and second search transistors and a gate voltage that increases from a low-level storage voltage. Threshold voltage between the gate voltage.

In the semiconductor memory device having such a configuration, 2
No diode is connected between the connection midpoint of the two search transistors and the match line. Further, the two capacitors are respectively connected between the gate and the drain (match line) of the search transistor, and wiring for supplying a constant voltage to the capacitors is unnecessary.

The operation method of the semiconductor memory device according to the second aspect of the present invention, in the above-described configuration, comprises the steps of:
A voltage corresponding to the stored data is set to the first and second bit lines, the word line is activated to make the first and second write transistors conductive, and the first and second bit lines are set to the set voltage. The corresponding voltage is transmitted to the gates of the first and second search transistors. At the time of reading, the first and second bit lines are set to an electric floating state at a low level, and the match line is raised from a low level to a high level. At the time of search, the first and second bit lines and the match line are set to an electric floating state at a high level, and a voltage corresponding to search data is applied to the first and second bit lines.

In the operation method of the semiconductor memory device, at the time of writing, for example, the voltage obtained by subtracting the threshold voltage of the writing transistor from the voltage applied to the word line is applied to the storage node,
That is, the voltage is transmitted to the gate of the search transistor to which the write transistor is connected, and after the write transistor is cut off, the voltage is held at the storage node. At the time of reading, when the match line is raised to a high level, the storage node voltage rises due to the capacitive coupling of the capacitor, and it is determined whether the search transistor is on or off depending on the logic of the stored data. When the search transistor is turned on, a charge is supplied from the match line to the first or second bit line, and the voltage of the bit line, which has been floating at a low level in advance, rises. This bit line voltage change is amplified and read by, for example, a sense amplifier.

At the time of retrieval, the first and second bit lines and the match line are precharged at a high level. At this time, the gate voltage of the two search transistors, that is, the voltage of the storage node also increases by a constant voltage due to the capacitive coupling of the capacitors. In this state, one of the first and second bit lines is lowered to a low level according to the search data. When the search data matches the stored data, the stored data on the side lowered to the low level is at the low level, so that both of the two search transistors maintain the off state. On the other hand, if the search data does not match the storage data, the storage data on the side lowered to the low level is at the high level, so that the gate voltage of the search transistor on the storage data side is at the high level, and the source and the drain are connected. When a constant voltage is applied, one of the search transistors is turned on, and the precharge voltage of the match line is discharged to the low-level bit line through the search transistor in the on state. As the discharge proceeds and the voltage of the match line decreases to some extent, the gate voltage of the search transistor at the high level (the storage node voltage for writing “1”) also decreases,
The search transistor performing this discharge is cut off. Therefore, the match line drops from the high level but does not drop to the low level, the voltage drop stops at an intermediate level, and the discharge does not proceed any further. As described above, in the semiconductor memory device of the present invention, since the capacitor is connected between the match line and the storage node, the semiconductor memory device operates in the same manner as the conventional CAM cell without the diode in the conventional CAM cell.

[0017]

FIG. 1 is a circuit diagram showing a configuration of a CAM cell of a semiconductor memory device according to an embodiment of the present invention. Here, the case where the transistor is an n-channel type is described as an example. However, in the case where the transistor is a p-channel type, the polarity of the applied voltage is appropriately reversed and the following description can be similarly applied. This CA
The M cell has two write transistors Mw1, Mw2
And two search transistors Ms1 and Ms2 and two capacitors C1 and C2.

The write transistor Mw1 has a drain connected to the bit line BL, a source connected to the storage node SN1, and a gate connected to the word line WL. Similarly, the drain of the write transistor Mw2 is connected to the bit auxiliary line / BL, the source is connected to the storage node SN2, and the gate is connected to the word line WL. The drain of the search transistor Ms1 is connected to the match line ML, the source is connected to the bit line BL, and the gate is connected to the storage node SN1. Similarly, the drain of search transistor Ms2 is connected to match line ML, the source is connected to complementary bit line / BL, and the gate is storage node S.
Connected to N2. Storage node SN1 and match line M
The capacitor C1 is connected to L (the drain of the search transistor Ms1). Similarly, storage node S
The capacitor C2 is connected between N2 and the match line ML (the drain of the search transistor Ms2).

In this CAM cell, the search transistor M
s1 and Ms2 also function as read transistors. As will be described later, a function for searching stored contents is added. Specifically, the storage node SN
EXCLU with four inputs, SN2, bit line BL and bit supplementary line / BL, and output match line MS
The function of the SIVE-NOR circuit is added.

Next, the operation of the CAM cell (write, read and address search) will be described with reference to the drawings. 2A to 2E show a cell circuit diagram describing an applied voltage condition at the time of writing “1” and a timing chart showing voltage changes of each signal line and a storage node. 3A to 3E show a cell circuit diagram describing the applied voltage condition at the time of writing “0” and a timing chart showing voltage changes of each signal line and a storage node.

At the time of writing, first, a bit line pair BL, /
A voltage corresponding to the stored data is set in BL. At the time of writing “1”, as shown in FIG. 2D, 1.5 V is applied to the bit line BL and 0 V is applied to the bit auxiliary line / BL. At the time of writing “0”, as shown in FIG.
0 V is applied to the bit line BL, and 1.
5 V is applied. Next, the voltage of the word line WL is set to 1.5
V rises to the high level, and the write transistor M
w1 and Mw2 are turned on (FIG. 2 (B), FIG. 3
(B)). Thus, at the time of writing “1”, the word line WL applied voltage 1.5 V
threshold voltage Vthw of w1, Mw2, for example, 0.9
At the time of writing “1” shown in FIG. 2E, a voltage 0.6 V obtained by subtracting V is applied to the storage node SN1.
Is applied to the storage node SN2 when "0" is written. Further, the storage node SN2 at the time of writing “1”,
0 V is applied to the storage node SN1 at the time of writing “0”. By returning the voltage applied to the word line WL to 0 V, the storage nodes SN1 and SN2 are brought into an electrically floating state, and storage data of a predetermined voltage is held.

FIGS. 4A to 4D show a cell circuit diagram describing the applied voltage condition at the time of reading "1" and a timing chart showing a voltage change of each signal line. FIGS. 5A to 5D show a cell circuit diagram describing the applied voltage condition at the time of reading “0” and a timing chart showing a voltage change of each signal line.

At the time of reading, the bit line pair BL, / BL is discharged to a floating state at 0 V, and the match line ML is set to 0 as shown in FIGS. 4 (C) and 5 (C).
It rises from V to a high level of 1.5V. At this time, the voltage of the match line ML changes at a predetermined rate by the capacitors C1, C
2 are added to the storage nodes SN1 and SN2. For example, capacitors C1,
Assuming that the capacitance coupling ratio of C2 is 0.5, 0.75 V (= 1.5 V × 0.5) is added to each storage node voltage. Thus, the storage node SN1 for "1" read and the storage node SN2 for "0" read are 1.3.
5V (= 0.6V + 0.75V), the storage node SN2 for "1" read and the storage node SN1 for "0" read are 0.75V (= 0V + 0.75).
V). Here, the search transistors Ms1 and Ms2
Is preset to a voltage lower than the boosted high-side storage node voltage 1.35 V and higher than the boosted low-side storage node voltage 0.75 V, for example, 0.9 V.

Therefore, in the case of "1" read, the search transistor Ms1 is turned on and the search transistor Ms2 remains off. Therefore, as shown in FIG. 4D, the bit line BL receives the charge from the match line ML to be charged, and the bit auxiliary line / BL maintains 0V. Subsequently, when the sense amplifier is activated, the high-level bit line B
The L voltage is amplified to the power supply voltage, and the voltage difference from the low-level bit auxiliary line / BL is amplified to 1.5V. vice versa,
In the case of "0" read, the search transistor Ms2 is turned on, and the search transistor Ms1 remains off. Therefore, as shown in FIG. 5D, bit auxiliary line / BL receives charge from match line ML to be charged, and bit line B
L maintains 0V. Subsequently, when the sense amplifier is activated, the high-level bit auxiliary line / BL voltage is amplified to the power supply voltage, and the voltage difference from the low-level bit line BL is amplified to 1.5V. After this sensing operation, the match line ML is returned to the low level of 0V. By the above operation, the "1" storage data and the "0" storage data are correctly read to the bit line pair BL, / BL.

FIGS. 6A to 6C are timing charts showing a voltage change of each signal line at the time of refresh. In the refresh, the above-described reading and writing are continuously performed. That is, the bit line pair BL, / BL is discharged to be in a floating state at 0 V, the match line ML is raised from 0 V to a high level of 1.5 V, and the sense amplifier is activated to perform reading. When the word line WL is raised to 1.5 V after the voltage difference between the bit line pair BL and / BL has opened to 1.5 V, the read voltage is used as the write voltage as it is, and the voltage corresponding to the read data is changed to the storage node SN1. , SN2. Therefore, it is possible to easily restore the stored data deteriorated due to the off-leak current of the write transistors Mw1 and Mw2. Thereafter, the word line voltage is returned to 0 V, thereby completing the refresh.

FIGS. 7A to 7E show a cell circuit diagram describing the applied voltage conditions at the time of searching for the "1" storage data cell ("1" search) and the voltage change of each signal line. 4 shows a timing chart. FIGS. 8A to 8E show a cell circuit diagram describing the applied voltage conditions at the time of searching for a “0” storage data cell (“0” search) and timings showing voltage changes of each signal line. 2 shows a chart.

At the time of retrieval, first, as shown in FIGS. 7C to 7E and FIGS. 8C to 8E, the bit line pair B
L, / BL and the match line ML to the high level of 1.5V
Precharge with. At this time, the storage node voltage is boosted as in the read operation, and the high-side storage node voltage becomes 1.35 V and the low-side storage node voltage becomes 0.75 V. Thereafter, the voltage of the bit line BL or the bit auxiliary line / BL corresponding to the low level side of the search data falls from 1.5V to 0V.

When the search data matches the stored data, both search transistors Ms1 and Ms2 maintain the off state. This is because the search transistor whose source is lowered to a low level and the voltage between the drain and the source is 1.5 V has the gate voltage of the low-side storage node voltage 0.75 V
This is because it cannot be turned on because of V, and the other search transistors cannot be turned on because the voltage between the source and the drain is 0 V. Specifically, assuming that bit complement line / BL is set to 0 V at the time of "1" search as shown in FIG. 7E, when the search data matches the storage data, that is, when storage node SN1 has a high-level voltage of 1.35 V And the storage node SN2 is held at a low-level voltage of 0.75 V, as described above, the search transistor Ms1 cannot be turned on because the voltage between the source and the drain is not applied, and the gate voltage becomes Search transistor M for low reason
s2 cannot be turned on. Similarly, when the bit line BL is set to 0 V at the time of "0" search as shown in FIG. 8D, the search data matches the storage data, that is, the storage node S
If N1 is held at a low-level voltage of 0.75 V and storage node SN2 is held at a high-level voltage of 1.35 V, the reason is opposite to that at the time of "1" search, that is, the gate voltage is low. The search transistor Ms1 cannot be turned on, and the search transistor Ms2 cannot be turned on because the voltage between the source and the drain is not applied.

When the search data does not match the stored data, only the search transistor whose source is lowered to 0 V among the two search transistors Ms1 and Ms2 is turned on. This is because the gate voltage of the search transistor whose source is reduced to 0 V is 1.35 V on the high-side storage node. More specifically, assuming that the bit complement line / BL is set to 0 V at the time of "1" search as shown in FIG. 7E, the search data does not match the storage data, that is, the storage node SN1 has a low-level voltage of 0.75 V When the storage node SN2 is held at a high-level voltage of 1.35 V, the search transistor Ms2 has a source-drain voltage of 1.
5 V and the gate voltage is 1.35 V, which is larger than the threshold voltage 0.9 V, so that the transistor turns on, a current flows from the match line ML to the bit auxiliary line / BL, and the precharge voltage 1.5 V of the match line ML decreases. . At the same time, the voltage of storage node SN2 capacitively coupled to match line ML also decreases,
This voltage is the threshold voltage of the search transistor Ms2.
When the voltage becomes 9 V, the search transistor Ms2 is cut off. That is, when the match line ML is at 0.6V, the voltage of the storage node SN2 is 0.9V (= 0.6V +
0.6V × 0.5) so that the search transistor Ms2
Is cut off, the discharge of the match line ML stops at 0.6 V, and the voltage does not become lower than this. Similarly, FIG.
If the bit line BL is set to 0 V at the time of "0" search as shown in (D), if the search data does not match the storage data, that is, the storage node SN1 is held at the high-level voltage 1.35V, and the storage node SN2 is set at the low level. Level voltage 0.75
When held at V, the search transistor Ms1 is turned on because the source-drain voltage is 1.5 V and the gate voltage is 1.35 V, which is larger than the threshold voltage 0.9 V, and the search transistor Ms1 is turned on from the match line ML to the bit line. A current flows through BL,
The precharge voltage 1.5 V of the match line ML decreases.
At the same time, the voltage of the storage node SN1 capacitively coupled to the match line ML also decreases, and this voltage is
When the threshold voltage of s1 reaches 0.9 V, the search transistor Ms1 is cut off. That is, when the match line ML is 0.6V, the voltage of the storage node SN1 becomes 0.9V (= 0.6V + 0.6V × 0.5), so that the search transistor Ms1 is cut off, and the match line ML is cut off.
Discharge stops at 0.6V and does not become lower than this.

As described above, in both the "1" search and the "0" search, when the search data set in the bit line pair matches the storage data, the precharge voltage 1.5 V of the match line ML is increased. Match line ML only when there is no change and no match
Of the precharge voltage of 1.5 V drops to 0.6 V. In addition, the lower limit of the match line voltage drop in the case of a mismatch is the threshold voltage Vths of the search transistor and the capacitor Cth.
By changing the capacitance of C1 and C2, the voltage can be arbitrarily set within a range greater than 0V and less than 1.5V.

Usually, this search operation is performed simultaneously among a plurality of cells. For example, after all or a plurality of word lines WL and a plurality of match lines ML within a search target range are precharged to a high level all at once, a plurality of bit line pairs BL and / BL are used as search data for one page or A bit string of a specific length such as one word is set. At this time,
If even one bit does not match, the voltage of the match line ML decreases. However, only on the specific word line WL whose address matches, the match content of the same row completely matches the search content (storage bit string). Voltage does not change. In this way, an address where the bit string of the search data completely matches the storage content can be detected.

In the CAM cell according to the present embodiment, the lower limit of the voltage drop of the match line ML in the case of the above-mentioned mismatch can be arbitrarily set to 0 V or more. There is an advantage that the logic of the ML can be quickly determined. Assuming that the voltage of match line ML is reduced to 0 V, a plurality of cells connected to the same bit line pair are stochastically inconsistent in half, and a large cell current flows into bit line BL or bit auxiliary line / BL. Since the potential temporarily becomes higher than 0 V, the voltage drop rate of the match line ML may be slowed down. In the present embodiment, since the voltage of the match line ML is reduced only to about 0.6 V, for example, this does not occur, and the power consumption can be suppressed to a necessary minimum. In addition, if the logic amplitude of the match line ML is 0.6 V, sensing can be sufficiently performed.

Making the lower limit of the voltage drop of the match line ML larger than 0 V in the case of such a mismatch does not correspond to the diode Md in a conventional DRAM-based CAM cell.
(FIG. 9). In the CAM cell according to the present embodiment, since the capacitors C1 and C2 are connected between the match line ML and the storage nodes SN1 and SN2, the above object can be achieved without providing such a diode. There is an advantage that the area is small. Also,
Unlike the conventional CAM cell, a wiring for applying a constant voltage (cell plate voltage Vcp) to the capacitors C1 and C2 is not required. In this sense, the cell area can be reduced, and a manufacturing process for the wiring is unnecessary. .

For the above reasons, the CA according to this embodiment is
The M cell can reduce the bit cost as compared with the conventional CAM cell shown in FIG.

[0035]

According to the semiconductor memory device and the operation method thereof according to the present invention, the number of elements is smaller, the wiring for supplying a constant voltage is unnecessary, and the content address memory function has a reduced bit cost. A semiconductor memory device and an operation method thereof can be proposed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a CAM cell of a semiconductor memory device according to an embodiment.

FIG. 2A is a cell circuit diagram describing an applied voltage condition at the time of writing “1”. (B) to (E) are timing charts showing voltage changes of each signal line and the storage node when "1" is written.

FIG. 3A is a cell circuit diagram describing an applied voltage condition at the time of writing “0”. (B) to (E) are timing charts showing voltage changes of each signal line and a storage node when “0” is written.

FIG. 4A is a cell circuit diagram describing an applied voltage condition when “1” is read. (B) to (D) are timing charts showing the voltage change of each signal line when "1" is read.

FIG. 5A is a cell circuit diagram describing an applied voltage condition when “0” is read. (B) to (D) are timing charts showing voltage changes of the respective signal lines when "0" is read.

FIGS. 6A to 6C are timing charts showing a voltage change of each signal line at the time of refresh.

FIG. 7A is a cell circuit diagram describing an applied voltage condition at the time of “1” search. (B) to (E) are timing charts showing voltage changes of each signal line at the time of “1” search.

FIG. 8A is a cell circuit diagram describing an applied voltage condition at the time of “0” search. (B) to (E) are timing charts showing voltage changes of each signal line at the time of “0” search.

FIG. 9 shows a general-purpose DRAM as a kind of a conventional CAM cell.
FIG. 3 is a circuit diagram illustrating a configuration of a base CAM cell.

[Explanation of symbols]

Mw1, Mw2: write transistors, Ms1, Ms
2: Search transistor, C1, C2: Capacitor, WL
... word line, ML ... match line, BL ... bit line (first or second bit line), / BL ... bit auxiliary line (first or second bit line), SN1, SN2 ... storage node, Vth
w: threshold voltage of write transistor, Vths:
Search transistor threshold voltage.

Claims (6)

[Claims] A first write transistor having a gate connected to a word line and one of a source and a drain connected to a first bit line; a gate connected to a word line and one of a source and a drain connected to a second bit line; A second write transistor connected to the first write transistor, a first search transistor connected between the first bit line and the match line, and a gate connected to the other of the source and the drain of the first write transistor; A second search transistor connected between a second bit line and the match line and having a gate connected to the other of the source and the drain of the second write transistor; a gate of the first search transistor and the match line; And a second capacitor connected between the gate of the second search transistor and the match line. A semiconductor memory device having: 2. The first and second search transistors according to claim 1,
When a high level voltage is applied to the match line,
2. The semiconductor memory device according to claim 1, wherein the first and second search transistors have a threshold voltage between a gate voltage increased from a high-level storage voltage and a gate voltage increased from a low-level storage voltage. 3. A first write transistor having a gate connected to a word line and one of a source and a drain connected to a first bit line; and a gate connected to a word line and one of a source and a drain connected to a second bit line. A second write transistor connected to the first write transistor, a first search transistor connected between the first bit line and the match line, and a gate connected to the other of the source and the drain of the first write transistor; A second search transistor connected between a second bit line and the match line and having a gate connected to the other of the source and the drain of the second write transistor; a gate of the first search transistor and the match line; And a second capacitor connected between the gate of the second search transistor and the match line. A method of operating a semiconductor memory device comprising: setting a voltage according to storage data to the first and second bit lines at the time of writing, activating the word line and setting the first and second writing transistors A method of operating a semiconductor memory device, wherein the semiconductor memory device is turned on to transmit a voltage corresponding to a set voltage of the first and second bit lines to gates of the first and second search transistors. 4. The operating method of a semiconductor memory device according to claim 3, wherein said first and second bit lines are brought into an electrically floating state at a low level during reading, and said match line is raised from a low level to a high level. . 5. A search circuit according to claim 5, wherein said first and second bit lines and said match line are set to an electric floating state at a high level, and a voltage corresponding to search data is applied to said first and second bit lines. 4. The operation method of the semiconductor memory device according to 3. 6. The first and second search transistors include:
When a high level voltage is applied to the match line,
4. The semiconductor memory device according to claim 3, wherein said first and second search transistors have a threshold voltage between a gate voltage raised from a high-level storage voltage and a gate voltage raised from a low-level storage voltage. How it works.