JP2002092059A - System for designing wiring of printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system for designing the writing of a printed wiring board capable of eliminating any resuming process. SOLUTION: A circuit diagram based on specifications is generated, and NET information 22, component information 23 and manufacture information 24 are collected, the shortage of the component information is checked (25), and when the component information is short, the similar component information is added (26). Then, constraint information 27 including inter-line distance calculation 28, wiring length condition preparation 29, damping resistance value calculation 30 for impedance matching and wiring width calculation 31 is calculated, and its transition to arrangement/wiring processing 32 is performed. The arrangement/wiring processing is generated from the constraint information and the manufacture information 24, and when the result of wiring is compared with the constraint information (33), the constraint information is not fulfilled in most cases. Therefore, relaxing information 34 is added for making up for the difference, and it is verified that the constraint condition is fulfilled (35), and in the case of N.G., the design of the arrangement/wiring processing is changed, and in the case of OK, the data are adopted as board data (36).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board design system, and more particularly, to an algorithm in which circuit information including NET information and circuit element information is input and conditions necessary for printed wiring board design are determined in advance. The present invention relates to a computer system for automatically extracting based on a variable factor (relaxation information) that can be changed.

[0002]

2. Description of the Related Art FIG.
2 shows a manufacturing flow. Conventionally, circuit information (2, 3) is first created based on product specification 1, and then pattern information (4, 3) is created.
5) is prepared, and an actual wiring board is prepared (6). in this case,
In each phase, NET information, component information, and pattern information (wiring information) are combined. NET
The information means connection information between circuit elements.

However, this method has a problem that the design of circuit information and wiring information, particularly wiring information, often depends on human experience and sense, and it is difficult to process the information uniformly and in a short time. In recent years, the circuit operating frequency has been increased, and it is necessary to consider beforehand whether or not the designed pattern information satisfies the specifications by simulation in advance, and to redesign if there is any inconvenience. There is a problem that it takes time and productivity is low.

In general, various conditions have been studied for the wiring of signals having a high operating frequency.
Other elements in the actual circuit, such as area factors, other low-speed circuit elements, lack of information necessary to set theoretical conditions, lack of information flow due to division of labor between circuit design and pattern design For example, it was difficult to design as described in the literature.

FIG. 2 shows the design flow of this conventional printed circuit board. FIG. 2 (a) shows that the layout and wiring are evaluated by experiments. There is a lot of waste because you have to start over. FIG.
In (b), the placement / wiring is evaluated by simulation, but if the result is still bad, the substrate is created again. In the case of FIG. 2 (c) in which the constraint conditions are analyzed by simulation to determine the placement / wiring, repetitive work is required to satisfy the constraint conditions, and a certain amount of time is required for creating the constraint conditions. I need.

Hereinafter, problems of the related art will be summarized as follows.・ Experiments and analysis using simulators require human skills with specialized knowledge, and the amount that can be handled is limited. -The creation of design rules requires the judgment of a person with specialized knowledge, and the amount that can be handled is limited.・ Insufficient human resources with specialized knowledge.・ Education to have specialized knowledge requires cost and time.・ Each person needs to invest in analytical tools and support tools, such as simulators, used to create design rules.・ A certain amount of time is required for analysis and preparation using experiments and simulators, which generally leads to delays in product development. -It takes a certain amount of time to create design rules based on the results of analysis by experiments and simulators, which generally leads to delays in product development. -The analysis method and range differ depending on the level of the human being analyzed, which leads to variation in quality. -The content of the judgment varies depending on the level of the person who makes the judgment, which leads to the variation in quality. -Duplicate analyzes using duplicate experiments and simulators are occurring at multiple periods, multiple locations, and multiple products, resulting in waste.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring design system for a printed wiring board which eliminates the process of redoing.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in consideration of an algorithm or an algorithm in which circuit information including NET information and circuit element information is input and conditions necessary for wiring design are determined in advance. This is a computer system that outputs based on a constrained factor (relaxation information) that can be changed.

[0009] The connection information between circuit elements and the component information and circuit information (information indicating the properties of the component) output after the circuit design, which are related to the performance of the component, are input, and it is determined whether the component information is sufficient. . Generally, part information is IBIS, SPICE
This is information called a model, and is used by the above-described simulation device or the like. If there is insufficient component information, similar component information is added based on component information used in the past. In this case, the value may be added by a statistical method, but may be set to the strictest value in that case.

[0010] Based on the above information, wiring constraint information is created. Among them, the driving element capability and the load capacitance are used to determine the wiring length that determines the behavior of the signal. In addition, the pattern width and the damping resistance value are determined in order to match the drive element with the line impedance. The damping resistance value is variable depending on the mounting position between the lines. Finally, a gap for preventing crosstalk between the patterns is determined from the driving element capability and the wiring length.

The placement and routing process is performed based on the various types of constraint information obtained as described above. In this case, there is no problem if everything can be processed within the constraints, but it is practically difficult. Therefore, the constraint condition and the result are compared by the comparing means, the relaxation information is added, and finally the pass / fail is determined, and the transfer to the manufacturing data is performed.

A wiring design system for a printed wiring board according to the present invention extracts a design constraint condition or a design permissible condition from device capability information based on determined extraction conditions or extraction conditions determined each time, and satisfies the restriction conditions. The greatest feature is that the process that could not be performed is processed by adding relaxation information to the process, and the process of returning to the upstream (that is, redoing from the previous step) is eliminated. By doing so, it is possible to eliminate the need to repeatedly feed back and redesign wiring and the like, and to achieve wiring design that satisfies the specifications in a short time.

That is, the method for designing a printed wiring board according to the present invention includes circuit information, NET information,
Based on the extraction conditions determined from the component information or the extraction conditions determined each time, the design constraints or design permissible conditions are extracted and the placement / routing process is performed. By adding a relaxation condition, the circuit data is created without recreating the circuit information and the arrangement / wiring.

Further, the constraint conditions include calculation of a gap, preparation of a wiring length condition, calculation of a damping resistance value, and calculation of a wiring width, wherein impedance matching is first performed. Signaling transmission IC
Is characterized by including a condition for ignoring the output waveform.

Further, the relaxation condition may be such that the rising waveform at each receiver pin of the CLK signal in the case of multi-stage connection does not have a shelf, so that the wiring length is shortened, a buffer is added, or a buffer having a slow rising time is used. Or a change such as a parallel termination.

[0016]

FIG. 3 is a conceptual diagram showing a flow of a wiring design system for a printed wiring board according to the present invention.
As shown in FIG. 3, for a process that cannot satisfy the constraint condition, the relaxation information 17 is added to the arrangement 14 and the wiring 15 to perform the process again as in the related art (return to the upstream).
Satisfy the specifications without performing.

FIG. 4 shows a more detailed flow of the printed wiring board wiring design system of the present invention. FIG.
In the same manner as described above, first, a circuit diagram is created based on specifications (step 20), and NET information 22, component information 23, and
Are collected and checked for lack of parts information (step 25). When the component information is insufficient, similar component information is added and used (step 26). Next, calculation of the gap between the lines 28, preparation of the wiring length condition 29, calculation of the damping resistance value for impedance matching 3
The constraint information 27 such as 0 and the calculation 31 of the wiring width is calculated. Initially, the placement / wiring process is created from the NET information 22, the component information 23, and the manufacturing information 24, but when compared with the constraint information (step 33), the constraint condition is not satisfied at most once in most cases. . Therefore, the mitigation information 34 is used to fill the difference of the comparison.
And verify whether the constraints are satisfied (Step 3)
5). In the case of NG, a design change described later is added to the placement / wiring processing, and if a match with the relaxation information is found, the result is OK and adopted as substrate data (step 36).

FIG. 5 shows the internal configuration of this system. In FIG. 5, the NET information 22 determines the degree of importance of the signal based on the type of the signal as described later.
In accordance with LOGIC 3, impedance matching is first considered (37). Next, when the number of additional connections is plural, the maximum wiring length is extracted (39), and the wiring method is extracted (40). When the number of added connections is one-to-one connection, the maximum wiring length is not considered as satisfying the relaxation condition as described later. When the wiring method is determined, the process shifts to specific arrangement and wiring (41).

FIG. 6 shows a more detailed flow relating to the processing of the constraint information 27 of FIG. Since the layer structure 42 and the wiring width 43 of the printed circuit board are almost fixed as a standard, the characteristic impedance of the line is calculated based on these (step 44). NET information 22, parts information 23
From the calculation of the output impedance described later (step 4)
5), calculation of timing information (step 46), and review of relaxation information (step 47) are performed. The calculated output impedance is compared with the characteristic impedance of the line (Step 4).
8) The impedance matching is verified (step 49). If the matching has not been achieved, a change in the pattern width (51), a change (52) or addition (53) in the damping resistance value, or a change (54) in the layer configuration is considered and impedance matching is performed. After the impedance matching (matching) is obtained, the correspondence is changed according to the type of signal (step 56). In the case of CLK (clock signal), the wiring length is adjusted according to the wiring restriction information of the CLK signal (step 56). 57). In addition, timing conditions are added to all signals (58), and finally wiring constraint information is examined (step 59). For parts that do not satisfy the constraint conditions, the constraint conditions are satisfied by taking into account the relaxation conditions. (Steps 60 and 61). These are the outputs of the device.

FIG. 7 shows a known formula (general formula) for calculating the characteristic impedance of a line. The definition of the output impedance and the like are well known as shown in FIG. Also,
The equations for calculating the parameters of the microstrip line and strip line used in the present invention are shown in FIGS.

FIG. 8 is a conceptual diagram of impedance matching when a damping resistor is inserted. The output impedance Rs of the transmission IC by the damping resistor 75
And the characteristic impedance Zo of the line are adjusted. After these basic designs are completed, the following relaxation conditions are examined, and the board is designed without making significant changes in circuit layout and wiring again. In other words, the above-mentioned “relaxation condition” is adopted in order to somehow satisfy the specifications without making significant changes to the basic structure of the circuit arrangement and wiring.

Next, the relaxation information which is the most significant feature of the present invention will be described. FIG. 9 shows a flowchart of the mitigation information study. The placement / wiring processing 82 includes the constraint information 81
And the relaxation information 84 is examined for the wiring that does not satisfy the constraint information. This is the process 62 in FIG.

As shown in FIGS. 14, 15 and 16, the signals used in the electronic circuit include a CLK signal (clock pulse) and a signal pulse. Generally, a logic circuit determines the logic (1, 0) of a signal pulse when a CLK signal comes in as shown in FIG.
Since a logic output is output (for example, a set / reset / flip / flop circuit) and the CLK signal is detected at the rising and falling portions of the pulse, FIG.
As shown in (1), the rising 110 and falling 111 portions of the CLK signal are important. In other words, the area where noise enters and malfunctions are indicated by reference numerals 116 and 117 in FIG. 14. For example, even if noise is superimposed on the flat portion 112 of the pulse, the circuit operation is not significantly affected. This portion becomes a noise OK area. On the other hand, since it is important that the signal pulse other than CLK is in one of the states (1, 0) when the CLK signal enters, a flat portion of the pulse signal (FIG. 15) is opposite to the CLK signal. It is important that (114) is stable. Therefore, the signal pulse is set up before the time 118 when the CLK signal enters.
Time and the incoming time of the CLK signal 118
Is followed by Hold Time, and this period is a noise NG area. Therefore, in the case of a signal pulse, the region of the rising 113 and the falling 115 is a noise OK region. Further, since the CLK signal and the signal pulse need to be synchronized, care is taken that the time delays of the respective wiring lengths are the same. Note that the waveform of the flat portion of the signal pulse is distorted due to crosstalk or mismatch. However, if impedance matching and the interval between lines are sufficiently considered, malfunctions due to the disturbance of the flat portion almost occur. Absent.

FIG. 33 shows the relationship between these timings between a specific transmitting IC and a specific receiving IC. In FIG. 33, reference numeral 170 denotes a CLK signal (clock) of the transmission IC.
When this arrives at the receiving IC after a propagation delay, the waveform becomes a waveform 171. Similarly, reference numeral 172 denotes a signal pulse at the output terminal of the transmitting IC, which delays the propagation and causes
Reach C. In FIG. 33, f is a wavelength, and t _PD is a CLK signal output in the transmission IC (ASIC1).
This means an internal delay until a signal pulse is output in synchronization with the LK signal, and the internal delay varies depending on manufacturing conditions, use conditions, and the like. Therefore, max and min are displayed.

FIGS. 33B and 33C show the respective ICs.
The signal is detected at the point 174 as described above. FIG. 33 shows the case of the internal clock. FIG. 34 shows the case where the CLK signal to each IC is supplied from the external CLK source 175.
The basic operation is the same as in FIG. 33 except that the difference between the CLK signal reaching SIC1 and the CLK signal reaching ASIC2 is displayed as Skew Time 176.

The circuit line of the printed wiring board is formed of a distributed constant line, and its general form is shown in FIG.
It is shown in FIG. In FIG. 10A, 90 is a transmitting IC (driver), 92 and 94 are receiving ICs (receivers), and 91 and 93 are branch pins provided on a line. In the figure, the output terminal of the transmission IC matches the line impedance. Therefore, an output of 1/2 of the power supply voltage Vcc is generated at the output terminal of the transmission IC. One-on-one
In the case of connection, as shown in FIG. 13D, the output propagates on the line (106), and since the final end 105 is open, it is totally reflected at the final end to become a reflected wave 107. That is, returning to FIG. 10B, the traveling wave 95 is totally reflected at the final end C, and the signal voltage at the final end becomes Vcc due to the total reflection. The totally reflected reflected wave becomes a backward wave 96 and propagates toward the output terminal of the transmission IC. C at this time
FIGS. 11A and 11B show waveforms at the rising portion of the LK signal (clock signal).

In FIG. 11A, A1 is an output waveform at the output terminal of the transmitting IC, and its magnitude is 1/2 Vcc as described above. B1 is a waveform when this output reaches point B, and A1 appears with a delay of the propagation time between A and B. C1 is a waveform generated at the point C of the traveling wave, and appears with a delay of the propagation time between A and C.
C2 is a waveform generated at the point C by total reflection. Naturally, there is no time delay. Since the input waveform is Ｖ Vcc, the reflected wave is superimposed on this and rises from Ｖ Vcc as shown by C 2 １ ／ V
The voltage waveform has a magnitude of cc, that is, a voltage waveform up to Vcc. B2
Is a waveform when the reflected wave reaches the point B. The waveform occurs after C2 by a propagation time between C and B.
Similarly, A2 is a waveform when the reflected wave reaches point A. The waveform occurs after C2 by a propagation time between C and A.

FIG. 12 shows how the traveling wave and the reflected wave are combined at each point. A, B, and C in FIG. 12 are composite waveforms at the points A, B, and C, respectively. That is, A is A
1 + A2, B is B1 + B2, and C is C1 + C2. From the figure, it can be seen that the points 97 and 98 of the pulse rising characteristics occur at the points A and B. In the case of point C, 99, there is no time delay, so that the waveform is a waveform obtained by simply adding the traveling wave and the reflected wave.

As described above, in the case of the CLK signal, since the logic (1, 0) is detected at the rising or falling portion, the formation of the above-mentioned shelf portion in the CLK signal is a cause of malfunction, and should be avoided in the wiring design. There must be. However, the waveform is a problem at the receiver pins (for example, the points B and C), and the waveform collapse at the output terminal A of the transmission IC does not affect the circuit operation. Therefore, in the present invention, the collapse of the waveform at the output terminal A of the transmission IC is designed to be ignored. This is the basis of the "relaxation condition" in the present invention.

The reason why the shelf portion can be formed will be described with reference to FIG. 13. In FIG. 13 (d), the light proceeds from the transmission output end or the first reception end (PP) 104 (106) and is reflected at the final end 105. The total time of returning to the PP point (107) is defined as Tpd, and the rise time in FIG.
Assuming that r / 2, Tpd = Tr / as shown in FIG.
In the case of 2, the phases of the traveling wave and the reflected wave match, and a clear rising waveform 103 is obtained. Also, Tpd <Tr / 2
In the case of FIG. 1, the traveling wave and the reflected wave partially overlap as shown in FIG.
There is no problem because no shelf portion as shown in FIG. The problem is when the waveform of FIG. The Tpd is determined by the line length from the transmission output end or the first reception end (PP) to the last end.

Therefore, if Tpd ≦ Tr / 2, no shelf can be formed in the waveform. That is, in FIG. 13D, the wiring at the probe point (PP) → the last end is Tpd ≦ T
If r / 2, no shelf can be formed in the waveform. The reason why the circuit malfunctions when this shelf portion occurs is as follows.

[0032] it is determined generally logic pulse input (1,0), that is, whether the determination of the ON-OFF is below or exceeds the V _IH and V _IL of FIG. by the way,
The rising shelf portion is actually 10 in FIG.
As shown in FIG. 8, the first drop occurs at the shelf portion and then the second rise occurs, so that a few crossing points occur across a certain threshold in the logic uncertainty region between V _IH and V _IL . This means that a detection pulse is generated each time (generally called a hazard phenomenon), which causes a malfunction of the circuit.

As mentioned above, the problem of the shelf portion of the waveform is that of the receiver pin for detecting the pulse.
Therefore, the output terminal of the transmission IC and the receiver pin have a one-to-one correspondence.
In the case of connection, the timing can be satisfied because no shelf portion of the rising waveform occurs at the receiver pin,
If the waveform at the point A of the transmitting IC is ignored, the maximum wiring length need not be considered under the condition that the timing can be satisfied. However, for example, as shown in FIG. 10A, when the output terminal of the transmission IC and the receiver pin are connected in a one-to-many connection, a shelf portion of the rising waveform does not occur at the receiver pin C as described above. So the timing is satisfactory,
Since the reflected wave from point C has a time delay at point B, if the wiring length between B and C is long, the respective waveforms are changed as shown in FIG.
As shown in FIG. 12B, the combined waveform becomes B1 and B2, and a shelf portion occurs.

Based on the above assumptions, a specific description will be given of the "relaxation condition" which is the subject of the present invention. FIG. 17 shows a flowchart for studying the “relaxation condition” of the wiring length. When the circuit design considering the impedance matching is determined (step 130), the maximum wiring length (l) is calculated (step 131). The maximum wiring length is a wiring length that has a maximum delay time in which no shelf portion occurs at the rise of the CLK signal. Next, a placement operation is performed in consideration of the maximum wiring length extracted from the circuit (step 132). Next, C
The Manhattan length (lm) of each line of the LK signal is calculated (step 133). Here, the “Manhattan length” is as follows.

In general, a circuit board has a layered structure. For example, the upper layer is a wiring in the X-axis direction, the lower layer is a wiring in the Y-axis direction, and these are connected by through holes to realize a desired wiring. At this time, since the oblique wiring obstructs other wiring, it is not adopted in principle except for an extremely short wiring. Therefore, it is general that the wiring is first guided in the X-axis or Y-axis direction, and then wired at right angles in the Y-axis direction or the X-axis direction. Accordingly, the sum of the length of the wiring on the X axis and the length of the wiring on the Y axis is the normal wiring length, which is called "Manhattan length".

Next, if l <lm (step 134), it is verified whether the wiring is a multi-stage connection (step 135).
In the case of one-to-one connection, the wiring is adopted as it is because it satisfies the relaxation condition. In the case of multi-stage connection, consideration is given to reducing the wiring length from the first receiving end to the last receiving end (step 136). In the case of FIG. 10A as an example, since the point where the leading edge of the CLK signal has a ledge and causes a problem is point B, if the wiring length between B and C is shortened, the CLK at point B is reduced. This is because the rising portion of the signal no longer has a shelf portion, which satisfies the relaxation condition. In this way, if the wiring length from the first receiving end to the last receiving end can be 1 or less, the relaxation condition is satisfied and the wiring is adopted.

On the other hand, if the wiring is difficult, one buffer is added to the wiring and the design is changed so that the distance from the first receiving end to the last receiving end is equal to or less than the maximum wiring length (step 1).
38). The addition of the buffer is performed between B and C in the case of FIG. This is shown in FIG.

In FIG. 35, when the buffer D is added, the reflected wave from D reaches the point B with a delay that does not form the shelf, so that the above constraint is satisfied. That is, B ~
There is an effect that the wiring length between C is substantially shortened between B and D. Alternatively, a parallel termination scheme (step 140) may be employed. The parallel termination method is a special solution in which the terminal end is terminated with a line impedance 180 as shown in FIG. The termination scheme is shown in FIG.
In this case, matching between the driver 183 and the line impedance is not performed.

In FIG. 36, the output impedance of the driver 183 is 40Ω, but the characteristic impedance of the lines 184 and 182 attached on the way is 65Ω.

FIGS. 37A to 37F show the above-mentioned line 182.
Each waveform is shown when the length of is varied. Waveform 19
Although there is almost no delay between 0 and 191, the waveform 192 is
It can be seen that the longer the length of 82 is, the more it is delayed. However, since no reflected wave is generated as described above, no shelf occurs in the waveform of the CLK signal as described above at the receiving IC 181. In addition, since the reflected wave is not generated due to the matching termination, if the line impedance is matched with the driver 183 in the same manner as described above, only a voltage of 1/2 Vcc is output as the CLK signal. Since it is not taken, a voltage is generated up to a voltage higher than the threshold value depending on the wiring conditions. Or
The buffer is changed to one with a slower rise (step 142). If the buffer rises slowly,
The pulse rise time Tr / 2 in FIG. 11A is delayed, and the allowable Tpd in FIG. 13 can be increased. That is, the maximum wiring length can be increased. The order of the adjustment means of 136, 138, 140 and 142 may be changed as occasion demands.

Hereinafter, specific embodiments will be described with numerical values. FIG. 18 is a specific example for performing impedance matching. First, the transmission IC characteristics are confirmed. The table 151 in FIG. 18 is the component information of the transmission IC described by the IBIS model. For example, in the example of the uppermost stage 152, Vcc is 1.4000
In the case of (V), it means that a current of 3.916 × e ⁻² (A) typically flows. Here, e + 00 means e ⁰ .

In the case of FIG. 18A, the output impedance of the transmitting IC which becomes Vcc / 2 is about 40Ω. This is because Vcc is set to 3.3 V in this example,
It is calculated at a value of 1.6 V where cc / 2 is close.

Next, the characteristic impedance (Zo) at each wiring width is calculated from the layer structure, and a damping resistor 150 is inserted as needed. The characteristic impedance of each wiring is calculated according to FIGS. For example, if the line width is widened as in 154, Z ₀ is 40Ω and matching can be achieved. However, if it is difficult due to restrictions on the layout and wiring area, if the line width is reduced as in 153, it will be 75Ω. It is necessary to insert a damping resistor 150 on the output side of the IC to match at point 155.

FIG. 19 shows a specific example of study on the wiring constraint information (CLK signal). First, the rise time of the driver is confirmed from the component information. In FIG. 19, Table 160 shows the rise times displayed by the IBIS model. Ramp means a display item of the rise time. Incidentally, r in the upper part of the table means rise (rise), f in the lower part means fall (fall), and the upper part means that the voltage rises 1.01742 V at 951.044 picoseconds in a typical manner. From this, Tr ≒ 1.585 (nS) is obtained.

The propagation delay speed (nS / ft) is calculated from the relative permittivity of the material of the substrate. Each numerical value is as shown in FIG. In the case of FIG. 19, Tr / 4 is applied between the BC when there is no problem even if the driver waveform is distorted, and Tr / 4 is applied between AC when the driver waveform is distorted and problematic.

As described above, T <Tr / 4 is a formula for calculating the maximum wiring length. Here, T is the propagation delay time of the wiring, Tr
Is the rise time of the output pulse. The calculation is as follows.

From Tr = 1.585 (nS), T <1.
585/4 That is, T <0.39625 (nS) (a) In the case of a microstrip line, S ≒ 1.73 (nS / ft) ≒ 0.144 (nS / in
ch) Therefore, the wiring length satisfying T <0.39625 (nS) is 0.39625 / 0.144 = 2.7517... (inc
h) ≒ 69.8941 (mm) (b) In the case of a strip line, S ≒ 2.20 (nS / ft) ≒ 0.183 (nS / in
ch) Therefore, the wiring length satisfying T <0.39625 (nS) is 0.39625 / 0.183 = 2.1653... (inc
h) ≒ 54.9998 (mm).

FIG. 20 shows a calculation result of the propagation delay used in FIG. The layer structure of the printed wiring board will be described.
Although it depends on the wiring density, in the case of the embodiment of FIG.
3 shows a layer substrate. TOP to BOTTOM represent the L1 to L6 layers of the substrate. In the figure, S is a signal layer (a layer for laying signal lines), P is a Plane layer (a layer processed by a solid such as a power supply / GND), T is a thickness of a copper foil, and H is a thickness of an insulating layer.

As shown in the figure, the propagation time depends on the relative permittivity E
It is calculated by r. FIG. 21 shows an example of extraction of the rise / fall time and output impedance from NET information and component information. Note that a driver pin is an output pin having a transmission IC, and a driver model name is a device type of the transmission IC. The I / O buffer is a driving element. The table of FIG. 21A is also displayed based on the IBIS model. For example, in the case of NET1, the model name of the transmission IC is "TC7
4LCX244FT ", and the third pin of the transmission IC (IC1) has a model name" LCX_T "as an I / O buffer.
RI ”means that it is on. FIG.
(B) is a calculation of the output impedance for each of FIG. 21 (a).

In FIG. 22, the maximum wiring length is calculated from the propagation delay of FIG. 20 and the rise / fall characteristics of FIG. FIG.
3 shows an example in which the characteristic impedance is calculated based on the line width and the layer configuration, and an ideal damping resistance value for matching from the output impedance in FIG. 21 is obtained. If the impedance is not matched, overshoot or undershoot will occur,
Adjust the line width and damping resistance. FIG. 24 shows an example in which impedance matching is performed by changing the line width and the damping resistance value. FIG. 24 shows a modification example.
FIG. 24B shows a comparison with FIG. For example,
In the case of 170 in FIG. 24B, matching is performed only by the damping resistance without changing the line width. In the case of 171, matching is performed by changing the line width to 0.5 mm. In the case of 172, the line width is also changed and a damping resistor is used. In this way, the design is completed when the rating of the input IC is satisfied.

FIG. 25 shows an example of studying the timing information. The internal delay time of the transmitting IC and the setup / hold time of the receiving IC are extracted from the NET information and the component information. CLK is compared with wiring length information, and wiring length information that satisfies the timing is calculated.

The above-described wiring constraint information, impedance matching information, and timing information are fetched into design CAD, and wiring design is performed as shown in FIG. FIG. 27 shows an example of the completed substrate. The characteristics of the substrate are guaranteed, and the reworking operation as in the conventional case can be omitted, so that the efficiency is very high.

[0053]

As described above, when the method for designing a printed wiring board according to the present invention is adopted, the following techniques are required:-Conventionally, analysis using experiments, simulators, and the like requires human skills with expertise. Although there is a limit to the amount that can be obtained, the use of the method of the present invention facilitates substrate design without requiring specialty.

The creation of the conventional design rules requires the judgment of a person having specialized knowledge, and there is a limit to the amount that can be dealt with. However, when the method of the present invention is used, no specialty is required. The design rules can be created in advance, and the board design can be facilitated.

The conventional method requires specialized knowledge, lacks the human resources having the specialized knowledge, and costs and time are required for the education to have the specialized knowledge. With the use of, the board design can be facilitated without requiring any specialty, so that no special human resources are required.

In the conventional method, it is necessary to invest in an analysis tool and a support tool such as a simulator used for creating a design rule for each person. However, when the method of the present invention is used, such a support tool is particularly required. do not need.

Similarly, a certain period of time is required for analysis and preparation using a simulator or the like, which generally leads to delay in product development. Not required. Also, it takes a certain amount of time to create design rules based on the results of analysis by experiments and simulators, which generally leads to a delay in product development. However, the problem of the present invention does not occur. .

In the conventional method, the analysis method and the range are different depending on the level of the person to be analyzed, and the judgment contents are also different depending on the level of the person to be judged, which leads to the fluctuation of the quality. By using the method, you can easily design the board without requiring specialty,
There is no variation by the creator.

In the conventional method, duplicate experiments using duplicate experiments and simulators are performed at a plurality of timings, at a plurality of locations, and at a plurality of products, resulting in waste. Does not occur.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flow of designing and manufacturing a conventional printed circuit board.

FIG. 2 is a diagram showing a design flow of a conventional printed circuit board.

FIG. 3 is a diagram showing a design flow of the printed circuit board of the present invention.

FIG. 4 is a flowchart of a detailed wiring design system for a printed wiring board according to the present invention.

FIG. 5 is a diagram showing an internal configuration of a printed wiring board wiring design system of the present invention.

FIG. 6 is a more detailed flow relating to processing of constraint information of FIG. 4;

FIG. 7 is a diagram showing a calculation formula of a characteristic impedance.

FIG. 8 is an explanatory diagram of impedance matching.

FIG. 9 is a flow chart for studying relaxation conditions according to the present invention.

FIG. 10 is a diagram illustrating reflection of wiring.

FIG. 11 is a diagram illustrating a traveling wave and a reflected wave of a CLK signal.

FIG. 12 is a diagram illustrating a rising waveform of a CLK signal.

FIG. 13 is a diagram illustrating a rising waveform of a CLK signal.

FIG. 14 is an explanatory schematic diagram of a CLK signal.

FIG. 15 is an explanatory schematic diagram of signal pulses other than the CLK signal.

FIG. 16 is a diagram illustrating timing.

FIG. 17 is a flowchart for studying conditions for relaxing the wiring length.

FIG. 18 is a diagram showing a study example of impedance matching.

FIG. 19 is a diagram showing an example of studying a wiring length.

FIG. 20 is a diagram illustrating an example of studying a propagation delay time.

FIG. 21 is a diagram illustrating a study example of rise time.

FIG. 22 is a diagram illustrating an example of studying wiring constraint conditions.

FIG. 23 is a diagram showing a study example of impedance matching.

FIG. 24 is a diagram showing a study example of impedance matching.

FIG. 25 is a diagram showing a study example of timing information.

FIG. 26 is a schematic diagram for incorporation into CAD.

FIG. 27 is a diagram showing an example of a completed substrate.

FIG. 28 is a diagram showing a general expression of output impedance.

FIG. 29 is a diagram showing a calculation formula of characteristic impedance.

FIG. 30 is a diagram showing another example of the calculation formula of the characteristic impedance.

FIG. 31 is a diagram illustrating another example of the calculation formula of the characteristic impedance.

FIG. 32 is a diagram illustrating another example of the calculation formula of the characteristic impedance.

FIG. 33 is a diagram showing a time chart between a transmission IC and a reception IC.

FIG. 34 is a diagram showing another example of the time chart between the transmission IC and the reception IC.

FIG. 35 is a schematic diagram of buffer addition.

FIG. 36 is an explanatory diagram of a parallel termination method.

FIG. 37 is a waveform diagram of the parallel termination method.

FIG. 38 is an explanatory diagram of a parallel termination.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Circuit diagram 2 Circuit diagram CAD 3 Circuit information 4 Arrangement wiring CAD 5 Pattern information 11 Circuit 13 Restriction condition 14 Arrangement 15 Wiring 17 Relaxation condition 27 Restriction information 22 NET information 23 Component information 42 Layer configuration 43 Wiring width 75 Damping resistance 90 Transmission IC 92 Receiving IC 94 Receiving IC 101 Shelf part

[Procedure amendment]

[Submission date] September 26, 2000 (2009.2)
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction contents]

Next, the characteristic impedance (Zo) at each wiring width is calculated from the layer structure, and a damping resistor 150 is inserted as needed. The characteristic impedance of each wiring is calculated according to FIGS. For example, if the line width is widened as 154, Zo becomes 40Ω and matching can be achieved. However, if it becomes difficult due to restrictions on the layout and wiring area, if the line width is reduced as 153, it becomes 75Ω. , It is necessary to insert a damping resistor 150 at the output side and match at point 155.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 18 is a diagram illustrating a study example of impedance matching.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 23 is a diagram showing a study example of impedance matching.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 24 is a diagram showing a study example of impedance matching.

[Procedure amendment 5]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

FIG. 5

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoshi Yoshino 3-23-3 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Inside Shin-Yokohama Tobu AK Building SOWA CORPORATION (72) Inventor Tomoki Yamada Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa 3-23-3 Shin-Yokohama Tobu AK Building F-term in Sowa Corporation (reference) 5B046 AA08 BA05 BA06 JA03 KA05

Claims (10)

[Claims] 1. A design constraint condition or a design permissible condition is extracted based on an extraction condition determined from circuit information, NET information, and component information based on a product specification or an extraction condition determined each time. By adding relaxation conditions to the placement / wiring processing that did not satisfy the constraints or allowable conditions, the board data is created by a partial design change without basic reworking of circuit information and placement / wiring A method for designing a printed wiring board, characterized in that: 2. The print according to claim 1, wherein the constraint conditions include calculation of a gap, creation of a wiring length condition, calculation of a damping resistance value, and calculation of a wiring width, and first perform impedance matching. Wiring board design method. 3. The system according to claim 1, wherein said permissible condition is a transmission I of a CLK signal system.
3. The method for designing a printed wiring board according to claim 1, wherein a condition for ignoring the output waveform of C is included. 4. The method according to claim 1, wherein the relaxing condition is a multi-stage connection.
Any change such as shortening the wiring length, adding a buffer, using a buffer with a slow rise time, or using parallel termination so that there is no shelf in the rising waveform at each receiver pin of the K signal The method for designing a printed wiring board according to any one of claims 1 to 3, further comprising: 5. It has a NET information DB and a parts information DB,
A means for matching impedance based on circuit information based on product specifications, a means for extracting a maximum wiring length for a CLK signal system, and a means for extracting a wiring method for each determined wiring length are provided. A printed circuit board designing apparatus, which determines a basic circuit layout and wiring, and then extracts a relaxation condition that satisfies the maximum wiring length, and designs a board by partially changing the layout and wiring. . 6. The printed wiring according to claim 5, wherein the design of the impedance matching is performed by calculating a gap, creating a wiring length condition, calculating a damping resistance value, calculating a wiring width, and the like. Board design equipment. 7. The transmission condition of a CLK signal system is defined as the relaxing condition.
7. The printed wiring board designing apparatus according to claim 5, wherein a condition for ignoring the output waveform of C is included. 8. When the relaxation condition is a multi-stage connection,
Any change such as shortening the wiring length, adding a buffer, using a buffer with a slow rise time, or using parallel termination so that there is no shelf in the rising waveform at each receiver pin of the K signal The printed wiring board designing apparatus according to any one of claims 5 to 7, further comprising: 9. A process of calculating a characteristic impedance of a line from a layer configuration and a wiring width, a process of calculating output impedance, timing information, and relaxation information from NET information and component information, and comparing the characteristic impedance of the line with the output impedance. A step of performing impedance matching, a step of calculating a wiring length from wiring restriction information in the case of a CLK signal according to the type of signal and adding a timing condition thereto, and a step of adding only a timing condition in cases other than the CLK signal. A process of determining a circuit layout from the information and a process of determining a wiring, and performing a partial design change in consideration of the relaxation information to the above-described layout and wiring, and a process of determining a board design. A magnetic recording medium characterized by including an electronic program for use. 10. The relaxing condition includes a condition for ignoring an output waveform of a transmission IC of a CLK signal system. In particular, in a case of multi-stage connection, wiring is performed so that a rising waveform at each receiver pin of a CLK signal cannot have a shelf. 10. The printed wiring according to claim 9, comprising a step of making any change such as shortening the length, adding a buffer, adopting a buffer having a slow rise time, or using parallel termination. A magnetic recording medium comprising an electronic program for wiring design of a substrate.