JP2002091799A - State monitoring system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a state monitoring system, by which a state such as an abnormality on plural function boards can be monitored from one interrupt signal by a CPU board. SOLUTION: This system is provided with plural function boards FD1 and FD2 as objects to be monitored and a monitor board MD for monitoring the states of the plural function boards, and when an address transmitted from the monitor board is collated with an address set to its own board and these addresses are matched, on the basis of receiving of a strobe signal from the monitor board, each of plural function boards transmits state information to the side of the monitor board. Then, the monitor board successively transmits addresses to each function board, the occurrence of abnormality on any one function board is detected by ANDing the state information from each of the function boards and when abnormality is detected, the interrupt signal is transmitted to a control part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for interrupting a CPU and reading the status information of a functional board each time an abnormal state such as a failure occurs in a plurality of functional boards to be monitored. The present invention relates to a state monitoring system.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration example of a conventional state monitoring system. In FIG. 4, 1 is a state monitoring circuit that inputs various state information and outputs a state change signal when a state change occurs, 2 is an interrupt generation circuit that generates an interrupt to the CPU board by the state change signal, Reference numeral 3 denotes a state information register for holding state information input based on the state change signal. The state monitoring circuit 1, the interrupt generation circuit 2, and the state information register 3 are provided on each of the function boards BD1 and BD2. ing.

Next, the operation of the state monitoring system having the above configuration will be described with reference to the flowchart shown in FIG. First, in each of the status monitoring circuits 1 in the function boards BD1 and BD2, status information is monitored, and when a status change is detected, a status change signal is output (step S5).
1a ... S51b → S52a ... S52b → S5
3). With this signal, the interrupt generation circuit 2 outputs an interrupt signal to the CPU board (step S54), and the state information register 3 holds state information (step S55). Note that an interrupt signal for specifying each function board is assigned in advance for each function board, and the output step S54 of the interrupt signal and the state information holding step S55 may be performed first. The CPU board responds with an interrupt signal
By reading and reading the status information register 3, the status information can be checked and analyzed to know the status information of the function board in which the status change has occurred, and display, analysis, and correction (restarting) are performed (step S56, S57).

[0004]

However, in the state monitoring system described above, when monitoring a plurality of function boards, an interrupt signal for specifying each function board is allocated to each function board and output to the CPU board. Thus, there is a problem that the number of function boards that can be monitored is limited.

[0005] The present invention has been made in view of the above points, and has as its object to provide a state monitoring system in which a CPU board can monitor the state of a plurality of function boards, such as abnormalities, using a single interrupt signal.

[0006]

In order to achieve the above object, a state monitoring system according to the present invention comprises a plurality of function boards to be monitored and a monitoring board for monitoring the states of the plurality of function boards. The plurality of function boards, when the address transmitted from the monitoring board and the address set in the own board are compared and matched, based on the reception of the strobe signal from the monitoring board, the state information The monitoring board transmits the address to each of the function boards sequentially, and detects that an abnormality has occurred in any of the function boards by detecting the logical product of the status information from each of the function boards. When an error is detected, an interrupt signal is transmitted to the control unit.

[0007]

FIG. 1 is a block diagram showing a configuration of a state monitoring system according to an embodiment of the present invention. As shown in FIG. 1, a function board FD as a monitored object
1, FD2 and a monitoring board MD for monitoring the status of these function boards are connected by a common monitoring address bus, control bus and monitoring information bus. Function board F
D1 and FD2 have the same configuration, and taking the function board FD1 as an example, the monitoring board MD via the monitoring address bus
The address comparison circuit 6 compares and compares an address transmitted from the control board with an address preset in its own board and outputs "L" when the address matches, and a monitoring board MD via a control bus.
OR circuit 7 that obtains the logical sum of the strobe signal transmitted from the OR and the output from the address comparison circuit 6, and status information input based on the output from the OR circuit 7 via a monitoring information bus An information data output circuit 8 for outputting to the MD is provided. Note that addresses are sequentially assigned to each function board.

The monitoring board MD includes a timing generator 4 for generating a counter timing signal and a detection timing signal, and a functional board in a repetitive order at the rising edge of the counter timing signal from the timing generator 4 based on the address control signal. An address generator 5 which counts addresses allocated for each and outputs it to the function board via the monitoring address bus; and an AND circuit 9 which inputs status information output from the function board via the monitoring information bus. A sampling circuit 10 for sampling an output from the AND circuit 9 and outputting a state detection signal based on a detection timing signal from the timing generator 4, and a sampling circuit. 10 to the address generator 5 at the fall of the state detection signal from The address signal is set to "H" to stop the address generator 5, the stop is released based on the clear signal from the CPU, and the address controller 11 restarts the generation of the address. An interrupt generator 12 for generating an interrupt signal to the CPU board based on the status data and a status information register 13 for holding the data of the monitoring status bus and outputting the held data to the CPU board.

In the state monitoring system according to the embodiment of the present invention having the above configuration, an address value is allocated to each of the function boards FD1 and FD2, and the address values are sequentially called on the monitoring board MD. The function boards FD1 and FD2 to which the corresponding address values are set output the status information to the monitoring information bus so that the status information becomes “L” when there is an abnormality or the like (desired monitoring state). The monitoring board MD detects the logical product of all data on the monitoring information bus at the sample timing, and when detecting an abnormality, outputs an interrupt signal to the CPU board and simultaneously holds the state information in a register, The CPU allows browsing of status information such as abnormality by interruption.

Next, a specific operation will be described with reference to a timing chart of signals of respective parts shown in FIG. 2 and an operation flowchart shown in FIG. Addresses are allocated in advance to the function boards FD1 and FD2 as monitored boards in advance. The address generator 5 counts the address repeatedly at the rising edge of the counter timing signal (see FIG. 2A) output from the timing generator 4 and outputs the address to the monitoring address bus (see FIG. 2D). I do.

In the function boards FD1 and FD2, the address comparison circuit 6 compares and compares a preset address value with the value of the monitoring address bus.
Is output. When this signal and the strobe signal (see FIG. 2B) output from the timing generator 4 via the control bus are "L", "L" is output from the OR circuit 7 and the information data output circuit 8 At this time, status information such as abnormality is output to the monitoring information bus (see FIG. 2E) (steps S31a to S31b). Here, when the signal on the monitoring information bus is in the desired monitoring state, it is set to “L”.

The monitoring board MD inputs the data on the monitoring information bus to the logical product circuit 9. Then, in the sampling circuit 10, the output of the AND circuit 9 for obtaining the logical product of all data on the monitoring information bus is sampled at the rise of the detection timing signal (see FIG. 2C) output from the timing generator 4. (Step S32). When the output of the AND circuit 9 is “L” (“L” is output when any of the monitoring information is “L” because the desired monitoring state is “L”), the state detection from the sampling circuit 10 is performed. A signal (see FIG. 2F) is output (step S3).
3, an interrupt signal is output to the CPU board by the interrupt generator 12 (step S35), and the status information of the monitoring information bus is held in the status information register 13 (step S36). In the flowchart shown in FIG. 3, whichever of the step S35 of outputting the interrupt signal and the step S36 of holding the state information may be performed first.

In the address controller 11, the enable signal is set to "H" at the fall of the state detection signal, and the address generator 5 is stopped. Then, after the CPU board reads the status information register 13 by an interrupt,
The address generator 5 is restarted by releasing the address controller 13 based on the clear signal from the board (see FIG. 2 (g)).

The CPU board reads the status information register 13 by an interrupt signal to check and analyze the status information and the address to know the status information of the functional board whose status has changed. , Correction (restart) (steps S37, S38). In this way, the CPU board can monitor the status of a plurality of function boards, such as abnormalities, using one interrupt signal. In addition, when a backplane of the plug-in system is provided, it is not necessary to set an address value for each functional board by setting an address value on the backplane.

[0015]

As described above, according to the present invention, the CPU
It is possible to provide a state monitoring system in which a board can monitor the state of a plurality of function boards, such as an abnormality, using a single interrupt signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a state monitoring system according to an embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts in FIG.

FIG. 3 is a flowchart for explaining the operation of FIG. 1;

FIG. 4 is a block diagram showing a configuration of a conventional state monitoring system.

FIG. 5 is a flowchart for explaining the operation of FIG. 4;

[Explanation of symbols]

FD1, FD2 function board, MD monitoring board, 4
Timing generator, 5 address generator, 6 address comparison circuit, 7 OR circuit, 8 information data output circuit, 9
AND circuit, 10 sampling circuit, 11 address controller, 12 interrupt generator, 13 status information register.

Claims (1)

[Claims] 1. A plurality of function boards as monitored objects, and a monitoring board for monitoring a state of the plurality of function boards, wherein the plurality of function boards include an address transmitted from the monitoring board and a self board. When the addresses set in (1) and (2) match, the status information is transmitted to the monitoring board based on the reception of the strobe signal from the monitoring board, and the monitoring board sequentially transmits the address to each function board. A state monitor characterized by detecting that an abnormality has occurred in any of the function boards by logical AND of the state information from each function board, and transmitting an interrupt signal to the control unit when the abnormality is detected. system.