JP2002091575A - Constant voltage output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constant voltage output device which can immediately converge the fluctuation of constant voltage output caused by switching the power supply by attaining the switchable connection between a normal power supply and a backup power supply and always supplying the power to a constant voltage circuit in a prescribed time after the normal power supply is switched to the backup power supply. SOLUTION: This constant voltage output device is provided with a switch circuit 110 which performs switching of voltage between an external normal power supply and a backup power supply and transmits the voltage and also outputs a power switch signal to show selection of the normal or backup power supply, a constant voltage circuit 120 which outputs the constant voltage and a delay circuit 130 which delays the power switch signal that is outputted from the circuit 110. The circuit 120 is always driven in a prescribed time after the normal power supply is switched to the backup power supply, so that the fluctuation of constant voltage output caused by switching the normal power supply to the backup power supply can be immediately converged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an integrated circuit (IC).
And a constant voltage output device for supplying a constant voltage to an IC or the like.

[0002]

2. Description of the Related Art Conventionally, in a timer IC, an RTC (Real Time Clock) IC or the like having a built-in constant voltage circuit, when an external normal power supply is turned on, the constant voltage circuit is driven by the normal power supply. When the normal power supply is off, the constant voltage circuit is driven by an external backup power supply such as a backup battery.

FIG. 3 is a diagram showing a configuration example of such a conventional timer IC. In FIG. 3, a timer IC
300 switches a voltage from an external normal power supply (not shown) and a backup power supply (not shown) to
A switching circuit 310 for transmitting the voltage to the inside of the C300, and a constant voltage circuit 3 for supplying a constant voltage to each circuit inside the timer IC 300
20, an oscillating circuit 330 that oscillates when supplied with a constant voltage from the constant voltage circuit 320, and a timer circuit 340 that activates a timer when supplied with a constant voltage from the constant voltage circuit 320
And

The switching circuit 310 and the constant voltage circuit 320
They are connected by a power supply line 370. The constant voltage circuit 320 and the oscillation circuit 330 are connected to the constant voltage output line 38.
Connected by 0. Further, the constant voltage circuit 320 and the timer circuit 340 are connected by a constant voltage output line 380.

[0005] The normal power supply and the switching circuit 310 are connected by a power supply line 350. Normal power supply
The power is supplied to the switching circuit 310 via the power supply line 350. The backup power supply and the switching circuit 310 are connected by a power supply line 360. The power of the backup power supply is supplied through this power supply line 360,
The signal is supplied to the switching circuit 310.

Here, the normal power supply is turned on / off as appropriate. When the normal power supply is turned on, the output voltage (hereinafter, also referred to as VDD) of the normal power supply is 3 volts or 5 volts. Also, when the power is normally turned off, VD
D is 0 volt.

[0007] The backup power supply is a battery for maintaining the operation of the timer IC when the normal power supply is turned off. The output voltage of this backup power supply (hereinafter also referred to as VBK) is
It is kept between 1.5 volts and 3 volts.

Next, the operation of the conventional timer IC 300 will be described.

First, regarding the operation of the switching circuit 310, V
Description will be made assuming that DD is 5 volts and VBK is 3 volts.

When the normal power supply is on, that is, when VDD is 5 volts, the switching circuit 310 selects the normal power supply and connects the power supply line 350 and the power supply line 370.

When the normal power supply is off, that is, when VDD is 0 volt, the switching circuit 310 selects a backup power supply and connects the power supply line 360 and the power supply line 370.

Next, the operation of the constant voltage circuit 320 will be described.
explain.

As described above, when the normal power supply is turned on, the power supply line 370 is supplied with power from the normal power supply via the switching circuit 310. When the normal power supply is turned off, the power supply line 370 is supplied with power from the backup power supply via the switching circuit 310. That is, regardless of the ON / OFF state of the normal power supply, the power supply line 370 is always supplied with power from the normal power supply or the backup power supply via the switching circuit 310. Therefore, the constant voltage circuit 320 is constantly driven by either the normal power supply or the backup power supply. Therefore, the constant voltage circuit 320 always outputs a constant voltage to the constant voltage output line 380.

However, since the current consumption of the constant voltage circuit 320 is large, there is a problem that the driving time by the backup power supply is short. Therefore, it is conceivable that the constant voltage circuit 320 is intermittently driven without being constantly driven.

FIG. 4 is a diagram showing one configuration example of a timer IC for intermittently driving a constant voltage circuit. 4, a timer IC 400 includes a switching circuit 410 for switching a voltage from an external normal power supply (not shown) and a backup power supply (not shown) and transmitting the voltage to the inside of the timer IC 400.
A constant voltage circuit 420 that supplies a constant voltage to each circuit inside the timer IC 400; an oscillation circuit 430 that receives a constant voltage from the constant voltage circuit 420 and oscillates;
And a timer circuit 440 that operates the timer by receiving a constant voltage from 0.

The switching circuit 410 and the constant voltage circuit 420
The power supply line 470 and the power supply switching signal line 480 are connected. Further, the constant voltage circuit 420 and the oscillation circuit 43
0 is connected by a constant voltage output line 490.
Further, the constant voltage circuit 420 and the timer circuit 440 are connected by a constant voltage output line 490.

The normal power supply and the switching circuit 410 are connected by a power supply line 450. Normal power supply
The power is supplied to the switching circuit 410 via the power supply line 450. The backup power supply and the switching circuit 410 are connected by a power supply line 450. The power of the backup power supply is supplied through this power supply line 450,
It is supplied to the switching circuit 410.

Here, the normal power supply and the backup power supply are the same as those described above.

FIG. 5 is a diagram showing the internal configuration of the constant voltage circuit 420 and the connection relationship between the constant voltage circuit 420 and the switching circuit 410. 5, a constant voltage circuit 420 includes a two-input OR gate circuit 421 and a NOT gate circuit 422.
And n-channel MOS (Metal Oxide Semiconducto)
r) Transistor 423, p-channel MOS transistor 424, constant voltage source 425, operational amplifier 426
And

One of the two input terminals of the OR gate circuit 421 is connected to the power supply switching signal line 480. The other one of the two input terminals of the OR gate circuit 421 is connected to a clock generator (not shown) via a clock signal input line 427.

The drain of the MOS transistor 423 is
It is connected to the negative power supply input terminal of the operational amplifier 426.
The source of the MOS transistor 423 is grounded. Further, the gate of the MOS transistor 423 is
It is connected to the output terminal of the OR gate circuit 421.

The input terminal of the NOT gate circuit 422 is
It is connected to the output terminal of the R gate circuit 421. The output terminal of the NOT gate circuit 422 is connected to the gate of the MOS transistor 424.

The source of the MOS transistor 424 is connected to the power supply line 470. The drain of the MOS transistor 424 is connected to the positive power supply input terminal of the operational amplifier 426.

The positive output terminal of the constant voltage source 425 is connected to the non-inverting input terminal of the operational amplifier 426. The negative output terminal of the constant voltage source 425 is grounded.

The output terminal of the operational amplifier 426 is connected to a constant voltage output line 490. Also, the operational amplifier 426
Is connected to the inverting input terminal of the operational amplifier 426 in a negative feedback manner.

The operational amplifier 426 and the constant voltage source 425 constitute a voltage follower.

The timer IC 4 will now be described with reference to FIGS.
The operation of 00 will be described.

First, the operation of the switching circuit 410 when the normal power supply is turned on will be described.

When the normal power supply is turned on, the switching circuit 410 selects the normal power supply. And the switching circuit 4
10 connects the power supply line 450 and the power supply line 470. The switching circuit 410 outputs a signal of logic “H” indicating that the normal power supply is selected, to the power supply switching signal line 48.
Output to 0.

Next, the operation of the switching circuit 410 when the normal power supply is turned off will be described.

When the normal power supply is turned off, the switching circuit 410 selects a backup power supply. The switching circuit 410 includes a power supply line 450 and a power supply line 470.
And connect. Switching circuit 410 outputs a signal of logic “L” indicating that the backup power supply is selected, to power supply switching signal line 480.

As described above, when the normal power supply is turned on, the power supply line 470 is connected to the normal power supply, and a logic "H" signal is output to the power supply switching signal line 480. When the normal power supply is turned off, the power supply line 470 is connected to the backup power supply, and a logic “L” signal is output to the power supply switching signal line 480.

Next, the operation of the constant voltage circuit 420 will be described.
explain.

First, the operation of the constant voltage circuit 420 when the signal on the power supply switching signal line 480 is logic "H", that is, when the normal power supply is turned on will be described.

When a signal of logic “H” is input to the OR gate circuit 421 from the power supply switching signal line 480,
The output signal of the gate circuit 421 is connected to the clock signal input line 4
Regardless of the signal value of S.27, it becomes logic "H".

When the output signal of the OR gate circuit 421 is logic "H", a signal of logic "H" is input to the gate of the MOS transistor 423 connected to the output terminal of the OR gate circuit 421. Therefore, the MOS transistor 423 is turned on.

When the output signal of the OR gate circuit 421 is logic "H", a signal of logic "H" is input to the input terminal of the NOT gate circuit 422 connected to the output terminal of the OR gate circuit 421. You. Therefore, the output signal of the NOT gate circuit 422 becomes logic “L”. Therefore,
MOS connected to the output terminal of NOT gate circuit 422
A logic “L” signal is input to the gate of the transistor 424. Therefore, the MOS transistor 424 is turned on.

As described above, when the MOS transistor 423 is turned on, the negative power supply input terminal of the operational amplifier 426 is grounded. When the MOS transistor 424 is turned on, the power of the normal power is supplied to the positive power input terminal of the operational amplifier 426 via the power supply line 470. Therefore, the operational amplifier 426 is driven by a normal power supply. The operational amplifier 426 is connected to the constant voltage output line 490
Outputs constant voltage to

Next, the operation of constant voltage circuit 420 when the signal on power supply switching signal line 480 is at logic "L", that is, when the normal power supply is turned off, will be described.

When a signal of logic “L” is input from power supply switching signal line 480 to OR gate circuit 421,
The output signal of the gate circuit 421 is connected to the clock signal input line 4
27.

The signal on power supply switching signal line 480 is logic "L".
In addition, when the signal on the clock signal input line 427 is logic “H”, the output signal of the OR gate circuit 421 becomes logic “H”. Therefore, as described above, the MOS transistor 423 and the MOS transistor 424 are turned on. Therefore, the power of the backup power supply is
The signal is supplied to the positive power supply input terminal of the operational amplifier 426 via 70. The negative power input terminal of the operational amplifier 426 is
Grounded. Therefore, the operational amplifier 426 is driven by the backup power supply. And the operational amplifier 426
Outputs a constant voltage to the constant voltage output line 490.

The signal on power supply switching signal line 480 is logic "L".
In addition, when the signal of the clock signal input line 427 is logic “L”, the output signal of the OR gate circuit 421 becomes logic “L”. Therefore, a logic "L" signal is input to the gate of the MOS transistor 423 connected to the output terminal of the OR gate circuit 421. Therefore, the MOS transistor 423 is turned off. Also, the OR gate circuit 4
21 is a logical "L", the NOT gate circuit 42 connected to the output terminal of the OR gate circuit 421
A signal of logic “L” is input to the input terminal 2. Therefore, the output signal of the NOT gate circuit 422 becomes logic “H”. Therefore, a logic “H” signal is input to the gate of the MOS transistor 424 connected to the output terminal of the NOT gate circuit 422. Therefore, the MOS transistor 424 is turned off. When the MOS transistor 423 and the MOS transistor 424 are turned off, the supply of power to the power input terminal of the operational amplifier 426 is cut off. Therefore, the operational amplifier 426 is not driven.

As described above, when the signal on the power supply switching signal line 480 is at logic "H", the operational amplifier 426 is driven by a normal power supply. Then, the operational amplifier 426
The constant voltage is output to the constant voltage output line 490. When the signal on the power supply switching signal line 480 is logic “L” and the signal on the clock signal input line 427 is logic “H”, the operational amplifier 426 is driven by the backup power supply. Then, the operational amplifier 426 outputs the constant voltage to the constant voltage output line 490.
Output to On the other hand, when the signal on power supply switching signal line 480 is logic “L” and the signal on clock signal input line 427 is logic “L”, operational amplifier 426 is not driven.

As described above, the switching circuit 410 and the constant voltage circuit 420 intermittently operate the operational amplifier 426 in accordance with the clock signal while being driven by the backup power supply, thereby reducing the current consumption during driving by the backup power supply. Can be smaller.

[0045]

However, the conventional constant voltage circuit 420 has the following problems.

FIG. 6 shows the switching circuit 410 and the constant voltage circuit 4.
20 is a timing chart showing a change in input / output voltage of No. 20.

In FIG. 6, VDD is the output voltage of the normal power supply, VBK is the output voltage of the backup power supply, VPS is the voltage of the power supply line 470, VDDON is the voltage of the power supply switching signal line, and VREG is the voltage of the constant voltage output line 490. It is.

As shown in the timing chart of FIG. 6, VDD first changes from 0V to 5V at time t0. After that, VDD changes from 5V to 0V at the time t1. On the other hand, VBK keeps 3V throughout. Therefore, VDD remains at V
It is lower than BK. VDD is at time t
It is higher than VBK from 0 to t1. Further, VDD is lower than VBK after time t1.

Since VDD changes as described above, VPS
Is the same voltage as VBK until time t0, and from time t0 to t
1 and the same voltage as VDD, and VBK after time t1.
And the same voltage.

In addition, VDDON has a logic "L" from time t0 to a logic "H" from time t0 to t1, and a logic "L" after time t1, in accordance with the change of VDD. .

Since VDDON changes as described above, the operational amplifier 426 is intermittently driven in synchronization with the clock signal until time t0. Then, the operational amplifier 426 is constantly driven from time t0 to time t1. Further, the operational amplifier 426 is intermittently driven after time t1 in synchronization with the clock signal.

Here, VPS, which is the power supply input voltage of the operational amplifier 426, changes from 3V to 5V at time t0. Therefore, immediately after time t0, VREG, which is the output voltage of the operational amplifier 426, rises. However, from time t0 to t1, the operational amplifier 426 is constantly driven. Therefore, this voltage rise converges immediately.

The VPS changes from 5 V to 3 at time t1.
V. Therefore, immediately after time t1, the output voltage VREG of the operational amplifier 426 falls. However, after time t1, the operational amplifier 426 is intermittently driven in synchronization with the clock signal. Therefore, this voltage drop does not easily converge. Therefore, there is a problem that the timer IC 400 malfunctions due to the voltage drop.

The present invention has been made in view of the above problems, and has as its object to reduce the current consumption when driven by a backup power supply, extend the drive time by the backup power supply, and improve reliability. An object of the present invention is to provide a constant voltage generator that can be improved.

[0055]

In order to solve the above problems, a constant voltage output device according to the present invention includes a power supply input terminal for receiving power supply, and outputs a constant voltage by a power supply supplied from the power supply input terminal. A constant voltage output circuit, a first external power supply input terminal connected to a first external power supply that is appropriately turned on / off, and a second external power supply that is always on and outputs a voltage different from the first external power supply. A second external power supply input terminal to be connected, an output terminal, and when the first external power supply is turned on, connect the first external power supply input terminal and the output terminal; A switching circuit for connecting the second external power supply input terminal and the output terminal when the first external power supply is turned off, and a power supply switching for outputting a power supply switching signal indicating whether the first external power supply is on or off. Signal output circuit and power supply switching signal Signal when the power supply switching signal output from the signal output circuit changes from a signal indicating that the first external power supply is turned on to a signal indicating that the first external power supply is turned off. The power supply switching signal output from the output circuit is delayed by a predetermined delay time and output as a power supply switching delay signal. At other times, the power supply switching signal output from the power supply switching signal output circuit is left as it is without delay. A power switching signal delay circuit that outputs a switching delay signal; and a power switching delay signal that is output from the power switching signal delay circuit when the first external power supply is turned on. A switching circuit which is always connected to the power input terminal of the output circuit, and a power selection delay signal output from the power switching signal delay circuit indicates that the first external power is off. And a control circuit for intermittently connecting the output terminal of the constant voltage output circuit and the power input terminal of the constant voltage output circuit.

According to another aspect of the present invention, there is provided a constant voltage output device including a power input terminal for receiving a power supply, and outputting a constant voltage with the power supplied from the power input terminal. A circuit, a first external power supply input terminal connected to a first external power supply appropriately turned on / off, and a second external power supply connected to a second external power supply that is always turned on and outputs a voltage different from the first external power supply. Two external power input terminals and an output terminal are provided, and when the first external power is turned on, the first external power input terminal and the output terminal are connected, and the first external power is turned off. If so, a switching circuit for connecting the second external power input terminal and the output terminal; and a power switching signal output circuit for outputting a power switching signal indicating whether the first external power is on or off. Power supply switching signal output circuit When the power switching signal output from the power switching signal output circuit changes from a signal indicating that the first external power is turned on to a signal indicating that the first external power is turned off, The output power switching signal is delayed by a predetermined delay time and output as a power switching delay signal. Otherwise, the power switching signal output from the power switching signal output circuit is not delayed and the power switching delay signal is not changed. A power supply switching signal delay circuit that outputs a clock signal; a clock signal generation circuit that generates a clock signal; and a power supply switching delay signal that is output from the power supply switching signal delay circuit when the first external power supply is turned on. The output terminal of the switching circuit is always connected to the power input terminal of the constant voltage output circuit, and the power selection delay signal output from the power switching signal delay circuit is And a control circuit for intermittently connecting the output terminal of the switching circuit and the power supply input terminal of the constant voltage output circuit in accordance with a clock signal generated from the clock signal generation circuit. It is characterized by.

Here, the power supply switching signal delay circuit can be a CR oscillator, a timer clock frequency dividing circuit, or a charge / discharge circuit using a CR.

The first external power supply and the second external power supply are switchably connected to each other, and the power is intermittently supplied to the constant voltage output circuit when driven by the second external power supply.
Current consumption during driving by the second external power supply can be reduced. In addition, by constantly supplying power to the constant voltage output circuit for a predetermined time after switching from the first external power supply to the second external power supply, fluctuations in constant voltage output due to power supply switching are immediately converged. can do.

[0059]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a constant voltage output device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing one configuration example of the constant voltage output device of the present invention. In FIG. 1, a constant voltage output device according to the present invention is a power supply that switches and transmits voltages from an external normal power supply (not shown) and a backup power supply (not shown) and indicates which power supply is selected. A switching circuit 110 that outputs a switching signal, a constant voltage circuit 120 that outputs a constant voltage, and a delay circuit 130 that delays a power supply switching signal output from the switching circuit 110 are provided.

The switching circuit 110 and the constant voltage circuit 120
They are connected by a power supply line 170. The switching circuit 110 and the delay circuit 130 are connected to the power switching signal line 18.
Connected by 0.

The delay circuit 130 and the constant voltage circuit 120
They are connected by a power supply switching delay signal line 190.

The normal power supply and the switching circuit 110 are connected by a power supply line 150. Normal power supply
The power is supplied to the switching circuit 110 via the power supply line 150. Further, the backup power supply and the switching circuit 110 are connected by a power supply line 160. The power of the backup power supply is supplied through the power supply line 160,
It is supplied to the switching circuit 110.

Here, the normal power supply is turned on / off as appropriate. When the normal power supply is turned on, the output voltage (hereinafter, also referred to as VDD) of the normal power supply is 5 volts. Also,
VDD is 0 volts when the power supply is normally turned off. This normal power supply corresponds to a first external power supply.

The backup power supply is a battery for maintaining the operation of the constant voltage circuit 120 when the normal power supply is turned off. The output voltage of the backup power supply (hereinafter, also referred to as VBK) is maintained at 3 volts as long as the remaining battery power remains. This backup power supply corresponds to a second external power supply.

The constant voltage circuit 120 includes a two-input OR gate circuit 121, a NOT gate circuit 122, an n-channel MOS transistor 123, a p-channel MOS transistor 124, a constant voltage source 125, and an operational amplifier 1
26.

One of the two input terminals of the OR gate circuit 121 is connected to the power supply switching delay signal line 190. The other one of the two input terminals of the OR gate circuit 121 is connected to a clock generator (not shown) via a clock signal input line 195.

The drain of the MOS transistor 123 is
It is connected to the negative power supply input terminal of the operational amplifier 126.
The source of the MOS transistor 123 is grounded. Further, the gate of the MOS transistor 123 is
It is connected to the output terminal of the OR gate circuit 121.

The input terminal of the NOT gate circuit 122 is
It is connected to the output terminal of the R gate circuit 121. The output terminal of the NOT gate circuit 122 is connected to the gate of the MOS transistor 124.

The source of the MOS transistor 124 is connected to the power supply line 170. The drain of the MOS transistor 124 is connected to the positive power supply input terminal of the operational amplifier 126.

The positive output terminal of the constant voltage source 125 is connected to the non-inverting input terminal of the operational amplifier 126. The negative output terminal of the constant voltage source 125 is grounded.

The output terminal of the operational amplifier 126 is connected to the constant voltage output line 127. The operational amplifier 126
Is connected to the inverting input terminal of the operational amplifier 126 by negative feedback.

The operational amplifier 126 and the constant voltage source 125 constitute a voltage follower.

Hereinafter, the operation of the constant voltage output device of the present invention will be described with reference to FIG.

First, the normal power supply is turned on and VDD becomes VBK
The operation of the switching circuit 110 when the voltage is higher than that will be described.

When VDD is higher than VBK, switching circuit 110 selects the normal power supply. And the switching circuit 11
0 connects the power supply line 150 and the power supply line 170. Therefore, the voltage of the power supply line 170 becomes VDD. Switching circuit 110 outputs a signal of logic “H” indicating that the normal power supply is turned on, to power supply switching signal line 1.
Output to 80.

Next, the normal power supply is turned off, that is, VDD becomes VB
The operation of the switching circuit 110 when it is lower than K will be described.

When VDD is lower than VBK, switching circuit 110 selects a backup power supply. Then, the switching circuit 110 connects the power supply line 160 and the power supply line 170. Therefore, the voltage of the power supply line 170 is VB
It becomes K. Switching circuit 110 outputs a signal of logic “L” indicating that the normal power supply is turned off to power supply switching signal line 180.

As described above, when VDD is higher than VBK, the power supply line 170 is connected to the power supply line 150, and a signal of logic “H” is output to the power supply switching signal line 180. When VDD is lower than VBK, the power supply line 170 is connected to the power supply line 160, and a signal of logic “L” is output to the power supply switching signal line 180.

Next, the operation of the delay circuit 130 will be described.

The delay circuit 130 includes a power supply switching signal line 180
From the power supply switching signal. Then, the delay circuit 130
When detecting the falling edge of the power supply switching signal, the power supply switching signal outputs a signal obtained by delaying the power supply switching signal by a predetermined delay time to the power supply switching delay signal line 190 as a power supply switching delay signal. The delay circuit 130 outputs the power supply switching delay signal line 190 as a power supply switching delay signal without delaying the power supply switching signal except when the falling edge of the power supply switching signal is detected.
Output to

Next, the operation of the constant voltage circuit 120 will be described.
explain.

First, the operation of constant voltage circuit 120 when the signal on power supply switching delay signal line 190 is at logic "H" will be described.
explain.

Logic "H" from power supply switching delay signal line 190
Is input to the OR gate circuit 121 in the constant voltage circuit 120, the output signal of the OR gate circuit 121 is independent of the signal value of the clock signal input line 195.
It becomes logic "H".

When the output signal of the OR gate circuit 121 is logic "H", a signal of logic "H" is input to the gate of the MOS transistor 123 connected to the output terminal of the OR gate circuit 121. Therefore, the MOS transistor 123 is turned on.

When the output signal of the OR gate circuit 121 is logic "H", a signal of logic "H" is input to the input terminal of the NOT gate circuit 122 connected to the output terminal of the OR gate circuit 121. You. Therefore, the output signal of the NOT gate circuit 122 becomes logic “L”. Therefore,
MOS connected to the output terminal of NOT gate circuit 122
A signal of logic “L” is input to the gate of the transistor 124. Therefore, the MOS transistor 124 is turned on.

As described above, when the MOS transistor 123 is turned on, the negative power supply input terminal of the operational amplifier 126 is grounded. When the MOS transistor 124 is turned on, power is supplied to the positive power input terminal of the operational amplifier 126 via the power supply line 170. Therefore, the operational amplifier 126 is driven by the power supplied from the power supply line 170. Then, the operational amplifier 126 outputs a constant voltage to the constant voltage output line 127.

Next, the operation of constant voltage circuit 120 when the signal on power supply switching delay signal line 190 is at logic "L" will be described.
explain.

The logic "L" from power supply switching delay signal line 190
Is input to the OR gate circuit 121,
The output signal of the OR gate circuit 121 depends on the signal value of the clock signal input line 195.

When the signal on power supply switching delay signal line 190 is logic "L" and the signal on clock signal input line 195 is logic "H", the output signal of OR gate circuit 121 is logic "H". Therefore, as described above, the MOS
The transistor 123 and the MOS transistor 124 are turned on. Therefore, power is supplied to the positive power input terminal of the operational amplifier 126 via the power supply line 170. The negative power input terminal of the operational amplifier 126 is grounded. Therefore, the operational amplifier 126 is driven by the power supplied from the power supply line 170. Then, the operational amplifier 126 outputs a constant voltage to the constant voltage output line 127.

When the signal on power supply switching delay signal line 190 is logic "L" and the signal on clock signal input line 195 is logic "L", the output signal of OR gate circuit 121 is logic "L". Therefore, a logic "L" signal is input to the gate of the MOS transistor 123 connected to the output terminal of the OR gate circuit 121. Therefore, MOS
Transistor 123 is turned off. When the output signal of the OR gate circuit 121 is logic “L”, the OR
A logic “L” signal is input to an input terminal of the NOT gate circuit 122 connected to the output terminal of the gate circuit 121. Therefore, the output signal of the NOT gate circuit 122 becomes logic “H”. Therefore, a logic “H” signal is input to the gate of the MOS transistor 124 connected to the output terminal of the NOT gate circuit 122. Therefore, the MOS transistor 124 is turned off. Thus MOS
When the transistor 123 and the MOS transistor 124 are turned off, the supply of power to the power terminal of the operational amplifier 126 is cut off. Therefore, the operational amplifier 126 is not driven.

As described above, power supply switching delay signal line 190
Is a logical “H”, the operational amplifier 126 is driven by the power supplied from the power supply line 170. Then, the operational amplifier 126 outputs the constant voltage to the constant voltage output line 127. Also, power supply switching delay signal line 190
Is a logic “L” and the signal on the clock signal input line 195 is a logic “H”, the operational amplifier 126 is driven by the power supplied from the power supply line 170. Then, the operational amplifier 126 outputs the constant voltage to the constant voltage output line 19.
Output to 0. On the other hand, when the signal on the power supply switching signal line 180 is logic “L” and the signal on the clock signal input line 195 is logic “L”, the operational amplifier 126 is not driven.

FIG. 2 shows the switching circuit 110 and the constant voltage circuit 12.
7 is a timing chart showing changes in the input / output voltage of the delay circuit 130 and 0.

In FIG. 2, VDD is the output voltage of the normal power supply, VBK is the output voltage of the backup power supply, VPS is the voltage of the power supply line 170, and VDDON is the power supply switching signal line 1.
The voltage of 80, VDDON_D is the power switching delay signal line 19
A voltage of 0 and VREG is a voltage of the constant voltage output line 127.

As shown in the timing chart of FIG. 2, VDD changes from 0 V to 5 V at time t0. After that, VDD changes from 5V to 0V at the time t1. On the other hand, VBK keeps 3V throughout. Therefore, VDD remains at V
It is lower than BK. VDD is at time t
It is higher than VBK from 0 to t1. Further, VDD is lower than VBK after time t1.

Since VDD changes in this manner, VPS
Is the same voltage as VBK until time t0, and from time t0 to t
1 and the same voltage as VDD, and VBK after time t1.
And the same voltage.

VDDON is logic "L" from time t0, logic "H" from time t0 to t1, and logic "L" after time t1, according to the change of VDD.

VDDON_D indicates that VDON_D is not VD until time t1.
Since DON has no falling edge, the voltage is exactly the same as VDDON. Since a falling edge occurs at VDDON at time t1, the delay circuit 130 outputs the power supply switching signal to a predetermined delay time (in FIG. 2, at time t1).
And a signal delayed by a time between the time t2). Therefore, VDDON_D is at logic “H” until time t2. VDDON_D is at logic “L” after time t2.

Since VDDON_D changes in this manner, the operational amplifier 126 is intermittently driven by the power supply from the backup power supply in synchronization with the clock signal until time t0. Then, the operational amplifier 126 is constantly driven by a power supply from a normal power supply during a period from time t0 to t1. Further, the operational amplifier 126 is constantly driven by a power supply from a backup power supply from time t1 to time t2. Further, after time t2, constant voltage circuit 120 is intermittently driven by a power supply from a backup power supply in synchronization with a clock signal.

Here, VPS, which is the power supply input voltage of the operational amplifier 126, changes from 3V to 5V at time t0. Therefore, immediately after time t0, the output voltage VREG of the operational amplifier 126 rises. However, from time t0 to t1, the operational amplifier 126 is constantly driven. Therefore, this voltage rise converges immediately.

The VPS changes from 5 V to 3 at time t1.
V. Therefore, immediately after the time t1, the output voltage VREG of the operational amplifier 126 falls. But,
From time t1 to t2, the operational amplifier 126 is constantly driven by the power supply from the backup power supply.
Therefore, this voltage drop converges immediately.

As described above, in the constant voltage output device of the present invention, the current consumption during the driving by the backup power supply is reduced by intermittently operating the operational amplifier 126 according to the clock signal while being driven by the backup power supply. be able to. In the constant voltage output device according to the present invention, the operational amplifier 126 is constantly driven by the backup power supply for a predetermined time from the time when the normal power supply is switched to the backup power supply, so that the VREG drop caused by the power supply switching is reduced. It can converge immediately. In addition, between the time t1 and the time t2, the operational amplifier 1
26 is constantly driven by the backup power supply, but the increase in current consumption during this period is small and almost negligible.

Although the embodiment of the constant voltage output device of the present invention has been described above, the delay circuit 130 can be constituted by a CR oscillation circuit or a timer clock frequency dividing circuit.

[0104]

As described above, according to the constant voltage output device of the present invention, the constant voltage output circuit can be operated intermittently while being driven by the second external power supply, so that the second external power supply can be operated. As a result, current consumption during driving can be reduced. Further, according to the constant voltage output device of the present invention, the constant voltage output circuit is constantly driven by the second external power supply for a predetermined time after switching from the first external power supply to the second external power supply. Therefore, the fluctuation of the constant voltage output due to the power supply switching can be immediately converged.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of one embodiment of a constant voltage output device according to the present invention.

FIG. 2 is a timing chart of a configuration example of one embodiment of a constant voltage output device according to the present invention.

FIG. 3 is a diagram illustrating a configuration example of an IC using a conventional constant voltage circuit.

FIG. 4 is a diagram showing a configuration example of an IC using a conventional constant voltage circuit.

FIG. 5 is a diagram showing a configuration example of a conventional constant voltage circuit.

FIG. 6 is a diagram showing a timing chart of a conventional constant voltage circuit.

[Explanation of symbols]

 Reference Signs List 110 switching circuit 120 constant voltage circuit 121 OR gate circuit 122 NOT gate circuit 123, 124 MOS transistor 125 constant voltage source 126 operational amplifier 130 delay circuit 300 timer IC 310 switching circuit 320 constant voltage circuit 330 oscillation circuit 340 timer circuit 400 timer IC 410 Switching circuit 420 Constant voltage circuit 430 Oscillation circuit 440 Timer circuit

Claims (4)

[Claims] 1. A constant voltage output circuit comprising: a power input terminal for receiving a power supply; and a constant voltage output circuit for outputting a constant voltage by the power supplied from the power input terminal; A first external power supply input terminal to be connected, a second external power supply input terminal connected to a second external power supply that is always on and outputs a voltage different from the first external power supply, and an output terminal, When the first external power supply is turned on, the first external power supply input terminal is connected to the output terminal, and when the first external power supply is turned off, the second external power supply input terminal is connected. A switching circuit that connects a terminal to the output terminal; a power switching signal output circuit that outputs a power switching signal indicating whether the first external power is on or off; and a power switching signal output circuit. Before output from When the power switching signal changes from a signal indicating that the first external power is turned on to a signal indicating that the first external power is turned off, the power switching signal output circuit outputs The power supply switching signal output is delayed by a predetermined delay time and output as a power supply switching delay signal. At other times, the power supply switching signal output from the power supply switching signal output circuit is directly supplied without delay. A power supply switching signal delay circuit that outputs a switching delay signal; and a power supply switching delay signal that is output from the power supply switching signal delay circuit when the first external power supply is turned on. An output terminal is always connected to the power input terminal of the constant voltage output circuit, and the power selection delay signal output from the power switching signal delay circuit is supplied to the first external power supply. And a control circuit for intermittently connecting the output terminal of the switching circuit and the power supply input terminal of the constant voltage output circuit when indicating that the power supply is off. apparatus. 2. A constant voltage output circuit, comprising: a power supply input terminal for receiving a power supply; and a constant voltage output circuit for outputting a constant voltage by the power supply supplied from the power supply input terminal; A first external power supply input terminal to be connected, a second external power supply input terminal connected to a second external power supply that is always on and outputs a voltage different from the first external power supply, and an output terminal, When the first external power supply is turned on, the first external power supply input terminal is connected to the output terminal, and when the first external power supply is turned off, the second external power supply input terminal is connected. A switching circuit that connects a terminal to the output terminal; a power switching signal output circuit that outputs a power switching signal indicating whether the first external power is on or off; and a power switching signal output circuit. Before output from When the power switching signal changes from a signal indicating that the first external power is turned on to a signal indicating that the first external power is turned off, the power switching signal output circuit outputs The power supply switching signal output is delayed by a predetermined delay time and output as a power supply switching delay signal. Otherwise, the power supply switching signal output from the power supply switching signal output circuit is directly supplied without delay. A power switching signal delay circuit that outputs a switching delay signal; a clock signal generating circuit that generates a clock signal; and a power switching delay signal that is output from the power switching signal delay circuit when the first external power supply is turned on. If it indicates that the output terminal of the switching circuit and the power supply input terminal of the constant voltage output circuit are always connected, from the power supply switching signal delay circuit When the supplied power supply selection delay signal indicates that the first external power supply is turned off, the output terminal of the switching circuit and the power supply input terminal of the constant voltage output circuit are connected to the clock signal generation circuit. And a control circuit intermittently connected in accordance with the clock signal generated from the control circuit. 3. The constant voltage output device according to claim 1, wherein the power supply switching signal delay circuit is a CR oscillator. 4. The constant voltage output device according to claim 1, wherein said power supply switching signal delay circuit is a timer clock frequency dividing circuit.