JP2002083869A - Semiconductor device and production method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device provided with the etching stopper film of low dielectric constant suitable for a damascene method and a production method therefor. SOLUTION: A wiring layer HL of a top layer having a Cu layer 107 embedded in a trench hole 108 and a via hole 109 is formed on a wiring layer LL of a lower layer by the damanscene method. As an etching stopper film 110 to be used for the damascene method, a film (SiCN film) containing Si, C and B as main elements is used. This SiCN etching stopper film has a low dielectric constant (5 to 5.5) and a sufficient etching selection ratio can be taken with respect to a layer insulating film 106. Further, since Cu diffusibility is low, highly reliable wiring is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In order to improve the performance of semiconductor integrated circuits, the speed of wiring has been increased. To increase the speed of wiring, it is effective means to lower the dielectric constant of the interlayer insulating film and reduce the wiring resistance. As the low dielectric constant interlayer insulating film, an SiOF film (about 3.5) or the like is used instead of a conventional SiO ₂ film (about 4.0). In addition, in order to reduce the wiring resistance, Cu (1.9 μΩ · cm), which is superior in electromigration resistance and low in resistance (1.9 μΩ · cm), is used as a wiring metal compared to a conventional alloy mainly containing Al (resistivity: 2.7 μΩ · cm). It is often used as.

In the case of using Cu wiring, it is difficult to process by a conventional etching process. Therefore, a so-called damascene method is used as a method for realizing a multilayer wiring of Cu without etching Cu. Hereinafter, FIGS.
The damascene method will be described with reference to FIG.

First, an interlayer insulating film (base film) 6 made of, for example, SiOF is formed on a substrate or a lower wiring layer 601.
02, an etching stopper film 603 is formed in order (FIG. 11A). Next, a resist pattern 604 having an opening 604a is provided on the substrate surface (FIG. 11B).
Using this as a mask, a through hole 603a is formed in the etching stopper film 603 by plasma etching or the like (FIG. 11C). Furthermore, through holes 603a
A wiring groove 605 is formed by patterning using the etching stopper film 603 formed with the mask as a mask.
(D)). Subsequently, after forming a barrier metal film 606a as an adhesion layer of the metal film 606 by sputtering or the like, the metal film 606 is formed by plating or the like (FIG. 11).
(E)). After that, chemical mechanical polishing (Chemical Mecha
Unnecessary barrier metal film and metal film are removed by using the etching stopper film 603 as a stopper, and the surface is planarized by nical polishing (CMP) (FIG. 1).
1 (f)). A wiring layer is formed by the steps described above, and this step is repeated to form a multilayer wiring layer.

[0005]

In the above-described damascene method, an etching stopper film is used, and this etching stopper film functions as a mask in etching a base film. Therefore, a high etching selectivity with the base film is required. Further, since the etching stopper film also has a function as an interlayer insulating film in the semiconductor device, a low relative dielectric constant and a low metal diffusion property are required particularly when the wiring metal is Cu.

As such an etching stopper film, a film composed of Si and N as main elements (hereinafter, referred to as an etching stopper film).
A SiN-based film) and a film composed of Si and C as main elements (hereinafter, a SiC-based film) are known. However, the relative permittivity of the SiN-based film is as high as 7 to 8.
In addition, when the underlying film is a fluorine-containing film such as SiOF and plasma etching is performed, the SiN-based film is damaged by fluorine radicals and the like generated at the time of etching. Deteriorates. Also, SiC-based film (in particular, a film containing CH _n group) has good etch selectivity relative dielectric constant of 5
Although there is a nearby one, the diffusivity of Cu is high. As described above, the conventional etching stopper film does not sufficiently satisfy the conditions necessary for forming the wiring structure by the damascene method.

Accordingly, it is an object of the present invention to provide a highly reliable semiconductor device and a method for manufacturing the same.

[0008]

In order to achieve the above object, a semiconductor device according to a first aspect of the present invention comprises: a first insulating layer having a plurality of grooves or holes and having a low dielectric constant; Having a plurality of openings formed on the insulating layer, and overlapping the plurality of grooves or holes, a second insulating layer containing Si, C, and N as main elements, and the plurality of grooves or holes, And a conductor layer embedded in a plurality of wiring grooves or holes formed from the plurality of openings.

According to the above structure, the second insulating layer composed of Si, C and N is equal to or smaller than a conventional etching stopper film composed of Si and C or Si and N. It has the following dielectric constant, and has a better etching selectivity with the first insulating film than these etching stopper films. Thus, a highly reliable semiconductor device is provided.

[0010] In the above structure, the second insulating layer includes:
When the ratio of the number of C atoms to the number of Si atoms is 0.2 to 0.8
And the ratio of the number of N atoms to the number of Si atoms is preferably 0.15 to 1.0. When the abundance ratio of Si, C, and N in the SiCN-based film is within the above range, Si
The etching selectivity of the CN film with respect to the first insulating layer is high, and the Cu diffusivity is reduced.

In the above structure, the first insulating layer is
It may be composed of silicon fluoride oxide or carbon fluoride. These fluorine-containing films are accompanied by generation of fluorine radicals and the like during plasma etching. But S
iCN-based second insulating layer (etching stopper film)
Are resistant to these radicals, and have a sufficient etching selectivity with respect to the first insulating layer.

In the above structure, the conductor layer may be made of Cu. That is, since the second insulating layer composed of Si, C, and N has low Cu diffusivity,
A highly reliable wiring layer using u is formed.

In the above structure, it is preferable that a barrier metal layer is formed in the wiring groove or the hole, and the conductor layer is formed on the barrier metal layer. With this configuration, not only the diffusion of the metal forming the conductor layer can be suppressed, but also the adhesion between the conductor layer and the interlayer insulating layer can be increased, and the reliability of the semiconductor device can be improved.

In the above structure, it is preferable that a third insulating layer having the same structure as that of the second insulating layer is further formed on the second insulating layer and the conductor layer. Thus, diffusion of metal from a conductor layer such as Cu can be suppressed.

In order to achieve the above object, a method for manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a first insulating layer, and a step of forming Si and C on the first insulating layer. Forming a second insulating layer containing N as a main element, and partially exposing the surface of the first insulating layer.
Selectively etching the second insulating layer to form an opening; and etching the first insulating layer using the selectively etched second insulating layer as a mask;
Forming a wiring groove or hole, filling the opening and the wiring groove or hole to form a conductor layer, and polishing the conductor layer using the second insulating layer as a stopper. It is characterized by having.

According to the above configuration, the second insulating layer composed of Si, C and N is equal to or smaller than a conventional etching stopper film composed of Si and C or Si and N. In addition to having the following dielectric constant, it has a better etching selectivity with the first insulating layer, which is a general interlayer insulating film, than these etching stopper films. Therefore, a highly reliable semiconductor device can be manufactured.

In the above structure, the second insulating layer is
When the ratio of the number of C atoms to the number of Si atoms is 0.2 to 0.8
And the ratio of the number of N atoms to the number of Si atoms is preferably 0.15 to 1.0. When the abundance ratio of Si, C, and N in the SiCN-based film is within the above range, Si
The etching selectivity of the CN film to the underlying film is high, and the Cu diffusivity is reduced.

In the above structure, the first insulating layer is
It may be composed of silicon fluoride oxide or carbon fluoride. These fluorine-containing films are accompanied by generation of fluorine radicals and the like during plasma etching. But S
iCN-based second insulating layer (etching stopper film)
Are resistant to these radicals, and have a sufficient etching selectivity with respect to the first insulating layer.

In the above structure, the conductor layer may be made of Cu. That is, since the second insulating layer composed of Si, C, and N has low Cu diffusivity,
A highly reliable wiring layer using u is formed.

Preferably, the above structure further comprises a step of forming a barrier metal layer between the conductor layer and the opening and the wiring groove or hole. With this configuration, not only the diffusion of the metal forming the conductor layer can be suppressed, but also the adhesion between the conductor layer and the interlayer insulating layer can be increased, and the reliability of the semiconductor device can be improved.

Preferably, the above structure further includes a step of forming a third insulating layer having the same structure as the second insulating layer on the second insulating layer and the conductor layer. Thus, diffusion of metal from a conductor layer such as Cu can be suppressed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. FIG.
FIG. 1 is a partial cross-sectional view illustrating a configuration of a semiconductor device according to the present embodiment. In this semiconductor device, a multilayer wiring layer is formed on an insulating film (not shown) covering elements such as MOS transistors formed on a substrate such as Si. FIG. 3 shows a wiring layer.

As shown in FIG. 1, a first base film (interlayer insulating film) 101, a first conductor layer 102, and a first etching stopper film 105 are provided below the uppermost wiring layer HL. Lower wiring layer LL is formed.

The first underlayer 101 is composed of a silicon fluoride oxide (SiOF) film, a fluorine-containing carbon film, or the like.
Trench hole 103 and a first via hole 104 are formed. First trench hole 103 formed
The first conductor layer 102 is formed in the first via hole 104. The first conductor layer 102 is made of a conductor such as Cu. First base film 101 and first conductor layer 1
02, a first barrier metal film 102a is formed. The first barrier metal film 102a is formed of Ta / Ta
It is composed of a multilayer film of a high melting point metal such as N, W / WN, Ti / TiN or an alloy of the metal, and functions to prevent diffusion of a metal such as Cu and to enhance adhesion between the base film 101 and the conductor layer 102. have. The first conductor layer 102 is connected to a lower wiring layer (not shown) or a Si substrate.

The first etching stopper film 105 is made of S
This is an SiCN-based insulating film including i, C, and N as main elements. This SiCN-based film has a number of C atoms of Si
The ratio (C / Si) to the number of atoms is 0.2 to 0.8, and the ratio of the number of N atoms to the number of Si atoms (N / Si)
Is 0.15 to 1.0. The relative permittivity of the SiCN-based film is 5 to 5.5,
SiN-based (S) known as an etching stopper film
i) and (N) as main elements) film (around 7),
It is as low as an iC-based film (having Si and C as main elements) (around 5).

On the lower wiring layer LL, a second base film 106 and a second etching stopper film 110 are formed. Similarly to the lower wiring layer LL, the second base film 106 and the second etching stopper film 110
Is formed, and a second barrier metal film 10 is formed inside these.
The second conductor layer 107 is buried through 7a.

A third etching stopper film 111 is formed on the uppermost wiring layer HL.
And N have the same structure as the first and second etching stopper films constituted as main elements, and have a function of suppressing diffusion of metal from a conductor layer made of Cu or the like. Further, on the third etching stopper film 111, a third base film 112 and a passivation film 113 (for example,
An SiO ₂ film and a SiON film) are sequentially formed. These are protective layers on the substrate surface that are easily oxidized.

Next, a method of manufacturing the above-described semiconductor device will be described. In this embodiment mode, a semiconductor device is manufactured by using a dual damascene method in which a trench hole and a via hole are formed, which is a modification of the damascene method.

FIGS. 2 to 6 are diagrams sequentially showing the steps of forming the Cu wiring by the dual damascene method. Hereinafter, description will be made sequentially with reference to the drawings.

First, as shown in FIG. 2A, a lower wiring layer LL composed of a first underlying film 101, a first conductor layer 102, a first etching stopper film 105, and the like is formed.
Second base film 106, second etching stopper film 11
0 are sequentially formed. The second base film 106 is a SiOF film, and is provided with an electron cyclotron resonance (Electron Cyclotron).
For example, SiH ₄ / SiF ₄ / O ₂ (flow ratio: 50/50) by chemical vapor deposition (CVD) using Resonance (ECR) plasma.
/ 200) under the condition of about 0.8 μm (8000 °).

The second etching stopper film 110 is made of S
It is an iCN-based film.
A film is formed to a thickness of about 05 μm. For film formation, for example, SiH₄
/ C ₂H₄/ N₂(Flow rate ratio: 10/15/15)
Gas is used.

Next, as shown in FIG. 2B, a first resist film 201 made of an organic material or the like is formed on the second etching stopper film 110, and a via hole pattern 201a is formed by photolithography. To form

Subsequently, as shown in FIG. 3A, the second etching stopper film 110 is etched by, for example, a plasma gas of CF _{4 using} the first resist film 201 on which the via hole pattern 201a is patterned as a mask. Then, an opening 110a for forming a via hole is formed.

Next, as shown in FIG. 3A, anisotropic etching is performed using the second etching stopper film 110 as a mask to form a hole 106a in the second base film 106. Here, the etching of the second base film (SiOF film) 106 is performed, for example, by reactive ion etching (Reactive Ion Etching: O ₂ / CF ₄ plasma gas).
RIE). Further, since the O ₂ plasma gas is added, the first resist film 201 can be removed at the same time.

Subsequently, as shown in FIG. 4A, a second resist film 202 is formed on the second etching stopper film 110.
Then, a trench hole pattern 202a is formed by a known lithography technique. Using the second resist film 202 as a mask, the second etching stopper film 110 is anisotropically etched to form an opening 110b for forming a trench hole.

Next, as shown in FIG. 4B, using the second etching stopper film 110 in which the opening 110b for forming a trench hole is formed as a mask, the second base film 1 is formed.
06 is etched. At this time, the etching is performed to a predetermined depth from the surface of the second base film 106 by appropriately adjusting the etching conditions. As a result, a second trench hole 108 and a second via hole 109 are formed in the second base film 106. Here, the formation of the second trench hole 108 and the second via hole 109 is as follows.
As in the formation of the hole 106a described above, for example, O ₂
This is performed by RIE using / CF ₄ plasma gas, and at this time, the second resist film 202 can be simultaneously etched.

Subsequently, as shown in FIG. 5A, a second barrier metal film 107a and a second conductor layer 107 are sequentially formed on the entire surface of the substrate. Second barrier metal film 10
7a is a film (Ta / TaN) composed of, for example, a TaN layer and a Ta layer, and is formed by, for example, sputtering. In addition, the second conductor layer 107 is, for example,
This is a Cu film, and is formed by an electroless plating method or the like after forming a Cu seed layer by sputtering. Thereafter, as shown in FIG. 5B, chemical mechanical polishing (Chem.
Excess barrier metal and Cu are polished and removed by ical mechanical polishing (CMP).

Finally, as shown in FIG. 6, a third etching stopper film 111 having a thickness of 0.05 μm is formed on the surface of the substrate under the same film forming conditions as the second etching stopper film 110. Further, the thickness of the third underlayer 112 is set to 0.05 μm.
m and passivation film (SiO ₂ film) 113
Are sequentially formed at 0.8 μm. Here, the formation of these three layers is performed continuously in the same chamber by the ECR plasma CVD method. As described above, the semiconductor device of the present embodiment can be manufactured using the dual damascene method.

Here, a description will be given of a SiCN-based film used as a mask for etching the second base film 106 in the above-described semiconductor device manufacturing process. FIG. 7 shows that, in the above-described formation of the SiCN-based etching stopper film by the ECR plasma CVD method, the film is formed by changing the mixture ratio of the C ₂ H ₄ gas and the N ₂ gas, which are source gases, and the film formation conditions ( 6 shows the results of examining the ratio of the number of C atoms and the number of N atoms to the number of Si atoms in the SiCN-based film formed in I-VII). Here, the SiCN-based film is formed by using SiH ₄ gas and C
Using a mixed gas of ₂ H ₄ gas and N ₂ gas, the flow rate ratio was S
iH ₄ gas / (C ₂ H ₄ gas + N ₂ gas) = 10/30
And the mixture ratio of C ₂ H ₄ gas and N ₂ gas was changed. The ratio of the number of each of Si, C, and N atoms in the film is determined by the Rutherford Backscatter method.
Spectroscopy (RBS).

As can be seen from FIG. 7, the abundance ratio of C and N in the film to be formed depends on the C-containing gas and N
Although it does not match the mixing ratio of the contained gas, it can be seen that it changes according to the mixing ratio. That is, if the mixture ratio of the C ₂ H ₄ gas is increased (the mixture ratio of the N ₂ gas is decreased), the abundance ratio of C atoms in the formed film increases (the abundance ratio of N atoms decreases), and vice versa. Then, the abundance ratio of C atoms decreases (the abundance ratio of N atoms increases). Here, in condition I, C
_{Since 2} H ₄ gas is not used, SiN containing no C atoms
A system film is formed. Further, under the condition VII, since no N ₂ gas is used, a SiC-based film containing no N atoms is formed.

In the following, under the above film forming conditions (I to VII),
For the formed film, the etching selectivity and metal expansion
The dispersibility will be described. FIG. 8 shows the etching of a SiCN-based film.
The results of a study on the selectivity of the SiN-based film
Other conditions when the etching rate of item I) is set to 1
The etching rate ratio of the SiCN-based film formed below is shown.
You. Here, the etching is O₂/ CF ₄Plasma gas
And the underlying film is a SiOF film.

As can be seen from FIG. 8, as the C content in the film increases, the etching rate ratio increases, and the condition V
II (SiC-based film) shows a value slightly less than twice that of the condition I (SiN-based film). In other words, the higher the C content in the film, the higher the selectivity and the better the etched shape.
Thus, the ratio of the number of C atoms to the number of Si atoms (C
If / Si) is at least 0.2 or more, a good etched shape can be obtained.

FIG. 9 shows the results of examining the metal diffusivity of the SiCN-based film, particularly the diffusivity of Cu. Cu is
It is a metal having the highest diffusibility among metals conventionally used for wiring. Specifically, the above condition (I
-VII) Film formed under 500 下 (0.05 μm)
A Cu layer 2000 (0.2 μm) is formed on the
After heat treatment at 0 ° C. for 7 hours, Cu SIMS (Secondary Ion Mass Spectroscop) at the Si / SiCN interface was performed.
y) The strength was checked. In general, under the above conditions, if SIMS does not detect diffusion of Cu into the Si layer, there is no problem in using the device.

As can be seen from FIG. 9, under the conditions I to VI, the diffusion amount of Cu into the Si layer is below the detection limit of SIMS, and only the film (SiC-based film) under the film forming condition VII has C
The diffusion of u was detected. Thus, N atoms in the film
The ratio of at least the number of N atoms to the number of Si atoms (N /
If Si) is present so as to be 0.15 or more, Cu
It can be seen that the diffusion of is suppressed.

Therefore, as shown in FIGS.
/ Si is 0.2 to 0.8 and N / Si is 0.1 to 0.8.
The SiCN-based film of the present embodiment having a composition of 15 to 1.0 is an etching stopper film having a low relative dielectric constant (5 to 5.5), and having good etching selectivity and metal diffusivity. You can see that there is.

As described above, according to the present invention, S
A highly reliable semiconductor device containing i, C, and N as main elements and a method for manufacturing the same are provided. Specifically, the present invention provides a semiconductor device having an etching stopper film suitable for a damascene method and having a low dielectric constant, a high etching selectivity with respect to a base film, and a low Cu diffusion property, and a method for manufacturing the same.

The present invention is not limited to the above embodiment,
Various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, the SiCN-based film as the etching stopper film is formed by ECR plasma CVD. However, the film forming method is not limited to this, and an inductively coupled plasma (ICP), a helicon (He
(Licon) type, parallel plate type or the like.

In the above embodiment, the conductor layer forming the wiring is made of Cu, but is not limited to Cu.
Alternatively, an Al-containing alloy or the like may be used.

In the above embodiment, the etching of the base film is performed.
O as gas₂/ CF₄Gas was used. Only
While O₂/ CF₄H instead of gas₂Gas and Ar
Gas and N₂Use a plasma such as a gas mixture with a gas.
Both are possible. Also, CF ₄Gas is C_mF_n(M,
(n is an integer of 0 or more) chlorocarbon-based gas
Can be

In the above embodiment, the etching stopper film 111, the SiOF film 112, the passivation film 11
The film formation of No. 3 by the ECR plasma CVD method was performed in the same chamber. However, the present invention is not limited to this.
The F film 112 and the passivation film 113 may be formed in different chambers, or all the films may be formed in separate chambers and different plasma processing methods may be used. However, in general, since semiconductor materials are easily oxidized or adsorbed with moisture, it is preferable to perform all processes in the same chamber under high vacuum and clean air conditions.

In the above embodiment, the SiCN-based film is made of S
iH ₄ , C ₂ H ₄ and N ₂ were formed as source gas compounds. However, the raw material compound is a compound containing Si, C, and N, and may be any compound that can form a SiCN-based film by itself or by a reaction in which these are appropriately combined.

For example, as in this embodiment, Si,
When three kinds of source gas compounds containing C and N are used, SiH ₄ is used as a Si-containing compound, and C ₂ H ₄ , CH ₄ , C ₂ H ₆ , C ₃ H ₈ , C _{2 is} used as a C-containing compound.
H _{2 and the} like, as N-containing compounds, N ₂ , NF ₃ , N ₂ O,
N ₂ O ₄ , NO, N ₃ H _{8 and the} like may be appropriately combined.

Further, a raw material compound containing Si and C and N
May be formed by mixing two kinds of gases of a raw material compound containing
No. In this case, the above-mentioned N-containing compound is used.
Alkyl silanes, a
Using an organic silane such as alkoxysilane,
Can be combined. As an alkylsilane, for example
For example, methylsilane (SiH₃(CH₃)), Dimethylsi
Run (SiH₂(CH ₃)₂), Trimethylsilane (S
iH (CH₃)₃), Tetramethylsilane (Si (CH
₃)₄Methylated silanes such as
As the silane, for example, trimethoxymethylsilane
(Si (CH₃) (OCH₃)₃)
Silane. Conversely, Si and N
The source gas containing C and the source gas containing C
Is also good. In this case, the C-containing compound is as described above.
And the compounds containing Si and N include, for example,
For example, disilazane (SiH₃-NH-SiH₃)
These may be appropriately combined.

Further, a compound containing all of Si, C and N
Can be used as a source gas. like this
The compound has a silazane bond (-Si-N-)
Organic silazane compounds can be used. Organic sila
When using a cyanide compound, for example,
The film can be formed by more thermal polymerization. Available Available
As the silazane compound, for example, triethylsilaza
(SiEt₃NH₂), Tripropylsilazane (Si
Pr₃NH₂), Triphenylsilazane (SiPh)₃N
H₂), Tetramethyldisilazane (SiMe)₂H-NH
-SiMe₂H), hexamethyldisilazane (SiMe)
₃-NH-SiMe₃), Hexaethyldisilazane (S
iEt₃-NH-SiEt₃), Hexaphenyldisila
Zan (SiPh)₃-NH-SiPh₃), Heptamethyl
Disilazane (SiMe₃-NMe-SiMe₃), Zip
Ropyl-tetramethyldisilazane (SiPrMe₂-N
H-SiPrMe₂), Di-n-butyl-tetramethyl
Disilazane (SiBuMe ₂-NH-SiBuM
e₂), Di-n-octyl-tetramethyldisilazane
(SiOcMe₂-NH-SiOcMe₂), Triet
Ru-trimethylcyclotrisilazane ((SiEtH-N
Me)₃), Hexamethylcyclotrisilazane ((Si
Me₂-NH)₃), Hexaethylcyclotrisilazane
((SiEt₂-NH)₃), Hexaphenylcyclot
Lysilazane ((SiPh₂-NH)₃), Octamethyl
Cyclotetrasilazane ((SiMe₂-NH)₄), Oh
Kutaethylcyclotetrasilazane ((SiEt₂-N
H)₄), Tetraethyl-tetramethylcyclotetracy
Razan ((SiHEt-NMe)₄), Cyanopropyl
Methylcyclosilazane (SiMeNC (CH₂)₃-N
H), tetraphenyldimethyldisilazane (SiMeP)
h₂-NH-SiMePh₂), Diphenyl-tetrame
Tildisilazane ((SiMe₂Ph)₂-NH), bird
Vinyl-trimethylcyclotrisilazane ((CH₂= C
H-SiMe-NH)₃), Tetravinyl-tetramethyl
Rucyclotetrasilazane (CH₂= CH-SiMe-N
H)₄, Divinyl-tetramethyldisilazane (CH₂=
CH-SiMe₂-NH-SiMe₂-CH = CH₂)
Is mentioned. In the above formula, Me is a methyl group (CH₃),
Et is an ethyl group (C₂H₅) And Pr are propyl groups (C₃
H₇) And Oc are n-octyl groups (nC ₈H₁₇), P
h is a phenyl group (C₆H₅).

Further, in the above example, one kind of source gas containing Si, C, and N only needs to be used. However, the present invention is not limited to this. For example, in addition to organic silane and N ₂ , C ₂ H ₂ the gas and the addition, gas may be used in which the N ₂ is added to the other organic silazane.

In the above embodiment, an etching stopper film made of Si, C, and N was formed on a single-layered interlayer insulating film made of SiOF or the like, and via holes and trench holes were formed using the etching stopper film as a mask. However, the step of forming a wiring layer using the etching stopper film of the present embodiment is not limited to the above step. For example, a via hole and a trench hole are sequentially formed by using the process shown in FIGS.
The configuration shown in FIG. In this case, the lower insulating layer 501 is first selectively etched by using the etching stopper film 502 for forming a via hole containing Si, C, and N as main elements as a mask to selectively etch the via hole 504.
To form Subsequently, an upper insulating layer 503 is formed, and a trench hole 505 is formed by etching using a resist film or the like as a mask.

By forming the wiring layer so as to sandwich the etching stopper film 502 between the insulating layers 501 and 503 as described above, a problem arises when the trench hole is etched to a predetermined depth. The bottom of the trench hole 505 is not flat, or the trench hole 50 formed at the center and the end of the wafer to be processed.
Variations in the etching shape, such as a difference in the depth of 5, can be suppressed. Also, in the structure shown in FIG. 10, as described in the above embodiment, the etching stopper film containing Si, C, and N as main elements has a low relative dielectric constant, and thus sufficiently functions as an insulating film.

[0059]

As described above, according to the present invention,
A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. More specifically, the present invention provides a semiconductor device having an etching stopper film having low dielectric constant, high etching selectivity with a base film, and low metal diffusion, and a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a view sequentially showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a view sequentially showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a view sequentially showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a view sequentially showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 6 is a view sequentially showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a diagram showing the composition of a SiCN-based film formed by changing the content ratio of C and N.

FIG. 8 shows a SiCN-based film having the CN composition shown in FIG.
FIG. 3 is a diagram showing an etching rate ratio when an etching rate of a SiN-based film is set to 1;

FIG. 9 shows C of the SiCN-based film having the CN composition shown in FIG. 7;
It is a figure which shows the result of having investigated about SIMS intensity | strength about u diffusivity.

FIG. 10 is a partial cross-sectional view of a semiconductor device according to another embodiment of the present invention.

FIGS. 11A to 11C are diagrams sequentially illustrating a wiring layer forming process by a damascene method.

[Explanation of symbols]

 Reference Signs List 101 first base film 102 first conductor layer 102a first barrier metal film 103 first trench hole 104 first via hole 105 first etching stopper film 106 second base film 107 second conductor layer 107a Second barrier metal film 108 Second trench hole 109 Second via hole 110 Second etching stopper film 111 Third etching stopper film 112 Third base film 113 Passivation film 201 First resist film 202 Second Resist film

Continued on the front page (72) Inventor Gohei Kawamura 650 Mitsuzawa, Hosaka-cho, Nirasaki-shi, Yamanashi Prefecture F-term in Tokyo Electron Co., Ltd. (reference) KK01 KK08 KK09 KK11 KK18 KK19 KK21 KK32. BF26 BF29 BF30 BJ02

Claims (12)

[Claims] A first insulating layer having a low dielectric constant having a plurality of grooves or holes, and a plurality of openings formed on the first insulating layer and overlapping the plurality of grooves or holes; And a second insulating layer containing C and N as main elements, and a conductor layer embedded in a plurality of wiring grooves or holes formed from the plurality of grooves or holes and the plurality of openings. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the second insulating layer has a ratio of the number of C atoms to the number of Si atoms of 0.2 to 0.8;
The semiconductor device according to claim 1, wherein a ratio of the number of N atoms to the number of atoms is 0.15 to 1.0. 3. The semiconductor device according to claim 1, wherein said first insulating layer is made of silicon fluoride oxide or carbon fluoride. 4. The semiconductor device according to claim 1, wherein said conductor layer is made of Cu. 5. The semiconductor device according to claim 1, wherein a barrier metal layer is formed in the wiring groove or the hole, and the conductor layer is formed on the barrier metal layer. 3. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 1, further comprising a third insulating layer formed on the second insulating layer and the conductor layer and having the same configuration as the second insulating layer. Item 6. The semiconductor device according to any one of Items 1 to 5. 7. A step of forming a first insulating layer; a step of forming a second insulating layer mainly containing Si, C and N on the first insulating layer; Selectively etching the second insulating layer to form an opening so that the surface of the first insulating layer is partially exposed; and using the selectively etched second insulating layer as a mask, Forming a wiring groove or hole by etching a first insulating layer; forming a conductive layer by filling the opening and the wiring groove or hole; and forming the conductive layer on the second insulating layer. Polishing the semiconductor device using the substrate as a stopper. 8. The second insulating layer has a ratio of the number of C atoms to the number of Si atoms of 0.2 to 0.8;
The method according to claim 7, wherein a ratio of the number of N atoms to the number of atoms is 0.15 to 1.0. 9. The method according to claim 7, wherein the first insulating layer is made of silicon fluoride oxide or carbon fluoride. 10. The method according to claim 7, wherein the conductor layer is made of Cu. 11. The semiconductor device according to claim 7, further comprising a step of forming a barrier metal layer between said conductor layer and said opening and said wiring groove or hole. Method. 12. A third semiconductor device having the same structure as the second insulating layer on the second insulating layer and the conductor layer.
The method of manufacturing a semiconductor device according to claim 7, further comprising: forming an insulating layer.