JP2002082902A - Access competition control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an access competition control circuit for plural DSPs of which overall constitution is simple, which has extendibility and which enables improve the performance of the DSPs. SOLUTION: An interrupting signal 10 of a phase difference time (t) and an interrupting interval (T) are inputted from an interruption generating circuit 8 to plural DSPs 1-4 arranged in parallel. An access request signals 12 from the DSPs 1-4 are inputted through a mask circuit 7 to a priority encoder 5, and a selection signal 16 is inputted to a control signal generating circuit 6, and an access permission signal 14 is transmitted to a selected DSP among the DSPs 1-4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access conflict control circuit, and more particularly to a circuit in which a plurality of DSPs (Digital Signal Processors) or CPUs (Central Processing Units) operate simultaneously and in parallel. The present invention relates to a circuit for avoiding a situation that occurs.

[0002]

2. Description of the Related Art The prior art or related art of such an access conflict control circuit is disclosed in, for example, "Control DSP arithmetic processing unit" in Japanese Patent Application Laid-Open No. 2-213947 and Japanese Patent Application Laid-Open No. 5-29.
No. 8248, “Data transfer control method” and the like. In the former, a program timer is used to switch an input signal to a shared circuit such as a memory or a register. Also, the program processing cycles in the two DSPs are reversed. These techniques disclose a technique for avoiding contention. In the latter case, a control signal is issued to the control unit at the time of writing to the DSP so that writing of the DSP and reading from the CPU do not conflict with each other with respect to the CPU read / write register unit. Then, the control unit suspends the read operation from the CPU based on the control signal. Then, a technique is disclosed in which the control circuit releases the suspension when the DSP finishes the write operation.

[0003]

The prior art as described above has several problems to be solved. First, the switching operation of the input signal by the program timer is mainly realized by hardware, but a procedure for cooperating with a program (software) operating inside the DSP tends to be complicated.

Second, there are two or more methods for avoiding contention by operating the program processing cycle in reverse between the two DSPs, thereby avoiding performing the same processing in the same time zone. When expanding, D
The extensibility is low because the program inside the SP needs to be changed.

Third, a method of avoiding contention between write / read operations to a register is to avoid contention by suspending the operation of the CPU when the DSP accesses the register. However, CPU which operates asynchronously in this way
When the control for asynchronously suspending the operation between the DSP and the DSP is performed, the performance of the CPU is reduced. Further, when this control is applied to a plurality of DSPs, there is a concern that the performance of each DSP may decrease.

[0006]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a simple hardware circuit which can avoid contention for access to a shared circuit by a plurality of DSPs, has excellent expandability, and does not need to change a program in the DSP. An object of the present invention is to provide an access conflict control circuit which can be easily extended. Also, DS
Regardless of the number of Ps, DSPs can have their own occupied time zones, and each DS
An object of the present invention is to provide an access contention control circuit that does not degrade the performance of P.

[0007]

An access contention control circuit according to the present invention operates a plurality of DSPs (digital signal processors) in parallel to avoid access contention when accessing a shared circuit such as a memory or a register. An interrupt signal having a phase difference is input to each DSP to a shared circuit in which a conflict may occur, and the interrupt signal having the phase difference is used as a starting point of internal processing of each DSP. According to a preferred embodiment of the present invention, the interrupt signals to the plurality of DSPs have a predetermined phase difference time (t) and an interrupt interval (T). The interrupt interval (T) of the interrupt signal can be changed according to the expansion of the system using the DSP or the processing time inside the DSP.

An access contention control circuit according to the present invention includes a plurality of DSPs arranged in parallel, an interrupt generation circuit for inputting an interrupt signal having a phase difference to these DSPs sequentially, and an access request signal from the DSP. The control circuit includes a selection circuit that outputs a selection signal, and a control signal generation circuit that receives the selection signal and inputs an access permission signal to one of the plurality of DSPs. Further, according to a preferred embodiment of the present invention, the selection circuit includes a mask circuit to which an access request signal from the DSP is input and a priority encoder to receive a signal from the mask circuit. In addition, a chain system is adopted in place of the priority encoder.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a preferred embodiment of an access contention control circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a preferred embodiment of an access contention control circuit according to the present invention. The access contention control circuit includes a plurality (four in this specific example) of DSPs 1 to 4, a priority encoder 5, a control signal generation circuit 6, a mask circuit 7, and an interrupt generation circuit 8.

The plurality of DSPs 1 to 4 receive the interrupt signal 10 from the interrupt generation circuit 8 and the access permission signal 14 from the control signal generation circuit 6. Then, an access request signal 12 is output from the DSPs 1 to 4 to the mask circuit 7. The access request signal 12 ′ masked by the mask circuit 7 is input to the priority encoder 5. The output of the priority encoder 5 is input to the control signal generation circuit 6. Further, the control signal generation circuit 6 outputs the access permission signal 14 to the DSPs 1 to 4 as described above, and the control signal is input to the mask circuit 7.

The preferred embodiment of the access contention control circuit according to the present invention described above with reference to FIG.
Although the number includes 1 to 4, the maximum number of DSPs does not need to be limited to 4 and can be arbitrarily selected according to a specific application.
Each of the DSPs 1 to 4 has a general-purpose port capable of defining an access request signal 12 and an access permission signal 14, and an external interrupt input.

Next, the priority encoder 5 will be described. With this priority encoder 5,
The highest priority DSP (for example, DSP1) is selected from the access request signals 12 from the DSPs 1 to 4, and the selection signal 16 is output to the control signal generation circuit 6. The control signal generation circuit 6 generates and transmits an access permission signal 14 to each of the DSPs 1 to 4 based on the selection signal 16 from the priority encoder 5. A similar signal is input to the mask circuit 7.

The mask circuit 7 transmits the access permission signal 14 from the control signal generation circuit 6 to the DSP (for example, DS).
It has a function of masking access request signals from DSPs other than P1) (for example, DSPs 2 to 4). The interrupt generation circuit 8 generates an interrupt signal 10 for each of the DSPs 1 to 4. One example of these interrupt signals 10 is shown in the timing chart of FIG. 2A shows an interrupt signal 10a to the DSP 1, FIG. 2B shows an interrupt signal 10b to the DSP 2, and FIG. 2C shows an interrupt signal 10c to the DSP 3. These interrupt signals 10a to 10c
As is clear from FIG. 5, each interrupt signal 10 is a signal at a time interval T having a phase difference of t times from each other. In this specification, the interrupt signal 10 is defined as interrupt signals 10a to 1
0c is a generic term.

Next, the operation of the access conflict control circuit shown in FIG. 1 will be described. The interrupt generation circuit 8 is provided for each of the DSPs 1 to
4 are input with interrupt signals 10a to 10c each having a phase difference by t time. Each of the DSPs 1 to 4 performs program processing internally from the interrupt signals 10a to 10c. Since the interrupt has a phase difference of t time, a processing time difference of an integral multiple of t time is inevitably generated between the DSPs 1 to 4.

Each of the DSPs 1 to 4 accesses a shared circuit such as a memory or a register as needed. First,
The DSPs 1 to 4 activate the access request signal 12 to obtain the right to access the shared circuit. The active access request signal 12 is input to the priority encoder 5 and the highest priority DSP
(For example, DSP1) is selected. Since there is a phase difference in the internal processing of each of the DSPs 1 to 4, a single DSP activates the normal access signal, and the DSP is necessarily selected by the priority encoder 5.

In the control signal generation circuit 6, the selected DS
P (eg, DSP1) access permission signal 14
Is activated, and other DSPs (for example, DSP2
In 4), the inactive state is maintained. Further, the mask circuit 7 masks the access request signal 12 other than the selected DSP by the mask signal from the control signal generation circuit 6 to obtain an access request signal 12 '. This is the selected D
This is so that even if a DSP having a higher priority than the SP activates the access request signal 12, the result selected earlier does not hinder. Selected D
The SP receives the access permission signal 14 and accesses a series of shared circuits. The selected DSP inactivates the access permission signal 14 after a series of accesses is completed.

In the priority encoder 5, since all the access request signals 12 become inactive, the operation shifts to the idle mode. In the control signal generation circuit 6, all the access permission signals 14 are made inactive, and in the mask circuit 7, all the masks are turned off, and the process proceeds to the next phase.

[0019]

Other Embodiments In the preferred embodiment of the access contention control circuit according to the present invention described above, the processing starting point in the DSP is executed by interruption. Instead of this, each D
A timer may be provided for each of the SPs 1 to 4, and the timer value may be used as a starting point of the processing. Priority encoder 5 shown in FIG.
, And a chain method may be used. By using the chain method, data processing time can be reliably given to each DSP regardless of the number of DSPs. The interrupt interval T time can be adjusted by the processing time inside the DSP. The same applies to the time t.

The configuration and operation of the preferred embodiment of the access conflict control circuit according to the present invention have been described in detail. But,
It should be noted that such embodiments are merely examples of the present invention and do not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.

[0021]

As will be understood from the above description, the access contention control circuit of the present invention has the following practically significant effects. That is, by using simple hardware, it is possible to effectively avoid contention for access to the shared circuit by a plurality of DSPs. In addition, it is excellent in extensibility, and can be easily extended without changing the program inside the DSP. Regardless of the number of DSPs, each DSP can have its own occupied time zone, so that the performance of each DSP is not degraded by expansion or contention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a preferred embodiment of an access conflict control circuit according to the present invention.

FIG. 2 is a timing chart of an interrupt signal of the access conflict control circuit shown in FIG. 1;

[Explanation of symbols]

 1-4 DSP 5 priority encoder 6 control signal generation circuit 7 mask circuit 8 interrupt generation circuit 10 interrupt signal 12, 12 'access request signal 14 access permission signal 16 selection signal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 15/16 620 G06F 15/16 620G 15/177 680 15/177 680A

Claims (6)

[Claims] 1. A plurality of DSPs (digital signal processors)
Are operated in parallel to avoid an access conflict when accessing a shared circuit such as a memory or a register. In the access conflict control circuit, an interrupt signal having a phase difference with respect to the shared circuit where a conflict may occur is provided. An access conflict control circuit, wherein an interrupt signal input to each of the DSPs and having the phase difference is used as a starting point of internal processing of each of the DSPs. 2. The access contention control circuit according to claim 1, wherein said interrupt signals to said plurality of DSPs have a predetermined phase difference time (t) and an interrupt interval (T). 3. The system according to claim 1, wherein an interruption interval (T) of the interruption signal can be changed in accordance with expansion of a system using the DSP or processing time inside the DSP. Access conflict control circuit. 4. A plurality of DSPs arranged in parallel, and said DSPs
An interrupt generation circuit for sequentially inputting an interrupt signal having a phase difference, a selection circuit for receiving an access request signal from the DSP and outputting a selection signal, and selecting one of the plurality of DSPs for receiving the selection signal. And a control signal generation circuit for inputting an access permission signal to the two DSPs. 5. The apparatus according to claim 4, wherein said selection circuit comprises a mask circuit to which an access request signal from said DSP is inputted and a priority encoder to which a signal from said mask circuit is inputted. Access contention control circuit. 6. The access contention control circuit according to claim 5, wherein a chain system is adopted in place of said priority encoder.