JP2002077309A - Signal-processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal-processing circuit for PCI that can prevent wasteful power consumption. SOLUTION: The signal-processing circuit comprises a physical layer circuit 11 for monitoring the connection state of an IEEE 1394 serial interface bus BS, and generating and transmitting a CAN signal that indicates that an IEEE 1394 serial interface bus cable is not connected to a connection node if it is not connected; and a link layer circuit 12 having a clock control circuit 120 for determining that the IEEE 1394 serial interface bus cable is not connected to the connection node of the physical layer circuit 11, when it receives the CAN signal from the physical layer circuit 11; setting a CLKRUN# signal to a high level; and reporting to a central resource that a PCI cock is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit used for a digital serial interface.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Elect) has realized high-speed data transfer and real-time transfer.
ricaland Electronic Engineers) 1394, High
Performance Serial Bus has been standardized.

[0003] In the data transfer of the IEEE 1394 serial interface, an asynchronous (Asynchronous) method of requesting and acknowledgment request and reception confirmation of the related art is used.
Transfer includes isochronous transfer in which data is always sent from a certain node once every 125 μs.

As described above, an I having two transfer modes
The data in the EEE1394 serial interface is
Transfer is performed in packet units. And IEEE13
In the H.94 standard, the minimum data unit handled is one quadlet (= 4 bytes = 32 bits).

IEEE 1394 for transmitting and receiving packets
As shown in FIG. 9, the signal processing circuit of the serial interface mainly includes a physical layer circuit 1 that directly drives the IEEE 1394 serial interface bus BS and a link layer circuit 2 that controls data transfer of the physical layer circuit 1. Be composed. Note that the physical layer circuit 1 and the link layer circuit 2 are practically used as individual LSIs. Then, the PCI (P
personal computer interface), MPEG transporter (Transporter), DVCR (Digital Video Cassette®)
ecorder) is connected.

[0006]

By the way, PCI M
In the object Design Guide, CLKR
A signal called UN # (clock run signal) is defined. Devices connected to the PCI bus are so-called PCs.
By setting this CLKRUN # signal to a low level at the time of the I master, a PC is connected to a central resource (Central Resource) which is a clock supply source.
Request I clock. Conversely, when the PCI clock is not required, the CLKRUN # signal is set to a high level to notify the central resource that the PCI clock is not required. Then, the central resources are all the CLKRUNs on the same PCI bus.
After confirming that the # signal is not low asserted, the PCI clock can be stopped. This method of controlling clock supply using the CLKRUN # signal is an effective method for reducing power consumption in current mobile PCs.

However, the IEEE 1394-PCI link layer circuit that controls the IEEE 1394 device does not have a valid trigger for asserting the CLKRUN # signal, and requests a clock even when the PC is not connected to the IEEE 1394 device. And wasted power.

[0008] The present invention has been made in view of such circumstances, and has as its object to reduce the power consumption to prevent unnecessary power consumption.
An object of the present invention is to provide a signal processing circuit for CI.

[0009]

In order to achieve the above object, the present invention provides a PCI (Personal Computer Interface).
Connected between the bus and the serial interface bus, arbitrating data for both buses and setting a prescribed clock run signal to a first level,
A signal processing circuit for requesting a clock from a clock supply source on the side of the side and setting a clock run signal to a second level to notify that the clock supply source does not require a clock. There is provided a means for monitoring whether or not the connection is established and, if it is determined that the serial interface bus is not connected, setting the clock run signal to the second level to stop a request for a clock.

The present invention also relates to a PCI (Personal Computing).
er Interface) is connected between the bus and the serial interface bus, arbitrates data for both buses, and sets a specified clock run signal to the first level to request a clock from the clock supply source on the PC side. A signal processing circuit for notifying the clock supply source that a clock is unnecessary by setting a clock run signal to a second level, wherein the serial interface bus is connectable and the serial interface bus is connected Monitoring whether or not the serial interface bus is not connected, and when it is determined that the serial interface bus is not connected, the physical layer circuit for generating a non-connection signal indicating that the serial interface bus is not connected is connected to the PCI bus, When data is exchanged with the physical layer circuit and the disconnection signal is received, The Kkuran signal is set to a second level and a link layer circuit comprising a clock control circuit for stopping the request clock.

In the present invention, the physical layer circuit has a unique control timing within a predetermined allowable range, sends packet data to the serial interface bus, and the link layer circuit A holding circuit capable of setting control timing data; receiving packet data from a PCI bus to generate packet data; and generating the generated packet data at a timing based on the control timing data set in the holding circuit. Send to circuit.

According to the present invention, for example, in a physical layer circuit, the connection state of the IEEE 1394 serial interface bus is monitored, and the connection state of the IEEE 1394 serial interface bus is monitored.
If the 1394 serial interface bus cable is not connected to the connection node, a disconnection signal indicating that fact is generated and sent to the clock control circuit of the link layer circuit. When the clock control circuit receives the non-connection signal from the physical layer circuit, it receives the IEEE signal.
It is determined that the 1394 serial interface bus cable is not connected to the connection node of the physical layer circuit, and the specified clock run (CL
KRUN #) signal is set to a second level, eg, a high level, and the central resource is notified that a clock is not required. Thereby, when the IEEE 1394 serial interface bus cable is not connected to the connection node of the physical layer circuit,
Since the request for the clock is stopped, unnecessary power consumption is suppressed.

On the other hand, in the physical layer circuit, when the IEEE 1394 serial interface bus cable is connected to the connection node, no non-connection signal is generated, and the non-connection signal is set to an inactive state. Accordingly, the clock control circuit of the link layer circuit determines that the IEEE 1394 serial interface bus cable is connected to the connection node of the physical layer circuit, and sets the clock run (CLKRUN #) signal to the first level. For example, it is set to a low level, and a clock is required of a central resource. As a result, the PCI clock is supplied from the central resource to the link layer circuit.

[0014]

FIG. 1 is a block diagram showing an embodiment of a PCI signal processing circuit according to the present invention applied to an IEEE 1394 serial interface, and FIG.
FIG. 2 is a block diagram showing a specific configuration example of a link layer circuit of FIG. 1.

The signal processing circuit 10 includes a physical layer circuit 11, a link layer circuit 12, and a storage circuit 13. The physical layer circuit 11 is connected to an IEEE 1394 serial interface bus BS, and the link layer circuit 12 is connected to a PCI bus. In addition, physical
The layer circuit 11 and the link layer circuit 12 are formed as individual LSIs, respectively.

Physical layer circuit (PHY) 11
Is the IEEE 1394 serial interface bus BS
Is directly driven to transmit each packet to the IEEE 1394 serial interface bus BS and to receive various transmitted packets. Communication between the physical layer circuit 11 and the link layer circuit 12 mainly includes a request (Request), a status (Status), and a transmission (T
There are four types, ransmit) and receive (Receive), the contents of which will be described later. Also, the physical layer circuit 11 has a function of monitoring the connection state of the IEEE 1394 serial interface bus BS.
When the 1394 serial interface bus cable is not connected to the connection node, a CNA (Cable Not Connect) as a non-connection signal indicating the fact is provided.
ted) A signal is generated and sent to the link layer circuit 12.

The link layer circuit (Link) 12 includes:
Control of asynchronous transfer and isochronous transfer,
And controls the physical layer circuit 11. In addition, the link layer circuit 12 is a PCI Mobile
CLKRUN specified in Design Guide
Communication with a central resource (clock controller) on the PCI side (not shown) corresponding to the # protocol. C
LKRUN # is an open-drain bidirectional signal, and the link layer circuit 12 asynchronously enables CLKRUN #, and starts and accelerates the clock to the central resource.
Request maintenance. Then, the link layer circuit 12
The input of the CLKRUN # signal is monitored as a clock status. The link layer circuit 12 is a so-called PCI
When the master is set, the CLKRUN # signal is set to a low level to request a PCI clock from a central resource which is a clock supply source. When the PCI clock is not required, the link layer circuit 12 sets the CLKRUN # signal to a high level to notify the central resource that the PCI clock is unnecessary. When the CLKRUN # signal is set to a high level, the signal from the physical layer circuit 11
This includes the case where the NA signal is received.

Specifically, the link layer circuit 12
As shown in FIG. 2, the clock control circuit (CLK CTL) 12
0, a link core 121, a receiving direct memory access (ARDMA) controller 122 for asynchronous communication, and a transmitting DMA controller (A).
TDMA) 123, receiving DMA for isochronous communication
Controller (IRDMA) 124, transmission DMA controller (ITDMA) 125, reception FIFO (RFIF) for asynchronous communication and isochronous communication
O: FIFO; First-InFirst-Out) 126, transmission FIFO for asynchronous communication (ATFIFO) 127, transmission FIFO for isochronous communication (ITFIFO) 12
8, a control register 129, a master bus interface circuit (MBIUMUX) 130, an internal bus interface circuit (INT BUS) 131, and a PCI interface circuit (PCI INF) 132.

In the circuit of FIG. 2, the link cores 121, D
MA controllers 122 and 123, FIFOs 126 and 1
27 constitutes an asynchronous communication system circuit. Then, the link core 121, the DMA controller 124,
An isochronous communication system circuit is constituted by the 125 and the FIFOs 126 and 128.

The clock control circuit 120 sets the CLKRUN # signal to a low level in accordance with the CLKRUN # protocol specified in the PCI Mobile Design Guide, as described above, so that the clock is transmitted through the PCI interface circuit 132. Request a PCI clock from the central resource that is the source. When the PCI clock is not required, the CLKRUN # signal is set to the high level to notify the central resource via the PCI interface circuit 132 that the PCI clock is unnecessary. Further, when the clock control circuit 120 receives the CNA signal from the physical layer circuit 11, it receives the IEEE
It is determined that the 1394 serial interface bus cable is not connected to the connection node of the physical layer circuit 11, and the CLKRUN # signal is set to a high level to notify the central resource that the PCI clock is unnecessary, and Reduce power consumption.

The basic operation corresponding to the CLKRUN # function in the link layer circuit 12 including the clock control circuit 120, except when the CNA signal is received, is as follows.
As described below, the operation is performed corresponding to the three modes.

First mode: After a chip reset, it does not participate in the control of CLKRUN # until the enable clock RUN bit of the control register 129 is set.

Second mode: The enable clock RUN bit of the control register 129 is set, but the link-on bit of the control register 129 is reset. When the link layer circuit 12 is accessed, it always requires the clock input to be active, for example, for four clock cycles or more to complete the internal process.
The clock control circuit 120 outputs CL at the end of the bus cycle.
Monitor the RUN # signal. If the CLKRUN # signal is at the high level when the sampling is performed, the clock control circuit 120 further controls the CLKRUN # for another two clocks.
The N # signal is driven low to request the central resource to provide a clock during this additional period. As a result, a sufficient clock margin for completing an internal process following the bus cycle is secured.

Third mode: The enable clock RUN bit of the control register 129 is set, and the link-on bit is also set. The clock control circuit 120 requests that the central resource always maintain the clock. Clock control circuit 120 continuously monitors the CLKRUN # signal to perform this. When the clock control circuit 120 samples the CLKRUN # signal in the high level state, the clock control circuit 120 always outputs the signal CLKR # for two clocks.
After the UN # signal is driven to low level, the clock is released. This process continues as long as the enable clock RUN bit and the link on bit are set.

The link core 121 is a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets, an interface circuit of these packets with the physical layer circuit 11 which directly drives the IEEE 1394 serial bus BS, and is reset every 125 μs. It comprises a cycle timer, a cycle monitor and a CRC circuit. The interface circuit between the physical layer circuit 11 and the link layer circuit 12 is read from an external storage circuit or the like and set in the control register 129 when the power is turned on, for example. Interface bus LPBS
Based on the control timing, the transmission and reception of packets between the link layer circuit 12 (link core 121) and the physical layer circuit 11 are controlled.

FIG. 3 shows an interface bus LPBS between the link layer circuit 12 and the physical layer circuit 11.
FIG. 4 shows the main signals propagated above, and FIG.
FIG. 4 is a diagram showing a circuit (Link or PHY) for driving each signal shown in FIG. 3 and its contents.

D [0: n] is the link layer circuit 12
And data transmitted and received between the physical layer circuit 11. The value of n differs depending on the maximum speed of the device. For example, when the maximum speed is 100 Mbps (Mega bit per second), n = 1 (D [0: 1]) for 2-bit data, and when the maximum speed is 200 Mbps, 4 bits. N = 3 in the data
(D [0: 3]), when the maximum speed is 400 Mbps,
N = 7 (D [0: 7]) for 8-bit data.

Ctl [0: 1] is transmitted / received between the link layer circuit 12 and the physical layer circuit 11.
This is a bit control signal. Physical layer circuit 11
The communication between the communication and the link layer circuit 12 mainly includes a request, a status, and a transmission.
t) and reception (Receive).
It is defined by two bits of tl [0: 1]. The contents are different between when the physical layer circuit 11 is controlling and when the link layer circuit 12, ie, the link core 1
20 is different when controlling.

FIG. 5 shows the contents of the control signal Ctl [0: 1] when the physical layer circuit 11 is controlling, and FIG. 6 shows the control signal when the link layer circuit 12 is controlling. Shows the contents of Ctl [0: 1].

When the physical layer circuit 11 is controlling, as shown in FIG. 5, the control signal Ctl [0:
When the two bits of [1] are "00", the bus is idle (I
dle) state.

When the two bits of the control signal Ctl [0: 1] are "01", the communication state is the status, and the physical layer circuit (PHY) 11 transmits the status information to the link layer circuit (Link) 12. Is sent.

When the two bits of the control signal Ctl [0: 1] are "10", it indicates that the receiving state is in effect and the physical layer circuit 11 is transmitting a packet to the link layer circuit 12.

When the two bits of the control signal Ctl [0: 1] are "11", it indicates that the transmission is in the transmission state and the transmission of the packet to the link layer circuit 12 is permitted.

When the link layer circuit 12 is controlling, as shown in FIG. 6, when the two bits of the control signal Ctl [0: 1] are "00", the bus is idle (Idl).
e) In the state, it indicates that the link layer circuit 12 has completed the packet transmission.

When the two bits of the control signal Ctl [0: 1] are "01", it is a hold (Hold) period,
Until the link layer circuit 12 is ready for transmission, the bus L
This indicates that the PBS is held, in other words, that it has exclusive use. Alternatively, it indicates that the link layer circuit 12 is transmitting another packet without arbitration. This hold period is up to 47 clocks (MAX) depending on the standard. HO
LD) is a variable time allowed. In other words, it means that the time for sending a packet to the IEEE 1394 serial interface bus BS can be controlled by this time. This clock number data is data in accordance with the inherent timing of the physical layer circuit 11 to be connected, and is set in the control register 129, for example, when the power is turned on, and “47” is given from the control register 129. Can be

When the two bits of the control signal Ctl [0: 1] are "10", the transmission state is in effect, indicating that the link layer circuit 12 is transmitting a packet to the physical layer circuit 11.

It is to be noted that two bits of the control signal Ctl [0: 1] when the link layer circuit 12 is controlling are "1".
The state of “1” is not specified, for example, and is unused.

LReq is a request signal from the link layer circuit 12 to the physical layer circuit 11 and is used to request access to a bus and read / write of a register of the physical layer circuit 11. That is, the request signal LReq is mainly used when the link layer circuit 12 transmits a packet to indicate to the physical layer circuit 11 that preparation for packet transmission is completed. For example, in the case of isochronous communication, a cycle start packet is transmitted, and after the two bits of the control signal Ctl [0: 1] change from "10" indicating transmission to "00" indicating transmission completion, the state becomes idle. The standard defines that the clock must not be later than 8 clocks before the request signal LReq is output to transmit the next packet. In other words, it means that any number of clocks may be used in this range.
This clock number data is data in accordance with the unique timing of the physical layer circuit 11 to be connected,
For example, when the power is turned on, the value is set in the control register 129, and “6” is given from the control register 129, for example.

FIG. 7 shows an example of a timing chart of the request signal LReq and the control signal Ctl [0: 1].

SClk is a physical layer circuit 11
Is a system clock supplied to the link layer circuit 12 from the. The system clock SClk has a frequency of any of 12.288 MHz, 24.576 MHz, or 49.152 MHz, as shown in FIG.

LPS is a signal indicating to the physical layer circuit 11 that the link layer circuit 12 is operating with the power on.

LinkON indicates that the signal LPS has caused a logical error or that the link of the register of the physical layer circuit 11 The physical layer circuit 11 notifies the link layer circuit 1 that the active bit has become 0.
2.

DMA 122 for reception of asynchronous communication
And the transmission DMA 123 are mainly PCI
Arbitration such as writing and reading of asynchronous communication packets between the communication side and the reception FIFO 126 and the transmission FIFO 127 is performed.

DMA 124 for reception in isochronous communication
And the transmission DMA 125 are mainly PCI
Arbitration such as writing and reading of packets for isochronous communication between the receiving side and the receiving FIFO 126 and the transmitting FIFO 128 is performed.

The receiving DMA 124 is a link core 101
And transmits the isochronous communication packet stored in the receiving FIFO 126 to the PCI side via the master bus interface circuit 130 and the PCI interface circuit 132.

The transmission MDA 124 receives data from the PCI side via the master bus interface circuit 130 and the PCI interface circuit 132, and
For isochronous communication of the EE1394 standard, the data length is adjusted in quadlet (4 byte) units, and a 4-byte source packet header (SPH), 1394 header, CIP headers 1 and 2 are added, and the transmission FIFO 1
28.

IEEE 139 is provided in the receiving FIFO 126.
4 asynchronous communication packets transmitted through the serial bus BS, and the IEEE 1394 serial bus B
Stores an asynchronous communication packet to be transmitted to S.

The control register 129 stores the link core 120
Control timing data used when the link core 120 transmits / receives a signal including control and data to / from the physical layer circuit 11 when the power is turned on.
Alternatively, it is set at an initial time such as a reset. As described above, the clock number data relating to the hold period, for example, “47” and the clock number data for defining the output timing of the request signal LReq, for example, “6” are also set in the set timing data.

The master bus interface circuit 130
Requests from the various DMA controllers 122 to 125 are received, priorities are set based on the state of the link layer circuit 12 (chip), and the highest priority request is sent to the PCI interface circuit 132.

The PCI interface circuit 132 is a PC
It operates in both the I bus master and slave states. P
The CI interface circuit 132 operates as a slave to perform decoding, and responds to access to an internal register (not shown) of the link layer circuit 12. Further, the PCI interface circuit 132 is connected to the DMA controller 122.
Operate as a PCI bus master for
Generate an I-bus transaction.

Next, the IEEE 1394 serial bus BS
The operation when transmitting an isochronous communication packet to the network will be described.

In the physical layer circuit 11,
The connection state of the IEEE 1394 serial interface bus BS is monitored, and if the IEEE 1394 serial interface bus cable is not connected to the connection node, a CNA signal indicating this is generated, and the clock control of the link layer circuit 12 is performed. Circuit 120
Sent to

When the clock control circuit 120 receives the CNA signal from the physical layer circuit 11, it receives the IE signal.
It is determined that the EE1394 serial interface bus cable is not connected to the connection node of the physical layer circuit 11, the CLKRUN # signal is set to the high level, and the central resource is notified that the PCI clock is not required. As a result, the IEEE
When the 1394 serial interface bus cable is not connected to the connection node of the physical layer circuit 11, the clock request is stopped, so that unnecessary power consumption is suppressed.

On the other hand, in the physical layer circuit 11, when the IEEE 1394 serial interface bus cable is connected to the connection node, the CNA
No signal is generated and the CNA signal is set to the inactive state. Thus, in the clock control circuit 120 of the link layer circuit 12, the IEEE 1394 serial interface bus cable connects the physical layer circuit 1
It is determined that it is connected to one connection node, the CLKRUN # signal is set to low level, and the PCI clock is requested from the central resource. As a result, the PCI clock is supplied from the central resource.

For example, in the third mode in which the enable clock RUN bit of the control register 129 is set and the link-on bit is also set, the clock control circuit 120 requests that the central resource always maintain the clock. . Clock control circuit 12
At 0, the CLKRUN # signal is monitored continuously to perform this.

At an initial stage such as when power is turned on or at the time of reset, the link core 120 is connected to the physical core.
Control timing data used when transmitting / receiving a signal including control and data with the layer circuit 11 is read from an external storage circuit or the like, and is set in the control register 129. The setting data includes data on the number of clocks related to the hold period, for example, “47”, which is data for which an appropriate value can be selected within an allowable range defined by the standard, and a clock that defines the output timing of the request signal LReq. Numerical data, for example, “6” is also included.

Here, the data transmitted through the PCI bus reaches the link layer circuit 12, is input to the transmission MDA 125 via the PCI interface circuit 132 and the master bus interface circuit 130, and is transmitted by the IEEE.
The data length is adjusted in quadlets (4 bytes) for isochronous communication of the E1394 standard, and a 4-byte source packet header (SPH), a 1394 header, and the like are added and stored in the transmission FIFO 128. Then, it is determined that there is a packet to be transmitted.
0 is reported.

The control signal Ctl is output from the link core 120.
[0: 1] 2-bit data is set to “01”,
The physical layer circuit 11 is notified of the hold state, that is, the preparation for transmission and the fact that the bus is held during that time. The control timing of this hold period is determined by the control register 12
9 is automatically set when the power is turned on, and the hold period is maintained for 47 clocks.

When the transmission preparation is completed, a request signal LReq indicating that the packet transmission preparation is completed is output to the physical layer circuit 11, and the control signal Ctl is output.
The physical layer circuit 11 is notified that the 2-bit data of [0: 1] is set from "01" to "10" and is in the transmission state, and, for example, a cycle start packet is transmitted to the physical layer circuit 11. Sent to. When the transfer of the cycle start packet is completed, the 2-bit data of the control signal Ctl [0: 1] is changed to "1".
The value is set from “0” to “00”, and the physical layer circuit 11 is notified that the transmission has been completed and the device has entered the idle state.

Transmit a cycle start packet,
Two bits of the control signal Ctl [0: 1] indicate "1" indicating transmission.
After the idle state of “00” indicating transmission completion from “0”, a request signal LReq is output to transmit the next packet.
Is output in accordance with the unique timing of the physical layer circuit 11 of the transmission partner.
The next request signal LReq and the control signal Ctl [0: 1] set to "10" are output after 6 clocks based on the setting data.

Then, the physical layer circuit 11 receives the request signal LReq and receives the IEEE 1394 signal.
Arbitration of the serial interface bus BS is performed,
If successful, the packet is sent to the IEEE 1394 serial interface bus BS.

Thereafter, the same operation is performed until there are no more packets to be transmitted.

As described above, according to the present embodiment, the IEEE 1394 serial interface bus BS
And a physical layer circuit 11 that generates a CNA signal indicating that the IEEE 1394 serial interface bus cable is not connected to the connection node and sends it to the link layer circuit 12 if the IEEE 1394 serial interface bus cable is not connected to the connection node. When the CNA signal from the physical layer circuit 11 is received, it is determined that the IEEE 1394 serial interface bus cable is not connected to the connection node of the physical layer circuit 11 and CLKR
Since the link layer circuit 12 having the clock control circuit 120 for setting the UN # signal to a high level and notifying the central resource that the PCI clock is unnecessary is provided, the IEEE 1394 serial interface bus cable is connected to the physical layer circuit. When not connected to the eleventh connection node, there is an advantage that unnecessary power consumption can be prevented because the clock request is stopped.

The link core 121 of the link layer circuit 12 has a physical link having a unique control timing.
Control timing data which is used when transmitting / receiving a signal including control and data with the layer circuit 11 and which is selected according to a unique control timing of the physical layer circuit 11 connected to the link layer circuit 12 is, for example, Since the control register 129 which is set from an external storage circuit or the like is provided at the time of power-on or at the initial stage such as at the time of resetting, there is an advantage that variation in transmission timing of packets transmitted to the serial interface bus can be prevented. Further, the link layer circuit 12 is connected to, for example, a PC.
When the connection is made to the I or the like, the operation can be performed immediately after the connection without initialization.

It is also possible to configure so that the control timing data can be set as appropriate from the application side circuit.

[0066]

As described above, according to the present invention,
When the serial interface bus cable is not connected to the connection node of the physical layer circuit, there is an advantage that the clock request can be stopped, thereby preventing unnecessary power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a signal processing circuit according to the present invention applied to an IEEE 1394 serial interface.

FIG. 2 is a block diagram showing a specific configuration example of a link layer circuit according to the present invention.

FIG. 3 is a diagram showing main signals propagated on an interface bus between a link layer circuit and a physical layer circuit.

FIG. 4 is a circuit (Lin) for driving each signal shown in FIG. 3;
FIG. 7 is a diagram showing the contents of the data (k or PHY) and their contents.

FIG. 5 is a diagram illustrating the content of a control signal Ctl [0: 1] when the physical layer circuit is controlling.

FIG. 6 is a diagram showing the contents of a control signal Ctl [0: 1] when the link layer circuit is controlling.

FIG. 7 shows a request signal LReq and a control signal Ctl.
It is a figure which shows the example of a timing chart of [0: 1].

FIG. 8 is a diagram showing a conventional signal processing circuit applied to an IEEE 1394 serial interface.

[Explanation of symbols]

10: signal processing circuit, 11: physical layer circuit,
12: link layer circuit, 120: clock control circuit
(CLK CTL), 121 ... Link Core, 122
... Receiving DMA controller for asynchronous communication (A
RDMA), 123 ... DMA controller for transmission (AT
DMA), 124... DMA for receiving isochronous communication
Controller (IRDMA), 125: DMA controller for transmission (ITDMA), 126: FIFO (RFI) for reception of asynchronous communication and isochronous communication
FO), 127 ... FIFO for transmission of asynchronous communication
(ATFIFO), 128: FIFO for transmission of isochronous communication (ITFIFO), 129: control register,
130: Master bus interface circuit (MBIUMU
X), 131 ... Internal bus interface circuit (INTB
US), 132 ... PCI interface circuit (PCI
INF).

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // G06F 1/04 301

Claims (3)

[Claims] 1. PCI (Personal Computer Interface)
Connected between the bus and the serial interface bus, arbitrating data for both buses and setting a prescribed clock run signal to a first level,
A signal requesting a clock from a clock supply source on the side, and setting a clock run signal to a second level to notify that the clock supply source does not require a clock. A signal processing circuit having means for monitoring whether or not the connection is established and, when judging that the serial interface bus is not connected, setting the clock run signal to a second level and stopping a request for a clock; . 2. PCI (Personal Computer Interface)
Connected between the bus and the serial interface bus, arbitrating data for both buses and setting a prescribed clock run signal to a first level,
A signal requesting a clock from a clock supply source on the side, and setting a clock run signal to a second level to notify that the clock supply source does not require a clock. A physical layer circuit that can be connected and monitors whether or not the serial interface bus is connected, and generates a non-connection signal indicating that the serial interface bus is not connected when it is determined that the serial interface bus is not connected. A clock control for connecting the PCI bus, exchanging data with a physical layer circuit, and receiving the non-connection signal, setting the clock run signal to a second level and stopping a clock request; And a link layer circuit including the circuit. 3. The physical layer circuit has a specific control timing within a predetermined allowable range, sends out packet data to the serial interface bus, and the link layer circuit transmits the control timing data to the serial interface bus. A holding circuit that can be set, generates packet data by receiving data from the PCI bus, and transmits the generated packet data to the physical layer circuit at a timing based on control timing data set in the holding circuit; The signal processing circuit according to claim 2.