JP2002073181A - Operation guarantee voltage control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly integrate an integrated circuit and to guarantee the normal operation of an electronic circuit even when there is environmental fluctuation and the dispersion of device characteristics. SOLUTION: The operation timing of a logic circuit 2 or the like in a semiconductor integrated circuit 1 is deteriorated by the reduction of a power supply voltage Vout to be supplied and operation delay is increased. A delay deciding circuit 3 decides the delay quantity of the logic circuit 2 or the like, an output voltage control circuit 4 controls the output voltage Vout of an output voltage variable power supply part 5 corresponding to the decided result and when the delay quantity is great, the output voltage Vout is increased. By optimal feedback control based on the delay quantity of operation such as switching of the logic circuit or the like, an operation margin is suppressed to a minimum, operation guarantee is secured, a circuit capable of being highly integrated at much higher speed is provided and power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an operation assurance voltage control method in a semiconductor integrated circuit, and more particularly, to an operation assurance voltage control method capable of operating at an optimum power supply voltage.

[0002]

2. Description of the Related Art In recent years, the scale and speed of semiconductor integrated circuits such as LSIs and FPGAs have been increasing. However, the higher the operating speed and the higher the degree of integration of circuits, the more difficult the operation timing design becomes. It is becoming difficult to secure operation margins such as internal setup / hold timing. That is, the switching delay and wiring delay in the device vary due to the environment (temperature, voltage) in which the device is used and the variation in the characteristics of the device itself due to manufacturing. It's getting tougher.

FIG. 5 is a diagram showing a configuration of a conventional semiconductor integrated circuit. A conventional electronic circuit is roughly composed of a semiconductor integrated circuit 1, an in-device logic circuit 2, and a power supply voltage supply unit 3.

As shown in FIG. 5, a conventional semiconductor integrated circuit 1
In this case, the constant voltage Vout is constantly supplied from the power supply voltage supply unit 3, and the internal logic circuit 2 supplies the supply voltage Vout.
It works by. Here, regarding the power supply voltage, the logic circuit is designed so that the switching delay and the wiring delay in the device can be guaranteed to operate properly due to the environment (temperature, voltage) in which the device is used and the characteristic variation of the device itself due to manufacturing. 2 and the like are supplied with a voltage value at which a stable operation is performed.

[0005]

However, in the power supply configuration of the conventional semiconductor integrated circuit, the power supply voltage Vout output from the power supply voltage supply unit 3 is always supplied to the semiconductor integrated circuit 1 as a constant value as it is. When the delay time of the internal device of the semiconductor integrated circuit 1 changes due to a change in the environment in which the semiconductor integrated circuit operates, a change in temperature during operation, a variation in device characteristics, and the like, the semiconductor integrated circuit 1 The timing margin for normal operation of a logic circuit or the like is reduced, and in the worst case, a malfunction may occur. In addition, due to variations in manufacturing such as FPGA and timing changes due to process changes,
There was also a possibility that an operation failure occurred.

Therefore, in order to avoid such a malfunction, it is necessary to design a circuit by setting strict standards for various specification items so as to secure a timing margin for the maximum fluctuation. In an environment in which the circuit can operate normally, the circuit may supply an unnecessarily high voltage value.

(Object) It is an object of the present invention to provide an operation assurance voltage control method capable of supplying an optimum power supply voltage for guaranteeing a normal operation of an electronic circuit.

Another object of the present invention is to provide an operation assurance voltage control method capable of realizing higher integration of an integrated circuit and guaranteeing normal operation of an electronic circuit even if there are environmental fluctuations and variations in device characteristics. To provide.

[0009]

The operation assurance voltage control method of the present invention comprises a semiconductor integrated circuit (for example, 1 in FIG. 1) and an output voltage variable power supply voltage supply means for supplying a power supply voltage to the semiconductor integrated circuit. (For example, 5 in FIG. 1), delay determining means (for example, 3 in FIG. 1) for detecting an operation delay of an internal circuit (for example, 2 in FIG. 1) of the semiconductor integrated circuit, and an output of the delay determining means. Output voltage control means (for example, 4 in FIG. 1) for controlling the output voltage of the output voltage variable power supply voltage supply means so as to secure a desired timing margin based on the output voltage control means.
And characterized in that:

The delay determining means detects a delay amount of the internal circuit and outputs a result of comparison with a maximum delay amount at which the internal circuit can operate normally as a determination output, and the output control means responds to the determination output. The output voltage of the variable output voltage type power supply means is controlled to increase or decrease.

[0011] In the above invention, the delay determination means includes:
The delay amount detected from the internal circuit is compared with the maximum delay amount, and if the delay amount is larger than the maximum delay amount,
And outputs a second logic level when the delay amount is smaller than the maximum delay amount. The output control means outputs the second logic level when the output of the delay determination means is the first logic level. Increasing the output voltage of the output voltage variable power supply means, and fixing the output voltage of the output voltage variable power supply means in the case of the second logic level, or The means compares a delay amount detected from an internal circuit with the maximum delay amount, and outputs a first logical level when the delay amount is larger than the maximum delay amount, and the delay amount is smaller than the maximum delay amount. Outputting the second logic level in the case,
When the output of the delay determination means is at the first logic level, the output voltage of the output voltage variable power supply voltage supply means is increased, and when the output is at the second logic level, the output voltage variable power supply voltage supply means is increased. Is characterized by lowering the output voltage.

In any one of the above inventions, the internal circuit is a logic circuit, and the delay amount detected by the delay determination means is a delay amount of a signal having a maximum number of logic stages of the logic circuit.

(Operation) In general, the operation timing of a logic circuit or the like in a semiconductor integrated circuit is degraded due to a decrease in supplied power supply voltage, and the operation delay increases. Therefore, the power supply voltage of the semiconductor integrated circuit is optimally feedback-controlled based on the amount of operation delay, such as switching inside the circuit, thereby securing a minimum timing margin and minimizing the operation margin.
An operation is guaranteed, and a circuit that can be integrated at a higher speed and with higher integration is realized. In addition, the supply of a power supply voltage capable of normal operation avoids the occurrence of operation failure and reduces power consumption.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the operation assurance voltage control system of the present invention will be described in detail with reference to the drawings. (Description of Configuration) FIG. 1 is a diagram showing a circuit realization configuration of an embodiment of an operation assurance voltage control method according to the present invention.

This embodiment comprises a semiconductor integrated circuit 1, an in-device logic circuit 2, an in-device delay determination circuit 3, an output voltage control circuit 4, and an output voltage variable power supply voltage supply unit 5.

The present embodiment is different from the conventional circuit configuration in that the device of the semiconductor integrated circuit 1 includes the delay determination circuit 3 and that the output from the delay determination circuit 3 varies the output voltage. In that an output voltage control circuit 4 for controlling the output voltage Vout of the power supply voltage supply unit 5 is provided, and that an output voltage variable power supply voltage supply unit 5 for varying the output voltage is provided. is there.

(Explanation of Operation) The delay determination circuit 3 determines the maximum delay of a device in which the logic circuit 2 can operate normally based on the maximum number of logic stages in the logic circuit 2. If the operation is not possible, an "ON" level is output. For example, the delay determination circuit 3 detects a delay amount of a signal having the maximum number of logic stages between flip-flops in a logic circuit as a voltage value, and detects the detected voltage value and a reference voltage value corresponding to the maximum delay. Operable or non-operable by voltage comparison using the above comparator, and the above-described "ON" and "OFF" level control signals can be output.

The output voltage control circuit 4 controls the output voltage variable power supply voltage supply unit 5 so as to increase the output voltage Vout when the input is at the “ON” level based on the delay determination result from the delay determination circuit 3. At the time of inputting the “OFF” level, a method of controlling the output voltage variable power supply unit 5 so that the output voltage Vout is fixed as it is can be adopted.

FIG. 2 is a diagram showing an example of an operation flow in the present embodiment. The operation of the present embodiment will be described in detail below with reference to FIG. (1) First, an output voltage variable power supply voltage supply unit 5
Outputs a voltage that is low enough that the logic circuit 2 cannot operate normally due to device delay (S1). (2) At this time, the delay determination circuit 3 determines the delay amount, determines that the delay is such that the logic circuit 2 cannot operate normally, and outputs an “ON” level (S2). (3) The output voltage control circuit 4 detects the input at the “ON” level and controls the output voltage variable power supply voltage supply unit 5 to increase the output voltage Vout (S5). (4) The output voltage variable power supply voltage supply unit 5 increases the output voltage Vout under the control of the output voltage control circuit 4 (S6). (5) The above-described operations (2) to (4) are repeated, and when the voltage reaches a voltage that is a delay amount at which the logic circuit 2 can operate normally, the delay determination circuit 3 outputs an “OFF” level ( S2). (6) The output voltage control circuit 4 detects the output of the level from the delay determination circuit 3 and outputs the output voltage variable power supply voltage
, The output voltage Vout is kept at the current level (S4). (7) The output voltage variable power supply voltage supply unit 5 stops changing the output voltage Vout under the control of the output voltage control circuit 4 (S4).

The control based on the operation flow described above is suitable when the power of the semiconductor integrated circuit 5 is turned on or when the circuit operation starts, and the output voltage Vout is set as an optimum value that can be operated when the change stops. You.

(Other Embodiments) In the operation of the embodiment of the present invention, in addition to the above-described operation flow, a voltage value corresponding to a delay amount of a logic circuit and a reference value corresponding to an operable delay amount are used. By controlling the rise and fall of the output voltage of the variable output voltage power supply unit 5 by the control signals of the "ON" and "OFF" levels of the comparison result, a stable operation can be performed in a range of an expected environmental change or the like. Minimum output voltage Vou
It is possible to always control to supply t.

FIG. 3 is a diagram showing an operation flow for performing such control. The delay determination circuit 3 detects the delay amount of the logic circuit (S10), generates a voltage value proportional to the delay amount, compares the generated voltage value with a reference voltage value corresponding to the optimum delay amount (S20), and detects the delay value. If the voltage value proportional to the delay amount is larger than the reference voltage value, the output voltage control circuit 4
An N ″ level control signal is output (S50), and the output voltage of the output voltage variable power supply voltage supply unit 5 is increased (S6).
0). If the voltage value that is substantially proportional to the detection delay amount is smaller than the reference voltage value, the output voltage control circuit 4 outputs “OF”.
An F ″ level control signal is output (S30), and the output voltage of the output voltage variable power supply voltage supply unit 5 is decreased (S4).
0).

Further, in the embodiment shown in FIG.
Output voltage control circuit 4 and output voltage variable power supply voltage supply unit 5
Has been described outside of the semiconductor integrated circuit 1.
Output voltage control circuit 4 and output voltage variable power supply voltage supply unit 5
Can be provided in the same semiconductor integrated circuit 1.

FIG. 4 is a diagram showing such an embodiment of the present invention. The output voltage control circuit 4 and the output voltage variable power supply voltage supply unit 5 are configured in the semiconductor integrated circuit 1 together with the logic circuit 2 and the delay determination circuit 3 to supply an external power voltage to the output voltage variable power supply voltage in the semiconductor integrated circuit 1. It is configured to supply to the logic circuit 2 via the section 5.

The delay determination circuit 3 in the above embodiment
Among a plurality of logic circuits in the semiconductor integrated circuit 1,
The configuration of determining whether operation is possible or not based on a delay amount in a logic circuit portion having the strictest timing margin or a part thereof can suppress the scale of the determination circuit. Further, it is possible to divide an enormous logic circuit in the semiconductor integrated circuit into a plurality of blocks, obtain an average value of delay amounts of each block or a part of the blocks, and determine the average value by the delay determination circuit. is there.

[0026]

In the present invention, since the power supply voltage Vcc for operating the semiconductor integrated circuit is optimally feedback-controlled, the minimum timing margin for allowing the internal circuit to operate normally is provided. As a result, the following effects can be obtained. (1) First, the timing margin is minimized at the time of logic circuit design by setting the operation margin in consideration of the operation margin due to the fluctuation of the operation environment, the manufacturing variation of the device, and the process fluctuation to the optimum delay value by controlling the power supply voltage. As a result, a higher-speed and highly integrated circuit can be realized. (2) Further, since a voltage for normal operation is supplied under each operating environment, it is possible to reduce the probability of causing an operation failure in a field. (3) Further, since operation is performed at an optimum power supply voltage at which normal operation is possible, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an operation flow of the present invention.

FIG. 3 is a diagram showing another operation flow of the present invention.

FIG. 4 is a diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing a power supply configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Logic circuit 3 Delay determination circuit 4 Output voltage control circuit 5 Output voltage variable power supply

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Koji Nishi 1-4-4, Mita, Minato-ku, Tokyo NEC Communication Systems Co., Ltd. F term (reference) 5H410 BB01 BB04 CC02 DD02 EA02 EB14 EB15 EB37 FF10 FF11 FF13 FF16 FF26 5J056 AA39 BB38 BB39 BB40 BB60 CC05 GG06

Claims (5)

[Claims] A semiconductor integrated circuit; an output voltage variable power supply for supplying a power supply voltage to the semiconductor integrated circuit; a delay determining means for detecting an operation delay of an internal circuit of the semiconductor integrated circuit; And an output voltage control means for controlling an output voltage of the output voltage variable power supply voltage supply means so as to secure a desired timing margin based on an output of the means. 2. The delay judging means detects a delay amount of an internal circuit and makes a result of comparison with a maximum delay amount at which the internal circuit can operate normally a judgment output. The output control means responds to the judgment output. 2. The operation assurance voltage control method according to claim 1, wherein the output voltage of said variable output voltage power supply voltage supply means is controlled to increase or decrease. 3. The delay determination means compares a delay amount detected from an internal circuit with the maximum delay amount, and outputs a first logic level when the delay amount is larger than the maximum delay amount, and outputs the first logic level. If the amount is less than the maximum delay amount, the second
The output control means increases the output voltage of the output voltage variable power supply voltage supply means when the output of the delay determination means is the first logic level,
3. The operation-guaranteed voltage control method according to claim 2, wherein the output voltage of said output voltage variable power supply voltage supply means is fixed in the case of said second logic level. 4. The delay determination means compares a delay amount detected from an internal circuit with the maximum delay amount, and outputs a first logical level when the delay amount is greater than the maximum delay amount, and outputs the first logic level. If the amount is less than the maximum delay amount, the second
The output control means increases the output voltage of the output voltage variable power supply voltage supply means when the output of the delay determination means is the first logic level,
3. The operation-guaranteed voltage control method according to claim 2, wherein the output voltage of said output voltage variable power supply voltage supply means is decreased in the case of said second logic level. 5. The device according to claim 1, wherein the internal circuit is a logic circuit, and the delay amount detected by the delay determination unit is a delay amount of a signal having a maximum number of logic stages of the logic circuit. The operation assurance voltage control method according to 3 or 4.