JP2002064150A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a gate tunnel current during standby required for a low power consumption. SOLUTION: As a transistor to become an on-state during standby, transistors (PQa, PQc, NQb and NQa) each having a large gate tunnel barrier are used. As a transistor to become an off-state during standby, a thin MIS transistor of a gate insulating film is used. As a hierarchical power source constitution, main and sub-power source lines (30, 32) and main and sub-ground lines (34, 36) are isolated during standby.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including an insulated gate field effect transistor (hereinafter, referred to as MIS transistor) as a component, and more particularly, to a miniaturized CMOS transistor (P and N channel MIS transistor). To a structure for reducing power consumption in a semiconductor device having the same. More specifically,
The present invention relates to a configuration for suppressing a gate tunnel current of a miniaturized MIS transistor.

[0002]

2. Description of the Related Art When the size of a MIS transistor in a CMOS semiconductor device is miniaturized, an operating power supply voltage is reduced in order to secure transistor reliability and reduce power consumption. When the size of the MIS transistor is reduced in accordance with the decrease in the operating power supply voltage, each parameter value of the transistor is reduced according to a certain scaling rule. According to this scaling rule, it is necessary to reduce the thickness Tox of the gate insulating film of the MIS transistor and to reduce the absolute value Vth of the threshold voltage. However, the absolute value of the threshold voltage cannot be reduced according to the scaling rule. The threshold voltage is defined as a gate-source voltage that causes a predetermined drain current under a predetermined drain voltage application condition.
When the absolute value Vth of the threshold voltage decreases,
Even when the gate-source voltage Vgs becomes 0 V, a weak inversion layer is formed in the channel region, and a subthreshold leak current (hereinafter, referred to as an off-leak current) flows through the inversion layer. This off-leak current increases as the absolute value of the threshold voltage decreases. Therefore, the MIS
In a standby cycle in which the transistor is off, a problem arises in that an off-leak current increases and a standby current increases. Particularly when such a semiconductor device is used in a battery-driven device such as a portable device,
From the viewpoint of battery life, reducing the off-leak current is a major issue.

If the absolute value Vth of the threshold voltage is increased in order to reduce the off-leak current, the effect of reducing the operating power supply voltage cannot be obtained, and high-speed operation cannot be guaranteed. Therefore, in order to reduce the off-leak current in the standby cycle and to guarantee the high-speed operation, the MT-
A CMOS (multi-threshold CMOS) configuration has been proposed.

FIG. 104 is a diagram showing an example of the configuration of a conventional MT-CMOS circuit. FIG. 104 shows five stages of cascaded inverter circuits IV0 to IV4 as an example. For these inverter circuits IV0-IV4, main power supply line MVL coupled to the power supply node, sub power supply line SVL coupled to main power supply line MVL via switching transistor SWP, and main ground connected to the ground node Line MGL and sub-ground line SGL coupled to main ground line MGL via switching transistor SWN are arranged.

Each of these inverter circuits IV0-IV4 has a P-channel MIS transistor P0-P4,
Inverter circuits IV0-IV4 each include N-channel MIS transistors N0-N4, and each have a CMOS inverter configuration. This MT-CMOS circuit has a standby cycle in a standby state and an active cycle in which an actual input signal changes. The input signal IN in the standby cycle is fixed at L level. Switching transistors SWP and SWN are turned off in the standby cycle in response to control signals / φ and φ, respectively. Switching transistor SW
P and SWN have relatively large (medium) threshold voltage absolute values M-Vth. On the other hand, MIS transistors P0-P4 and N0-N4 of inverter circuits IV0-IV4 are L-Vth transistors having a small absolute value of the threshold voltage.

[0006] Input signal I during standby cycle
In response to the logic level of N, the source of the MIS transistor that is turned on during the standby cycle is
VL and main ground line MGL. That is, the sources of MIS transistors P0, P2 and P4 are connected to main power supply line MVL, and the sources of MIS transistors N1 and N3 are connected to main ground line MGL. On the other hand, MI which is turned off during the standby cycle
The source of the S transistor is connected to the sub power supply line SVL and the sub ground line SGL. That is, the sources of MIS transistors P1 and P3 are connected to sub power supply line SVL, and the sources of MIS transistors N0, N2 and N4 are connected to sub ground line SGL. Next, FIG.
The operation of the MT-CMOS circuit shown in FIG. 105 will be described with reference to a signal waveform diagram shown in FIG.

In the standby cycle, input signal IN is at L level, and control signals φ and / φ are at L level and H level, respectively. In this state, switching transistors SWP and SWN
Is turned off. Switching transistor SWP
Is an M-Vth transistor, and the off-state leakage current in the off state is sufficiently small.

In inverter circuits IV0-IV4,
MIS transistors P0, P2, and P4 are on, and no sub-threshold leak (off-leak) current is generated. On the other hand, MIS transistors P1 and P3 are turned off, causing off-leakage current from sub power supply line SVL. The off-leak current flowing through these MIS transistors P1 and P3
It flows to main ground line MGL via S transistors N1 and N3, respectively. However, the off-leak current flowing through MIS transistors P1 and P3 is determined by the off-leak current flowing through switching transistor SWP. Therefore, this sub power supply line S
The voltage level of VL is the switching transistor SWP
And the sum of the off-leak current flowing through the MIS transistors P1 and P3 is balanced at a voltage level. The voltage level of sub power supply line SVL is lower than power supply voltage VCC, and MIS transistors P1 and P3 have their gate-source voltages in a reverse-biased state, are turned off more strongly, and have a sufficient off-leakage current. Can be reduced.

Similarly, an off-leak current also flows through MIS transistors N0, N2 and N4.
The off-leak current of IS transistors N0, N2 and N4 is determined by the off-leak current flowing through switching transistor SWN. The switching transistor SWN is an M-Vth transistor, and its off-leak current is sufficiently small. Accordingly, the off-leak current of these MIS transistors N0, N2, and N4 can be sufficiently suppressed.

At this time, the voltage level of sub-ground line SGL is a voltage level at which the sum of the off-leak currents flowing through MIS transistors N0, N2 and N4 and the off-leak current flowing through switching transistor SWN are balanced, and is higher than ground voltage GND. Voltage level. Therefore, at this time, the MIS transistors N0, N2
N4 and N4 are in a reverse bias state between the gate and the source, are in a deeper off state, and the off leak current is sufficiently suppressed.

In an active cycle in which an operation is actually performed, control signals φ and / φ are set to H level and L level, respectively, and switching transistor S
WP and SWN are turned on, sub power supply line SVL is connected to main power supply line MVL, and sub ground line SGL is connected to main ground line MGL. Therefore, these inverter circuits IV0 to IV4 include the L-Vth transistor as a component, and change at a high speed according to the input signal IN.

As shown in FIG. 104, by making the impedance of the power supply line different between the standby cycle and the active cycle, the off-leak current during the standby cycle can be reduced even when the L-Vth transistor is used as a component. It is possible to realize a CMOS circuit that can be sufficiently suppressed, can guarantee high-speed operation in an active cycle, and operates with low power consumption and at high speed.

[0013]

Various parameters such as the size of the MIS transistor are reduced according to a certain scaling rule. In this scaling law, MI
The gate length of the S transistor and the thickness of the gate insulating film are:
It is assumed that the images are reduced at the same reduction ratio. For example, M having a gate length of 0.25 μm (micrometer)
The thickness of the gate insulating film of an IS transistor is generally
The thickness of the gate insulating film of the MIS transistor having a gate length of about 0.1 μm is about 2.0 to 2.5 nm. As described above, when the gate insulating film is thinned with a decrease in the operating power supply voltage, for example, when the gate insulating film is thinned to about 3 nm according to the condition that the power supply voltage is 1.5 V or less,
A tunnel current flows through the gate insulating film of the MIS transistor in the on-state, which causes a problem that the power supply current in the transistor in the on-state increases.

FIGS. 106 (A)-(C) schematically show the energy bands of the MIS structure. Fig. 106
In (A)-(C), a metal band is shown as an example of a gate energy band. Normally, in the MIS structure, the gate is made of impurity-doped polysilicon and has semiconductor properties. However, metal is used for the gate to simplify the description. The semiconductor substrate region is a P-type substrate.

Consider a state in which a negative voltage is applied to the gate as shown in FIG. In this case, the holes contained in the P-type substrate are attracted toward the interface with the insulating film, and the energy band of the P-type substrate is bent upward at the interface between the insulating film and the P-type substrate, and valence electrons are generated. Obi Ev,
The conduction band Ec approaches the Fermi level EF, and also bends upward near this interface. When the negative voltage is applied, the Fermi level EF of the gate (corresponding to the conduction band Ec in the case of a polysilicon gate) also increases. In this state, the density of majority carriers (holes) is higher at the interface than at the inside, and this state is called an accumulation state. In this state, the conductor Ec is bent upward and the barrier against electrons is high, so that no current is tunneled through the gate insulating film.

On the other hand, as shown in FIG. 106 (B), when a low positive voltage is applied to the gate, the Fermi level (conduction band) of the gate decreases, and accordingly, the conduction level also increases in the P-type substrate region. The band Ec and the valence band Ev are bent downward at the interface with the insulating film. In this state, holes are rejected from the interface of the insulating film, and a majority carrier deficiency state occurs. The Fermi level EF at the interface is located almost in the center of the forbidden band. Called. In this depletion state, no carrier exists at the interface, and no tunnel current occurs.

As shown in FIG. 106 (C), when a larger positive voltage is applied, the Fermi level EF of the gate further decreases, and the band bending near the interface further increases. In the vicinity, the Fermi level EF of this gate becomes higher than the intermediate value of the energy gap Eg, and electrons serving as minority carriers are accumulated. This state is called an inverted state because the conduction type of the interface is reversed from that inside. This state is MIS
In a transistor, this corresponds to a state where a channel is formed. At this time, when the thickness δ of the gate insulating film is, for example, 3 nm, electrons that are minority carriers flow to the gate due to a tunneling phenomenon. That is, the MIS transistor in which the channel is formed, that is, M
In the IS transistor, a tunnel current flows from the channel region directly to the gate. This is called (direct) gate tunnel current. The same applies to the case where the substrate region is N-type, except that the polarity of the voltage applied to the gate and the direction in which the energy band bends are reversed.

That is, when the thickness of the gate insulating film is reduced to, for example, 3 nm in the MIS transistor, a gate tunnel current flows directly from the channel region to the gate. That is, MT-C as shown in FIG.
In a MOS circuit, a tunnel current flows from its channel region to a gate in a MIS transistor which is in an ON state in a standby cycle, and a through current flows from a power supply node to a ground node, thereby increasing current consumption in a standby cycle. The problem arises.

FIG. 107 shows the MT-C shown in FIG.
FIG. 3 is a diagram showing a path of a tunnel current in a standby cycle of a MOS circuit.

In FIG. 107, an inverter circuit IV
1 shows the configuration of the parts 1 and IV2. Inverter circuit I
In V1, MIS transistor N1 is connected to main ground line M
GL has its source and back gate connected, and MI
The source of the S transistor P1 is connected to a sub power supply line (not shown). In the inverter circuit IV2,
The MIS transistor P2 has a back gate and a source connected to the main power supply line MVL.
Has a source connected to a sub-ground line (not shown). In the standby cycle, the inverter circuit IV1
Is supplied with an H-level signal. Therefore, the output signal of inverter circuit IV1 is in a standby cycle.
At the L level of the ground voltage GND level, MIS transistor P2 is turned on in inverter circuit IV2. In the MIS transistor P2, a tunneling current It flows from the substrate region to the gate,
It flows to the main ground line MGL via the S transistor N1.
That is, as shown by the broken line in FIG.
Through current flows from the main power supply line MVL to the main ground line MGL due to the gate tunnel current of the transistor P2.

FIG. 108 shows the MT-CMO shown in FIG.
FIG. 4 is a diagram showing a configuration of a portion of an inverter circuit IV2 and IV3 of the S circuit. During the standby cycle,
L level signal is applied to inverter circuit IV2. The sources of MIS transistors P2 and N3 are connected to main power supply line MVL and main ground line MGL, respectively. The sources of MIS transistors N2 and P3 are connected to a sub-ground line and a sub-power supply line (not shown). In this state, during the standby cycle,
MIS transistor P2 is on, and supplies a current from main power supply line MVL to the gate of MIS transistor N3.

MIS transistor N3 is on, so that a gate tunnel current It flows in MIS transistor N3, and the gate tunnel current flows to main ground line MGL (via a source region and a back gate region). When the back gate of the MIS transistor N3 is biased to a voltage level different from the ground voltage GND, the gate tunnel current It of the MIS transistor N3 flows from this channel region via the source region. Therefore, even in this case,
A through current due to the gate tunnel current It flows from the main power supply line MVL to the main ground line MGL.

The gate tunnel current becomes substantially equal to the off-leak current when the thickness of the gate oxide film is about 3 nm or less, and becomes larger than the off-leak current when the gate oxide film is thinner. Therefore, when the operating power supply voltage is lowered and the gate insulating film is thinned in accordance with the scaling rule, the gate tunnel current becomes a value that cannot be ignored, and the problem that the current consumption in the standby cycle increases. .

The gate tunnel current J substantially satisfies the relationship represented by the following equation. J ~ E ・ exp [-Tox ・ A ・
√ψ] Here, ψ indicates the height of the barrier at the gate insulating film interface, and is approximately expressed by the difference between the Fermi level and the surface potential φs at the interface. A is a constant determined by the impurity concentration (effective mass of electrons) of the semiconductor substrate in the channel region, and E is an electric field applied to the gate insulating film. The barrier height ψ is determined by the dielectric constant εi of the gate insulating film.
And a function of the film thickness Tox of the gate insulating film. Therefore, for example, when a gate insulating film is formed of a silicon oxide film and a tunnel current is generated at 3 nm, the gate tunnel current is the same in a gate insulating film having the same barrier height as the silicon oxide film having a thickness of 3 nm. Occurs. As the gate insulating film, there is a silicon nitride oxide film in addition to the silicon oxide film.

Therefore, the finer M
When an IS transistor is included as a constituent element, in the standby state, the gate tunnel current of the MIS transistor becomes substantially equal to or larger than the off-leakage current, and the current consumption in the standby cycle cannot be reduced. Occurs.

An object of the present invention is to provide a semiconductor device suitable for high integration, which can sufficiently suppress current consumption in a standby state.

Another object of the present invention is to provide a semiconductor device capable of sufficiently suppressing a gate tunnel current of a MIS transistor in a standby state.

[0028]

A semiconductor device according to the present invention includes a first power supply node, a logic gate receiving a voltage on a first power supply line as one operation power supply voltage and performing a predetermined operation, and a first power supply node. And a first switching transistor connected between the power supply node and the first power supply line and selectively conducting in response to an operation mode instruction signal instructing the operation mode of the logic gate. The logic gate includes a MIS transistor having a first gate tunnel barrier as a component, and the first switching transistor has a gate tunnel barrier larger than the gate tunnel barrier of the MIS transistor of the logic gate.

Preferably, the first gate tunnel barrier has a size equal to or smaller than a gate tunnel barrier provided by a silicon oxide film having a thickness of 3 nanometers.

Further, the first gate tunnel barrier is:
It is provided by an insulating film having a thickness of 3 nanometers.

According to another aspect of the present invention, a semiconductor device includes: a first MIS transistor connected between a first power supply node and a first output node and receiving an input signal at a gate; A second MIS transistor connected between the node and a second power supply node and receiving an input signal at its gate; The first MIS transistor is turned on in accordance with this input signal during a standby cycle and has a first gate tunnel barrier. Second MI
The S transistor is turned off according to the input signal in the standby cycle and has a gate tunnel barrier smaller than the first gate tunnel barrier.

Preferably, the gate insulating film of the first MIS transistor is thicker than the second MIS transistor.

Preferably, the semiconductor device further includes third and fourth MIS transistors connected between the first power supply node and the second power supply node and receiving the signal of the first output node at respective gates. . The third MIS transistor is turned off during the standby cycle, and
The fourth MIS transistor is turned on during the standby cycle and has the first gate tunnel barrier.

A semiconductor device according to another aspect of the present invention includes a first MIS transistor connected between a first power supply node and a first output node and receiving an input signal at a gate; A second M connected between the output node and the second power supply node and receiving an input signal at its gate;
An IS transistor and a control circuit for reducing the amount of gate tunnel current leakage of the first and second MIS transistors during the standby cycle as compared with the active cycle.

This control circuit preferably includes a circuit for making the back gate bias of the first and second MIS transistors deeper in the standby cycle than in the active cycle.

Alternatively, the control circuit includes a circuit for switching the voltage polarity of the first and second power supply nodes between a standby cycle and an active cycle.

Alternatively, the first and second M
The IS transistor has a thickness of 3 nm as a gate insulating film.
An insulating film having a gate tunnel barrier equal to or greater than the gate tunnel barrier provided by the silicon oxide film.

Alternatively, preferably, the control circuit supplies first and second power supply voltages used during normal operation of the first and second power supply nodes during an active cycle, and supplies these voltages during a standby cycle. A circuit for applying third and fourth voltages having absolute values smaller and larger than the first and second power supply voltages, respectively;

A semiconductor device according to still another aspect of the present invention has a first gate tunnel barrier connected between a first power supply node and a first output node and having a gate receiving an input signal at a gate. An MIS transistor, a second MIS transistor connected between the first output node and the sub-power supply node and receiving an input signal at the gate and conducting complementarily with the first MIS transistor; A first switching transistor connected between the power supply node and the second power supply node and selectively conducting in response to an operation cycle instruction signal. The second MIS transistor has a second gate tunnel barrier smaller than the first gate tunnel barrier.

The first switching transistor is preferably turned off during a standby cycle, and
The absolute value of the threshold voltage is smaller than that of the MIS transistor described above, and the second MIS transistor is turned off during the standby cycle.

Preferably, the first MIS transistor has a larger gate tunnel barrier than a gate oxide barrier provided by a silicon oxide film having a thickness of 3.0 nm, and the second MIS transistor has a larger thickness than the first MIS transistor. A gate insulating film having a gate tunnel barrier smaller than that provided by the MIS transistor;

Preferably, the first switching transistor and the first MIS transistor have different back gate potentials.

A semiconductor device according to another aspect has a first switching transistor connected between a power supply node and a power supply line, selectively turned on in response to an operation cycle instruction signal, and a voltage of the power supply line. On the other hand, a gate circuit which receives as an operating power supply voltage and performs predetermined processing, a replica circuit including an element obtained by proportionally reducing the gate circuit and the first switching transistor, and a power supply line which outputs an output voltage of the replica circuit in accordance with an operation cycle instruction signal And a transmission circuit for transmitting the data to the communication device. The reduced gate circuit of the replica circuit receives the voltage of the output node as one operating power supply voltage, and the reduced transistor of the first switching transistor supplies a voltage to the output node from the power supply node.

The transmission circuit preferably includes a comparison circuit which compares the voltage of the output node of the replica circuit with the voltage of the power supply line during operation, and drives the power supply line according to the comparison result.

A semiconductor device according to another aspect of the present invention includes a first switching transistor connected between a first power supply node and a first power supply line and selectively conducting in response to an operation cycle instruction signal. A first gate circuit receiving the voltage of the first power supply line as one operation power supply voltage;
A second switching transistor connected between the power supply node and the second power supply line and selectively conducting in response to an operation cycle instruction signal, and receiving the voltage of the second power supply line as one operation power supply voltage And an operating second gate circuit. These first and second gate circuits include an MIS transistor as a component and have the same configuration.

Preferably, the ratio between the transistor size of the first gate circuit and the transistor size of the first switching transistor is equal to the ratio between the transistor size of the second gate circuit and the size of the second switching transistor. Is set to

The first gate circuit is preferably connected to a first power supply line, and receives a first input signal at its gate.
A first MIS transistor having a thickness of the gate insulating film and a second gate insulating film which is connected to the third power supply line, receives the first input signal at the gate, and is thicker than the first gate insulating film. A first unit gate circuit having a second MIS transistor having a film thickness is included. Preferably, the second gate circuit is connected to a second power supply line, receives a second input signal at its gate, and has a third MIS transistor having a first gate insulating film thickness and a fourth gate circuit. A second unit gate circuit having a fourth MIS transistor having a source connected to the power supply line, receiving a second input signal at the gate, and further having a second gate insulating film thickness is included.

Preferably, a third gate circuit is cascaded with the first gate circuit, receives the voltage of the first power supply node and the third power supply line as an operation power supply voltage, and receives the output signal of the first gate circuit. A fourth gate circuit cascaded with the second gate circuit and receiving the voltage of the second power supply node and the fourth power supply line as a row operation power supply voltage;
A fourth switching transistor connected between the third power supply line and the third power supply node and turned on / off in phase with the first switching transistor in response to an operation cycle instruction signal; The ratio of the size of the third switching transistor to the size of the MOS transistor connected to the third power supply line of the third gate circuit depends on the size of the fourth switching transistor and the size of the fourth power supply line of the fourth gate circuit. It is equal to the size ratio of the MOS transistors to be connected.

The transistor connected to the first power supply node of the third gate circuit has a second gate insulating film thickness, and the transistor connected to the third power supply line has the second thickness. The first gate insulating film has a larger thickness.
The transistor connected to the second power supply node of the fourth gate circuit has a second gate insulating film thickness,
The transistor connected to the power supply line has a first gate insulating film thickness.

Preferably, a gate circuit having a size ratio equal to the ratio of the size of the transistor connected to the first or second power supply line of the first or second gate circuit to the size of the first or second switching transistor And a transmission circuit for transmitting a voltage corresponding to the output voltage of the replica circuit to the first and second power supply lines. The replica circuit includes a replica gate circuit and a replica switching transistor corresponding to the gate circuit and the switching transistor.

Preferably, the transmission circuit compares an operation power supply voltage output from the replica circuit with a voltage at the output node, adjusts the voltage at the output node according to the comparison result, and responds to the operation cycle instruction signal. And a switching circuit for coupling the output node to the first and second power supply lines.

Preferably, a switching circuit is further provided for coupling the first and second power supply lines in response to an operation cycle instruction signal.

The third or fourth gate circuit of the third
Alternatively, a replica gate circuit having a size ratio equal to the ratio of the total size of the transistors connected to the fourth power supply line to the size of the third or fourth switching transistor and a replica circuit including the replica transistor, and a response to an operation cycle instruction signal Preferably, a transmission circuit for transmitting a voltage corresponding to the operating power supply voltage generated by the replica circuit to the third and fourth power supply lines to the third and fourth power supply lines, respectively, is provided.

Preferably, the transmission circuit compares an operation power supply voltage output from the replica circuit with a voltage at the output node and adjusts the voltage at the output node according to the comparison result, and responds to an operation cycle instruction signal. And a switching circuit for coupling the output node to the third and fourth power supply lines.

Preferably, there is further provided a switching circuit for coupling the third and fourth power supply lines in response to an operation cycle instruction signal.

A semiconductor device according to another aspect of the present invention comprises:
SOI (silicon on insulator) structure first
A gate circuit including a first transistor and a second transistor, for performing predetermined processing on an input signal and outputting the same, and a bias voltage application circuit for applying a bias voltage to the body regions of the first and second transistors of the gate circuit. Prepare. The logic level of the input signal applied to the gate circuit is predetermined in the standby cycle,
Has a gate insulating film having a thickness of 3 nanometers or less. The bias voltage application circuit makes the bias of the body region of at least the transistor that is in the off state among the first and second transistors in the standby cycle deeper than in the active cycle.

A semiconductor device according to another aspect of the present invention has first and second MIS transistors having an SOI (silicon-on-insulator) structure, performs predetermined logic processing on an input signal, and outputs the processed signal. A gate circuit; and a bias voltage applying circuit for applying a bias voltage to the body regions of the first and second MIS transistors. This bias voltage applying circuit makes the bias in the body regions of the first and second transistors deeper than the bias in the active cycle both in the standby cycle.

A plurality of logic gate circuits cascaded to the gate circuit are preferably further provided. Each of the plurality of logic gate circuits includes third and fourth MIS transistors having an SOI structure. These third and fourth MIS transistors are connected between the first and second power supply nodes, and receive at respective gates the output signal of the preceding circuit. The bias voltage applying circuit applies a bias to the body regions of the third and fourth MIS transistors of the plurality of logic gate circuits to the first and second MIS transistors.
Control is performed in common with the bias of the body region of the transistor.

Further, a semiconductor device according to another aspect includes a first device.
A first MIS transistor connected between a power supply node and an output node and receiving an input signal at a gate; and a second MIS transistor connected between the output node and the second power supply node and receiving an input signal at a gate. An MIS transistor is provided. The input signal has a predetermined logic level in the standby cycle, the first MIS transistor is turned on according to the input signal in the standby cycle, and is formed of a buried channel MIS transistor.

The first and second MIS transistors are:
Preferably, the thicknesses of the gate insulating films are made equal.

[0061] The second power supply node is preferably coupled to the main power supply voltage supply line via a switching transistor which is turned off during a standby cycle.

The switching transistor is preferably
It is a buried channel type MIS transistor.

A semiconductor device according to another aspect is a semiconductor device according to the first aspect.
First MIS transistor connected between a power supply node and an output node and receiving an input signal at its gate, and a second MIS transistor connected between the output node and the second power supply node and receiving an input signal at its gate A transistor is provided.
The logic level of the input signal in the standby cycle is predetermined, and the first MIS transistor is turned on in response to the input signal in the standby cycle and is a gate depletion MIS transistor.

The first and second MIS transistors are:
Preferably, the thicknesses of the gate insulating films are made equal.

Preferably, the second power supply node is coupled to the main power supply voltage supply line via a switching transistor which is turned off in a standby cycle.

Preferably, the switching transistor is a gate depletion type MIS transistor.

A semiconductor device according to another aspect includes a latch circuit for latching a given signal, and a gate circuit for performing a predetermined process on a latch output signal of the latch circuit. The latch circuit is formed of a MIS transistor having a first gate tunnel barrier, and the gate circuit is formed of a MIS transistor having a gate tunnel barrier smaller than the first gate tunnel barrier.

Preferably, the transistor of the gate circuit has a gate insulating film for realizing a gate tunnel barrier equal to or smaller than a silicon oxide film having a thickness of 3 nm.

A semiconductor device according to another aspect has a first latch circuit for latching a given signal in an active cycle and a second latch circuit for latching a given signal in a standby cycle. Transferring the latch signal of the first latch circuit to the second latch circuit in response to the transition of the operation cycle instruction signal from the active cycle instruction to the standby cycle instruction, and changing the operation cycle instruction signal from the standby cycle instruction to the active cycle instruction. A transfer circuit for transferring a latch signal of the second latch circuit to the first latch circuit in response to the shift to the instruction; The first latch circuit has a first gate tunnel barrier, and the second latch circuit has a larger gate tunnel barrier than the first gate tunnel barrier.

Preferably, the transfer circuit continuously transfers the latch signal of the first latch circuit to the second latch circuit while the operation cycle instruction signal indicates an active cycle.

Preferably, the transfer circuit is activated when an operation is performed on the first latch circuit.
The first latch circuit is coupled to the pipeline stage, and the operation cycle instruction signal changes from an active cycle to a standby cycle in a cycle next to the cycle in which the operation of the first latch circuit is performed, and In the cycle, the transfer of the latch signal is performed from the first latch circuit to the second latch circuit via the transfer circuit.

A semiconductor device according to still another aspect includes a precharge transistor for precharging a precharge node to a predetermined voltage level in response to activation of a precharge instruction signal, and is coupled to the precharge node. And a gate circuit that enters a standby state when the precharge instruction signal is activated, and drives a precharge node according to a signal applied when the precharge instruction signal is inactive. The precharge transistor has a first gate tunnel barrier, and the MIS transistor of the gate circuit has a second gate tunnel barrier larger than the first gate tunnel barrier.

Preferably, a precharge auxiliary for precharging a precharge node to a predetermined voltage level in response to a precharge auxiliary instruction signal activated at the time of transition from inactivation to activation of a precharge instruction signal. A transistor is further provided. This precharge auxiliary transistor has a MIS having a second gate tunnel barrier.
It is a transistor.

Preferably, the precharge instructing signal is activated in response to a sleep mode instructing signal applied when the standby cycle continues for a predetermined time or more, and when the sleep mode instructing signal is inactivated, it is activated in the standby cycle and There are further provided a control circuit for generating a standby instruction signal for deactivating when the sleep mode instruction signal is activated, and a standby precharge transistor for precharging the precharge node to a predetermined voltage level when the standby instruction signal is activated. This standby precharge transistor is formed of a MIS transistor having a second gate tunnel barrier.

A semiconductor device according to another aspect is activated for a predetermined time at the time of transition from a standby cycle to an active cycle, and includes a precharge transistor for precharging a precharge node to a predetermined voltage level; A gate circuit for driving a precharge node according to a given signal;
This gate circuit has the same first gate tunnel barrier as the precharge transistor. The first gate tunnel barrier has the same size as or smaller than the gate tunnel barrier provided by the silicon oxide film having a thickness of 3 nm.

Preferably, a floating prevention transistor for holding a precharge node at a voltage level having a polarity different from a predetermined voltage during a standby cycle is provided. The floating prevention transistor has a larger gate tunnel barrier than the precharge transistor.

A precharge transistor activated in response to a precharge instruction signal activated in a standby cycle to precharge a precharge node to a predetermined voltage, and a precharge node according to a signal applied in an active cycle Is provided. The precharge transistor has a first gate tunnel barrier, and the gate circuit is formed of a MIS transistor having the first gate tunnel barrier. The semiconductor device further includes a control circuit for activating the precharge transistor for a predetermined period when the sleep mode is released and for holding the precharge transistor in the off state during the sleep mode. The sleep mode is set when the standby cycle lasts for a predetermined time or more.

A semiconductor device according to another aspect of the present invention includes a plurality of memory cells requiring storage data refresh and a refresh request activated in a refresh mode to instruct refresh of storage data in a plurality of memory cells. At a predetermined interval, a refresh address counter for generating a refresh address for specifying a memory cell row of the plurality of memory cells to be refreshed, and a plurality of memory cells according to the refresh request and the refresh address. A refresh circuit for refreshing data stored in a memory cell specified by the refresh address is provided. The timer circuit and the refresh address counter
The refresh-related circuit includes a MIS transistor having a second gate tunnel barrier having a size equal to or smaller than the first gate tunnel barrier as a component.

Preferably, the first gate tunnel barrier and the second gate tunnel barrier have the same size, and the semiconductor device is further inactivated in a refresh mode and has normal access to a memory cell. A row-related circuit that is enabled in the mode and selects a row of a plurality of memory cells in accordance with an applied address and control signal; This row-related circuit includes, as constituent elements, an MIS transistor having substantially the same operation as the refresh-related circuit and having a gate tunnel barrier having a small first gate tunnel barrier.

Preferably, a power supply transistor is provided for interrupting the supply of power supply voltage to the refresh-related circuit during a standby cycle in the refresh mode.

The power transistor is preferably a MIS transistor having a first gate tunnel barrier.

A plurality of memory cells are arranged in a matrix, and a refresh address specifies a memory cell row. A column-related circuit for performing an operation related to column selection of the plurality of memory cells, and a column-related power supply transistor for cutting off supply of power supply voltage to the column-related circuit in the refresh mode are further provided.

This column-related power supply transistor is constituted by a MIS transistor having a first gate tunnel barrier.

In operation, a logic circuit for performing arithmetic processing using data stored in at least a plurality of memory cells and a logic power supply transistor for cutting off supply of power supply voltage to the logic circuit in a refresh mode are provided. Provided.

The logic power supply transistor is constituted by a MIS transistor having a first gate tunnel barrier.

A semiconductor device according to another aspect is provided corresponding to an internal node of a logic circuit including an insulated gate field effect transistor as a component, and latches a signal of a corresponding internal node. And a test path coupled to the latch circuit for transferring a signal of the latch circuit. At least the logic circuit is set to a state where the gate tunnel current is reduced in the standby state.

The latch circuit preferably includes an insulated gate type field effect transistor having a larger leak current due to a gate tunnel leak current in a standby state than the insulated gate type field effect transistor which is a component of the logic circuit. Included as

Alternatively, the latch circuit is preferably constituted by an insulated gate field effect transistor having a gate tunnel barrier larger than that of the insulated gate field effect transistor which is a component of the logic circuit. You.

The latch circuit is preferably a scan register constituting a scan path for enabling the internal state of the logic circuit to be observed externally.

Instead of this, the latch circuit is a scan register constituting a scan path for enabling the internal state of the logic circuit to be controlled from the outside.

A semiconductor device according to still another aspect includes:
An internal circuit composed of a plurality of MIS transistors performing a predetermined operation when activated, and an internal circuit designating signal designating an internal circuit to be activated among the plurality of internal circuits in response to the internal circuit designating signal. An activation control circuit for generating an internal circuit activation signal for activating the circuit; and an inactive state of the plurality of internal circuits in response to the operation mode instruction signal and the internal circuit activation signal. Circuit M
A current control circuit is included for holding the gate tunnel current of the IS transistor smaller than the gate tunnel current of the MOS transistor of the active internal circuit. The operation mode instruction signal designates an active cycle, which is an operable period of the plurality of internal circuits, and a standby cycle in which the plurality of internal circuits stop operating.

The current control circuit preferably sets the gate tunnel current of the MOS transistors of the plurality of internal circuits to a small state in a standby cycle in response to the operation mode instruction signal.

A semiconductor device according to still another aspect includes a normal array having a plurality of normal memory cells, a redundant array having spare memory cells for relieving a defective normal memory cell having a defect of the normal array, and a normal array. A normal access circuit for accessing a selected memory cell of the array, a spare access circuit for accessing a spare memory cell of the redundant array, and a gate tunnel of a MOS transistor of a circuit in an inactive state of the spare access circuit and the normal access circuit A power supply control circuit for reducing the current to be smaller than the gate tunnel current of the MOS transistor of the active circuit is included.

Each of the spare access circuit and the normal access circuit preferably includes a plurality of selectively activated sub access circuits. The power supply control circuit replaces the unselected sub-access circuits of the spare access circuit and the normal access circuit with the MO of the selected sub-access circuit.
The state is set to have a gate tunnel current smaller than the gate tunnel current of the S transistor.

Preferably, a decision circuit for deciding which of the normal access circuit and the spare access circuit is to be activated according to the address signal, and activating one of the normal access circuit and the spare access circuit according to the decision result Is further provided. The determination circuit starts the determination operation before an operation mode instruction signal instructing a memory cell selection operation is activated.

Instead of this, preferably, it is determined whether to activate the normal access circuit or the spare access circuit according to the address signal, and one of the normal access circuit and the spare access circuit is activated according to the determination result. A determination circuit. This determination circuit performs a determination operation asynchronously with an operation mode instruction signal instructing a memory cell selection operation.

When there is a possibility that a gate tunnel current is generated, a countermeasure such as increasing the gate tunnel barrier or cutting off the current path is taken for the MIS transistor which may be generated. A MIS transistor miniaturized in accordance with a scaling rule is used for a transistor having no possibility of generating a gate tunnel current. With these measures, a semiconductor device which operates with low current consumption and operates at high speed is realized.

When the circuit is in a non-operating state, the gate tunnel current of the MIS transistor which is a component of the circuit is reduced, or the supply of the power supply voltage is stopped to reduce the consumption of the circuit in the non-operating state. The current can be reduced and a semiconductor device with low current consumption can be realized.

[0099]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] FIG.
FIG. 2 schematically shows a configuration of a semiconductor device according to a first embodiment of the present invention. In FIG. 1A, this semiconductor device is a cascade-connected CMOS inverter circuit IV0-
IV4. These CMOS inverter circuits IV0
-IV4 is a P-channel MIS transistor P
Q and an N-channel MIS transistor NQ as constituent elements. The film thickness Tox of the gate insulating films of the MIS transistors PQ and NQ is made sufficiently thin, and has a thickness of the gate insulating film that provides a gate tunnel barrier equal to or less than that of a 3 nm silicon oxide film. Here, the “gate tunnel barrier” means that the above equation of the gate tunnel current J includes the gate insulating film thickness Tox and the barrier height と し て as parameters, and the gate insulating film thickness Tox and the barrier Is defined as the product of the square root of the height ψ. The barrier height ψ is represented by the difference between the Fermi level and the surface potential during band bending. Usually the height of this barrierψ
Is approximated by the following equation.

Ψ = c2 ・ φG + c3 φG represents the work function of the gate electrode, and c2 and c3
Is represented by a function such as the dielectric constant of the gate insulating film and the thickness Tox of the gate insulating film.

CMOS inverter circuits IV0-IV4
Receive in common the voltages of sub power supply line 3 and sub ground line 4 as both operation power supply voltages. The sub power line 3 is connected to the main power node 1
Connected via a switching transistor SW1,
Sub ground line 4 is connected to main ground node 2 via switching transistor SW2. These switching transistors SW1 and SW2 have the same thickness as the gate insulating films of MIS transistors PQ and NQ, and their gate tunnel barriers are sufficiently large. In addition, these switching transistors SW1 and SW2 sufficiently supply an operating current to CMOS inverter circuits IV0-IV4 during an active cycle, so that their current driving capabilities are sufficiently larger than the current driving capabilities of MIS transistors PQ and NQ. ing. That is, these switching transistors SW1 and SW2 have a sufficiently large channel width.

These switching transistors SW1
And SW2 are selectively turned on / off in response to control clock signals / φ and φ, respectively. Control clock signals φ and / φ turn on switching transistors SW1 and SW2 during an active cycle in which CMOS inverter circuits IV0-IV4 actually operate, while CMOS inverter circuits IV0-I
During a standby cycle in which V4 enters a standby state, these switching transistors SW1 and SW2 are set to an off state.

In the structure shown in FIG. 1A, as shown in the signal waveform diagram of FIG. 1B, in the active cycle, control clock signals φ and / φ are at H level and L level, respectively. Then, switching transistors SW1 and SW2 are turned on, power supply node (main power supply line) and sub power supply line 3 are coupled, and sub ground line 4 is coupled to the main ground node. Switching transistors SW1 and SW2 have a sufficiently large current supply capability. CMOS inverter circuits IV0-IV4
Includes, as constituent elements, MIS transistors PQ and NQ whose gate insulating films have been sufficiently thinned. These MIS transistors PQ and NQ are miniaturized according to the operating power supply voltage VCC according to a scaling rule, and operate at high speed. .

In the standby state, as shown in FIG. 1B, control clock signal φ is at L level, control clock signal / φ is at H level, and switching transistors SW1 and SW2 are off. Switching transistor SW1 has its gate receiving control clock signal / φ at the power supply voltage VCC level, and switching transistor SW2 has its gate receiving control clock signal φ at the ground voltage level. Therefore, these switching transistors SW1 and SW2 are in a depleted state, a depletion layer is spread in the channel region of switching transistors SW1 and SW2, and the voltage applied to the gate capacitance of these switching transistors SW1 and SW2 is small. Become. This is because the depletion layer capacitance is connected in series with the gate capacitance, and the voltage between the gate electrode and the substrate region is divided by the gate capacitance and the depletion layer capacitance.

Therefore, almost no tunnel current is generated between the substrate region and the gate electrode, and only a gate tunnel current flows in the overlap region between the drain region and the gate electrode. This is smaller than the gate tunnel current flowing between the channel region and the gate by about two digits, and the gate tunnel current of these switching transistors SW1 and SW2 can be made sufficiently small in the standby cycle.

In CMOS circuits IV0-IV4,
MIS transistors PQ and NQ are coupled to sub power supply line 3 and sub ground line 4, respectively. Leakage current (gate tunnel current and subthreshold current) flowing through switching transistors SW1 and SW2 and CM
Only a leakage current occurs in OS inverter circuits IV0-IV4. Switching transistor SW1
The voltage levels of the sub power supply line 3 and the sub ground line 4 are in a balanced state at a voltage level at which the leak current flowing through the switches SW2 and SW2 and the leak current flowing through the CMOS inverter circuits IV0-IV4 are balanced. In this case, for example, even if a gate tunnel current flows through MIS transistor NQ and a gate tunnel current flows through sub-ground line 4, switching transistor SW2 is off and MIS transistor NQ
The gate tunnel current of Q is sufficiently suppressed. Similarly, M
When a gate tunnel current flows through IS transistor PQ, sub power supply line 3 is coupled to main power supply node 1 via switching transistor SW1, and the gate tunnel current flowing through MIS transistor PQ is sufficiently suppressed by switching transistor SW1. Is done. Thereby, the switching transistors SW1 and SW2
Thereby, the gate tunnel current between power supply node 1 and ground node 2 can be effectively cut off, and the current consumption in the standby state can be reduced.

That is, these CMOS inverter circuits IV0-IV4 are connected to power supply node 1 and ground node 2
Switching transistor SW1 which is turned off during the standby cycle as compared with the configuration directly connected to
And SW2 can sufficiently suppress the gate tunnel current.

[Modification] FIG. 2A shows a structure of a modification of the first embodiment of the present invention. This figure 2
In the configuration shown in (A), inverter circuits IV0-
Gate insulating films of MIS transistors PQ and NQ included in IV4 have a thickness Tox1 corresponding to a silicon oxide film thickness of 3 nm. On the other hand, switching transistor SW3 connected between power supply node 1 and sub-power supply line 3
Have a gate insulating film thickness Tox2 that is larger than the gate insulating film thickness Tox1 of the MIS transistors PQ and NQ. The switching transistor SW4 connected between the sub-ground line 4 and the ground node 2 also has a gate insulating film having a thickness of Tox2. The other configuration is shown in FIG.
And the corresponding parts are denoted by the same reference numerals.

As shown in the signal waveform diagram of FIG. 2B, control clock signals φ and / φ are supplied to inverter circuit IV0
The state becomes active / inactive according to the active cycle and the standby cycle of -IV4. The switching transistors SW3 and SW4 are configured by MIS transistors, and have a gate insulating film thickness Tox.
However, when the film thickness becomes as thick as Tox2, the gate tunnel barrier becomes large and the gate tunnel current becomes difficult to flow. When the thickness of the gate insulating film is increased, the absolute values of the threshold voltages of the switching transistors SW3 and SW4 are also increased, and the sub-threshold leakage current is suppressed. Therefore, the inverter circuits IV0-
In the standby state of IV4, the off-leak current is suppressed, and the gate tunnel current in inverter circuits IV0-IV4 is correspondingly suppressed (since the gate tunnel current is determined by the off-leak current of switching transistors SW3 and SW4).

In the structure shown in FIGS. 1A and 2A, the control circuit for generating control clock signals φ and / φ needs to increase the thickness of the gate insulating film as a component. . This is the switching transistor S
A gate tunnel current flows in W1-SW4, and there is a possibility that a path through which a through current due to the gate tunnel current flows between the power supply node and the ground node via the MIS transistor of the control circuit. In order to prevent a through current caused by a gate tunnel current in the clock control circuit, the clock control circuit uses a MIS transistor having a thick gate insulating film to suppress a through current caused by the gate tunnel current.

However, the switching transistor SW3
In the case of using SW4 and SW4, the gate insulating film is thickened and the gate tunnel current is sufficiently suppressed.
MIS of circuit for generating control clock signals φ and / φ
The thickness of the gate insulating film of the transistor may be reduced.

As described above, according to the first embodiment of the present invention, the power / ground node of the CMOS circuit having a thin gate insulating film is connected to the power / ground via the switching transistor which is turned off during the standby cycle. In the standby cycle, only the off-leak current of the switching transistor serves as a source of the gate tunnel current of the CMOS circuit.
Compared to connecting the circuit directly to the power / ground node,
Gate tunnel current can be greatly reduced.

[Second Embodiment] FIG. 3A schematically shows a structure of a semiconductor device according to a second embodiment of the present invention. In FIG. 3, four stages of CMOS inverter circuits are cascaded. These CMOS inverter circuits are directly coupled to power supply node 1 and ground node 2. That is, the P-channel MIS transistor PQ1-
Each source of PQ4 is coupled to power supply node 1,
The respective sources of N channel MIS transistors NQ1-NQ4 are coupled to ground node 2. As shown in FIG. 3B, the input signal IN is held at the L level in the standby state and driven to the H level in the active cycle. The MIS transistors PQ1, PQ3, NQ2 which are turned on in the standby state in the CMOS inverter circuit in accordance with the logic level of the input signal IN in the standby state.
And the thickness of the gate insulating film of NQ4 is set to be Tox2 which is large. On the other hand, the gate insulating film thickness of the MIS transistors NQ1, PQ2, NQ3 and PQ4 which are turned off in the standby state is set to the film thickness Tox1. The thickness Tox1 is 3 nm in the case of a silicon oxide film.
(Nanometers).

In the structure shown in FIG. 3A, the gate insulating films of MIS transistors PQ1, NQ2, PQ3 and NQ4 which are turned on in the standby state have a large thickness, and therefore, the gate tunnel barrier And the gate tunnel current during the standby period can be sufficiently suppressed. In the case of the configuration shown in FIG. 3A, as shown in FIG.
In the standby state of the IS transistor PQ1,
Although turned on in response to the input signal IN, the gate insulating film has the thickness Tox2, and the gate tunnel current It1 can be sufficiently suppressed. N channel M
In IS transistor NQ1, off-leak current I
off1 flows. MIS transistor NQ1 is off, and its gate tunnel current is sufficiently small. The MIS transistor NQ2 is turned on in response to receiving an H level signal at its gate in the standby state, but its gate insulating film is Tox2, which is sufficiently thick, and its gate tunnel current It2 is sufficiently suppressed. can do. Also in this case, the off-leak current Ioff2 simply flows through the MIS transistor PQ2.

Therefore, the gate tunnel current in the standby state can be sufficiently suppressed by increasing the thickness of the gate insulating film of the MIS transistor which is turned on in the standby state. By taking appropriate measures for the off-leak current, the current consumption in the standby state can be sufficiently suppressed.

At the time of transition to the active cycle, the MIS transistor NQ having a thin gate insulating film is used.
1, PQ2, NQ3 and PQ4 merely shift from the off state to the on state, the gate insulating film thickness is as thin as Tox1, the absolute value of the threshold voltage is small, and the off state is turned on at high speed. The input signal I
In accordance with the change of N, the state of the output signal can be driven to the defined state at a high speed, and there is no problem such as an increase in access time. Each CMOS in standby state
The output signal of the inverter circuit is in a fixed state, and each CMO
It is possible to prevent the power supply / ground node of the S circuit from floating and the level of its output signal to be undefined, and to prevent the logic state of the output signal from becoming undefined at the transition to the active cycle.

[Third Embodiment] FIG. 5 shows a structure of a semiconductor device according to a third embodiment of the present invention. FIG. 5 also shows a four-stage CMOS inverter circuit. The P-channel MI of these CMOS inverter circuits
The back gates of S transistors PQ1-PQ4 are commonly connected to N well 5, and their sources are connected to power supply node 1. N-channel MIS transistor N
Q1-NQ4 have their sources connected to ground node 2 and their back gates commonly coupled to P well 6. Well voltage VWN on N well 5 and well voltage VWP on P well 6 are changed according to the operation cycle.

FIG. 6 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG. As shown in FIG. 6, in the standby state, voltage VW applied to N well 5 is applied.
N is set to the high voltage Vpp level, and the voltage applied to P well 6 is set to the negative voltage VBB level. In the active cycle, voltage VWN applied to N well 5 is at the level of power supply voltage VCC, and voltage VWP applied to P well 6 is at the level of ground voltage GND.

In general, when the back gate bias becomes deep in the MIS transistor, the depletion layer in this substrate region expands, and the absolute value of the threshold voltage increases. When the depletion layer spreads, the electric field applied to the gate insulating film decreases (equivalently, the capacitor value of the gate insulating film increases), and accordingly, the electric field applied to the gate insulating film decreases and the gate tunnel current is suppressed. can do. In the standby state, the absolute values of the bias voltages applied to N well 5 and P well 6 are increased, and MIS transistors PQ1-PQ4 and N
The absolute value of the threshold voltage of Q1-NQ4 is large, and these sub-threshold leak currents (off-leak currents) can be suppressed. Therefore, both the suppression of the gate tunnel current and the suppression of the off-leak current can be realized, and the current consumption in the standby state can be significantly reduced.

In the structure shown in FIG. 5, C
The MOS inverter circuit includes a power supply node 1 and a ground node 2
The logic levels of these output signals are in a defined state, and the output signal OUT can be changed according to the voltage level of the input signal IN at a high speed during the transition to the active cycle. Further, during the standby period, the back gate bias (substrate bias) is made common to the MIS transistors PQ1-PQ4 and NQ1-NQ4, and the gate tunnel current and off-leak current are reduced regardless of the logic level of the input signal IN in the standby state. It can be reduced at the same time.

FIG. 7 schematically shows a structure of the CMOS inverter circuit shown in FIG. In FIG.
MIS transistors PQ and NQ of the CMOS inverter circuit are formed in N wells 11 and 12 formed on the surface of P type semiconductor substrate 10 with a gap therebetween.
N well 12 receives power supply voltage Vcc via N type impurity region 12a. A P well 13 is formed on the surface of the N well 12, and the P well 13
Used as a substrate region of the S transistor NQ.

P-type impurity regions 11a and 11b are formed on the surface of N well 11 with a space therebetween, and a gate electrode 11c is formed between these impurity regions 11a and 11b via a gate insulating film (not shown). Gate electrode 1
The gate insulating film below 1c has a thickness that provides a tunnel barrier equal to or less than a gate tunnel barrier provided by a silicon oxide film having a thickness of 3 nm. In the following description, unless otherwise specified, the thin gate insulating film of the MIS transistor has a thickness Tox1 that provides a gate tunnel barrier equal to or less than a gate tunnel barrier provided by a silicon oxide film having a thickness of 3 nm.

P-channel MIS transistor PQ is formed by impurity regions 11a and 11b formed in N well 11 and gate electrode 11c.

On the surface of N well 11, an N type impurity region 11d is formed. Well bias voltage VWN from N well bias circuit 15 is applied to N well 11 via N type impurity region 11d.

On the surface of P well 13, N-type impurity regions 13a and 13b are formed at intervals. These N
Gate electrode 13c is formed on the channel region between mold impurity regions 13a and 13b via a thin gate insulating film. These P well 13 and N type impurity region 13a
And 13b and gate electrode 13c form an N-channel MIS transistor NQ. This P-well 1
On the three surfaces, a P-type impurity region 13d is also formed. P-type impurity region 13 d receives well bias voltage VWP from P-well bias circuit 20, and applies well bias voltage VWP to P-well 13.

Impurity regions 11b and 13b are coupled to an output node generating output signal OUTa, and power supply voltage Vcc and ground voltage Vss (= GND) are applied to impurity regions 11a and 13a, respectively. Input signal INa is commonly applied to gate electrodes 11c and 13c.

The bias voltages of N well 11 and P well 13 are switched according to the standby cycle and the active cycle. In the standby cycle, N
When well 11 is set at the high voltage Vpp level, the PN junction between impurity regions 11a and 11b and N well 11 is in a deep reverse bias state, and the depletion layer is expanded. Similarly, the negative voltage V in the standby state is
By applying BB, the reverse bias state of the PN junction between the P well 13 and the N-type impurity regions 13a and 13b is deepened, and the depletion layer is expanded.

FIG. 8A is a diagram schematically showing the distribution of the depletion layer DP in the MIS transistor. This FIG.
In (A), even when the inversion layer is formed in the channel region on the surface of the substrate region (well) SUB,
Around the source region SR and the drain region DR,
A depletion layer DP is formed. This depletion layer is a region where carriers do not exist, acts similarly to the insulating layer, and a depletion layer capacitance Cd is formed on the surface of the substrate region SUB. Accordingly, the depletion layer capacitance Cg is connected in series with the gate insulation film capacitance Cg of the gate insulation film between the gate electrode GT and the substrate region SUB.
d is connected. Therefore, as shown in FIG. 8B, when the gate insulating film capacitance Cg and the depletion layer capacitance Cd are connected in series, the gate voltage Vg and the substrate voltage Vs
ub is divided by these capacitances Cg and Cd, the electric field applied to the gate insulating film is reduced, and the gate tunnel barrier is equivalently increased. Therefore, in the standby state, by increasing the well bias, the thickness of the gate insulating film is equivalently increased and the gate tunnel barrier is increased.

Although a gate tunnel current flows between the gate electrode GT and the drain region DR, the facing area is sufficiently small, and sufficiently smaller than the gate tunnel current from the channel region. Thereby, the gate tunnel current can be reliably suppressed.

FIG. 9 is a diagram schematically showing a configuration of N well bias circuit 15 shown in FIG. In FIG. 9, N
The well bias circuit 15 generates a high voltage Vpp.
pp generating circuit 15a, level shifter 15b for converting the level of internal operation instruction signal φACT indicating an internal operation cycle, and switching control signal φ from level shifter 15b.
The high voltage Vp from the VPP generation circuit 15a according to MXN
multiplexer (MUX) 15c that selects one of p and power supply voltage Vcc to generate N-well bias voltage VWN
including. Internal operation instructing signal φACT is at power supply voltage Vcc.
And ground voltage GND (= Vss). The level shifter 15b converts the internal operation instruction signal φACT of the amplitude power supply voltage Vcc to the switching control signal φMX of the amplitude high voltage Vpp.
Convert to N Thereby, in the multiplexer 15c, one of the power supply voltage Vcc and the high voltage Vpp can be reliably selected to generate the N-well bias voltage VWN.

The Vpp generating circuit 15a for generating the high voltage Vpp is composed of a normal circuit utilizing a charge pump operation of a capacitor. Also, level shifter 1
5b is also configured using, for example, a normal latch type level conversion circuit. For example, a normal transmission gate is used for multiplexer 15c.

The correspondence between the logic levels of internal operation instruction signal φACT and switching control signal φMXN is appropriately determined according to the logic level when internal operation instruction signal φACT indicates the standby state and the active state.

FIG. 10 is a diagram schematically showing a configuration of P-well bias circuit 20 shown in FIG. 10, P well bias circuit 20 includes a VBB generating circuit 20a for generating negative voltage VBB and an internal operation instruction signal φAC
A level shifter 20b for performing level conversion of T and a multiplexer (M) that selects one of ground voltage GND and negative voltage VBB to generate P-well bias voltage VWP according to switching control signal φMXP from level shifter 20b.
UX) 20c.

Level shifter 20b provides an internal operation instructing signal φAC changing between power supply voltage Vcc and ground voltage GND.
T is converted into a switching control signal φMXP that changes between the power supply voltage Vcc and the negative voltage VBB. The correspondence between the logic levels of internal operation instruction signal φACT and switching control signal φMXP is appropriately determined according to the logic level when internal operation instruction signal φACT is in the standby state and the configuration of multiplexer 20c. In the standby state, the multiplexer 2 operates in accordance with the switching control signal φMXP.
0c selects negative voltage VBB from VBB generating circuit 20a, and in an active cycle, multiplexer 20c sets ground voltage GBB according to switching control signal φMXP.
Select ND.

VBB generating circuit 20a is formed of a charge pump circuit utilizing a charge pump operation of a capacitor, and level shifter 20b is formed of, for example, a latch type level conversion circuit.

In the structure shown in FIG. 5, the voltages of P well 6 and N well 5 are both changed according to the operation cycle. However, the bias voltage of only one of the P well and the N well may be switched according to the operation cycle.

Further, only the substrate bias of the MIS transistor which is turned on in the standby state may be configured to be deep.

[First Modification] FIG. 11 schematically shows a structure of a first modification of the third embodiment of the present invention. FIG.
1, a four-stage CMOS inverter circuit is shown. These CMOS inverter circuits have a P-channel M
IS transistors PQ1-PQ4 and N-channel MIS
It includes transistors NQ1-NQ4. The sources of the MIS transistors PQ1 to PQ4 are connected to the power supply line 21,
The sources of the MIS transistors NQ1-NQ4 are connected to the ground line 23. These power lines 21 and 23
Are coupled to power supply switching circuits 22 and 24, respectively. Power supply switching circuits 22 and 24 change the voltage levels of voltages PV and NV on power supply line 21 and ground line 23 according to internal operation instruction signal φACT.

FIG. 12 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG. Hereinafter, the operation of the semiconductor device shown in FIG. 11 will be described with reference to FIG.

In the standby state, power supply switching circuit 22 supplies ground voltage GN as voltage PV on power supply line 21.
D, and power supply switching circuit 24 transmits power supply voltage Vcc to ground line 23 as voltage NV. MIS transistors PQ1-PQ4 have their sources connected to ground voltage GN.
In response to D, they are turned off regardless of the respective gate voltages. MIS transistors NQ1-NQ4 also receive power supply voltage Vcc at their sources, and are turned off regardless of the voltage level of each gate. Therefore, these MIS transistors PQ1-PQ4
And NQ1-NQ4, almost no gate tunnel current is generated regardless of the logic level of input signal IN.

When the active cycle starts, power supply switching circuit 22 supplies power supply voltage V on power supply line 21 as power supply voltage V.
cc, and power supply switching circuit 24 supplies ground voltage GN
D is transmitted on ground line 23 as voltage NV. Therefore, in this state, MIS transistor PQ1-
PQ4 and NQ1-NQ4 are connected to power supply voltage Vc, respectively.
c and CMO using the ground voltage GND as both operating power supply voltages
It operates as an S inverter circuit and generates an output signal OUT according to the input signal IN. At this time, all of the MIS transistors PQ1-PQ4 and NQ1-NQ4 have thin gate insulating films Tox1 and can operate at high speed.

In the structure shown in FIG. 11, by setting the source voltages of MOS transistors PQ1-PQ4 to the ground voltage level in the standby state, the depletion layer in the substrate region of MIS transistors PQ1-PQ4 expands, and the gate insulating film The electric field applied to
Gate tunnel current can be suppressed. Therefore, the gate tunnel current of each of MIS transistors PQ1-PQ4 is reliably suppressed regardless of the logic level of input signal IN in the standby state. Also in MIS transistors NQ1-NQ4, when the source is at the level of power supply voltage Vcc, the source / substrate is deeply reverse-biased, the depletion layer expands, and is applied to the gate insulating films of MIS transistors NQ1-NQ4 accordingly. The electric field can be reduced, and the gate tunnel current can be suppressed. In the MIS transistors NQ1-NQ4 and PQ1-PQ4, a tunnel current may flow between the gate and the drain.
Voltages PV and NV of power supply line 21 and ground line 23 can be suppressed by setting them to ground voltage GND and power supply voltage Vcc during the standby cycle, respectively.
MIS transistors PQ1-PQ4 and NQ1
-NQ4 has an increased absolute value of its threshold voltage,
Off-leak current is also reduced, so that current consumption in the standby state can be reduced.

In general, by setting the bias state between the gate and the source to a reverse bias state deeper than the bias state in the normal operation, a state equivalent to a state in which the substrate bias is deepened in the normal operation is realized. To increase the depletion layer and increase the absolute value of the threshold voltage,
Gate tunnel current and off-leak current can be reduced.

Note that power supply switching circuits 22 and 24 simply supply power supply voltage Vcc in accordance with internal operation instructing signal φACT.
In addition, it is only necessary to have a configuration for transmitting one of ground voltage GND to power supply line 21 and ground line 23, respectively.

[Modification 2] FIG. 13 schematically shows a structure of a modification 2 of the embodiment 3 of the invention. In the configuration shown in FIG. 13, a power supply switching circuit 26 for switching the voltage of power supply line 21 in response to internal operation instruction signal φACT is provided for power supply line 21, and ground line 23 is provided.
Similarly, power supply switching circuit 28 for switching the voltage level of ground line 23 in accordance with internal operation instruction signal φACT is provided. Power supply switching circuit 26 transmits voltage V1 lower than power supply voltage Vcc to power supply line 21 during the standby cycle, and transmits power supply voltage Vcc to power supply line 21 during the active cycle (in the active state). . In a standby cycle (standby state), power supply switching circuit 28 applies voltage V2 to ground line 2.
3 in the active cycle, and transmits the ground voltage GND to the ground line 23. Another configuration is shown in FIG.
1, and corresponding parts are denoted by the same reference numerals.

In the structure shown in FIG. 13, voltage V
1 is lower than the power supply voltage Vcc, and the voltage V2 is higher than the ground voltage GND. These voltages V
1 and V2 may be equal voltage levels.

In the configuration of the semiconductor device shown in FIG. 13, voltage PV of power supply line 21 is equal to power supply voltage V
cc, and the voltage NV of the ground line 23 is also set to a voltage V2 higher than the ground voltage GND. MIS
When the source voltage changes, the voltage between the gate and the source of the transistor is lowered, so that the "body effect"
As shown in FIG. 15, a depletion layer spreads in the substrate region (well region) as shown in FIG. 15, and the same effect as that of changing the well potential can be obtained.

Therefore, in particular, the voltages V1 and V2
, The voltages V1 and V2 realize the gate-source voltages of MIS transistors PQ1-PQ4 and NQ1-NQ4 in the active cycle even in the active cycle, even if the voltage levels are different from ground voltage GND and power supply voltage Vcc. Similarly, the gate tunnel current can be suppressed as long as the voltage is set to a reverse bias state deeper than the applied bias state.

Therefore, for example, even if voltage V1 is negative voltage VBB and voltage V2 is high voltage VPP,
Similar effects can be obtained. The configuration of power supply switching circuits 26 and 28 can use the same configuration as that shown in FIGS. 9 and 10, and an appropriate level shifter may be used as needed according to the polarity / voltage level of voltages V1 and V2. It should just be used.

As described above, according to the third embodiment of the present invention, in the standby state, the substrate PN junction is
Since the reverse bias state is set deeper than during the active cycle, the depletion layer can be extended to the well region (substrate region), and the electric field applied to the gate insulating film can be reduced accordingly.
Tunnel current can be suppressed. In addition, the electric field generated near the drain is reduced by the depletion layer capacitance, the electric field between the gate and the drain is correspondingly reduced, and the tunnel current between the gate and the drain can be suppressed.

Furthermore, when the MIS transistor is in the standby state, the depletion layer is widened, the absolute value of the threshold voltage is equivalently increased, and the off-leak current can be reduced.

By using a so-called LDD (lightly doped drain) structure, the drain electric field can be reduced, and accordingly, the tunnel current between the gate and the drain can be suppressed.

In FIG. 15, the voltages V1 / V2
And the source voltage is switched between Vcc and GND. When the voltage V1 / V2 is applied, the substrate area SUB
, The depletion layer DP becomes wider. In either case, the reverse bias of the PN junction between the source region SR and the substrate region SUB becomes deep, and the depletion layer DP expands.

[Fourth Embodiment] FIG. 16 schematically shows a structure of a semiconductor device according to a fourth embodiment of the present invention. In the configuration shown in FIG. 16, input signal IN
The logic level in the standby cycle is L level and is predetermined. In FIG. 16,
Similar to the third embodiment, a four-stage CMOS inverter circuit is shown. P channel MIS transistors PQ1 and PQ3 which are turned on in the standby cycle
Is an N-well 5 whose back gate (substrate region) receives a bias voltage VWN from an N-well bias circuit 15.
Formed. N-channel MIS transistors NQ2 and NQ which are turned on during the standby cycle
4, a back gate is formed in the P well 6 receiving the well bias voltage VWP from the P well bias circuit 20.

On the other hand, MIS transistors PQ2, PQ4, NQ1 which are turned off in the standby cycle
And NQ3 have their respective back gates connected to their respective sources. That is, the MIS transistor P
The back gates of Q2 and PQ4 are connected to the power supply node, and the sources of MIS transistors NQ1 and NQ3 are connected to ground node 2. N-well bias circuit 15
And P-well bias circuit 20 has the same configuration as the configuration shown in FIGS. Further, these MIS transistors PQ1-PQ4 and NQ1-NQ
4 is that the gate insulating film is made sufficiently thin (film thickness T
ox1).

Next, the operation of the semiconductor device shown in FIG. 16 will be described with reference to a signal waveform diagram shown in FIG.

In a standby cycle or a standby state, input signal IN is at L level of the ground voltage level, and well bias voltage VW of N well 5 is applied.
N is set to the high voltage Vpp level. Well bias voltage VWP of P well 6 is set to negative voltage VBB. P-channel MIS transistors PQ1 and PQ3
, The well bias voltage VWN is at the high voltage Vpp level even if each gate receives an L level signal, and the depletion layer spreads over the substrate region (N well region) in the channel regions of MIS transistors PQ1 and PQ3. Therefore, the gate tunnel current is sufficiently suppressed. In N channel MIS transistors NQ2 and NQ4, well bias voltage VWP of P well 6 is at the level of negative voltage VBB. In these MIS transistors PQ2 and NQ4, the depletion layer is widened in the channel region, and the gate tunnel current is reduced. Does not occur.

In the active state, N well 5
Is set to the level of power supply voltage Vcc, and well bias voltage VWP of P well 6 is
Are set to the level of the ground voltage GND. Therefore,
MIS transistors PQ1-PQ4 receive the same back gate bias and operate under the same operating conditions.
The transistors NQ1 to NQ4 also have the same back gate bias and operate at high speed under the same operating conditions during operation in the active period. Therefore, in the active state, output signal OUT can be generated at high speed in accordance with input signal IN. In the configuration shown in FIG.
The N-well bias circuit 15 and the P-well bias circuit 20 drive the well regions of half of the MIS transistors compared to the configuration of FIG. Therefore, the area of the well region to be driven is reduced by half, the load driven by N-well bias circuit 15 and P-well bias circuit 20 is reduced, and current consumption is correspondingly reduced.

[First Modification] FIG. 18 schematically shows a structure of a first modification of the fourth embodiment of the present invention. FIG.
In 8, the input signal IN is at the L level during standby. MIS that is turned on during this standby cycle
The sources of transistors PQ1 and PQ3 are connected to power supply line 21.
And the sources of MOS transistors PQ2 and PQ4 which are turned off in the standby cycle are coupled to power supply node 1.

Similarly, the sources of MIS transistors NQ2 and NQ4 which are turned on during the standby cycle are
The sources of MIS transistors NQ1 and NQ3 connected to ground line 23 and turned off in the standby cycle are connected to ground node 2. Voltage PV from power supply switching circuit 26 (or 22) is applied to power supply line 21,
A power supply switching circuit 28 (or 24) is connected to the ground line 23.
Is applied. Power supply switching circuit 26 applies voltage V1 (or ground voltage GND) to power supply line 21 as voltage PV during the standby cycle, and power supply switching circuit 28 applies voltage V2 (or power supply voltage Vcc) to ground line 23 during the standby cycle. )give. In the active cycle, power supply switching circuit 26 (or 22)
Supplies power supply voltage Vcc as voltage PV, and power supply switching circuit 28 (or 24)
A ground voltage GND is applied to the ground line 23 as the voltage NV.
These power supply switching circuits 26 (or 22) and 28
The configuration of (or 24) is the same as the configuration shown in FIGS. This MIS transistor PQ1-PQ
4 and NQ1-NQ4 are the film thickness Tox of the gate insulating film.
One.

In the configuration shown in FIG. 18, in the standby cycle, a voltage (ground voltage or voltage V1) lower than power supply voltage Vcc in the active cycle is applied to the sources of MIS transistors PQ1 and PQ3 which are turned on. . Therefore, these MIS
Transistors PQ1 and PQ3 are turned off (the depletion layer expands), and gate tunnel current is suppressed. Similarly, MIS transistors NQ2 and NQ4
In the standby cycle, each source is supplied with the power supply voltage or the voltage V2, and is turned off (the depletion layer expands). Therefore, also in MIS transistors NQ2 and NQ4, the gate tunnel current can be sufficiently suppressed.

In the active cycle, power supply switching circuit 26 (or 22) supplies power supply voltage Vcc as voltage PV to power supply line 21, and power supply switching circuit 28
(Or 24) transmits the ground voltage GND to the ground line 23 as the voltage NV. Therefore, in this state, MIS transistors PQ1-PQ4 and NQ1-
NQ4 operates under the same operating conditions, and changes output signal OUT according to input signal IN at high speed.

As shown in FIG. 18, when the logic level of input signal IN in the standby cycle is predetermined, the MIS transistor to be turned on is turned on by increasing its source bias and turning off the MIS transistor. By setting to, the gate tunnel current in the standby state can be sufficiently suppressed.

[Fifth Embodiment] FIG. 19 schematically shows a structure of a semiconductor device according to a fifth embodiment of the present invention. In FIG. 19, sub power supply line 32 is connected to main power supply line 30 receiving power supply voltage Vcc via switching transistor SWa. Switching transistor SWa is turned off in the standby cycle in response to control clock signal φ, and turned on in the active cycle. Further, a main ground line 34 receiving ground voltage GND (Vss) is provided. This main ground line 34 is connected to sub-ground line 36 via switching transistor SWb. Switching transistor SWb responds to control clock signal / φ to switch transistor Sb.
As in the case of Wa, it is turned off in the standby state and turned on in the active state.

For the hierarchical power supply structure of the main / sub power supply line and the main / sub ground line, a CMOS inverter circuit forming a logic circuit is arranged. Input signal IN is fixed at a logic L level in the standby state. Input signal IN is received by, for example, a four-stage CMOS inverter circuit. These CMOS inverter circuits have a P-channel M
IS transistor PQa-PQd and N-channel MIS
Includes transistors NQa-NQd. The MIS transistors PQa and PQc which are turned on in the standby state have a thick gate insulating film (thickness To).
x2) Set and connect the source to the main power supply line 30. On the other hand, MIS transistors PQb and PQd that are turned off in the standby state have their gate insulating films as thin as Tox1 and have their sources connected to sub-power supply line 32.

As for the N-channel MIS transistor, the MIS transistors NQb and NQd which are turned on in the standby state have a gate insulating film having a thickness of T.
ox2 and connect each source to the main ground line 34. M that is off in standby mode
In IS transistors NQa and NQc, the gate insulating film thickness is set to Tox1, and the sources are connected to sub-ground line.

The film thickness Tox2 is larger than the film thickness Tox1, so that the MIS transistors PQa and PQa
c is larger than MIS transistors PQb and PQd.
The gate tunnel barrier is large, and MIS transistors NQb and NQd have a larger gate tunnel barrier than MIS transistors NQa and NQc. Next, the operation of the semiconductor device shown in FIG. 19 will be described with reference to a signal waveform diagram shown in FIG.

In the standby state, input signal I
N is set to L level, and control clock signal φ is set to H level.
Level (power supply voltage Vcc level), and control clock signal / φ is at L level of ground voltage GND level. Therefore, switching transistors SWa and SWb are turned off, and main power supply line 30 is connected to sub-power supply line 32.
And the auxiliary ground line 36 is separated from the main ground line 34. In this state, off-leak current Ioff flows from main power supply line 30 to sub-power supply line 32 via switching transistor SWa, and off-leakage current Ioff flows from sub-ground line 36 to main ground line 34 via switching transistor SWb. . In the CMOS inverter circuit, MIS transistors PQa, PQ
c, NQb and NQd are on. However, these on-state MIS transistors PQa, PQa, P
Qc, NQb, and NQd have a gate insulating film thickness of Tox2.
Therefore, the gate tunnel current is sufficiently suppressed. on the other hand,
Off-state MIS transistors PQb, PQd, NQa
And NQc, the gate insulating film thickness is Tox1
, But each is in the off state (accumulation state),
Almost no gate tunnel current occurs. These MI
In S transistors PQb, PQd, NQa and NQc, an off-leak current flows between the drain and the source.

However, these off-leak currents are suppressed by switching transistors SWa and SWb, and power supply voltage Vccs on sub power supply line 32 has a voltage level lower than power supply voltage Vcc due to the off-leak current and a slight gate tunnel current. Becomes On the other hand, the voltage Vsss on the sub-ground line 36 has a voltage level higher than GND due to the off-leak current / gate tunnel current. These voltages Vccs and Vsss are:
Switching transistors SWa and SWb and MI
Off-leak current / gate tunnel current flowing through S transistors PQa-PQd and NQa-NQd are stabilized at a balanced voltage level.

Therefore, voltage V on sub power supply line 32
ccs is lower than power supply voltage Vcc, and
The upper voltage Vsss is also at a voltage level higher than the ground voltage GND, and M is turned off in the standby state.
IS transistors PQb, PQd, NQa and NQc
Is in a reverse bias state, and the source-drain off-leakage current is sufficiently suppressed. Therefore, both the suppression of the gate tunnel current and the off-leak current between the source and the drain can be reliably suppressed, and the current consumption in the standby state can be sufficiently reduced.

In the structure of the semiconductor device shown in FIG. 19, the gate insulating film which is turned on has a large thickness.
IS transistors PQa, PQc, NQb and NQd
Have their sources connected to the main power supply line 30 and the main ground line 34, respectively, and the output voltage level of each CMOS inverter circuit is fixed at the power supply voltage Vcc and the ground voltage GND level, so that an undefined state does not occur. Therefore, when transitioning from the standby state to the active state,
By the MIS transistor with a thin gate insulating film,
The output signal OUT can be reliably driven to the defined state without causing the logic undefined state according to the change of the input signal IN.

At the time of transition to the active cycle, switching transistors SWa and SWb are in the ON state, and a current is supplied from main power supply line 30 to sub-power supply line 32 by the large current driving force, and voltage Vc
cs is returned to the level of the power supply voltage Vcc at a high speed.
Can be returned to the ground voltage GND level at a high speed, and can operate at a high speed in an active cycle to input signal I
The output signal OUT can be driven to a definite state according to the change of N.

Switching transistors SWa and S
In order to minimize the off-leak current and the gate tunnel current in the off state, the absolute value of the threshold voltage of Wb is increased and the gate tunnel barrier is increased. However, the current driving force in the ON state is made sufficiently large to drive this CMOS inverter circuit at high speed.

FIGS. 21A to 21C are diagrams showing an example of the configuration of the switching transistors SWa and SWb. In FIG. 21A, in order to increase the impurity concentration in the channel region between the source region S and the drain region D, the channel impurity doping is set to a high concentration, and the absolute value Vth of the threshold voltage is increased.

In the configuration of FIG. 21B, in the switching transistor SW (SWa, SWb), the thickness of the insulating film below the gate G is set to be as thick as Tox3. The gate insulating film thickness Tox3 is equal to or greater than the film thickness Tox2. This increases the absolute value of the threshold voltage of the switching transistors SWa and SWb,
Also, increase the gate tunnel barrier.

Further, as shown in FIG. 21C, a bias voltage Vbias applied to the substrate region (well region)
Is deeper than other MIS transistors, the absolute value of the threshold voltage is increased, and the gate tunnel barrier is increased. Any of these configurations shown in FIGS. 21A to 21C may be used, and the absolute value Vth of the threshold voltage of switching transistors SWa and SWb is increased.
It suffices if the off-leak current / gate tunnel current is sufficiently suppressed.

At the time of transition from the standby cycle to the active cycle, MI having a small gate insulating film thickness is used.
For example, in order to change the output signal of each CMOS inverter circuit from the off state to the on state at a high speed and change the output signal of each CMOS inverter circuit, for example, a dynamic semiconductor memory device (DR)
A problem such as an increase in access time in AM or the like does not occur.

As described above, according to the fifth embodiment of the present invention, the MIS transistor utilizing the hierarchical power supply structure and turned on in the standby state has a thick gate insulating film and mainly uses the source thereof. The gate insulating film of the MIS transistor which is connected to the power supply line / main ground line and turned off in the standby state (during the standby cycle) is thinned and its source is connected to the sub power supply line / sub ground line. Off leak current / gate tunnel current in the state can be sufficiently suppressed, and current consumption in the standby state can be reduced. At the time of transition to the access cycle, the MIS transistor having a small gate insulating film thickness transitions from the off state to the on state. In the standby state, the output signal voltage level of each circuit is in a definite state, and the output signal is indefinite. It is driven to the defined state at a high speed without passing through the state, and the output signal can be changed at a high speed in accordance with the input signal, and the high-speed operability in the active cycle is sufficiently ensured.

[Sixth Embodiment] FIG. 22 schematically shows a structure of a semiconductor device according to a sixth embodiment of the present invention. Also in the semiconductor device shown in FIG. 22, a hierarchical power supply structure is used, and main power supply line 30, sub power supply line 32, sub ground line 36, and main ground line 34 are arranged. The logic circuit 40 uses the voltages on these hierarchical power supplies as operating power supply voltages,
A predetermined process is performed on the input signal IN to generate an output signal OUT. Input signal IN is at the L level in the standby state. Therefore, in the logic circuit 40, similarly to the configuration shown in FIG. 19, the MIS transistors PQa and PQc which are turned on in the standby state have a thick gate insulating film (thickness Tox).
2) The respective sources are connected to the main power supply line 30, and the gate insulating films of the MIS transistors NQb and NQd are thickened, and the respective sources are connected to the main ground line 34. MIS transistors PQb and PQd and N which are turned off in the standby state and may cause off-leakage current
As for Qa and NQc, each gate insulating film has a thickness Tox1 corresponding to a thickness of 3 nm of a silicon oxide film.
And thin, guarantee high-speed operation. Sources of these MIS transistors PQb and PQd are connected to the sub power supply line 32, and MIS transistors NQ
a and NQc have respective sources connected to the auxiliary ground line 36.
Connected to.

Sub power supply line 32 is connected to main power supply line 30 via switching transistor SWa, and sub ground line 36 is connected to main ground line 34 via switching transistor SWb. These components are the same as those shown in FIG. The semiconductor device according to the sixth embodiment shown in FIG. 22 further includes a logic circuit 40 and a replica circuit of switching transistors SWa and SWb. A voltage adjusting circuit is provided for driving the voltage level of the ground line to a predetermined voltage level.

The voltage adjusting circuit 42 generates a balanced voltage of the sub-power supply line 32 and the sub-ground line 36 in the standby state, and has a high speed at the transition to the standby state. The voltage levels of sub power supply line 32 and sub ground line 36 are driven to a stable state. Therefore, at the time of transition to the active cycle, the sub power supply line 3
2 and the voltage level of the auxiliary ground line 36 can be prevented from becoming unstable due to insufficient standby cycle time,
Accordingly, the internal operation can be started at a high speed after the start of the active cycle.

As shown in FIG. 23, in the active cycle, switching transistors SWa and SWb are both on, voltage Vccs on sub power supply line 32 is at the level of power supply voltage Vcc, and the voltage on sub ground line 36 is Is at the level of the ground voltage Vss.

Referring to FIG. 23, when a standby cycle is entered at time t0, switching transistor SW
a and SWb are both turned off. An off-leak current flows through the switching transistors SWa and SWb. On the other hand, in logic circuit 40, the current of sub power supply line 32 is consumed by the off-leak current (and tunnel leak current) of MIS transistors PQb and PQd. Therefore, voltage Vcc on sub power supply line 32
s is the leak current (off-leak current and gate tunnel current) supplied by the switching transistor SWa
Then, the leakage current flowing through MIS transistors PQb and PQd gradually changes to a voltage level in a state of equilibrium. Similarly, the voltage Vs
ss shifts to a voltage level where the leakage current flowing through the MIS transistors NQa and NQc and the leakage current flowing through the switching transistor SWb are balanced. Balanced voltage Vce of these voltages Vccs and Vsss
The transition to Vse and Vse takes a long time due to the leak current, and at time t1, these voltages Vccs and Vsss reach balanced voltages Vce and Vse, respectively.

At the time of transition from the standby cycle to the active cycle, switching transistors SWa and SWb having a relatively large current driving capability provide
The voltages on sub power supply line 32 and sub ground line 36 return to power supply voltage Vcc and ground voltage Vss, respectively. However, before entering the standby cycle and before time t1,
When the active cycle starts again, the voltage levels of voltages Vccs and Vsss of sub-power supply line 32 and sub-ground line 36 at the time of transition to the active cycle are the voltage levels in the transient state, and the starting voltage level at the time of transition to the active cycle is Therefore, the time required to recover the voltage levels of the sub power supply line and the sub ground line is different from the voltage Vccs
And Vsss. Therefore, after the transition to the active cycle, the time during which the voltage Vccs on the sub-power supply line 32 and the voltage Vsss on the sub-ground line 36 are in a definite state varies, the operation speed of the transistor differs, and a malfunction occurs due to a shift in internal operation timing. May occur.

Therefore, as shown in FIG. 22, the voltage adjusting circuit 42 constantly generates the balanced voltages Vce and Vse, and forcibly forces these sub-power supply lines 32 and sub-ground lines 3
6 is driven to the equilibrium voltages Vce and Vse shortly after the transition to the standby cycle. Thereby, after transition to the standby cycle, the time Tt at which the voltages Vccs and Vsss reach an equilibrium state is equivalently shortened, and the starting voltage levels of the voltages Vccs and Vsss at the transition to the active cycle can be made the same. Eliminate variations in the recovery time of the power supply voltage during cycle transition,
Ensure accurate and stable internal circuit operation.

FIG. 24 is a circuit diagram showing the voltage adjustment circuit 42 shown in FIG.
FIG. 3 is a diagram showing the configuration of FIG. 24, a voltage adjustment circuit 42 includes a replica circuit 42a for generating balanced voltages Vce and Vse, and a balanced voltage Vce from replica circuit 42a.
a differential amplifier 42b for differentially amplifying the reference voltage Vref1 corresponding to ce and the voltage of the node 42h;
Reference voltage Vref corresponding to balanced voltage Vse from 2a
Differential amplifier 4 that differentially amplifies the voltage of node 2 and the voltage of node 42i
2c, ON state in a standby cycle in response to control clock signals φ and / φ, transmission gate 42d transmitting the voltage on node 42h onto sub power supply line 32, and control clock signals φ and / φ. And transmission gate 42e conducting in the same phase as transmission gate 42d and transmitting the voltage on node 42i onto sub-ground line 36.

The differential amplifier 42b includes a replica circuit 42a
Of the reference voltage Vref1 on the output node 42f and the voltage on the node 42h, and the result of the differential amplification is transmitted to the node 42h. Therefore, node 42h
, A balanced voltage Vce having the same voltage level as the reference voltage Vref1 is generated.

The differential amplifier 42c also has a replica circuit 4
The reference voltage Vref2 on the output node 42g of 2a and the voltage of the node 42i are differentially amplified, and the result of the differential amplification is transmitted to the node 42i. Therefore, this node 42
The voltage on i also becomes the same voltage level as reference voltage Vref2, and balanced voltage Vse is generated at node 42i.

Replica circuit 42a is connected between power supply node 1 and node 42f and has a gate connected to power supply node 1 for P channel MIS transistor SW1r.
And an N-channel MIS connected between node 42g and ground node 2 and having its gate connected to ground node 2
Transistor SW2r, power supply node 1 and node 42g
-Channel MIS transistor RP1 and N-channel MIS transistor RN1 connected between ground node 2 and ground node 2, and node 42f
-Channel MIS transistors RP2 and N connected between MIS transistors RP1 and RN1 and having their gates connected to MIS transistors RP1 and RN1 respectively.
Includes channel MIS transistor RN2. The thickness of the gate insulating film of the MIS transistors RP1 and RN2 is large and is set to the thickness Tox2, and the thickness of the gate insulating film of the MIS transistors RN1 and RP2 is Tox1.

This replica circuit 42a is a simulation circuit of the logic circuit 40 and the switching transistors SWa and SWb shown in FIG. That is, the MIS transistor RP1 is different from the MIS transistor PQ shown in FIG.
a and PQc, and a MIS transistor RP2
Is the MIS connected to the sub power supply line 32 shown in FIG.
Represents transistors PQb and PQd. Also MI
S transistor RN1 represents MIS transistors NQa and NQc shown in FIG. 22, and MIS transistor RN2 represents MIS transistors NQb and NQd shown in FIG. The MIS transistor SW1r
And SW2r represent the switching transistors SWa and SWb shown in FIG.

In replica circuit 42a and logic circuit 40 shown in FIG. 22, MIS transistors SW1r and M
The size (the ratio of gate width / gate length) of IS transistor RP2 is set to be equal to the ratio of the total size of switching transistor SWa and MIS transistors PQb and PQd. Here, the total size of the MIS transistors PQb and PQd is the total value of the current driving capability, and indicates the total of the ratio of the channel width to the channel length. Similarly, the size ratio (the ratio between the channel width and the channel length) between the MIS transistor SW2r and the MIS transistor RN1 is the switching transistor SWb shown in FIG.
And the total size of the MIS transistors NQa and NQc (the total current driving force, which is the sum of the ratio of the channel width to the channel length). MIS transistors RP1 and RN2 are connected to replica circuit 4
2a corresponds to a reduction in the total size of MIS transistors PQa and PQc, and MIS transistor RN2 is a MIS transistor NQ shown in FIG.
This corresponds to a proportional reduction of the total size of b and NQd.

In the replica circuit 42a, the size of each component is determined so as to simulate the current flowing through the sub power supply line 32 and the sub ground line 36 in the standby state. The components are reduced according to the reduction ratio. In the standby cycle, input signal IN (see FIG. 22) is at L level,
Therefore, the replica circuit 42a in FIG. 24 simulates the standby current flowing through the logic circuit 40 and the voltages of the sub power supply line 32 and the sub ground line 36 during the standby cycle.

In replica circuit 42a, node 42
The voltage Vref1 of f is determined by the sum of the off-leak current Ioffc supplied from the MIS transistor SW1r, the gate tunnel current between the gate and the drain of the MIS transistor SW1r, and the off-leak current Ioff1 and the gate tunnel current flowing through the MIS transistor RP2. You. The gate tunnel current between the gate and the drain of the MIS transistor SW1r indicates that the MIS transistor SW1r is in the off state and the off-leak current I
offc. Therefore, the voltage Vref1 of this node 42f is a voltage level at which the off-leak current Ioffc of the MIS transistor SW1r and the off-leak current Ioff1 of the MIS transistor RP2 are approximately balanced. That is, the reference voltage Vref1 is
The sum of the off-leak currents flowing through MIS transistors PQb and PQd of logic circuit 40 in FIG. 22 and the voltage level of voltage Vccs in which the off-leak current flowing through switching transistor SWa is balanced is equal.

The reference voltage Vref2 is also determined by M
Neglecting the gate tunnel current of IS transistor SW2r, the voltage level at which off-leak currents Ioff2 and Ioffs of MIS transistors RN1 and SW2r are balanced is maintained. The off-leak currents Ioff2 and Ioffs are equivalent to the off-leak current flowing through the MIS transistors NQa and NQc and the off-leak current flowing through the switching transistor SWb in FIG. 22, respectively. Therefore, this reference voltage Vref2 is equal to voltage Vs on sub-ground line 36 during the standby cycle.
ss is equal to the equilibrium voltage level.

The reference voltages Vref1 and Vref2 are
Received by differential amplifiers 42b and 42c, balanced voltages Vce and Vse equal to reference voltages Vref1 and Vref2 are generated at internal nodes 42h and 42i. In the standby cycle, transmission gates 42d and 42e are turned on, so that sub power supply line 32 and sub ground line 36 are driven by differential amplifiers 42b and 42c, respectively, and these sub power supply line 32 and sub ground line 36 Is driven at high speed to the voltage levels of balanced voltages Vce and Vse.

Therefore, as shown in FIG. 23, at the time of transition from the active cycle to the standby cycle,
The voltage adjusting circuit 42 can drive the sub-power supply line 32 and the sub-ground line 36 to the voltage levels of the balanced voltages Vce and Vse at high speed. Therefore, when shifting from the standby cycle to the active cycle,
The voltage levels of the sub power supply line 32 and the sub ground line 36 can be prevented from changing from the transient state, and the internal circuit can be operated accurately and early at the time of transition to the active cycle.

The voltage adjusting circuit 42 is formed by the same manufacturing process as the switching transistors SWa and SWb and the logic circuit 40. Therefore, voltage adjusting circuit 42 can also monitor fluctuations in power supply voltage Vcc and changes in temperature with respect to the actual circuit, and generate balanced voltages Vce and Vse adapted to changes in these power supply voltages and operating temperatures. Thus, the balanced voltages Vce and Vse can be stably and accurately generated and transmitted to the sub power supply line 32 and the sub ground line 36 irrespective of changes in the operating environment.

Further, by using the replica circuit 42a, the influence of the gate tunnel current (current between the gate and the drain) flowing through the MIS transistor in the off state and the gate tunnel current flowing through the MIS transistor in the on state can be ensured. The effects of the leakage current caused by the gate tunnel current and the off-leak current can be accurately monitored, and the reference voltages Vref1 and Vref2 can be generated.

[First Modification] FIG. 25A schematically shows a structure of a first modification of the sixth embodiment of the present invention. In FIG. 25A, a plurality of sub power supply lines 32-1 to 32-n are provided for a main power supply line 30. These sub power supply lines 32-1 to 32-n are connected to P-channel M
It is coupled to main power supply line 30 via switching transistors SWC-1 to SWC-n formed of IS transistors.

The main ground line 34 is connected to the sub ground line 36-1.
To 36-n. These auxiliary ground lines 36-1 to 36-1
36-n are switching transistors SWS-1 to SWS each configured by an N-channel MIS transistor.
It is coupled to main ground line 34 via Sn. Sub power line 3
2-i and the auxiliary ground line 36-i, the CMOS logic circuit 4
0-i is provided (i = 1-n).

Switching transistors SWC-1 to SWC-S
WC-n and SWS-1 to SWS-n are the sub power supply lines 3 of the corresponding CMOS logic circuits 40-1 to 40-n, respectively.
The size (the ratio of the channel width to the channel length) is set according to the size of the MIS transistor connected to 2-1 to 32-n and the MIS transistor connected to sub-ground lines 36-1 to 36-n. . CMOS logic circuit 40-
1 to 40-n are input signals IN1-IN, respectively.
The connection of the MIS transistor to the sub power supply line, the main power supply line, the sub ground line and the main ground line is determined according to the logic level in the n standby cycle.

Switching transistors SWC-1 to SWC-1
By adjusting the sizes of WC-n and SWS-1 to SWS-n individually according to the configuration of corresponding CMOS logic circuits 40-1 to 40-n, sub power supply lines 32-1 to 32-32 in the standby cycle are provided. -N voltage Vccs1-V
ccsn to the balanced voltage Vce, and
The voltages Vss1-Vssn of 6-1 to 36-n are made to coincide with the same voltage Vse in the standby cycle.

Therefore, as shown in FIG.
During the active cycle, these sub power supply lines 32
-1 to 32-n are at the voltage Vcc level, and the voltages Vss1-Vssn of the sub-ground lines 36-1 to 36-n are at the same level.
Is the ground voltage Vss during the active cycle,
When a standby cycle is entered and the control clock signal φ goes high and the complementary control clock signal / φ goes low and the switching transistors SWC-1 to SWC-n and SWS-1 to SWS-n are turned off, By the gate tunnel current and the off-leak current, these sub power supply lines 32-1 to 32-n and sub ground lines 36-1 to 36-1
36-n are the same balanced voltages Vce and Vs
e.

When shifting from the standby cycle to the active cycle, the voltage levels of sub power supply lines 32-1 to 32-n and sub ground lines 36-1 to 36-n are all the same,
Even if these CMOS logic circuits 40-1 to 40-n are operated at the same timing in an active cycle, the recovery time of the power supply voltage and the ground voltage is the same in these CMOS logic circuits 40-1 to 40-n. A malfunction due to a timing mismatch due to an unstable signal can be prevented from occurring.

FIG. 26 is a diagram showing an example of the configuration of the CMOS logic circuit 40-i (i = 1-n) shown in FIG. In FIG. 26, this CMOS logic circuit 40-i
Are P-channel MIS transistors PQ1-PQ4;
N-channel MIS transistors NQ1-NQ4 connected in series with these MIS transistors PQ1-PQ4
including.

In the standby cycle, input signal I
N is at L level, MIS transistors PQ1 and PQ3 have their sources connected to main power supply line 30, and MIS transistors PQ2 and PQ4 have their sources connected to sub power supply line 3.
2-i. Similarly, the MIS transistor NQ1
And NQ3 have their sources connected to sub-ground line 36-i, and MIS transistors NQ2 and NQ4 have their sources connected to main ground line 34. Since MIS transistors NQ1, NQ3, PQ2, and PQ4 are off during the standby cycle, the gate insulating film is thinned (thickness Tox1), while MIS transistors PQ1,
The thicknesses of the gate insulating films of PQ3, NQ2 and NQ4 are increased to a thickness Tox2.

The switching transistor SWC-i between the sub-power supply line 32-i and the main power supply line 30 has an off-leakage current / gate tunnel current of MI in the standby cycle.
The size (the ratio between the channel width and the channel length) is set so as to be balanced with the leak current (the sum of the off-leak current and the gate tunnel current) flowing through S transistors PQ2 and PQ4. Switching transistor SW
Si is set to have a size (ratio of channel width to channel length: W / L) such that a leakage current flowing through MIS transistors NQ1 and NQ3 and its off-leakage current and gate tunnel current are balanced in a standby cycle. You.

In the standby cycle, MIS
Transistors PQ1 and PQ3 are on. However, the thickness of the gate insulating film is Tox2, and the gate tunnel current is almost suppressed. MIS transistors PQ2 and PQ4 each having a thin gate insulating film are off in the standby cycle, and off-leakage current flows between the drain and the source as shown by the arrow in FIG. At this time, a gate tunnel current also flows between the gate and the drain. However, the MIS transistor P
Q2 and PQ4 are off in the standby cycle, and the gate tunnel current is extremely small. In MIS transistors NQ1 and NQ3, a gate tunnel current flows from the drain to the gate, and
An off-leak current flows between the sources. The gate tunnel current of these MIS transistors NQ1 and NQ3 is a sufficiently small value. This gate tunnel current is
The current of the sub-ground line 36-i is hardly affected. Therefore, by adjusting the sizes of switching transistors SWC-i and SWS-i in consideration of only the factor of the off-leakage current, the voltage of sub power supply line 32-i and sub ground line 36-i during the standby cycle is adjusted. Can be set to a predetermined voltage level.
At the time of this size adjustment, the MIS transistors PQ2 and PQ4
Is the sum of the off-leakage currents of the switching transistors S
The size of the switching transistor SWC-i is determined so that the off-leak current flowing through the WC-i becomes equal (the voltage level of the voltage Vccs in the standby cycle reaches a predetermined equilibrium value). The same applies to the switching transistor SWS-i.

[Modification 2] FIG. 27 schematically shows a structure of a modification 2 of the embodiment 6 of the invention. FIG.
7, a voltage adjustment circuit 52 is provided commonly to the power supply system (sub power supply line and sub ground line) of the CMOS logic circuits 40-1 to 40-n. CMOS logic circuit 40-1
To 40-n and the switching transistor SWC-1
To SWC-n and SWS-1 to SWS-n are shown in FIG.
This is the same as the configuration shown in FIG. Therefore, in the standby cycle, these sub power supply lines 32-1 to 32-1
The size (the ratio of the channel width to the channel length) of the switching transistors SWC-1 to SWC-n is adjusted so that the voltage of 32-n becomes equal to the balanced voltage Vce. These switching transistors SWS- are controlled so that the voltage becomes the balanced voltage Vse.
The sizes of 1 to SWS-n are adjusted. These structures are the same as the structure shown in FIG.

Voltage adjusting circuit 52 is provided commonly to sub-power supply lines 32-1 to 32-n and sub-ground lines 36-1 to 36-n. This voltage adjusting circuit 52 includes a replica circuit for one CMOS logic circuit and corresponding switching transistors SWC and SWS, and generates balanced voltages Vce and Vse during a standby cycle. The configuration of voltage adjusting circuit 52 is the same as the configuration shown in FIG. 24, and generates balanced voltages Vce and Vse based on the leak current of the replica circuit.

In response to control clock signal / φ, output voltage Vce of voltage adjusting circuit 52 is supplied to sub power supply lines 32-1 to 32 through transfer gates (or transmission gates) PX1 to PXn which are rendered conductive during a standby cycle.
-N. Balanced voltage Vse from voltage adjusting circuit 52 is supplied to sub-ground lines 36-1 to 36-n via transfer gates (or transmission gates) NX1-NXn which are turned on in the standby cycle in response to control clock signal φ. Is transmitted to In FIG. 27, transfer gates PX1-PXn are represented by P-channel MIS transistors, and transfer gates NX1-PXn are shown.
1-NXn is represented by an N-channel MIS transistor. These transfer gates PX1-PXn and NX1
-NXn may be configured with a CMOS transmission gate.

The sizes of switching transistors SWC-1 to SWC-n are adjusted so that the equilibrium voltages of the sub power supply lines 32-1 to 32-n in the standby cycle are the same, and the sub ground line 36-1 The sizes of the switching transistors SWS-1 to SWS-n are adjusted such that the equilibrium voltages during the standby cycle of the power supply transistors 36-n are the same. Therefore, the voltages of sub-power supply lines 32-1 to 32-n and the voltages of sub-ground lines 36-1 to 36-n that are finally reached in the standby cycle are all the same. Therefore, during the standby cycle, the balanced voltage Vce from one voltage adjusting circuit 52 is transferred to transfer gate P
By transmitting the signals to the sub-power supply lines 32-1 to 32-n via X1-PXn and to the sub-ground lines 36-1 to 36-n via the transfer gates NX1 to NXn,
The voltages of these sub-power supply lines 32-1 to 32-n can be driven to the balanced voltage Vce level at a high speed.
The voltages of 1 to 36-n can also be driven to the balanced voltage Vse at high speed during the standby cycle. Therefore,
At the time of transition from the standby cycle to the active cycle, the voltage levels of these sub power supply lines 32-1 to 32-n are all the same, and the voltage of sub ground lines 36-1 to 36-n at the time of transition from the standby cycle to the active cycle All the levels can be the same, and these sub power supply lines 32-1 to 32-1 due to the length of the standby cycle can be obtained.
32-n voltage level variation and sub-ground line 36-n.
1 to 36-n can be prevented, and these CMs can be set at an early timing after transition to the active cycle.
The operating power supply voltage of the OS logic circuits 40-1 to 40-n can be stabilized, and the stability of the operation of the internal circuit can be guaranteed.

[Third Modification] FIG. 28 schematically shows a structure of a third modification of the sixth embodiment of the present invention. The configuration shown in FIG. 28 differs from the configuration shown in FIG. That is, the sub power supply lines 32-1 to 32-1
32-n, transmission gates CTM1, which conduct in a standby cycle in response to control clock signals φ and / φ from control clock signal generation circuit 54,
CTM2,..., CTMn-1 are provided. In addition, transmission gates STM1, STM2,..., STMn which conduct to standby ground in response to control clock signals φ and / φ from control clock signal generation circuit 54 also apply to sub-ground lines 36-1 to 36-n. -1 is provided. Therefore, in the standby cycle, these transmission gates CTM1-CT
Mn-1 interconnects sub-power supply lines 32-1 to 32-n, and transmits transmission gates STM1-ST.
The sub ground lines 36-1 to 36-n are interconnected by Mn-1. The other configuration is the same as the configuration shown in FIG. 25A, and the corresponding portions are denoted by the same reference numerals and detailed description thereof will not be repeated.

Control clock signal generating circuit 54 generates control clock signals φ and / φ according to internal operation instruction signal φACT. During the standby cycle,
The switching transistors SWC-1 are controlled so that the voltage levels of the balanced voltages of the sub-power supply lines 32-1 to 32-n are the same.
To SWC-n, and the switching transistors SWS so that the balanced voltages of the sub-ground lines 36-1 to 36-n are the same in the standby cycle.
-1 to SWS-n are adjusted in size. Therefore, in the standby cycle, the transmission gates CTM1-CTMn-1 activate the sub power supply lines 32-1 to 32-3.
2-n and the transmission gate S
By using TM1-STMn-1, the auxiliary ground lines 36-1 to 36-36
−n, these sub-power lines 32
-1 to 32-n during the standby cycle can be stabilized to the same balanced voltage level, and the sub-ground lines 36-1 to 36-n can be similarly balanced voltage V
It can be stabilized to se.

Therefore, in the standby cycle, the voltage levels of sub power supply lines 32-1 to 32-n are reliably set to the same level, and sub ground lines 36-1 to 36-36 are set.
n is surely set to the same voltage level during the standby cycle.
To 32-n and the sub-ground lines 36-1 to 36-n can have the same voltage recovery time, and the operation start timings of the CMOS logic circuits 40-1 to 40-n in the active cycle can be made uniform. , Stable and accurate internal operation can be guaranteed.

At a high speed, these sub power supply lines 32-1
32-n and the voltages of the sub-ground lines 36-1 to 36-n can be stabilized at the balanced voltage level. In this balanced voltage, the CMOS logic circuits 40-1 to 40-40 are
The -n standby current (off-leakage current and gate tunnel current) is minimized, and the current consumption in the standby cycle can be set to the minimum.

[Modification 4] FIG. 29 schematically shows a structure of a modification 4 of the sixth embodiment of the present invention. The configuration shown in FIG. 29 differs from the configuration shown in FIG. 28 in the following points. That is, the balanced voltages Vse and Vce from voltage adjusting circuit 52 are transmitted to sub-ground line 36-n and sub-power supply line 32-n during the standby cycle, respectively. These sub-ground lines 36-1 to 36-n are interconnected by a transmission gate STM1-STMn-1 during the standby cycle.
-1 to 32-n are also interconnected by the transmission gate CTM1-CTMn-1 during the standby cycle. Therefore, during the standby cycle, the balanced voltages Vse and Vce from voltage adjusting circuit 52 are transmitted to the sub-ground line and the sub-power line, respectively, so that the voltages of sub-power lines 32-1 to 32-n can be quickly adjusted to the balanced voltage. Vce
And the auxiliary grounding lines 36-1 to 36-36
-N also has a high speed during the standby cycle and a balanced voltage Vse
Can be driven. Here, the voltage adjusting circuit includes a monitor circuit 52a including a replica circuit and balanced voltages Vse and Vce in response to control clock signals φ and / φ.
To transmission sub-ground line 36-n and sub-power supply line 32-n, respectively.
including. The monitor circuit 52a includes a CMOS logic circuit 40-
A replica circuit for 1 to 40-n is included, and the configuration is similar to the configuration shown in FIG. 24, and includes both the replica circuit and the differential amplifier.

Therefore, by utilizing the structure shown in FIG. 29, the length of the standby period is short, and sub power supply lines 32-1 to 32-n and sub ground lines 36-1 to 36-36 are provided.
It is possible to prevent a state in which the voltage levels of n differ from each other, and to stably operate the internal circuit at an early timing when shifting to the active cycle.

At a high speed, the sub power supply lines 32-1 to 32-32
n and the sub-ground lines 36-1 to 36-n reach the equilibrium voltage, and the standby current of the CMOS logic circuits 40-1 to 40-n can be driven to the minimum value at high speed. Current consumption can be reduced.

As described above, according to the sixth embodiment of the present invention, the voltage adjusting circuit drives the sub power supply line / sub ground line at high speed to the equilibrium voltage during the standby cycle or the sub power line / sub ground line. The equilibrium voltage of the lines is set to the same voltage level, which prevents the fluctuation of the operating power supply voltage recovery time due to the standby cycle period length at the time of transition to the active cycle, and stabilizes the internal circuit operation at high speed with the transition to the active cycle When can be done.

Seventh Embodiment FIG. 30 is a diagram schematically showing a sectional structure of a CMOS inverter circuit having an SOI (silicon-on-insulator) structure used in a seventh embodiment of the present invention. In FIG. 30, SO
The MIS transistor having the I structure is formed in a semiconductor layer on the surface of a buried oxide film (insulating film) 61 formed on the surface of a silicon (Si) substrate 60. N-type impurity regions 63a and 63b are formed on buried oxide film 61 at intervals. A P-type impurity region is formed between these N-type impurity regions 63a and 63b. A gate electrode 67 is formed on P-type impurity region 65 via a gate insulating film 69a. Impurity regions 63a, 63b and 65, gate insulating film 69a and gate electrode 67 form an N-channel MIS transistor. P-type impurity region 65 is called a body region and functions as a substrate region of this N-channel MIS transistor. A bias voltage to be described later is applied to the body region 65.

On buried oxide film (insulating film) 61, P-type impurity regions 64a and 64b are further formed at intervals, and these impurity regions 64a and 64b
An N-type impurity region 66 is formed therebetween. A gate electrode 68 is formed on the N-type impurity region 66 via a gate insulating film 69b.
Is formed. An element isolation insulating film 62b formed of, for example, a silicon oxide film is formed between impurity regions 63b and 64a. Outside the impurity regions 63a and 64b, insulating films 62a and 62c for element isolation formed of, for example, a silicon oxide film are formed, respectively.

P channel M is formed by impurity regions 64a, 64b, 66, gate insulating film 69b and gate electrode 68.
An IS transistor is formed. Impurity region 66 functions as a substrate region of the P-channel MIS transistor, and is called a body region.

[0224] The transistor having such an SOI structure is as follows.
Since the junction capacitance is small and no substrate leakage current is generated (because a buried oxide film (insulating film) is formed), there is an advantage that high-speed operation is performed and leakage current is small.

However, even in such an SOI transistor, the gate insulating films 69a and 69a
When the thickness of b is reduced to, for example, 3.0 nm, a gate tunnel current occurs.

FIG. 31A schematically shows a planar layout of the N-channel MIS transistor shown in FIG. In FIG. 31, the gate electrode layer 6 has a T-shape.
7, impurity regions 63a and 63b are separated by a P-type impurity region formed thereunder. A high-concentration P-type impurity region 70 is formed facing these N-type impurity regions 63a and 63b. High-concentration P-type impurity region 70 is coupled to P − -type impurity region 65 in the body region formed below gate electrode 67 to transmit bias voltage Vbp.

FIG. 31B is a diagram schematically showing the distribution of the depletion layer and the inversion layer of the MIS transistor shown in FIG. In FIG. 31B, impurity regions 63a and 63b function as a source and a drain, respectively. In this case, the thickness of the inversion layer is gradually reduced from the impurity region 63a in the source region toward the impurity region 63b in the drain region. A depletion layer 72 is formed below the inversion layer 71. The thickness of the depletion layer 72 decreases as the distance from the impurity region 63a gradually increases (due to the effect of the voltage applied from the gate electrode 67). Next, when approaching the drain impurity region 63b, the thickness of the depletion layer 72 increases again due to the drain electric field. A bias voltage Vbp is applied via the impurity region 70 to the body region where the depletion layer and the inversion layer are formed. By applying the bias voltage Vbp to this body region, the so-called “substrate floating effect” can be prevented,
The effect of the residual charge can be prevented. In the body region as shown in FIG. 31B, depletion layer 72 is formed only in a part of the body region, and the SOI structure shown in FIGS. 31A and 31B is formed. MIS
The transistor is called a partially depleted MIS transistor.

FIG. 32 schematically shows another planar layout of the MIS transistor having the SOI structure. In the layout shown in FIG. 32, impurity regions 63a and 63b are separated by a P-type impurity region formed below gate electrode layer 67. Also, this gate electrode 6
7, the impurity region 63a and the high-concentration P-type impurity region 73 are separated by the gate electrode portion extending in the horizontal direction in FIG. A P-type impurity region is formed between impurity region 73 and impurity region 63. This impurity region 7
Reference numeral 3 is electrically connected to a P-type impurity region formed below the gate electrode 67 in the shape of a triangle, and transmits the bias voltage Vbp to the body region. Even in the arrangement shown in FIG. 32, bias voltage Vbp can be transmitted to the body region. In the structure shown in FIG. 32 as well, a partially depleted MIS transistor is realized.

FIG. 31 shows a P-channel MIS transistor.
In (A) and FIG. 32, the P-type and the N-type are interchanged to obtain the planar layout.

In the seventh embodiment, a partially depleted MIS transistor having this SOI structure is used.

FIG. 33A shows Embodiment 7 of the present invention.
1 is a diagram showing an example of a configuration of a semiconductor device according to FIG. FIG.
In (A), a CMOS circuit including an SOI transistor as a component is used. This CMOS circuit has 4
Stage CMOS inverters IV1-IV4. These CMOS inverters IV1-IV4 include P-channel MIS transistors SPQ1-SPQ4 having an SOI structure,
SOI structure N-channel MIS transistor SNQ1-
Includes SNQ4. These MIS transistors SPQ1
-SPQ4 and SNQ1-SNQ4 each have a thickness Tox whose gate insulating film provides a gate tunnel barrier comparable to that of a silicon oxide film having a thickness of 3 nm. In this case, a large gate tunnel current flows through the ON-state MIS transistor. In order to prevent this, N body regions of MIS transistors SPQ1-SPQ4 are commonly connected, and the voltage of N body region 76 is switched according to the standby cycle and the active cycle. Also, the MIS transistors SNQ1-SN
Also in Q4, the voltage level of P body region 75 is similarly switched according to the standby cycle and the active cycle. That is, N body region 76
At the time of the standby cycle, the MIS transistor SP
A bias voltage for turning off Q1-SPQ4 is applied, and in the active cycle, the bias of N body region 76 of these MIS transistors SPQ1-SPQ4 is made shallow so that these MIS transistors SPQ1-SPQ4 operate at high speed. To work with.

MIS transistors SNQ1-SN
Also in Q4, the bias voltage of P body region 75 is increased during the standby cycle to set MIS transistors SNQ1-SNQ4 to the off state, thereby reducing the off leak current and the gate tunnel current. on the other hand,
In the active cycle, the P body region 7
5 and the MIS transistor SNQ1
-Operate SNQ4 at high speed.

In the configuration shown in FIG.
The logic level of the input signal IN during the standby cycle may be undefined. By the bias voltages of N body region 76 and P body region 75, MIS transistors SPQ1-SPQ4 and SNQ1-SNQ4 are all turned off, and both the gate tunnel current and off leak current are reduced.

FIG. 33 (B) is a signal waveform diagram representing an operation of the semiconductor device shown in FIG. 33 (A). First, FIG.
As shown in (B), in the standby cycle, high voltage Vpp is applied to N body region 76,
The absolute values of the threshold voltages of these MIS transistors SPQ1-SPQ4 are increased, and all of them are turned off regardless of the voltage level applied to the gate. In the N body region 76, at the interface of the insulating film, even if the MIS transistors SPQ1 to SPQ4 receive the L-level signal at the gate due to the high voltage Vpp, no inversion layer is formed and no gate tunnel current occurs. At most, a tunnel current between the gate and the drain only occurs, but this is extremely small and can be almost ignored. Also, an N-channel MIS transistor SNQ
Also in 1-SNQ4, negative voltage VBB is applied to P body region 75 during the standby cycle,
IS transistors SNQ1-SNQ4 are turned off, and the gate tunnel current is sufficiently suppressed.

On the other hand, in the active cycle,
Power supply voltage Vcc is applied to N body region 76, and ground voltage GND (= Vss) is applied to P body region 75.
Is applied. MIS transistors SPQ1-SPQ4
In SNQ1-SNQ4, the back gate and the source are at the same potential, the absolute value of the threshold voltage is sufficiently small, and because of the characteristics of the transistor having the SOI structure, no substrate leakage current occurs and the junction capacitance is small. In this active cycle, it operates at high speed.

[Modification] FIG. 34A shows a structure of a modification of the seventh embodiment of the present invention. FIG. 34
In the configuration shown in (A), input signal IN is fixed at L level during a standby cycle. MIS transistor SPQ which is turned on during the standby cycle in accordance with the logic level of this input signal IN during the standby cycle
1 and SPQ3 have their body regions commonly coupled to N body region 76. On the other hand, MIS transistors SPQ2 and SPQ which are turned off during the standby cycle
4 has its body region coupled to the power supply node and is kept at the same voltage level as its source. Similarly, also in N channel MIS transistors SNQ1-SNQ4, MIS transistors SNQ2 and SNQ4 which are turned on in the standby cycle have their body regions commonly coupled to P body region 75, and are turned off in the standby cycle. SNQ1 and SN
Q3 has its body region coupled to the ground node, and its source and body regions are held at the same voltage.

These MIS transistors SPQ1-S
PQ4 and SNQ1-SNQ4 are all transistors having an SOI structure, and have a thin gate insulating film (Tox). In the standby cycle, as shown in FIG.
High voltage Vpp is applied to P body region 75 and negative voltage VB is applied to P body region 75.
B is applied. Although the input signal IN is at the L level,
Due to the high voltage Vpp of N body region 76, MIS transistors SPQ1 and SPQ3 are turned off,
Gate tunnel current is suppressed. Also, in MIS transistors SNQ2 and SNQ4, P body region 75 is at a negative voltage, and MIS transistors SNQ2 and SNQ4 are off, and gate tunnel current is suppressed.

Therefore, when the logic level of the input signal IN during the standby cycle is known, the bias of the body region of the MIS transistor which is turned on during the standby cycle is increased, so that even if the gate insulating film is thin, Gate tunnel current can be suppressed.

In the active cycle, N body region 76 receives power supply voltage Vcc, and P body region 75 receives ground voltage GND (= Vss). Therefore, these MIS transistors SPQ1-SPQ4
And SNQ1-SNQ4 operate at high speed in accordance with input signal IN to generate output signal OUT.

In the seventh embodiment, the structure of switching the voltages of N body region 76 and P body region 75 can use the structure of the well bias circuit shown in FIG. In a semiconductor device using an MIS transistor having such an SOI structure, off-leakage current can be reduced by using a power supply arrangement having a hierarchical structure. Alternatively, since the internal node is connected to the main ground line, the voltage level of the internal node can be held at a fixed state during a standby cycle (because a leak current flows through a transistor having a deep well bias). Output signal OU
T can be prevented from being in a logic indeterminate state, and high-speed and accurate operation can be guaranteed.

As described above, according to the seventh embodiment of the present invention, the bias of the body region of the transistor having the SOI structure is changed in accordance with the operation cycle, and the transistor having the thin gate insulating film has the SOI structure. Even if it is used, it is possible to obtain a semiconductor device which operates at high speed with low current consumption while suppressing gate tunnel current.

[Eighth Embodiment] FIG. 35 schematically shows a sectional structure of a buried channel MIS transistor used in an eighth embodiment of the present invention. In FIG. 35, a buried channel MIS transistor includes impurity regions 81 and 82 formed on a surface of a substrate region 80 at a distance, and a thin gate insulating film formed on a channel region between these impurity regions 81 and 82. It includes a film 83 and a gate electrode 84 formed on the thin gate insulating film 83.

In the buried channel MIS transistor, when conducting, a channel (inversion layer) 85 is formed in a substrate region slightly away from the substrate surface. On the surface of the channel region, the depletion layer 86 spreads from the source to the drain region. Under the channel (inversion layer) 85, a depletion layer 87 is formed. The depletion layer capacitance formed on this surface is equivalently added to the capacitance formed by gate insulating film 83. Therefore, the thickness of the gate insulating film with respect to the gate tunnel current is equivalently increased, and the tunnel current between the inversion layer 85 and the gate electrode 84 can be suppressed. This buried channel MIS transistor is
Therefore, it can be used as a MIS transistor having a large gate tunnel barrier. That is, a buried channel MIS transistor can be used instead of a MIS transistor having a thick gate insulating film.

FIGS. 36A and 36B schematically show an impurity concentration profile of the channel region of the N-channel MIS transistor. FIG. 36A shows a channel impurity concentration profile when a P + type polysilicon gate is used as a gate electrode. P
When + polysilicon is used as the gate electrode, the difference in work function between the gate and the P-type substrate is small, and a depletion layer is hardly formed. In order to adjust the threshold voltage, an N-type impurity concentration is implanted into the surface, and then a deep portion is heavily doped with a P-type impurity concentration for forming an inversion layer. Therefore, in this case, the surface of the channel region of the P-type substrate region is an N-type region. During conduction, a depletion layer is formed in the N-type impurity region, and an inversion layer is formed in the P-type impurity region.
This inversion layer region is a channel, and this N-MIS transistor can be used as a buried channel type N-channel MIS transistor.

FIG. 36B is a diagram showing an impurity concentration profile when an N + polysilicon gate is used for an N-channel MIS transistor. When an N + polysilicon gate is used, the difference in work function between the gate and the P-type semiconductor substrate region is large, and a depletion layer is easily formed. Therefore, in this case, a high concentration P-type impurity region is formed in the channel region to form an inversion layer. The threshold voltage is adjusted by the concentration of the P-type impurity on the surface. The channel region is formed on the surface of the P-type semiconductor substrate region, and a surface channel type N-channel MIS transistor is formed.

FIG. 37A is a diagram showing an impurity concentration profile of a channel region of a P-channel MIS transistor using an N-type semiconductor substrate region. An N + polysilicon gate is used as the gate electrode. When N + polysilicon is used as the gate electrode, the difference in work function between the gate and the N-type semiconductor substrate region is small, and a depletion layer is not easily formed. Therefore, in order to easily form a depletion layer and adjust the threshold voltage, a P-type impurity concentration is implanted into the surface of this channel region, and N
A peak concentration region of the type impurity is formed. Therefore,
In the MIS transistor using the N + polysilicon gate, when conducting, the P-type impurity region functions as a depletion layer, and the N-type impurity implantation region functions as an inversion layer.
Therefore, in FIG. 37A, a buried channel type P-channel MIS transistor is formed.

When a P + polysilicon gate is formed on the surface of an N-type semiconductor substrate region as shown in FIG. 37B, the difference in work function between the gate electrode and the substrate region is large, and a depletion layer is easily formed. Is formed. An N-type impurity for adjusting a threshold voltage is implanted into the surface of the channel region, and an N-type impurity region having a peak concentration for forming an inversion layer is formed therein. In the case of the structure shown in FIG. 37B, when conducting, an inversion layer is formed over the entire N-type impurity region on the surface. When a P + polysilicon gate is used, a surface channel P-channel MIS transistor is formed.

Here, the peak concentration region of the surface channel type MIS transistor is a region having a depth substantially equal to the junction depth of the source / drain diffusion layers, and suppresses the short channel effect and the increase in the substrate bias effect.

Therefore, FIG. 36 (A) and FIG.
By using the MIS transistor having the impurity concentration profile shown in FIG.
An S transistor can be realized, and the gate tunnel current can be suppressed accordingly.

FIG. 38A shows Embodiment 8 of the present invention.
1 is a diagram showing an example of a semiconductor device according to FIG. FIG. 38
The configuration shown in FIG. 3A corresponds to the configuration shown in FIG. 3, and in the configuration shown in FIG.
Instead of transistors, buried channel type MIS transistors BQ1-BQ4 are used. The input signal IN is
As shown in FIG. 38B, buried channel type MIS transistors BQ1 to BQ4 are used as MIS transistors which are at the L level in the standby cycle and turned on in the standby cycle. Even if the gate insulating film has a small thickness Tox1, these M
IS transistors BQ1-BQ4 are embedded channel type M
In the ON state, a depletion layer is formed on the surface when the transistor is turned on. The equivalent gate capacitance of the depletion layer and the gate insulating film is large. Does not occur.

[Modification] FIG. 39A shows a structure of a modification of the eighth embodiment of the present invention. This FIG.
The structure illustrated in FIG. 19A corresponds to the semiconductor device illustrated in FIG. In FIG. 39A, the input signal IN is
As shown in (B), it is at the L level during the standby cycle. In this case, the MIS transistor which is turned on during the standby cycle is provided with a buried channel type MIS transistor.
Transistors BQa, BQb, BQc and BQd are used. These MIS transistors BQa-BQd
Are the MIS transistors PQ shown in FIG.
a, NQb, PQc, and NQd. The buried channel type MIS transistors BQa-BQd have a gate insulating film thickness of Tox1.

Control clock signals φ and / φ are at H level during the standby period, respectively, as shown in FIG.
Level and L level. Therefore, switching transistors SWa and SWb are off in the standby cycle, and gate insulating film thickness T
ox1 MIS transistors PQb and PQd, NQ
In a and NQc, a gate tunnel current hardly occurs, and an off-leak current is suppressed.

On the other hand, although the buried channel MIS transistors BQa-BQd having the gate insulating film thickness Tox1 are turned on during the standby cycle, the gate insulating film is equivalently formed by the depletion layer formed on the surface of the channel region. The gate tunnel current is suppressed accordingly.
Therefore, by using the buried channel MIS transistors BQa-BQd as the MIS transistors that are turned on during the standby cycle, the gate tunnel current can be sufficiently suppressed even when the gate insulating film is thin. .

The power supply switching transistor SW
a and SWb may also be buried channel MIS transistors having a thin gate insulating film.

Further, the buried channel type MIS transistor can be applied to the MIS transistor which may cause a gate tunnel current in the first to seventh embodiments.

As described above, according to the eighth embodiment of the present invention, a buried channel type MIS transistor is used for a MIS transistor which may cause a gate tunnel current, and this gate is surely used. Tunnel current can be suppressed, and power consumption of the semiconductor device during the standby period can be reduced.

[Ninth Embodiment] FIG. 40A shows an N-channel MIS used in a ninth embodiment of the present invention.
FIG. 3 is a diagram schematically illustrating a cross-sectional structure of a transistor. FIG.
At 0 (A), the N-channel MIS transistor
N-type impurity regions 91a and 91b formed at intervals on the surface of P-type semiconductor substrate 90, and a gate electrode formed via a gate insulating film 94 on a channel region between these impurity regions 91a and 91b. 92. This gate electrode 92 is doped with an N-type impurity, but the amount of doping is made slightly smaller than in the case of an N + -doped polysilicon gate of a normal surface channel MIS transistor. When the N-doped polysilicon is used as the gate electrode 92, an inversion layer 93 is formed in the channel region of the P-type substrate 90 when the MIS transistor is turned on. At this time, in the gate electrode 92, the depletion layer 92a is formed wider in a portion in contact with the gate insulating film 94. This is because when N-doped polysilicon is used as the gate electrode 92, the energy band bending during conduction is larger than when N + -doped polysilicon is used as the gate electrode, and a depletion layer is easily formed. . The depletion layer 92a is a region where no electric charge exists, and functions as an insulating film. Therefore, the gate insulating film 94 and the wide depletion layer 92a
2 and the inversion layer 93, the thickness of the insulating film with respect to the gate tunnel current becomes equivalently thicker correspondingly, and the gate tunnel barrier increases. Therefore, the gate insulating film 9
4, a gate tunnel current can be suppressed by the depletion layer 92a even if a thin gate insulating film (thickness Tox1) is used.

FIG. 40B shows a ninth embodiment of the present invention.
FIG. 4 is a drawing schematically showing a cross-sectional structure of a P-channel MIS transistor used in the embodiment. In FIG. 40B, a P-channel MIS transistor has P-type impurity regions 96a and 96b formed on the surface of N-type substrate 95 at intervals, and a channel region between these impurity regions 96a and 96b. It includes a gate electrode 97 formed with a gate insulating film 99 interposed therebetween. The gate electrode 97 is formed of P-doped polysilicon, and the MIS transistor
This is a surface channel type MIS transistor. However, the amount of the P-type impurity doped into the gate electrode 97 is reduced. Therefore, when the inversion layer 98 is formed in the channel region during conduction of the MIS transistor, a wider depletion layer 97a is formed in the gate electrode 97 due to band bending at the interface between the insulating films.

Therefore, also in the structure shown in FIG. 40B, since gate insulating film 99 and wide depletion layer 97a are interposed between gate electrode 97 and inversion layer 98, the thickness of gate insulating film 99 is reduced. The thickness can be equivalently increased, and the gate tunnel current can be suppressed.

In the ninth embodiment, FIG.
A gate depletion type MIS transistor shown in FIGS. 1A and 1B is used as a MIS transistor having a large gate tunnel barrier.

FIG. 41 shows an example of a structure of a semiconductor device according to the ninth embodiment of the present invention. The configuration of the semiconductor device illustrated in FIG. 41 corresponds to the configuration of the semiconductor device illustrated in FIG. In the structure shown in FIG. 41, MIS transistors PQ1 and PQ1 having a thick gate insulating film shown in FIG.
A gate depletion type MIS transistor GQ having a gate insulating film thickness Tox1 instead of Q3, NQ2 and NQ4
1-GQ4 is used. The input signal IN is at the L level during standby. Therefore, the gate depletion type MIS transistors GQ1 to GQ4 are used as MIS transistors which are turned on in the standby state and in which a gate tunnel current may flow. The remaining MIS transistors NQ1 and PQ that are turned off in the standby state
2, NQ3 and PQ4 have gate insulating film thickness Tox
One surface channel type MIS transistor is used. In the gate depletion type MIS transistors GQ1 to GQ4, a wide depletion layer is formed in the gate electrode from the interface of the insulating film to the gate electrode in the ON state, thereby suppressing the gate tunnel current. Therefore, even when the thickness of the gate insulating film is small (the thickness Tox1), the gate tunnel current can be sufficiently suppressed.

[Modification] FIG. 42 shows a structure of a semiconductor device according to a modification of the ninth embodiment of the present invention. The semiconductor device shown in FIG. 42 corresponds to the semiconductor device having the hierarchical power supply structure shown in FIG. In the semiconductor device shown in FIG. 42, in the configuration of the semiconductor device shown in FIG.
Instead of MIS transistors PQa, PQc, NQb and NQd which are turned on during a standby cycle, gate depletion type MIS transistors GQa, GQb, GQc
And GQd are used. The other configuration is the same as the configuration shown in FIG.

In the hierarchical power supply structure shown in FIG. 42, gate depletion type MIS transistors GQa-GQd are used as MIS transistors in an on state where a gate tunnel current may flow in a standby state. Therefore, in the case of the configuration shown in FIG. 42, the gate tunnel current during the standby period can be suppressed, and the off-leak current flowing through the MIS transistor in the off state can be reduced.

It should be noted that a gate depletion type MIS transistor (gate insulating film thickness Tox1) may be used as switching transistors SWa and SWb. Another MIS transistor having a large gate tunnel barrier may be used.

This gate depletion type MIS transistor has:
Embodiments 1 to 7 can be applied to MIS transistors in which gate tunnel current may occur.

As described above, according to the ninth embodiment of the present invention, since the gate depletion type MIS transistor is used for the MIS transistor which is turned on in the standby state, the gate tunnel current during the standby period is reduced. And the current consumption during the standby period can be reduced accordingly.

[Tenth Embodiment] FIG. 43 shows a structure of a semiconductor device according to a tenth embodiment of the present invention. In FIG. 43, the semiconductor device includes four-stage CMOS inverter circuits IVa-IVd. The output of the CMOS inverter circuit IVc is
This is fed back to the input of Vb. Therefore, these CMOS inverter circuits IVb and IVc form an inverter latch.

The CMOS inverter circuit IVa includes a P channel MIS transistor PT1 and an N channel MIS
CMOS inverter circuit I including transistor NT1
Vd is equal to the P-channel MIS transistors PT2 and N
Includes channel MIS transistor NT2. These M
IS transistors PT1, PT2, NT1 and NT2
Has a thickness Tox1.

CMOS inverter circuit IVb includes a P channel MIS transistor PTR1 and an N channel MI
The CMOS inverter circuit IVc includes an S transistor NTR1 and includes a P-channel MIS transistor PTR2 and an N-channel MIS transistor NTR2. These CMOS inverter circuits IVa-IVd use the voltage of power supply node 1 and the voltage of ground node 2 as operating power supply voltages.

CMOS inverter circuits IVb and IV
c included in the MIS transistors PTR1, PTR2,
NTR1 and NTR2 have gate tunnel barriers with C
It is made larger than the gate tunnel barrier of the transistors of MOS inverter circuits IVa and IVd. These MIS transistors PTR1, PTR2, NTR1 and NTR2 may be MIS transistors having a thick gate insulating film, and the MIS transistors having a deep well bias may be used.
An S transistor may be used, and a buried channel type MIS
It may be a transistor, and a gate depletion type MIS
It may be a transistor. In the following description, an MIS transistor having a large gate tunnel barrier for suppressing the gate tunnel current is referred to as a “tunnel current reduction M”.
IS transistor (ITR transistor) ". For other circuits such as a logic circuit, an MIS transistor with a thin gate insulating film is used.

As shown in FIG. 43, IT is applied to the latch circuit.
R transistors PTR1, PTR2, NTR1 and N
By utilizing TR2, the logic level of input signal IN is changed in accordance with the operation state, and in the standby state, inverter IVb constituting this latch circuit
Even when the logic levels of latch signals IVc and IVc cannot be predicted in advance, an ITR transistor is used between power supply node 1 and ground node 2 to suppress gate tunnel current.

[First Modification] FIG. 44 shows a structure of a first modification of the tenth embodiment of the present invention. In FIG. 44, the semiconductor device includes a clocked CMOS inverter circuit that latches signals at nodes 100a and 100b. This clocked CMOS inverter circuit includes an ITR connected in series between power supply node 1 and ground node 2.
Includes transistors PTR3, NTR3 and NTR4. The gates of ITR transistors PTR3 and NTR3 are connected to node 100b. Set signal SET is applied to the gate of ITR transistor NTR4.

Similarly, the other CMOS inverter circuit
I connected in series between power supply node 1 and ground node 2
TR transistors PTR4, NTR5, and NTR6
including. The gates of ITR transistors PTR4 and NTR5 are connected to node 100a, and a reset signal RST is supplied to the gate of ITR transistor NTR6. Output signal OUT is generated from node 100b.

The semiconductor device further includes a node 100
P-channel ITR transistor PTR5 which conducts in response to set signal SET for transmitting the voltage of power supply node 1 to node 100a, and conducts when reset signal RST is at L level for setting signal states of a and 100b And a P-channel ITR transistor PTR6 transmitting the voltage on power supply node 1 to node 100b. These ITR transistors PTR3-PTR6 and NT
As described above, the gate tunnel barrier of R3-NTR6 is sufficiently large, and the gate tunnel current is suppressed. The operation of the semiconductor device shown in FIG. 44 will now be described with reference to a signal waveform diagram shown in FIG.

In the standby state (latch state), set signal SET and reset signal RST are both at H level, and ITR transistors PTR5 and PTR6 are both off, while ITR transistors NTR4 and NTR6 are on. . Therefore, nodes 100a and 100b are kept in the set state or the reset state. MIS transistors NTR4 and NTR6 are ITR transistors, and have a sufficiently small gate tunnel current even in the ON state. MIS transistors PTR3, PTR
4, NTR3 and NTR5 are also ITR transistors, and the gate tunnel current is sufficiently small. Therefore, regardless of the signal voltage level of nodes 100a and 100b, that is, regardless of the signal level of this CMOS inverter latch, the gate tunnel current is sufficiently suppressed.

When set signal SET falls to L level, ITR transistor PTR5 is turned on, and ITR transistor PTR5 is turned on.
The transistor NTR4 is turned off, and the node 100 is turned off.
a is driven to the power supply voltage level. ITR transistor PTR6 is off, and when the voltage level of node 100a attains an H level, ITR transistor PTR4,
The voltage level of node 100b is set to L level by the CMOS inverter circuit by NTR5 and NTR6. When set signal SET attains H level, nodes 100a and 100b are held at H level and L level, respectively. Therefore, output signal OUT falls from H level to L level in response to the fall of set signal SET (at the time of transition from the reset state to the set state).

Next, when the reset signal RST falls to the L level when the semiconductor device is in the set state, I
TR transistor PTR6 is turned on, while I
TR transistor NTR6 is turned off. Node 1
00b is driven to H level, and accordingly, node 100a is driven to L level by ITR transistors PTR3, NTR3 and NTR4. Reset signal RS
When T rises to the H level, nodes 100a and 10a
0b is held at the L level and the H level, respectively. Therefore, when reset signal RST falls to L level, output signal OUT rises to H level.

In the semiconductor device shown in FIG. 44, during operation, set signal SET and reset signal R
ST is driven to the L level to be set to the set and reset states. However, in a standby state in which both set signal SET and reset signal RST are held at H level, nodes 100a and 100b
Is held at H level and L level or L level and H level. Even in this state, the latch circuit
Since a TR transistor is used, the gate tunnel current is sufficiently suppressed.

The ITR transistor PT for setting
R5 and reset ITR transistor PTR6
Is off in the standby state, and is selectively turned on only when setting / resetting the semiconductor device. Therefore, ITR transistors PTR5 and PTR6 may be formed of MIS transistors having a thin gate insulating film.

[Modification 2] FIG. 46 shows a structure of a modification 2 of the tenth embodiment of the present invention. In FIG. 46, P connected between power supply node 1 and ground node 2
Channel MIS transistor PTR7 and N channel MI
The S transistor NTR7 forms one CMOS inverter circuit. Similarly, P-channel MIS transistor PTR8 and N-channel MIS transistor NTR8 connected between power supply node 1 and ground node 2 are connected to another C
A MOS inverter circuit is configured. These CMOS inverter circuits form a latch circuit. That is, M
The drains of IS transistors PTR8 and NTR8 are connected to the gates of MIS transistors PTR7 and NTR7. MIS transistors PTR7 and N
The drain of TR7 is connected to the gates of MIS transistors PTR8 and NTR8. These MIS transistors PTR7, PTR8, NTR7 and NTR8
Are all composed of ITR transistors. Transfer gate XF1, which conducts in response to control clock signals φX and / φX, is connected to the gates of MIS transistors PTR7 and NTR7. The flow of the signal via the transfer gate XF1 is determined by the current driving force of the MIS transistors PTR7, PTR8, NTR7 and NTR8. When the current driving capability of the CMOS inverter circuit composed of MIS transistors PTR8 and NTR8 is large, a signal is output from the latch circuit to the outside via transfer gate XF1. On the other hand, MIS transistors PTR7 and NT
When the current driving capability of R7 is large, a signal is externally applied to this latch circuit via transfer gate XF1.

In the standby state, control clock signals φX and / φX are at L level and H level, respectively, transfer gate (transmission gate) XF1 is off, and MIS transistors PTR7, PTR8, NTR7 and NTR8 are in the latch state. It is in. In this state, the logic level of the latch signal is determined by the logic level of the signal applied in the previous active cycle. However, whatever the logic level of this latch signal, these MIS transistors PTR7, PTR8, NTR7 and NTR8
Are all ITR transistors, and the gate tunnel current is sufficiently suppressed.

In the standby state, transfer gate XF1 is off, and almost no gate tunnel current is generated. Even if this transfer gate XF1 is formed of a MIS transistor having a thin gate insulating film, no gate tunnel current is generated. There is no increase problem.

As described above, Embodiment 10 of the present invention
According to the above, the components of the latch circuit are composed of ITR transistors, and the gate tunnel current during the latch state can be suppressed.

[Eleventh Embodiment] FIG. 47 shows a structure of a semiconductor device according to an eleventh embodiment of the present invention. In FIG. 47, the semiconductor device includes an active latch circuit AL for latching a signal activated and applied during an active period, and a standby latch circuit SL for holding a latch signal of the active latch circuit AL during a standby period. Active latch circuit AL is coupled to a logic circuit via transfer gate XF2 which conducts in response to control clock signals φX and / φX.

Active latch circuit AL is formed of CMOS including MIS transistors PQ10 and NQ10.
Inverter and MIS transistors PQ11 and NQ
11 includes a CMOS inverter circuit. These CMOS inverter circuits are coupled to power supply node 101 and ground node 102. MIS transistor P
The drain node 106a of Q11 and NQ11
Coupled to the gates of IS transistors PQ10 and NQ10. The transfer gate XF2
Coupled to the gates of IS transistors PQ10 and NQ10. These MIS transistors PQ10,
PQ11, NQ10 and NQ11 are MIS transistors having a thin gate insulating film (thickness Tox1).

Standby latch circuit SL includes a CMOS inverter circuit composed of a P-channel MIS transistor PTR10 and an N-channel MIS transistor NTR10 coupled between power supply node 1 and ground node 2, and a power supply node 1 and a ground node 2. A P-channel MIS transistor PTR11 and an N-channel MIS transistor NTR11 are connected in series. These M
IS transistor PTR10, PTR11, NTR10
And NTR11 are ITR transistors with reduced gate tunnel current. MIS transistor PTR
11 and the drain node 106b of the NTR 11
Connected to the gates of IS transistors PTR10 and NTR10. Each of these latch circuits AL and SL forms a so-called inverter latch circuit.

This semiconductor device further includes a node 106
a and 106b, transfer control signals φA and φB
Transfer circuit 105 that transfers signals bidirectionally according to
including. The bidirectional transfer circuit 105 is provided with a transfer instruction signal φ
A clocked inverter circuit 105a inverting the signal on node 106a in response to A and transmitting the inverted signal to node 106b.
Clocked inverter circuit 1 for transferring the signal at node 106b to node 106a in accordance with transfer instructing signal φB.
05b.

At the time of transition from the active period to the standby period, transfer instruction signal φA is activated, and the signal on node 106a is transmitted to node 106b. On the other hand, at the transition from the standby period to the active period, transfer instruction signal φB is activated, and the signal on node 106b latched by standby latch circuit SL is transferred to active latch circuit AL. Next, the operation of the semiconductor device shown in FIG. 47 will be described with reference to a signal waveform diagram shown in FIG.

During the active period, control clock signal φ
X is at H level, transfer gate XF2 is on, and active latch circuit AL is coupled to a logic circuit. The active latch circuit AL latches a signal applied from a logic circuit or supplies a signal latched by the active latch circuit AL to the logic circuit.

When the active period ends and the standby period starts, first, transfer instructing signal φA is activated, the signal on node 106a is transmitted to node 106b, and the signal on node 106b is latched by standby latch circuit SL. Is done. After the transfer of the signal to standby latch circuit SL is completed, the active latch circuit stops the supply of the power supply voltage to power supply node 101 or activates the gate tunnel current reduction circuit provided for nodes 101 and 102. The gate tunnel current in active latch circuit AL is reduced.
Therefore, in active latch circuit AL, after the signal transfer to standby latch circuit SL is completed, the logic level of the holding signal at node 106a is in an indefinite state. On the other hand, the standby latch circuit SL is connected to the power supply node 1
Supplies an operating power supply voltage at all times, and latches the signal at node 106b.

At the end of the standby period and the transition to the active period, first, transfer instructing signal φB is activated, and the signal at node 106b is transmitted to node 106a via clocked inverter circuit 105b. As a result, the active circuit AL returns to the state in which the signal latched in the previous active cycle is held.
Here, before activation of transfer instruction signal φB, power supply voltage Vcc and ground voltage GN are applied to power supply node 101 and ground node 102 of active latch circuit AL.
D (= Vss) is supplied.

When the signal transfer to active latch circuit AL is completed, control clock signal φX goes high.
And the active latch circuit AL is coupled to the logic circuit.

Therefore, during the standby period, the ITR
Standby latch circuit S composed of transistors
The signal is latched by L, while the active latch circuit is set in a state where the gate tunnel current is suppressed. Therefore, current consumption during the standby period can be reduced. At the time of transition to the active period, the signal stored in the standby latch circuit SL has been transferred to the active latch circuit AL, and the active latch circuit can be accurately restored to the original state.

FIG. 49A schematically shows a structure of a portion generating transfer instructing signals φA and φB shown in FIG. In FIG. 49A, a transfer instruction signal generating unit generates a standby instruction signal φSTB in accordance with an operation mode instruction signal CMD, and responds to activation of standby instruction signal φSTB from mode detection circuit 110. One-shot pulse generation circuit 111 for generating a one-shot pulse signal, inverter 112 for inverting standby instruction signal φSTB, and one-shot pulse generation for generating a one-shot pulse signal in response to the rise of the output signal of inverter 112 Circuit 1
13, the output signal of the one-shot pulse generation circuit 113 and the standby instruction signal φS from the mode detection circuit 110.
Includes NOR circuit 115 receiving TB. Transfer instruction signal φA is output from one-shot pulse generation circuit 111,
Transfer instruction signal φ from one-shot pulse generation circuit 113
B is generated, and the control clock signal φX is output from the NOR circuit 115. Next, the operation of the transfer instruction signal generating section shown in FIG. 49A will be described with reference to a signal waveform diagram shown in FIG.

During the active period, the mode detection circuit 11
0 maintains the standby instruction signal φSTB at L level. Therefore, the one-shot pulse signals φA and φ
B is not generated. Therefore, during this active period, control clock signal φX from NOR circuit 115 is at H level, and transfer gate X shown in FIG.
F2 is turned on.

When operation mode instruction signal CMD applied to mode detection circuit 110 is an active period end instruction signal (for example, a sleep mode instruction signal), mode detection circuit 110 raises standby instruction signal φSTB to an H level. In response to the rise of standby instruction signal φSTB, one-shot pulse generation circuit 111 generates a one-shot pulse signal, and transfer instruction signal φA is activated. At this time, standby instruction signal φSTB
Clock control signal φX from NOR circuit 115 falls to L level. Therefore, when transfer gate XF2 in FIG. 47 is turned off, a signal is transferred from active latch circuit AL to standby latch circuit SL by bidirectional transfer circuit 105. When transfer instruction signal φA is inactivated, a mechanism for reducing gate tunnel current of active latch circuit AL is activated (activation of gate tunnel current reduction circuit or stop of power supply).

Next, when operation mode instruction signal CMD gives an instruction to end the standby period (for example, when a sleep mode end instruction signal is given), mode detection circuit 110
Lowers standby instructing signal φSTB to L level. In response to the fall of standby instruction signal φSTB, the output signal of inverter 112 rises, one-shot pulse generation circuit 113 generates a one-shot pulse signal, and transfer instruction signal φB is activated accordingly. Even when standby instruction signal φSTB attains an L level, transfer instruction signal φB is at an H level, and control clock signal φX maintains an L level. The gate tunnel current reducing mechanism is inactivated in accordance with standby instruction signal φSTB, and active power supply voltage is supplied to active latch circuit AL. Therefore, activation of transfer instruction signal φB causes standby latch circuit SL
Is transferred to the active latch circuit AL, the transfer signal is reliably latched by the active latch circuit AL.

In the structure shown in FIG. 49A, NOR circuit 115 is set in response to the rise of transfer instruction signal φB and reset in response to the fall of standby instruction signal φSTB. Set /
A reset flip-flop may be used. After the transfer instructing signal φB is inactivated and the transfer of the signal from the standby latch circuit SL to the active latch circuit AL is completed, the control clock signal φX can be set to the H level.

The gate tunnel current reducing mechanism for active latch circuit AL is inactivated in response to inactivation of standby instruction signal φSTB.
A structure that is activated in response to the fall of transfer instruction signal φA may be used. For example, the rising delay signal of standby instruction signal φSTB can be used as a signal for controlling the gate tunnel current reducing mechanism of active latch circuit AL.

Control clock signal φX may be formed by inverting the fall delay signal of standby instructing signal φSTB.

[Modification 1] FIG. 50 is a signal waveform diagram representing an operation of a modification 1 of the embodiment 11 of the invention. In the first modification, the semiconductor device shown in FIG. 47 is used. That is, an active latch circuit AL and a standby latch circuit SL are used, and a signal is transferred by the bidirectional transfer circuit 105 between the active latch circuit AL and the standby latch circuit SL.

In the configuration of the first modification, first, transfer instruction signal φA changes in synchronization with control clock signal φX. Therefore, during the active period, the latch signal of active latch circuit AL is transmitted to standby latch circuit SL via bidirectional transfer circuit 105. Therefore, during this active period, the active latch circuit A
When an operation is performed on L and the logical level of the latch signal changes, the signal change of the active latch circuit AL is transmitted to the standby latch circuit SL via the bidirectional transfer circuit 105 immediately.

In the standby cycle, control clock signal φX attains L level, and transfer gate X
F2 is turned off. At the same time, the transfer instruction signal φ
A goes low, and the clocked inverter circuit 105
a becomes an output high impedance state. In response to the inactivation of control clock signal φX, active latch circuit AL and standby latch circuit SL are disconnected from each other, and active latch circuit AL has its gate tunnel current reducing mechanism activated and active latch circuit AL Are in an indeterminate state. However, the standby latch circuit SL keeps latching the applied signal during this standby period (because the power supply voltage is supplied).

At the end of the standby period and the transition to the active period, first, transfer instruction signal φB is activated, and the signal latched by standby latch circuit SL is transmitted to active latch circuit AL via bidirectional transfer circuit 105. Will be transferred. At this time, the active latch circuit A
The gate tunnel current reduction mechanism of L becomes inactive,
The active latch circuit AL surely latches a signal supplied from the standby latch circuit SL via the bidirectional transfer circuit 105.

When transfer instruction signal φB is inactivated, control clock signal φX and transfer instruction signal φA attain an active state of H level. Therefore, the change in the latch signal of active latch circuit AL is immediately transmitted to standby latch circuit SL again.

This standby latch circuit SL is formed of an ITR transistor having a large gate tunnel barrier, and has a lower operation speed than an MIS transistor having a thin gate insulating film. Therefore, the standby latch circuit S
By transferring the latch signal from the active latch circuit AL to L during the active period, it is not necessary to consider the latch / transfer timing, and the transfer period at the transition to the standby period can be shortened. , Can be transferred from the active latch circuit AL to the standby latch circuit SL and latched by the standby latch circuit SL.

Although the standby latch circuit SL has a lower operation speed than the active latch circuit AL, it latches a signal in the standby state, and the latch signal is in a definite state, and shifts from the standby period to the active period. Sometimes, the standby latch circuit SL
When the signal is transferred to the active latch circuit AL via the bidirectional transfer circuit 105 in accordance with the latch signal, the active latch circuit AL can accurately latch the transferred signal at high speed.

FIG. 51A schematically shows a structure of a control signal generator for generating control clock signal φX and transfer instruction signals φA and φB shown in FIG.
In FIG. 51A, a control signal generating section activates standby instruction signal φSTB when standby mode is designated according to operation mode instruction signal CMD, and a standby instruction signal φSTB
Set / reset flip-flop 117 which is set in response to the rising edge of a clock signal, and standby instruction signal φSTB.
Is delayed for a predetermined period, and standby instructing signal φSTB
And a one-shot pulse generation circuit 118 that generates a one-shot pulse signal in response to the rising edge of the output signal of the inversion delay circuit 116. Set / reset flip-flop 117 is reset in response to the fall of the one-shot pulse from one-shot pulse generation circuit 118. From output / Q of set / reset flip-flop 117, transfer instruction signal φA and control clock signal φ
X is output. Next, the operation of the control signal generator shown in FIG. 51A will be described with reference to a signal waveform diagram shown in FIG.

During the active period, standby instructing signal φSTB is at L level, set / reset flip-flop 117 is in the reset state, and control clock signal φX and transfer instructing signal φA are both at H level. When operation mode instruction signal CMD specifies the standby mode, standby instruction signal φSTB rises to H level. In response to the rise of standby instructing signal φSTB, set / reset flip-flop 117
Is set, and control clock signal φX and transfer instruction signal φA fall from H level to L level. At this time, the power supply voltage of active latch circuit AL is controlled in response to the rise of standby instruction signal φSTB (activation of gate tunnel current reduction mechanism such as stop of power supply voltage).

When operation mode instruction signal CMD instructs the end of the standby period, standby instruction signal φSTB from mode detection circuit 115 is inactivated. Inversion delay circuit 116 delays standby instruction signal φSTB by a predetermined time. During the delay time of inversion delay circuit 116, power supply recovery to active latch circuit AL is performed in response to inactivation of standby instruction signal φSTB (inactivation of gate tunnel current reduction mechanism). After a predetermined period has elapsed, the output signal of inverting delay circuit 116 rises, and one-shot pulse generating circuit 118
Is activated for a predetermined period. After transfer instruction signal φB reaches L level, set / reset flip-flop 117 is reset, and transfer instruction signal φA and control clock signal φX rise to H level. Therefore, after the signal is transferred from standby latch circuit SL to active latch circuit AL, active latch circuit AL sets the corresponding transfer gate XF
2 to a logic gate.

After the power supply voltage to active latch circuit AL is restored, the latch signal is transferred from standby latch circuit SL to active latch circuit AL, and active latch circuit AL must accurately latch the transferred signal. Can be.

Note that the clocked inverter circuits 105a and 105b of the bidirectional transfer circuit have both the gate tunnel current and the sub-threshold leakage current (off-leakage current) by forming the MIS transistor for the clock control part by an ITR transistor. Can be reduced.

[Modification 2] FIG. 52 is a signal waveform diagram representing an operation of a modification 2 of the embodiment 11 of the invention. 52, the semiconductor device used includes active latch circuit AL, standby latch circuit SL, and bidirectional transfer circuit 105 shown in FIG. In the second modification, data transfer between active latch circuit AL and standby latch circuit SL is performed in accordance with active cycle defining signal φACTA which defines a cycle in which active latch circuit AL operates.

When active cycle instruction signal φACTA is activated, transfer instruction signal φB is first activated.
In bidirectional transfer circuit 105, data transfer from standby latch circuit SL to active latch circuit AL is performed. At this time, the active latch circuit AL
, The power supply voltage is stabilized. When transfer instruction signal φB is inactivated and the signal transfer from standby latch circuit SL to active latch AL is completed, control clock signal φX is activated, and transfer gate XF2 is turned on. Thereby, the active latch circuit AL is coupled to the corresponding logic circuit, and processing such as transfer of a latch signal or latching of a signal from the logic circuit is performed.

When the processing for active latch circuit AL is completed, transfer instruction signal φA is activated with a delay of a predetermined time from the rise of control clock signal φX. Clocked inverter circuit 105a is activated in accordance with activation of transfer instruction signal φA, and a signal is transferred from active latch circuit AL to standby latch circuit SL. When the signal transfer from active latch circuit AL to standby latch circuit SL is completed and a predetermined time has elapsed, active cycle instruction signal φACTA is inactivated, and the operation cycle for active latch circuit AL is completed. In response to the deactivation of active cycle instruction signal φACTA, the power supply voltage to active latch circuit AL is controlled to reduce the gate tunnel current (for example, the supply of the power supply voltage is cut off). Standby latch circuit SL receives and processes the signal processed by active latch circuit AL in response to activation of transfer instruction signal φA during the activation period of active cycle instruction signal φACTA. Therefore, high-speed operability can be ensured without adversely affecting the logic processing speed during the active period, and current consumption during the standby period can be reduced. Since then
This operation is repeatedly performed each time the operation on active latch circuit AL is performed.

FIG. 53 is a diagram schematically showing a configuration of a control signal generating portion for generating each signal shown in FIG. FIG.
, The control signal generation unit includes the operation mode instruction signal CM
D, an active cycle instructing signal φACTA indicating a period during which operation on active latch circuit AL is performed, and an active cycle instructing signal φA from mode detecting circuit 120.
One-shot pulse generation circuit 121 for generating a one-shot pulse signal in response to activation of CTA, inverter circuit 122 for inverting the pulse signal from one-shot pulse generation circuit 121, and output signal of inverter circuit 122 An AND circuit 123 receiving cycle instruction signal φACTA, a one-shot pulse generating circuit 124 for generating a one-shot pulse signal in response to a rise (activation) of an output signal of AND circuit 123,
A delay circuit 125 for delaying a pulse signal output from the one-shot pulse generation circuit 124 for a predetermined time;
5 includes a one-shot pulse generation circuit 126 for generating a one-shot pulse signal in response to the rise of the output signal of FIG.

Transfer instruction signals φB and φA are output from one-shot pulse generation circuits 121 and 126, respectively. Further, control clock signal φX is generated from one-shot pulse circuit 124. Delay circuit 125 has a delay time equal to the period required for the processing of the signal to active latch circuit AL and for the latch signal of active latch circuit AL to be in a defined state.

In the control signal generating portion shown in FIG. 53, when an operation mode designating signal (or command) CMD is applied, mode detection circuit 120 provides an active cycle designating signal for a period during which operation on active latch circuit AL is performed. Activate φACTA. this is,
For example, the entire device including the active latch circuit operates in synchronization with clock signal CLK, and when operation mode designating signal CMD designates a certain operation mode, active cycle designating signal φACTA in synchronization with clock signal CLK. Corresponds to, for example, a configuration that is activated for a predetermined period in synchronization with the activation timing of the active latch circuit after a predetermined cycle of the clock signal elapses.

Active cycle instruction signal φACT
When A is activated, the one-shot pulse generation circuit 12
1 is activated, and the signal is transferred from standby latch circuit SL to active latch circuit AL. Active cycle instruction signal φAC
When TA is activated and transfer instruction signal φB is deactivated, one-shot pulse generation circuit 124 activates control clock signal φX. More specifically, in active latch circuit AL, power supply control is performed by active cycle instructing signal φACTA to restore the power supply voltage, and after completion of data transfer from standby latch circuit SL, control clock signal φX is activated to activate active latch circuit AL. Circuit AL is coupled to a corresponding logic circuit.

When control clock signal φX is activated, transfer instruction signal φA changes to one-shot pulse generation circuit 126 after the delay time of delay circuit 125 has elapsed.
Generated by Therefore, after signal processing of the active latch circuit AL by the logic circuit is completed and the latch signal of the active latch circuit AL is determined, the transfer instruction signal φA is activated, and the signal from the active latch circuit AL to the standby latch circuit SL is activated. Is executed. The signal of standby latch circuit SL is transferred in the cycle in which the processing for active latch circuit AL is executed, and there is no need to provide a special cycle for this transfer. The signal transfer of the circuit SL does not adversely affect the processing operation of the logic circuit, and a reduction in the operation speed of the entire device is prevented.

Note that control clock signal φX is inactivated at an appropriate timing when transfer instruction signal φA is activated, and transfer gate XF2 is turned off.

[Third Modification] FIG. 54 is a signal waveform diagram representing an operation of a third modification of the eleventh embodiment of the present invention. In the third modification, the clock signal CLK defines an operation cycle. The configuration of the semiconductor device is the same as the configuration shown in FIG. 47, and includes an active latch circuit AL and a standby latch circuit SL;
Includes transfer gate XF2 coupling active latch circuit AL to a logic circuit. Next, the operation of the third modification will be described with reference to a signal waveform diagram shown in FIG.

In cycle # 1 of clock signal CLK, active cycle instruction signal φACTA is activated according to the operation mode instruction signal. In accordance with activation of active cycle instruction signal φACTA, power supply recovery processing for active latch circuit AL is performed. When the power supply recovery process for the active latch circuit AL is completed, the transfer instruction signal φB is activated, and the signal latched at the node 106b of the standby latch circuit SL is transferred to the active latch circuit AL via the bidirectional transfer circuit 105. Is transferred to the node 106a. Accordingly, the signal potential of node 106a of active latch circuit AL becomes
The signal potential level is defined by the latch signal of the standby latch circuit SL.

In cycle # 2 of clock signal CLK, control clock signal φX, which is an activation signal for active latch circuit AL, is activated, and active latch circuit AL is coupled to the logic circuit via transfer gate XF2. The logic circuit performs processing on the signal latched by active latch circuit AL.

In cycle # 2 of clock signal CLK, necessary processing is performed, and signal processing for active latch circuit AL is performed. In accordance with this signal processing, the signal potential of node 106a of active latch circuit AL changes. This change timing is determined by the signal processing timing of the logic circuit. Therefore,
In FIG. 54, the signal potential change timing of the node 106a is shown with a certain time width.

When the processing for active latch circuit AL is completed in clock cycle # 2, control clock signal φX is inactivated in the next cycle # 3. When control clock signal φX is inactivated, transfer instructing signal φA is subsequently activated, and the signal latched by active latch circuit AL is applied to standby latch circuit S
L. When the signal transfer to standby latch circuit SL is completed, power supply control for active latch circuit AL is performed, and gate tunnel current is reduced.

Active cycle instruction signal φACTA
May be inactivated in clock cycle # 3, or may be kept active while another logic circuit is operating.

As shown in FIG. 54, the signal is transferred from the active latch circuit to the standby latch circuit SL in the cycle following the cycle in which the signal processing for the active latch circuit AL is performed, whereby the active latch circuit AL is transferred. There is no need to determine the cycle period of the clock signal in consideration of the transfer time from the active latch circuit SL to the standby latch circuit SL. Current consumption can also be reduced.

FIG. 55 is a diagram schematically showing a configuration of a control signal generating portion for generating each signal shown in FIG. FIG.
, The control signal generation unit includes the operation mode instruction signal CM
D and the clock signal CLK, and the clock signal C
At the rise of LK, mode detection circuit 130 for activating active cycle instruction signal φACTA in accordance with the state of operation mode instruction signal CMD, shifter 131 for transferring active cycle instruction signal φACTA in accordance with clock signal CLK, and output signal of shifter 131 a set / reset flip-flop 132 which is set in response to the rise of φSH to set control clock signal φX to an H level;
A shifter 133 for transferring in accordance with K, a one-shot pulse generation circuit 134 for generating a one-shot pulse signal in response to a rise of an output signal of shifter 133, a delay circuit 135 for delaying active cycle instruction signal φACTA for a predetermined time, A one-shot pulse generation circuit 136 for generating a one-shot pulse signal in response to the rise of the output signal of delay circuit 135 is included.

Set / reset flip-flop 132
, Control clock signal φX is output, and one-shot pulse generation circuits 134 and 136 output transfer instruction signals φA and φB, respectively. Delay circuit 135
Has a delay time equal to the time required for the operation power supply voltage recovery of active latch circuit AL when active cycle instruction signal φACTA is activated. By providing this delay circuit 135, at the time of transition to the active cycle, after the power supply voltage of the active latch circuit AL is sufficiently recovered, the signal is transferred from the standby latch circuit SL to the active latch circuit AL. Guarantees the proper signal latch.

Shifters 131 and 133 each transfer and delay the applied signal over a predetermined clock cycle period. Therefore, shifters 131 and 1
Each of the reference numerals 33 can set its delay time in a unit of a half cycle of the clock signal CLK. By adjusting the number of transfer cycles of shifter 131, the clock cycle period in which control clock signal φX is activated can be set to both cycles # 1 and # 3 shown in FIG. By using the shifter 133, after the control clock signal φX becomes inactive,
Transfer instruction signal φA can be generated. The shifter 133 can also adjust the activation period of the control clock signal φX in half clock cycle units.

The control signal generating portion is further set / reset flip-flop 137 which is set in response to the rise of active cycle instruction signal φACTA and reset in response to the fall of transfer instruction signal φA.
including. This set / reset flip-flop 137
From the output Q of the set / reset flip-flop 137 as a control clock signal φ for the power switch transistor in the hierarchical power supply configuration. used).

In the signal waveforms shown in FIG. 54, when the clock transfer cycle of shifter 131 is set to 0, clock cycles # 1 and # 2 are regarded as one clock cycle, and active latch circuit and standby latch circuit SL Is performed between the signals.

[Modification 4] FIG. 56A schematically shows a structure of a modification 4 of the embodiment 11 of the invention. In the configuration shown in FIG. 56A, a plurality of stages of logic circuits LG # 1-LG # n are synchronously designed, and sequentially execute processing in accordance with activation signals φL1-φLn. Latch circuits LT # 1-LT # n are provided corresponding to these logic circuits LG # 1-LG # n, respectively. Since latch circuits LT # 1-LT # n have the same configuration,
14A representatively shows the configuration of latch circuit LT # i. The latch circuit LT # i includes an active latch circuit A
L, standby latch circuit SL, control clock signal φX
i, the active latch circuit AL and the logic circuit LG #
transfer gate XF2 coupled to circuit i, and bidirectional transfer circuit 105 for performing signal transfer between active latch circuit AL and standby latch circuit SL in accordance with transfer instruction signals φAi and φB. Transfer instruction signal φAi for controlling signal transfer from active latch circuit AL to standby latch circuit SL is supplied to latch circuit LT # 1-L
Generated individually for T♯n. On the other hand, when the standby state ends, a transfer instruction signal φB instructing a signal transfer from the standby latch circuit SL to the active latch circuit AL is given by:
It is generated commonly for latch circuits LT # 1-LT # n. Next, the operation of the semiconductor device shown in FIG.
This will be described with reference to a signal waveform diagram shown in FIG.

When the standby period is completed and the active cycle starts, first, transfer instructing signal φB is activated, and signal transfer from standby latch circuit SL to active latch circuit AL is performed in latch circuits LT # 1-LT # n. Is performed. At this time, the power supply to the active latch circuit AL for which power supply control was performed in the standby state has been restored. When active cycle instructing signal φACTA is activated, logic circuits LG # 1-LG # n are sequentially activated in accordance with activation control signals φL1-φLn, and execute processing on signals given from the preceding logic circuits, respectively. . At this time, in latch circuits LT # 1-LT # n, when activation control signal φLi for the corresponding logic circuit is activated,
Control clock signal φXi is activated at a predetermined timing, transfer gate XF2 is rendered conductive, and active latch circuit AL and logic circuit LG # i are coupled.

In logic circuits LG # 1-LG # n, operations are performed in accordance with activation control signals φL1-φLn, respectively, and the execution results are latched in active latch circuits AL of latch circuits LT # 1-LT # n. In the next cycle, the signal latched by active latch circuit AL is transferred to corresponding standby latch circuit SL via bidirectional transfer circuit 105. That is, in logic circuits LG # 1-LG # n, activation control signals φL1-φL
When n is activated, in the next cycle, transfer instructing signal φ
A1-φAn is activated. Therefore, the logic circuit L
In the cycle following the cycle in which G # i operates and performs signal processing, a signal is transferred from the active latch circuit to the standby latch circuit SL. Therefore, in each operation cycle, it is not necessary to consider the signal decision timing of the active latch circuit AL based on the signal processing timing of the logic circuit and the signal transfer timing to the standby latch circuit SL. To standby latch circuit S
Signals can be transferred to L, and a circuit for adjusting timing is not required, so that the number of circuit elements can be reduced and power consumption can be reduced accordingly.

FIG. 57A schematically shows a structure of a portion for generating transfer instruction signal φAi shown in FIG. 56A. In FIG. 57A, transfer instruction signal generating section includes shifter 140 for transferring activation control signal φLi for one clock cycle in synchronization with clock signal CLK, and one-shot in response to the rise of the output signal of shifter 140. It includes a one-shot pulse generation circuit 141 for generating a pulse signal. This one-shot pulse generation circuit 141
Outputs transfer instruction signal φAi. Clock signal CLK corresponds to logic circuit LG # 1-LG shown in FIG.
信号 n is a signal that defines an operation cycle. This FIG.
The operation of the transfer instruction signal generator shown in FIG.
This will be described with reference to the timing chart shown in FIG.

Active control signal φLi is applied to clock signal CLK.
When activated in synchronization with the rise of
Captures the activation control signal φLi and outputs the captured signal at the next rise of the clock signal CLK. Therefore, when activation control signal φLi is activated in clock cycle #i and activation control signal φLi + 1 for the next logic circuit LG # (i + 1) is activated in the next clock cycle # i + 1, clock cycle # i + 1 , A one-shot is generated from one-shot pulse generation circuit 141 and transfer instruction signal φA
i is activated. Therefore, the signal latched by clock cycle #i in active latch circuit AL is transferred from active latch circuit AL to standby latch circuit SL in the next clock cycle # i + 1.

It is sufficient that control clock signal φXi is activated at an appropriate timing in response to activation control signal φLi.

Active control signals φL1-φLn are generated from a shift register which performs a shift operation in synchronization with clock signal CLK when active cycle instruction signal φACTA is activated.

When logic circuits LG # 1 to LG # n perform sequential processing in a pipeline in synchronization with a clock signal, registers operating in accordance with the clock signal are provided in the input / output section of the pipeline stage. . Signal transfer between pipeline stages is performed by this register. The signal is transferred from the active latch circuit AL to the standby latch circuit SL in synchronization with the transfer of signals between pipeline stages by this register. Also in pipeline processing, signal transfer in the next cycle is realized.

[Fifth Modification] FIG. 58 is a signal waveform diagram representing an operation of a fifth modification of the eleventh embodiment of the present invention. In FIG. 58, the semiconductor device has a normal mode and a low power consumption mode. The low power consumption mode is a sleep mode in which the logic circuit stops operating in the case of a logic circuit, and is a self-refresh mode in the case of a dynamic random access memory (DRAM). In the normal mode, the semiconductor device performs a predetermined process. As shown in FIG. 58, transfer instructing signal φ
A is activated when the mode shifts from the normal mode to the low power consumption mode, and the latch signal is transferred from the active latch circuit AL to the standby latch circuit SL. This period is the low power consumption entry mode. When the low power consumption entry mode is completed, power supply control is performed in the active latch circuit, and the gate tunnel current is reduced.

When the low power consumption mode is completed, power supply control is first performed on the active latch circuit. After the power supply is restored, transfer instruction signal φB to the active latch circuit is activated, and standby latch circuit SL switches from active latch circuit AL to active latch circuit AL. Transfer of the latch signal is performed. When the activation period of the transfer instruction signal φB ends and the low power consumption exit mode is completed, the semiconductor device can execute predetermined processing.

Therefore, in the normal mode, high-speed operation is performed using the MIS transistor having a thin gate insulating film. In the low power consumption mode, the gate tunnel current is reduced by controlling the power supply voltage of the active latch circuit AL. Reduce power consumption. The signal waveform shown in FIG. 58 is provided by replacing the standby period in the waveform diagram of FIG. 48 with the period of the low power consumption mode, and a control signal for realizing the waveform shown in FIG. 58 by a corresponding control signal generation unit. The generator is realized.

As described above, Embodiment 11 of the present invention
According to the above, in the case of a latch circuit in which the logic of the signal during the standby period is not predetermined, the signal is transferred from the active latch circuit to the standby latch circuit during the standby period, and the active latch circuit is set to the gate tunnel current reduction state. Thus, power consumption due to the gate tunnel current during the standby period can be suppressed. Also, at the time of transition from the standby period to the active period, the signal latched by the standby latch circuit is transferred to the active latch circuit, and it is possible to accurately restore the latched signal. With this active latch circuit,
High-speed operation can be realized.

[Twelfth Embodiment] FIG. 59A shows an example of a structure of a semiconductor device according to a twelfth embodiment of the present invention. In FIG. 59 (A), MIS conducting between power supply node and precharge node 150 when precharge instructing signal / φPR is activated (at L level)
A transistor PTR15 is provided. N channel MI is connected in parallel between precharge node 150 and the ground node.
S transistors NQ15, NQ16 and NQ17 are provided. These MIS transistors NQ15, NQ
Input signals IN1, IN2 and IN3 are applied to the gates of Q16 and NQ17, respectively.

Precharge instructing signal / φPR is set to the active state of L level during the standby period, and precharges node 150 to the level of power supply voltage Vcc. This precharge MIS transistor PT
An RTR transistor is used for R15, and its gate tunnel current leakage is suppressed. Input signals IN1-IN3
Transistors NQ15-NQ operating in response to
The MIS transistor 17 has a thin gate insulating film. During the standby period, the input signal IN1-
IN3 are all at L level and the MIS transistor N
Q15-NQ17 maintain the off state. Next, an operation of the semiconductor device shown in FIG. 59A will be described with reference to an operation waveform diagram shown in FIG.

During the standby period, precharge instructing signal / φPR is at L level, and precharge node 150
Are precharged to the power supply voltage level by the MIS transistor PTR15 for precharging. Input signal I
N1-IN3 are all at L level, and MIS transistors NQ15-NQ17 all maintain the off state.

In the precharge state, although MIS transistor PTR15 is turned on, precharge MIS transistor PTR15 is an ITR transistor, and its gate tunnel current is sufficiently suppressed. The MIS transistors NQ15-NQ17 are
In the off state, almost no gate tunnel current occurs. The precharge MIS transistor PT
R15 is an ITR transistor. For example, when the thickness of the gate insulating film is large, the absolute value of the threshold voltage increases, and the off-leak current can be reduced accordingly.

When the active cycle starts, precharge instructing signal / φPR attains an H level, and MIS transistor PTR15 for precharging is turned off.
The MIS transistors NQ15 to NQ17 receive the input signal I
The MIS transistors NQ15-NQ17 are selectively turned on / off according to the logic levels of N1-IN3. This MIS transistor NQ1
The voltage level during the active period of precharge node 150 is determined by the on / off state of 5-NQ17. When precharge node 150 is discharged to the ground voltage level, MIS transistors NQ15-NQ17
Is a MIS transistor having a thin gate insulating film, operates at high speed, and discharges the precharge node 150 to the ground voltage level.

Therefore, as shown in FIG. 59A, precharge node 150 is precharged to a predetermined voltage level during the standby period, and the voltage level of the precharge node is determined according to the input signal during the active period. When the dynamic operation is performed, the gate tunnel current can be suppressed by using the ITR transistor as the precharge MIS transistor.

The standby period and the active period are determined by activation instruction signal ACT. Figure 59
(C) is a diagram showing a general form of a semiconductor device according to a twelfth embodiment of the present invention. In FIG. 59C, the semiconductor device includes a precharge MIS transistor PT connected between a power supply node and a precharge node 150.
R15 and the precharge node 150 are connected to the input signal (group).
And a logic circuit 155 driven according to the following. The logic circuit 155 is constituted by a thin film transistor (Tr) having a thin gate insulating film. The configuration of the logic circuit 155 is as follows.
It is appropriately determined according to each use. It is sufficient that the precharge node 150 is driven in accordance with the input signal IN during the active cycle.

[First Modification] FIG. 60A shows a structure of a first modification of the twelfth embodiment of the present invention. FIG.
The structure shown in FIG. 0 (A) is the same as the structure shown in FIG. 59 (A), and further includes a precharge MIS transistor PQ15 which is conductive between precharge node 150 and the power supply node when precharge instructing signal / φPR2 is activated. Is provided.
The MIS transistor PQ15 has a thin gate insulating film, and can operate at high speed. Precharge instruction signal / φPR2 is activated in the form of a one-shot pulse at the time of transition from the active period to the standby period. Next, the operation of the semiconductor device shown in FIG. 60A will be described with reference to a signal waveform diagram shown in FIG.

In the standby state, activation instructing signal ACT is at the L level, precharge instructing signal / φPR1 is activated at the L level, precharge MIS transistor PTR15 is turned on, and node 150 is turned on. , Are precharged to the power supply voltage Vcc level. The precharge instruction signal / φPR2 is
This is the inactive state at the H level, and the precharge MIS transistor PQ15 maintains the off state. Therefore, this precharge MIS transistor PQ15
Is in an off state, and therefore, the thin MI
MIS transistor P for precharging S transistor
The MIS transistor PQ
15 does not generate a gate tunnel current. Input signal IN
1-IN3 is at the L level during the standby period.

When the active period starts, precharge MIS transistor P is activated in accordance with activation instruction signal ACT.
TR15 is turned off. Precharge instruction signal / φ
PR2 maintains the H level. Input signal IN1-I
N3 changes during the active period, and the MIS transistors NQ15-NQ17 change the input signals IN1-IN3.
Is selectively set to the on / off state, and the voltage level of precharge node 150 is set accordingly.

When the active period is completed, precharge instructing signal / φPR1 falls from H level to L level in response to inactivation of activation instructing signal ACT, and MIS
Transistor PTR15 is turned on, and precharge node 150 is precharged to power supply voltage Vcc level. At this time, precharge instruction signal / φPR
2 is at the L level, and the MIS transistor PQ15 for precharge is turned on.

The ITR transistor has a large gate tunnel barrier to suppress the gate tunnel current, and has an increased threshold voltage. Therefore, when precharge node 150 is precharged using MIS transistor PTR15, which is an ITR transistor, there is time until the voltage level of precharge node 150 returns to power supply voltage Vcc level, and the standby period and active period Is repeatedly executed, there is a possibility that the standby period cannot be shortened. Therefore, a high-speed MIS transistor having a thin gate insulating film is replaced with a precharge M
Used as IS transistor PQ15, precharge node 150 is returned to power supply voltage Vcc level at high speed. Thus, even when the standby period is short, the precharge node 150 is reliably connected to the power supply voltage Vc.
It can be precharged to the c level, and both reduction in current consumption during the standby period and high-speed operation during the active period can be realized.

FIG. 61 schematically shows a structure of the precharge instructing signal generating portion shown in FIG. FIG.
1, the precharge instructing signal generating section includes two stages of cascaded inverter circuits 155a and 155b receiving activation instructing signal ACT, and inverter circuit 15
A one-shot pulse generation circuit 156 that generates a one-shot pulse signal that is at the L level for a predetermined period in response to the rise of the output signal of 5a is included. Inverter circuit 155
b outputs precharge instruction signal / φPR1, and one-shot pulse generation circuit 156 outputs precharge instruction signal / φPR2.

Inverter circuits 155a and 155b form a buffer circuit, and generate a precharge instructing signal / φPR1 according to activation instructing signal ACT.
On the other hand, when the active period is completed, the inverter circuit 155a
Signal rises to H level, and one-shot pulse generation circuit 156 generates a one-shot pulse signal in response to drive precharge instructing signal / φPR2 to an active state for a predetermined period at the time of transition to the standby period. Thereby, precharge instructing signals / φPR1 and / φPR2 can be activated / deactivated in accordance with each operation cycle / period.

[Modification 2] FIG. 62 is a signal waveform diagram representing an operation of a modification 2 of the twelfth embodiment of the invention. The configuration of the semiconductor device used is that shown in FIG. 60A. For precharging of precharge node 150, precharging transistor PTR which is turned on in accordance with precharge instructing signals / φPR1 and / φPR2.
15 and PQ15 are used. In the signal waveform diagram shown in FIG. 62, the gate insulating film having a thin precharge M
Precharge instructing signal / φPR2 for turning on IS transistor PQ15 is activated in the form of a one-shot pulse at the start of the active period. That is, at the time of transition from the standby period to the active period,
Precharge instructing signal / φPR2 is activated for a predetermined period, and MIS transistor PQ15 reliably precharges precharge node 150 to a predetermined voltage level.

During the standby period, the MIS transistor P
When the precharge node 150 is precharged by the TR15, the length of the standby period is short and insufficient, and even if the precharge node 150 cannot be precharged to the specified voltage, the precharge is performed at the start of the active period. By the instruction signal / φPR2,
Precharge node 150 can be precharged to a predetermined voltage level. After the completion of the precharge, the MIS transistor NQ1 according to the input signals IN1-IN3.
5-NQ 17 is selectively turned on / off.

FIG. 63 schematically shows a structure of a portion for generating the precharge instruction signal shown in FIG. 62. The precharge instruction signal generating section shown in FIG. 63 is different from the precharge instruction signal generating section shown in FIG. 61 in the following points. That is, precharge instruction signal / φPR
2 is generated from a one-shot pulse generation circuit 157 which generates a one-shot pulse signal which is at L level for a predetermined period in response to the rise of activation instruction signal ACT.
At the start of the active period, precharge instructing signal / φPR2 is driven to an active state for a predetermined period.

FIG. 64 shows a general structure of a semiconductor device according to the first and second modifications of the twelfth embodiment of the present invention. In FIG. 64, precharge node 150
A logic circuit 15 for driving the signal according to an input signal (group) IN
5 are provided. The logic circuit 155 has a MIS transistor (thin film Tr) with a thin gate insulating film as a component. Precharge node 150 has MIS transistors PTR15 and PQ15 receiving precharge instructing signals / φPR1 and / φPR2 at their gates, respectively.
Thereby, it is precharged to the power supply voltage Vcc level.
This logic circuit 155 performs a predetermined logic process and selectively drives precharge node 150, similarly to the structure shown in FIG.

[Third Modification] FIG. 65 is a signal waveform diagram representing an operation of a third modification of the twelfth embodiment of the present invention. In the third modification, the semiconductor device has a sleep mode in which the operation is stopped in addition to the standby cycle and the active cycle in the normal operation mode.
The configuration of the semiconductor device is the same as the configuration shown in FIG. 60A, and includes a MIS transistor PTR15 and a precharge instruction signal / φP formed of an ITR transistor which is turned on in response to precharge instruction signal / φPR1.
An MIS transistor PQ15 which is turned on / off in response to R2 is provided as a precharge MIS transistor. Next, the operation of the third modification of the twelfth embodiment of the present invention will be described with reference to the signal waveform diagram shown in FIG.

When sleep mode instruction signal SLEEP is at the inactive L level, the standby cycle and the active cycle are repeatedly executed in accordance with activation instruction signal ACT. This sleep mode instruction signal SLE
When EP is at L level, precharge instructing signal / φ
PR1 maintains the H level, and MIS transistor PTR15 maintains the off state. In the normal operation mode (when the sleep mode instruction signal is inactivated), precharge instruction signal / φPR2 is driven to L level and H level according to activation instruction signal ACT.
In the standby cycle, precharge instructing signal / φPR2 attains L level, MIS transistor PQ15 for precharging is turned on, and precharge node 150 is charged at high speed. On the other hand, in the active cycle, precharge instructing signal / φPR2 attains H level, and MIS transistor P for precharge P
Q15 is turned off. In this active cycle, logic circuits or MIS transistors NQ15-NQ17 selectively drive precharge node 150 to the ground voltage level according to input signals IN1, IN2 and IN3.

When sleep mode instruction signal SLEEP attains an H level and a sleep mode in which the standby state continues for a predetermined time or more is designated, precharge instruction signal /
φPR2 attains the H level, and the precharge MIS transistor PQ15 maintains the off state during the sleep mode. On the other hand, the sleep mode instruction signal SL
Precharge instruction signal / φP in response to activation of EEP
R1 goes low, MIS transistor PTR15 for precharging is turned on, and precharge node 150 is precharged to power supply voltage Vcc level.
In the sleep mode, the current consumption is reduced as much as possible. By turning off MIS transistor PQ15 in the sleep mode, the gate tunnel current in precharge MIS transistor PQ15 is suppressed.

The MIS transistor PTR15 is connected to the ITR
It is a transistor, and the gate tunnel current in the ON state is sufficiently small. Therefore, precharge MIS transistor PTR1 in the sleep mode
5 and PQ15 can be suppressed. In the normal operation mode, the precharge node 150 is precharged using the MIS transistor PQ15 that operates at a high speed. Therefore,
During the transition from the active state to the standby state, the precharge node can be precharged at high speed,
High-speed operation becomes possible. At the time of transition to the sleep mode, the transition to the sleep mode does not require a high-speed operation. Therefore, even if the precharge node 150 is precharged to a predetermined voltage level using the ITR transistor, no problem occurs. Current consumption is reduced.

FIG. 66 shows an example of a structure of a portion generating precharge instructing signals / φPR1 and / φPR2 shown in FIG. 65. In FIG. 66, a precharge instructing signal generating portion includes two cascaded inverter circuits 160a and 160 receiving activation instructing signal ACT.
b, an OR circuit 160c receiving the output signal of the inverter circuit 160b and the sleep mode instruction signal SLEEP,
Includes inverter circuit 160d receiving sleep mode instruction signal SLEEP. Precharge instructing signal / φPR2 is output from OR circuit 160c, and inverter circuit 1
From 60d, precharge instructing signal / φPR1 is output.

Activation instruction signal ACT is generated according to an external signal in accordance with an operation cycle. Therefore, by utilizing the configuration shown in FIG. 66, when sleep mode instruction signal SLEEP is at L level,
Since OR circuit 160c operates as a buffer circuit and inverter circuits 160a and 160b operate as buffer circuits, precharge instruction signal / φPR2 changes according to activation instruction signal ACT. Since sleep mode instruction signal SLEEP is at L level, precharge instruction signal / φPR1 maintains H level.

When sleep mode instruction signal SLEEP goes high, precharge instruction signal / φPR2 from OR circuit 160c goes high, while precharge instruction signal / φPR1 from inverter circuit 160d goes low.

By using the structure shown in FIG. 66, the MIS transistor for precharging can be selectively used in the normal operation mode and the sleep mode.

[Modification 4] FIG. 67A shows a structure of a modification 4 of the twelfth embodiment of the present invention. In the configuration shown in FIG. 67A, a precharge instruction signal /
MIS transistor PQ which is turned on according to φPR
16 are provided. This MIS transistor PQ16
Is an MIS transistor having a thin gate insulating film. The MIS transistor N receiving the input signals IN1 to IN3 at the gates thereof is connected to the precharge node 150.
Q15-NQ17 are combined.

In the semiconductor device shown in FIG. 67A, precharge instructing signal / φPR is activated in a one-shot form at the start of an active cycle. That is, as shown in FIG. 67 (B), activation instruction signal ACT
Rises to the H level, precharge instructing signal / φPR accordingly becomes L level for a prescribed period, and precharge M /
IS transistor PQ16 is turned on, and precharge node 150 is precharged to a predetermined voltage level. MIS transistor PQ16 is a MIS transistor having a thin gate insulating film, and precharge node 150 is precharged to a predetermined voltage level at high speed in accordance with precharge instruction signal / φPR in the form of a one-shot pulse. After the completion of the precharge, the input signal IN1-
Precharge node 150 is selectively discharged to the ground voltage level according to IN3.

Even when the gate tunnel current of MIS transistor PQ16 is large, the period during which the gate tunnel current flows can be shortened by activating precharge instructing signal / φPR in the form of a one-shot pulse. Thus, the gate tunnel current in the precharge MIS transistor can be suppressed.

FIG. 68 schematically shows a structure of a portion for generating precharge instructing signal / φPR shown in FIG. 67 (A). In FIG. 68, operation mode instruction signal CM
A mode detection circuit 162 which detects an operation mode designated in accordance with D and generates activation instruction signal ACT, and a one-shot which attains L level for a predetermined period in response to a rise of activation instruction signal ACT from mode detection circuit 162. Is provided. From the one-shot pulse generation circuit 164,
Precharge instructing signal / φPR is output.

When an active cycle is designated according to external operation mode instruction signal CMD, mode detection circuit 162 drives activation instruction signal ACT to an active state (H level). One-shot pulse generation circuit 164
Responds to activation (rising) of activation instruction signal ACT, causing precharge instruction signal / φPR to fall for a predetermined period L.
Drive to the level. Thus, precharge node 150 can be precharged in one shot at the start of the active cycle.

In the standby state, all MIS transistors are turned off, and gate tunnel current can be suppressed.

[Modification 5] FIG. 69 shows a structure of a modification 5 of the twelfth embodiment of the present invention. This FIG.
In the configuration shown in FIG. 67, in addition to the configuration shown in FIG. 67A, an MIS transistor NTR15 selectively conducting in response to an inverted signal of activation instruction signal ACT is provided between precharge node 150 and the ground node. Provided. The MIS transistor NTR15 is formed of an ITR transistor having a large gate tunnel barrier. This MIS
Transistor NTR15 receives activation instruction signal ACT at its gate via an inverter. Therefore, when the active period (cycle) is completed and the standby period (cycle) is reached, MIS transistor NTR15 is turned on. When the active period starts, precharge instruction signal / φPR is activated in the form of one shot,
Precharge node 150 is precharged to a predetermined voltage level.

Therefore, during the standby period, MIS which is an ITR transistor having a large gate tunnel barrier is provided.
Precharge node 150 is held at the ground node by transistor NTR15. Thereby, precharge node 150 can be prevented from being in a floating state during the standby period, and malfunction due to an unstable voltage of precharge node 150 can be prevented.

During the standby period, other circuits receiving the signal of precharge node 150 are also in the standby state.
Not working. Therefore, even if precharge node 150 is held at the ground voltage level during the standby period, no adverse effect is exerted on other circuits. In the active operation, the operation starts when the precharge node 150 is precharged to a predetermined voltage level at the time of transition to the active period. By activating precharge instructing signal / φPR in the form of a one-shot pulse, other circuits are surely connected to precharge node 1
Accurate operation can be performed according to the 50 voltage levels.

Since the MIS transistor for preventing floating has a large gate tunnel barrier, the gate tunnel current in the ON state is sufficiently suppressed, and the current consumption during the standby period is sufficiently reduced.

FIG. 70 schematically shows a general structure of Modifications 4 and 5 of the twelfth embodiment of the present invention.
In the configuration shown in FIG. 70, a general logic circuit 165 is used instead of the NOR type logic circuit. The logic circuit 165 includes a MIS transistor having a thin gate insulating film as a constituent element. The logic circuit 165 selectively drives the precharge node 150 according to the input signal (group) IN. Other circuits execute predetermined processing according to the voltage level of precharge node 150.

[Modification 6] FIG. 71 shows a structure of a modification 6 of the twelfth embodiment of the invention. In FIG. 71, MI is rendered conductive between precharge node 150 and the power supply node in response to precharge instruction signal / φPR.
An S transistor PQ16 is provided. Between precharge node 150 and the ground node, there is provided MIS transistor NTR16 which becomes conductive when sleep mode instruction signal SLEEP is activated. Further, between the precharge node 150 and the ground node, as an example of a logic circuit,
MIS transistors NQ15, NQ16 and NQ17 which are selectively turned on according to input signals IN1-IN3 are connected in parallel.

The MIS transistor NTR16 is an ITR transistor having a large gate tunnel barrier, and the gate tunnel current is sufficiently suppressed. On the other hand, the MIS transistors NQ15 to NQ17 have a thin gate insulating film M
It is an IS transistor and operates at high speed in accordance with input signals IN1-IN3. Next, the operation of the semiconductor device shown in FIG. 71 will be described with reference to a signal waveform diagram shown in FIG.

In the normal mode in which processing on signals / data is performed, sleep mode instruction signal SL
EEP is at the L level and the MIS transistor NTR
Reference numeral 16 maintains the off state. This MIS transistor N
TR16 is an ITR transistor, and both the gate tunnel current and the off-leak current are small. In the normal mode, an active cycle and a standby cycle are repeatedly executed. In the active cycle, precharge instructing signal / φPR repeatedly deactivates / activates according to activation instructing signal ACT. During this active period, precharge instructing signal / φPR is in an inactive state. In the normal operation mode, precharge node 150 is precharged using MIS transistor PQ16 having a thin gate insulating film. Therefore, in the normal operation mode (normal mode),
At a high speed, precharge node 150 can be charged / discharged in accordance with activation instruction signal ACT.

In the sleep mode, on the other hand, sleep mode instruction signal SLEEP attains an H level, MIS transistor NTR16 is turned on, and precharge node 150 is fixed at the ground voltage level. On the other hand, precharge instructing signal / φPR maintains H level and MI
S transistor PQ16 is turned off.

In the sleep mode, input signals IN1-IN3 are all set at L level, and MIS
All transistors NQ15-NQ17 are off. Therefore, in the sleep mode where low current consumption is required, MIS transistors PQ16 and NQ15-NQ17 each having a thin gate insulating film are all off, and these MIS transistors PQ16 and NQ
The gate tunnel current in the 15-NQ 17 can be suppressed.

When the sleep mode ends, sleep mode instruction signal SLEEP returns to the L level, and MIS transistor NTR16 is turned off. When sleep mode instruction signal SLEEP attains an L level, precharge instruction signal / φPR attains an L level, MIS transistor PQ16 is turned on, and precharge node 150 is precharged to power supply voltage Vcc level at high speed. At the time of transition from the sleep mode to the standby state in the normal mode, a predetermined period is specified in the specifications until the start of the active cycle, and a sufficient time is guaranteed. Therefore, at the time of transition from the sleep mode to the standby state, the precharge M
Precharge node 150 can be reliably precharged to a predetermined voltage level using IS transistor PQ16.

FIG. 73 schematically shows a structure of a portion for generating the precharge instruction signal and the sleep mode instruction signal shown in FIG. 71. In FIG. 73, a control signal generating unit receives an operation mode instruction signal CMD from outside, and receives activation instruction signal ACT and sleep mode instruction signal SL.
A mode detection circuit 170 for selectively activating EEP according to a designated operation mode;
, Cascade-connected inverter circuits 171 and 172 receiving an activation instruction signal ACT from the inverter, an output signal of inverter circuit 172 and sleep mode instruction signal SLE
An OR circuit 173 generating a precharge instruction signal / φPR in response to EP is included.

When operation mode designating signal CMD designates an active state, activation designating signal ACT attains an H level. Accordingly, precharge instruction signal / φPR becomes
When sleep mode instruction signal SLEEP is at L level, it is activated. Therefore, sleep mode instruction signal S
When LEEP is at L level, precharge instructing signal / φPR is generated according to activation instructing signal ACT.

On the other hand, sleep mode instruction signal SLEEP
At the H level of the active state, precharge instructing signal / φPR from OR circuit 173 is fixed at the H level. Thereby, the activation mode of precharge instruction signal / φPR can be switched according to the operation mode.
In the sixth modification, the precharge instruction signal /
φPR may be generated in the form of a one-shot pulse.

The general form of the semiconductor device according to the sixth modification of the twelfth embodiment shown in FIG. 71 is substantially the same as that shown in FIG.

As described above, the twelfth embodiment of the present invention is described.
According to the above, when a MIS transistor having a large gate tunnel barrier is used as a MIS transistor for precharge, the MIS transistor having a thin gate insulating film is used to compensate for the precharge operation, and the MIS transistor having a thin gate insulating film is used. Is used as a MIS transistor for precharging, in an operation mode in which reduction of current consumption is required, this M
The IS transistor is turned off or turned on only for a very short time. Thus, the gate tunnel current in the standby state where low current consumption is required can be suppressed without affecting the operation speed.

[Thirteenth Embodiment] FIG. 74A schematically shows a structure of a main portion of a semiconductor device according to a thirteenth embodiment of the present invention. The semiconductor device shown in FIG. 74A is a dynamic semiconductor memory device (DRAM) and includes a memory cell array 200 having a plurality of memory cells arranged in a matrix. This memory cell array 2
The memory cells arranged in a matrix at 00 are dynamic memory cells, and the stored data needs to be refreshed at a predetermined cycle.

The semiconductor device further includes a row address circuit 203 for generating a row address designating a row of the memory cell array 200, and a row address circuit 2
03 according to the row address from memory cell array 20
A row system including a word line drive circuit for driving a word line corresponding to a row addressed to 0 to a selected state and a sense system circuit for detecting and amplifying data of a memory cell connected to the selected row It includes a circuit block 204 and a column-related circuit block 205 including other peripheral circuits for performing column selection and data input / output.

A row address circuit 203 receives an applied row address and generates an internal row address, a row decode circuit for decoding a row address from the row address buffer, a row address buffer and a row address buffer. A row address control circuit for controlling the operation of the decode circuit is included.

[0397] Row-related circuit block 204 including the word-line drive circuit and the sense-related circuit includes a row-related control circuit for controlling the operations of the word-line drive circuit and the sense-related circuit. The row-related circuit block 204 includes the memory cell array 20
0, a circuit for controlling a precharge / equalize circuit for precharging each column to a predetermined intermediate voltage level, and the conduction of a bit line isolation gate in the case of a shared sense amplifier configuration. It includes a bit line isolation gate control circuit for controlling. Column-related circuit block 205 including other peripheral circuits operates when a column selection instruction is given.

The semiconductor device further includes a refresh address counter 201 for generating a refresh address designating a row to be refreshed in the (self) refresh mode, and a refresh timer for generating a refresh request at a predetermined interval in the self refresh mode. 202. The refresh address from the refresh address counter 201 is supplied to the row address circuit 203, and the refresh request signal from the refresh timer 202 is sent to the row address circuit 20.
3 and the row-related circuit block 204 to control the operation in each refresh mode.

The self-refresh mode includes a refresh active period in which refresh is actually performed and a refresh standby period in which a refresh request is issued. Even in the normal operation mode, there are an active cycle and a standby cycle. The self-refresh mode is usually a low power consumption mode, and it is preferable that the current consumption in the self-refresh mode be as small as possible. For this reason, the refresh address counter 201 and the refresh timer 202 operating in the refresh mode are configured by ITR transistors having a large gate tunnel barrier. For example, the refresh address counter 201 and the refresh timer 202 are configured using a thick-film transistor having a thick gate insulating film. On the other hand, the row address circuit 203, the row circuit block 204, and the column circuit block 205 need to operate even in the normal operation mode, and these require high-speed operability. It is composed of MIS transistors.

These refresh address counters 2
01 and the refresh timer 202 do not require any high speed operation in the self-refresh mode even if they are constituted by an ITR transistor having a large gate tunnel barrier. Row address circuit 20
3. Row related circuit block 204 and column related circuit block 2
Reference numeral 05 denotes the first and third embodiments in the refresh standby state in the self-refresh mode.
Based on the configuration shown in, suppression of the gate tunnel current is achieved. They may also be powered off. Therefore, the current consumption in the self-refresh mode can be reduced without impairing the high-speed operation in the normal operation mode.

In FIG. 74A, column-related circuit block 205 including other peripheral circuits performs a gate tunnel current suppressing operation such as stopping supply of power supply voltage in the self-refresh mode. In the row address related circuit 203 and the row related circuit block 204 related to row selection, the gate tunnel current suppressing mechanism is selectively activated according to the self refresh mode, the refresh standby state and the refresh active state.

FIG. 74B shows a structure of one stage of refresh address counter 201 shown in FIG. 74A. The structure shown in FIG. 74 (B) is provided by a necessary number according to the number of refresh address bits.
In FIG. 74 (B), refresh address counter 201 is selectively activated in response to refresh address bit / Qi-1, and clocked inverters 201a and 201b inverting a signal applied when activated.
An inverter 201c that inverts an output signal of the clocked inverter 201b and applies the inverted signal to an input of the clocked inverter 201a, an inverter latch 201d that latches an output of the clocked inverter 201a, and an inverter that latches an output signal of the clocked inverter 201b And a latch 201e. Clocked inverter 201
b outputs a refresh address bit Qi.
These inverters are all composed of ITR transistors, for example, thick film transistors. Next, FIG.
The operation of the refresh address counter shown in FIG.

When bit / Qi-1 is at H level, clocked inverter 201a is in an output high impedance state, while clocked inverter 201b is activated to invert the signal latched in inverter latch 201d. , Bit Qi. Since bit Qi is latched in inverter latch 201d, bit Qi changes when bit / Qi-1 attains an H level. That is, when the lower bit Qi changes from the H level to the L level, the logical level of the upper bit Qi changes. While bit / Q-i is at L level, clocked inverter 201b is in an output high impedance state, and bit Qi does not change. H of this lower bit
By changing the logic level of the upper bit when the level changes from the level to the L level, that is, when a carry occurs from the lower level, a count circuit can be configured.

[0404] The circuit configuration of the refresh timer is as follows.
A configuration similar to the conventional configuration using the charging and discharging time of the capacitor can be used.

[Modification 1] FIG. 75 schematically shows a structure of a modification 1 of the thirteenth embodiment of the invention. In FIG. 75, row address related circuit 203 and row related circuit block 207 activated in the refresh mode are arranged corresponding to row address related circuit 203 and row related circuit block 204, respectively. These row related circuit block 207 and row address related circuit 2
06 operates only in the refresh mode,
For example, I, which is a thick-film transistor having a thick gate insulating film,
A TR transistor is included as a component. In the normal operation mode, the memory cell array 2 is formed by a row address circuit 203 and a row circuit block 204 each including a MIS transistor having a thin gate insulating film as a component.
A row selection operation for 00 is performed. On the other hand, in the refresh mode (self-refresh mode), the row address-related circuit 206 and the row-related circuit block 207 execute a row selection operation of the memory cell array 200. The row address related circuit 203 and the row related circuit block 204 control the power supply voltage and the like so as to suppress the gate tunnel current in the refresh mode. Similarly, in column-related circuit block 205 including other peripheral circuits, the gate tunnel current reducing mechanism is activated. For example, the decode circuit of the row address circuit 206 is a thick-film transistor, and measures such as increasing the power supply voltage are required if necessary for accurate operation, so that the influence of the threshold voltage of the thick-film transistor is sufficient. Control to be suppressed.

As described above, by separately providing the row selection related circuits operating in the normal operation mode and the row selection related circuits operating in the self refresh mode, the self refresh can be performed without impairing the operation characteristics in the normal operation mode. The current consumption due to the gate tunnel current in the mode can be reduced.

The sense circuits included in row-related circuit blocks 204 and 207 correspond to memory array 200
Is a circuit block for controlling the operation of the sense amplifier arranged in the circuit. It is not necessary to separately provide a sense amplifier circuit for the normal operation mode and a sense amplifier circuit for the refresh mode. This is because all the MIS transistors cross-coupled constituting the sense amplifier circuit are turned off in the standby state. However, two sense amplifier activating transistors for activating the sense amplifier circuit may be provided separately for the normal operation mode and for the self refresh mode. The gate tunnel barrier of this refresh mode sense amplifier activating transistor is formed of a large MIS transistor, the current driving capability is reduced, the average DC current during the operation of the sense amplifier circuit is reduced, and the DC consumption in the self refresh mode is reduced. Reduce current.

FIG. 76 is a diagram schematically showing a configuration of a control unit for the configuration shown in FIG. Referring to FIG. 76, a refresh mode detecting circuit 210 for detecting that a self-refresh mode is designated according to an operation mode instruction signal CMD, and a refresh mode detecting circuit 21
A multiplexer (MUX) 214 for selecting one of the outputs of the row related circuit blocks 207 and 204 according to the refresh mode instruction signal SRF from 0, and the row address related circuit 20 according to the refresh mode instruction signal SRF.
3 and a gate tunnel current reducing mechanism 212 for controlling the power supply of the row related circuit block 204 and the like. The refresh mode detection circuit 210 includes a MIS transistor having a large gate tunnel barrier as a component.

When a refresh mode is designated and refresh mode instruction signal SRF is activated, gate tunnel current reducing mechanism 212 activates row address related circuit 203.
In addition, the power supply control and the like of the row-related circuit block 204 are performed to reduce the gate tunnel current. The gate tunnel current reducing mechanism 212 is simply provided by the row address circuit 203
Alternatively, the power supply voltage supply to the row-related circuit block 204 may be interrupted.

In the refresh mode, multiplexer 214 selects an output signal of row related circuit block 207 including a word line drive circuit and a sense related circuit and applies it to memory cell array 200. Self-refresh mode instructing signal S from refresh mode detecting circuit 210
RF is also supplied to refresh timer 202 and column-related circuit block 205. A gate tunnel current reduction mechanism is also provided for column-related circuit blocks,
In accordance with the refresh mode instruction signal SRF, the tunnel current is reduced by controlling the power supply or bias of column-related circuit block 205. Refresh timer 202 issues a refresh request at predetermined time intervals while refresh mode instruction signal SRF is active.

Note that this refresh mode detection circuit 2
10 in accordance with the refresh mode detection signal SRF from the row address circuit 206 and the row circuit block 20.
A configuration in which 7 is selectively activated may be used. In the normal operation mode in which refresh mode instruction signal SRF is inactive, power supply voltage supply to row address circuit 206 and row circuit block 207 may be stopped.

[Modification 2] FIG. 77 schematically shows a structure of a modification 2 of the thirteenth embodiment of the invention. The configuration shown in FIG. 77 differs from the configuration shown in FIG. 74 in the following points. More specifically, MIS transistor PTR20 receiving at its gate a precharge instruction signal / φPWR1 is provided for row address circuit 203 and row circuit block 204, and responds to precharge instruction signal / φPWR2 for column circuit 205. An MIS transistor PTR22 that is selectively turned on is provided as a power supply control transistor.

[0413] These MIS transistors PTR20 and PTR22 are formed of an ITR having a large gate tunnel barrier.
It is a transistor. The row address system circuit 203 and the word line drive circuit / sense system circuit 204 are composed of a MIS having a gate insulating film thickness as small as possible.
It is a transistor. The column circuit 205 including other peripheral circuits is formed of a MIS transistor having a thin gate insulating film. The other configuration is the same as the configuration shown in FIG. Next, the operation of the semiconductor device shown in FIG.
This will be described with reference to signal waveform diagrams shown in FIG.

In the normal operation mode (normal mode), refresh mode instruction signal SRF is at L level. In this state, power supply control signal / φPWR
1 and / φPWR2 are both at the L level, and power supply transistors PTR20 and PTR22 are on. Therefore, row address related circuit 203, row related circuit 204, and column related circuit 205 operate at high speed according to the applied signals.

When a refresh mode is designated, refresh mode instruction signal SRF rises to H level.
Accordingly, power supply control signal / φPWR2 attains H level,
The power transistor PTR22 is turned off. As a result, the supply of the power supply voltage to the column related circuit 205 is stopped, and the current consumption of the column related circuit (other peripheral circuits) 205 is reduced. On the other hand, when refresh mode instruction signal SRF is at H level
When the refresh activation signal RFACT generated according to the refresh request from the refresh timer 202 is activated, the power supply control signal /
φPWR1 becomes L level. On the other hand, in this refresh mode, refresh activation signal RFACT is at L level.
Power supply control signal / φPWR1 attains the H level in the inactive state of the level and in the standby state in the refresh mode. Therefore, in the refresh mode, power supply transistor PTR20 is turned on during the period when this refresh operation (row selection operation) is performed. In the standby state, supply of the power supply voltage to the row address circuit 203 and the row circuit (word line drive circuit / sense circuit) 204 is stopped. Therefore, current consumption in the refresh mode can be reduced.

In the structure shown in FIG. 77,
By power supply transistors PTR20 and PTR22,
Power supply voltage is controlled. However, in place of power supply voltage transistors PTR20 and PTR22, as shown in the first or third embodiment, the well bias is deepened, the polarity of the power supply voltage is switched. A structure in which a gate tunnel current suppressing mechanism such as disconnection is used, and the gate tunnel current reducing mechanism is activated when power supply control signals / φPWR1 and / φPWR2 are in an inactive state may be used.

FIG. 79 shows a structure of a portion for generating the control signal shown in FIG. 78. Refresh mode instruction signal SRF is generated from mode detection circuit 210 which detects that the refresh mode has been designated according to operation mode instruction signal CMD, similarly to the configuration shown in FIG. This refresh mode instruction signal SRF is buffered by buffer circuit 220, and power supply control signal / φPW
R2 is generated. In FIG. 79, the buffer circuit 22
0 includes, for example, two stages of cascaded inverters.

The refresh timer 202 issues a refresh request signal REFQ at a predetermined cycle when the refresh mode instruction signal SRF is in the active state of H level. One-shot pulse generating circuit 222 generates a one-shot pulse having a predetermined time width according to refresh request signal REFQ. The one-shot pulse from the one-shot pulse generation circuit 222 is used as the refresh activation signal RFACT in the circuit block 20.
3 and 204. During the activation period of refresh activation signal RFACT, row selection and memory cell data detection, amplification and rewriting are performed.

The control signal generating section further includes a refresh mode instructing signal SRF and a refresh activating signal R
NAND circuit 224 receiving FACT, output signal of NAND circuit 224 and refresh mode instruction signal SRF
Receiving circuit 226. Power supply control signal / φPWR1 is output from AND circuit 226. In the normal operation mode (normal mode), refresh mode instruction signal SRF is at L level, and power supply control signal / φPWR1 maintains L level. On the other hand, when refresh mode instruction signal SRF attains an H level, AND circuit 226 operates as a buffer circuit, and NAND circuit 224 operates as an inverter circuit. Therefore, in the refresh mode, the power supply control signal /
φPWR1 is generated.

Note that refresh activation signal RFA
CT is not the one-shot pulse generation circuit 222,
It may be generated from a set / reset flip-flop which is set in accordance with refresh request signal REFQ and reset after a predetermined time has elapsed after generation of a sense amplifier activation signal.

The components of this control signal generation circuit are all formed of MIS transistors having a large gate tunnel barrier. In the self-refresh mode, high-speed operability is not required. In the normal mode, power supply control signals / φPWR1 and / φPWR2 are both fixed at L level.
Even in the normal mode, no problem arises because no high-speed operation is required.

The control signals / PWR1 and / PWR
2 are both at the L level in the normal mode, and in the refresh mode, a state is realized in which the control signal / PWR1 is activated when the refresh is active, deactivated during the refresh standby, and the control signal / PWR2 is deactivated. If so, any configuration may be used to generate control signals / PWR1 and PWR2.

[Third Modification] FIG. 80 schematically shows a structure of a third modification of the thirteenth embodiment of the present invention. 80, this semiconductor device 250 includes a DRAM unit and a logic unit. This semiconductor device is a system L in which a logic and a DRAM are mounted on the same semiconductor chip.
SI. In this DRAM section, a memory cell array 200, a row address circuit 203, a word line drive / sense circuit (row circuit) 204, other peripheral circuits (column circuits) 205, a refresh address counter 201 and a refresh timer 202 Is divided into parts.

In this DRAM section, refresh address counter 201 and refresh timer 20
Except for the circuit element 2, a logic transistor (MIS transistor) having the same gate insulating film as the MIS transistor used in the logic section is used as a circuit component. The refresh address counter 201 and the refresh timer 202 are provided with a large gate tunnel barrier M
It is composed of an IS transistor (ITR transistor).

The operation modes of the system LSI include an active / standby cycle performed in a normal access cycle and a low current consumption standby state called a sleep mode. In this sleep mode, the operation of the logic unit is stopped. In the normal access cycle, a current consumption of several tens mA is allowed even in the internal standby cycle including the logic circuit of the logic unit.

In the sleep mode, on the other hand, the following operations are required. The logic unit realizes low power consumption of the logic unit by shutting off the power supply from the outside. DRA
In the M section, data stored in the memory cell array 200 is held with a minimum current. Therefore, the self-refresh operation in the sleep mode is performed using the minimum necessary power.

Therefore, a power transistor PTR20 is provided for the row address circuit 203 and the row circuit 204, and a power transistor PTR22 is provided for the other peripheral circuit (column circuit) 205. Power supply transistors PTR20 and PTR22 are ITR transistors and receive memory power supply voltage Vcd. In the logic section, a power transistor PTR24 composed of an ITR transistor is provided as a power transistor. The power supply transistor PTR24 is controlled by the power supply control signal / φPWR2.

In the normal operation mode, power supply transistors PTR20, PTR22 and PTR24 are all on. Here, the power supply control signal / φPWR1
The operation waveforms of / φPWR2 are the same as those shown in FIG. On the other hand, when the sleep mode is entered and the DRAM section enters the self-refresh mode, the power supply control signal /
A power supply voltage is supplied to row address related circuit 203 and word line drive circuit / sense related circuit (row related circuit) 204 only during a period in which refresh is performed in accordance with φPWR1, or a tunnel leak current reduction mechanism is deactivated. In the standby state in the sleep mode, the power supply control signal / φPWR1 activates the tunnel current reduction mechanism. Column-related circuit 205 including other peripheral circuits
The power supply transistor PTR22 is turned off by the power supply control signal / φPWR2, and the supply of the power supply voltage to the other peripheral circuits (column circuits) 205 is stopped.

When the logic unit enters the sleep mode,
Power supply transistor P according to power supply control signal / φPWR2
TR24 is turned off. Therefore, power consumption of the system LSI in the sleep mode can be reduced.

The power supply transistor PTR24 receives the logic power supply voltage Vcl for the logic portion, and the power supply transistor PTR24
May be simply stopped from the outside to supply the logic power supply voltage Vcl, and the logic power supply voltage Vcl may be discharged to the ground voltage level. In any case, in the logic portion and the DRAM portion, when power supply control signals / φPWR1 and / φPWR2 are inactivated, the gate tunnel current reduction mechanism may be activated.

In the structure of the system LSI shown in FIG. 80, the power supply control signal / φPWR of the DRAM portion
The circuit responding to 1 and / φPWR2 only needs to be a gate tunnel current reducing mechanism, and any of the configurations of the embodiments described above may be used.

FIG. 81 is a diagram schematically showing a configuration of a power supply control signal generating portion shown in FIG. In FIG. 81, a power supply control signal generation unit is provided in a logic unit, for example, an instruction OPC given from a system controller.
And a self-refresh entry command SRFin and a self-refresh mode exit command SRFout from the sleep mode detection circuit 260 to generate a self-refresh mode instruction signal SRF. Mode detection circuit 262
including. Mode detection circuit 262 receives memory power supply voltage Vcd, and preferably includes an ITR transistor as a component. This self-refresh instructing signal SR
F is applied to the circuit shown in FIG.
WR1 and / φPWR2 are generated.

[0433] Sleep mode detection circuit 260 is provided in the logic portion and receives logic power supply voltage Vcl as an operation power supply voltage. In this logic unit, when the sleep mode is entered, the sleep mode exit command SRF
When a predetermined time elapses after issuance of “in”, the supply of the logic power supply voltage Vcl is cut off. When the sleep mode is released, after the logic power supply voltage Vcl is supplied, a sleep mode release command is given as a command OPC from the system controller. Therefore, in the sleep mode, even if the supply of the power supply voltage Vcl of the logic unit is cut off, the sleep mode detection circuit 260 operates correctly,
Self-refresh entry command SRFin and self-refresh exit command SRFout can be generated and provided to mode detection circuit 262.

Note that this sleep mode detection circuit 260
May be configured to receive a memory power supply voltage Vcd. In this case, the sleep mode detection circuit 260
Is an instruction OP always given from the system controller.
C will be monitored.

The memory power supply voltage Vcd is always supplied to the refresh address counter 201 and the refresh timer 202.

[Modification 4] FIG. 82 schematically shows a structure of a modification 4 of the thirteenth embodiment of the invention. In FIG. 82 as well, semiconductor device 250 includes system L
This is an SI in which the DRAM unit and the logic unit are integrated on the same chip. In this DRAM unit, a power supply control signal / φPWR is supplied to each of a row address circuit and a word line drive circuit / sense circuit (row circuit) 204.
1. Gate tunnel current reduction mechanisms 270 and 272 selectively activated in response to 1 are provided. Further, a gate tunnel current reducing mechanism 274 selectively activated in response to power supply control signal / φPWR2 is also provided for other peripheral circuits (column-related circuits) 205. These gate tunnel current reduction mechanisms 270, 272 and 27
For the power supply 4, any of the configurations described in the above embodiments other than the stop of the power supply may be used (a configuration such as a well bias change, a hierarchical power supply configuration, and a source voltage change).

On the other hand, a logic power supply voltage Vcl is supplied to the logic section. The supply of the logic power supply voltage Vcl to the logic unit is stopped in the sleep mode. The memory power supply voltage Vcd is constantly supplied to the DRAM unit. These power supply control signals / φPWR1 and / φPWR2 are generated from a control signal generator shown in FIG. Even if the configuration shown in FIG.
Even in the case where the memory power supply voltage Vcd is constantly supplied to the AM unit, it is possible to reduce both the power consumption of the DRAM unit and the power consumption of the logic unit in the sleep mode where low power consumption is required.

As described above, the thirteenth embodiment of the present invention is described.
According to the above, the part related only to the refresh operation is represented by I
In the standby state where low current consumption is required, the other circuit sections are activated by the gate tunnel current reduction mechanism. Therefore, low power consumption is required without impairing high-speed operation. Current consumption in the standby state can be reduced.

[Embodiment 14] FIG. 83 schematically shows a whole structure of a semiconductor device according to an embodiment 14 of the invention. In FIG. 83, a semiconductor device 300
Is a scan path 302 including a plurality of internal circuits LK # 1-LK # 3, a plurality of scan registers (flip-flops) F1-F7 provided corresponding to the internal nodes, respectively, and these internal circuits LK # 1 And a test / power control circuit 304 for controlling the power of the LK # 3 and the scan path 302 and controlling the test.

In the scan path 302, scan registers F1-F7 are connected in series between a scan data input terminal 309a and a scan data output terminal 309b. During a test operation, scan data SCin is sequentially transferred and latched via scan path 302 under the control of test / power supply control circuit 304. Thereafter, internal circuits LK # 1-LK # 3 are operated, and the operation results of the internal circuits are latched again in scan registers F1-F7. Thereafter, the data latched in the scan registers F1 to F7 via the scan path 302 is sequentially used as scan data SCout as a scan data output terminal 309.
Output from b.

Scan registers F1-F7 operate as a through circuit during normal operation, and transfer the signal of the corresponding internal node to the next-stage internal circuit. Therefore, during normal operation, signals / data are input via normal input terminal group 306, and internal circuits LK # 1-LK # 3
Perform predetermined operations. At this time, scan path 302 transfers the signal of each internal node to the corresponding node of the next-stage internal circuit. Therefore, the processing result from internal circuit LK # 3 is output to normal signal output terminal group 308
Is output via

By providing such a scan path 302 in the semiconductor device 300, the test of the semiconductor device is facilitated. That is, by providing scan path 302, internal circuits LK # 1-LK # 3 surrounded by scan registers F1-F7 can be individually tested. During the test operation, the internal terminals LK # 1-LK # 3 in the semiconductor device 300 are connected to the external terminal group
6 can be accessed directly or via this scan path 302, and the controllability and observability of the internal nodes of the semiconductor device 300 can be improved.

For example, when testing internal circuit LK # 2, a test pattern is set via scan data input terminal 309a in scan registers F1-F3 provided at the input nodes of internal circuit LK # 2.
Internal circuit LK # 2 is operated, and the operation result is taken into scan registers F7 and F6 provided at the output node of internal circuit LK # 2. Then this scan path 30
2 via the scan data output terminal 309b as scan-out data SCout. By observing scan-out data SCout, the operation state of internal circuit LK # 2 can be observed.

The signal shift and latch operation in scan path 302 is performed by testing / power control circuit 304.
It is performed by This test / power control circuit 304
Controls the power supply to these internal circuits LK # 1-LK # 3 and scan path 302. Power supply voltage VCL is applied to internal circuits LK # 1-LK # 3, and scan registers F1-F7 of scan path 302 are provided.
Is supplied with a power supply voltage VCS. In a standby state such as a sleep mode, the internal circuit LK # 1
-The supply of the power supply voltage VCL of LK # 3 is stopped. The scan registers F1 to F7 of the scan path 302 latch output nodes of the internal circuits LK # 1 and LK # 2 before the power supply is stopped. The scan registers F1 to F7 of the scan path 302 are provided with transfer gates (logic gates) for switching between a test operation and a normal operation. Do. Thus, current consumption of the semiconductor device 300 in a standby state such as a sleep mode is reduced.

FIG. 84 schematically shows a structure of test / power supply control circuit 304 shown in FIG. In FIG. 84, a test / power supply control circuit 304 generates a shift clock signal SFT for controlling the shift operation of scan path 302 and an operation mode instruction signal MODE in accordance with operation mode instruction OPC, and an operation mode instruction OPC , And a non-conductive state in response to the standby instruction signal φST from the mode detection circuit 313 to detect that the standby mode has been designated, and the main power supply line 311 and the internal circuit power supply line 315 And a power supply transistor 314 that separates the power supply.
Test control circuit 312 and mode detection circuit 313 are supplied with an external power supply voltage VEX via power supply nodes 310a and 310b, respectively. The main power supply line 311 is coupled to the scan path power supply line 316, and always supplies the scan path power supply voltage VC to the scan path 302.
S is supplied according to the external power supply voltage VEX.

The test control circuit 312, mode detection circuit 313, and power supply transistor 314 are composed of MIS transistors having a large gate tunnel barrier. At the time of a test using a scan path, since high-speed operation is not so required for signal transfer via the scan path 302, these test control circuits 312 are provided with a MIS having a large gate tunnel barrier.
Even if a transistor is used, no particular problem occurs.

FIG. 85 shows the scan path 30 shown in FIG.
FIG. 3 is a diagram schematically showing a configuration of scan registers F1 to F7 included in No. 2; Scan registers F1-F7 have the same configuration, and FIG. 85 representatively shows one scan register F #.

In FIG. 85, scan register F #
Includes a multiplexer (MUX) 320 for selecting one of shift-in signal SI and internal signal DI according to shift mode instruction signal SFMD, and shift clock signal SFT.
(Shift register) that takes in and transfers the signal applied from multiplexer 320 according to
321 and a through latch 3 for taking in the output signal of flip-flop 321 in accordance with update instruction signal UPDATE.
22 and the internal signal DI according to the mode instruction signal MODE.
And a multiplexer (MUX) 323 for selecting and outputting one of the output signals of the through latch 322.

A shift control instruction signal SFMD, a mode control signal MODE, a shift clock signal SFT, and an update control signal UPDATE are generated from a test control circuit 312 shown in FIG.

The shift mode instruction signal SFMD indicates which of the internal signal DI and the signal (scan-in signal) SI shifted out from the preceding scan register in the scan path in the scan test mode. Flip-flop 321 forms a shift register in scan path 302, and shifts a signal provided from multiplexer 320 according to shift clock signal SFT. From this flip-flop 321, a shift-out signal SO for the next-stage scan register in the scan path 302 is generated.

The through latch 322 outputs the update instruction signal UP
When DATE is activated, flip-flop 321 is activated.
In a through state in which the output signal passes. When the update instruction signal UPDATE is inactive, the through latch 322 enters the latch state, and the flip-flop 321
Is not inhibited, and the output signal SO of the flip-flop 321 is simply latched.

The multiplexer 323 selects the internal signal DI when the mode instruction signal MODE specifies the normal operation mode, and selects the signal from the through latch 322 in the test operation mode.

Using the scan register F #, at the time of transition to the standby state, the multiplexer 320 and the flip-flop 321 are operated and the internal signal DI
Is latched in the flip-flop 321. Even if the power supply to the internal circuits LK # 1-LK # 3 is stopped in the standby state, the flip-flop 321 keeps the semiconductor device 300 in the standby state.
Of the internal node is held.

After the standby state is completed, the signal held in flip-flop 321 is supplied to the internal circuit by setting through latch 322 to the through state and causing multiplexer 323 to select the signal of through latch 322. Thereby, internal circuits LK # 1-LK # 3 can be returned to the original state at a high speed. In the configuration of the scan path shown in FIG. 83, no flip-flop is provided at the input node of internal circuit LK # 1. However, the input node of internal circuit LK # 1 is
Normally coupled to the signal input terminal group 306,
After the standby state is completed, the state of internal circuit LK # 1 can be returned to the original state by returning normal input terminal group 306 to the original state (this is performed by an external device).

The operation of the circuits shown in FIGS. 83 to 85 will now be described with reference to the timing chart shown in FIG.

When operation mode instruction OPC specifies the standby state, test control circuit 312 first activates shift clock signal SFT. Shift mode instruction signal S
FMD is set to, for example, L level in the normal operation mode, and multiplexer (MUX) 320
The internal signal DI provided from the preceding internal circuit is selected. Therefore, the flip-flop 321 controls the multiplexer 320 according to the shift clock signal SFT.
Captures the internal signal given via The shift clock signal SFT is inactivated, and the flip-flop 32
When the internal signal DI is latched at 1, the mode detection circuit 313 drives the standby instruction signal φST to the H level and sets the power transistor 314 to the off state. This completes the standby entry mode,
Power supply to internal circuits LK # 1-LK # 3 is stopped, and leakage current due to gate tunnel current in internal circuits LK # 1-LK # 3 is reduced.

When the standby state is completed, when the normal operation mode (normal mode) starts, operation mode instruction OPC falls to, for example, L level. In response to the standby completion instruction (fall) of the operation mode instruction, standby instruction signal φST from mode detection circuit 313 attains an L level, and internal circuit power supply line 315 changes to main power supply line 3.
11, and power supply voltage VCL is supplied to internal circuits LK # 1-LK # 3. Next, the test control circuit 312
Responds to the standby completion instruction (fall) of operation mode instruction OPC, internal circuits LK # 1-LK # 3
After the supply of the power supply voltage to is completed, the mode instruction signal MODE is set to, for example, H level, and the multiplexer 323 selects the output signal of the through latch 322. At this time,
Also, the update instruction signal UPD from the test control circuit 312
ATE becomes H level, the through latch 322 enters the through state, and the internal signal latched by the flip-flop 321 is supplied to the multiplexer 323. Therefore, the signal provided at the time of transition to standby is supplied again to the internal circuit of the next stage. As a result, the standby exit mode is completed, and the semiconductor device returns to a state of executing a predetermined operation in the next normal operation mode.

FIG. 84 does not show the signal response between test control circuit 312 and mode detection circuit 313. This, individually, considers the delay time,
These control signals may be generated, and the control signals may be generated in a predetermined operation sequence according to the response relation of each control signal. The through latch 322 takes into account a mode in a boundary scan standardized by a JTAG (joint test action group) described later, and the through latch 322 may not be particularly provided.

FIG. 87 shows the test control circuit 3 shown in FIG.
12 is a diagram illustrating an example of a configuration of a mode detection circuit 12 and a mode detection circuit 313. FIG. In FIG. 87, test control circuit 312
And a case where the operations of the mode detection circuit 313 have a responsive relationship with each other. These may be configured so that the operation sequence shown in FIG. 86 is executed by individually adjusting the delay time.

In FIG. 87, test control circuit 312
Is a test decoder 31 that decodes the test mode command TM and generates a signal indicating the designated operation mode.
2a, and a test control signal generating circuit 312b for generating a control signal required for the designated operation in accordance with a test operation mode instruction signal from test decoder 312a.
In FIG. 87, shift clock signal SHIFT and mode instruction signal MODE required in the fourteenth embodiment
T and an update instruction signal UPDATAT are representatively shown.

Test control circuit 312 further includes a one-shot pulse generation circuit 312c for generating a one-shot pulse signal in response to a standby state instruction (rising) of operation mode instruction OPC, and a standby mode from mode detection circuit 313. One-shot pulse generation circuits 312e and 312f respectively generating one-shot pulse signals in response to the fall of instruction signal φST, pulse signals from one-shot pulse generation circuit 312c, and shift clocks from test control signal generation circuit 312b An OR circuit 312d for generating shift clock signal SFT in response to signal SHIFT, and a mode instruction signal MO in response to a pulse signal from one-shot pulse generation circuit 312e and a mode instruction signal MODET from test control signal generation circuit 312b. An OR circuit 312g for generating E,
An OR circuit 312h that receives a pulse signal from one-shot pulse generation circuit 312f and an update instruction signal UPDATAT from test control signal generation circuit 312b to generate update instruction signal UPDATE is included.

The mode detection circuit 313 is reset in response to the standby completion instruction (fall) of the operation mode instruction command OPC and reset in response to the fall of the pulse signal from the OR circuit 312d, and outputs the standby mode instruction. Includes set / reset flip-flop 313a for generating signal φST. This mode detection circuit 31
3 is a power transistor 3 after the signal is latched in the flip-flop 321 by the shift clock signal SFT.
14 is turned off.

At the time of the scan test, test decoder 312a generates a test operation mode instruction signal in accordance with test mode command TM, and in accordance with the test operation mode instruction signal, each signal SFT, MODE and UP.
DATE is generated. On the other hand, in the standby state in the normal operation mode, shift clock signal SFT, mode instruction signal MODE and update instruction signal UPDATE are generated according to pulse signals from one-shot pulse generation circuits 312c, 312d and 312f. Therefore, the scan register included in the scan path can be easily used as a register circuit for data saving without changing the configuration of the test control circuit.

In the structure shown in FIG. 87, one-shot pulse generating circuit 312f may be supplied with an operation mode instruction command OPC as shown by a broken line instead of standby mode instruction signal φST. In the scan register circuit, even if the through operation and the latch operation are performed before the power supply voltage VCL for the internal circuit returns to the stable state in accordance with the update instruction signal UPDATE, the power supply voltage is applied to the scan register. No problem arises. When the mode instruction signal MODE is
After the power supply to the internal circuit is stabilized, the output signal of the through latch 322 is set to a state of selecting. This mode instruction signal MODE is supplied to the through latch 32 for a predetermined period.
After selecting the output signal of No. 2, the internal circuits respectively perform circuit operations (in the case of a logic circuit), and the internal state returns to the state before the transition to the original standby state. In this state, multiplexer 323 again selects the output signal of the corresponding internal node of the preceding internal circuit. in this case,
If the internal circuit operates in synchronization with the clock signal and a transfer gate is provided at the input / output node, the clock signal transfer gate of the internal circuit is set to a through state so that the clock signal is The logic level may be set in this standby exit mode.

[Modification 1] FIG. 88 schematically shows a structure of a modification 1 of the fourteenth embodiment of the invention. In FIG. 88, internal circuit LK # 1 of semiconductor device 300
−LK # 3, corresponding to the gate tunnel current reducing mechanism 33
2 are provided. This gate tunnel current reducing mechanism 33
Reference numeral 2 has a configuration for changing the source voltage of the MIS transistor included in the internal circuits LK # 1 to LK # 3 and / or increasing the well bias and stopping the supply of the power supply voltage. This gate tunnel current reducing mechanism 33
2, a test / current control mechanism 330 is provided.
The test / current control mechanism 330 has an operation mode instruction OPC
In the standby state, gate tunnel current reduction mechanism 332 is activated, and internal circuit LK # 1-L
The gate tunnel current at K♯3 is reduced. During the test and the normal operation mode, the internal circuit LK #
When 1-LK # 3 operates, gate tunnel current reducing mechanism 332 is inactivated. The other configuration is the same as that shown in FIG. 83, and a test signal is scanned via scan path 302 during a test.

In order to reduce the gate tunnel current of internal circuits LK # 1-LK # 3 during standby, separate power supply voltages are supplied to internal circuits LK # 1-LK # 3 and scan path 302 from outside. , Internal circuit LK # 1-L
K # 3 may be configured to stop supplying external power supply voltage VCL.

[Modification 2] FIG. 89 shows a structure of a modification 2 of the fourteenth embodiment of the invention. FIG. 89 representatively shows internal circuit LK # and scan register F # included in scan path 302. Internal circuit L
At K #, logic circuit LG includes a CMOS inverter. This CMOS inverter has a low threshold voltage (L
-Vth) MIS transistors PQRa and NQR
a.

On the other hand, unit circuit U of scan register F #
G includes a CMOS inverter. This unit circuit UG
Are the components of the flip-flop 312 and the through latch 322 of the scan register shown in FIG. When multiplexers 320 and 323 are formed of, for example, tri-state inverter buffers, similarly, unit circuit UG includes multiplexers 320 and 323
May be used. CMO in this unit circuit UG
The S inverter has a high threshold voltage (H-Vth) MI
Includes S transistors PQRb and NQRb. By using an MIS transistor having a high threshold voltage as a MIS transistor as a component of scan register F #, off-leak current Ioff in the standby state can be obtained.
, And the current consumption of the semiconductor device 300 in the standby state can be further reduced.

[Modification 3] FIG. 90 shows a structure of a modification 3 of the fourteenth embodiment of the invention. In FIG. 90, in the internal circuit LK #, the logic circuit LG
MIS transistors PQRa and NQR
a is an L-Vth thin film transistor having a small absolute value of the threshold voltage and a thin gate insulating film. On the other hand, in scan register F #, M
IS transistors PQRc and NQRc are ITR transistors having a high gate tunnel barrier. Therefore, in the standby state, scan path 3
In scan register F # 02, the gate tunnel current is suppressed while holding the internal signal, and the current consumption of semiconductor device 300 in the standby state can be reduced.

In the structure shown in FIG. 90, I
In the TR transistors PQRc and NQRc,
In the standby state, the well bias may be deepened.

[Modification 4] FIG. 91 schematically shows a structure of a modification 4 of the fourteenth embodiment of the invention. In FIG. 91, a semiconductor device 340 includes a boundary scan register BSR provided corresponding to each of the external input / output terminals, and a boundary scan register BS
It includes a test controller 350 for controlling the transfer of R signal / data, and an internal circuit 360 coupled to an external input / output terminal via a boundary scan register BSR. This internal circuit 360 may include a scan path so that each of its internal nodes can be observed.

[0472] The test controller 350 receives the test data select command TM
S, test clock signal TCK and test reset signal TRST, and receives boundary scan register BS
R and test input data TDI are sequentially set by a shift operation. The test controller 350 latches data in these boundary scan registers via the scan path SCP constituted by the boundary scan registers BSR, and then outputs output test data TDO by a shift operation. The test controller 350 also controls a gate tunnel current reduction mechanism provided in the internal circuit 360 so as to reduce the power supply current when the internal circuit 360 is in a standby state.
The internal node of internal circuit 360 is stored in corresponding boundary scan register BSR.

FIG. 92 schematically shows a structure of test controller 350 shown in FIG. In FIG. 92, internal circuit 360 includes an internal logic circuit 360a for performing a predetermined logic process, and a gate tunnel current reducing mechanism 360b coupled to internal logic circuit 360a. The internal logic circuit 360a is formed of a MIS transistor, and the gate tunnel current reduction mechanism 360b reduces the gate tunnel current when the internal logic circuit 360a is in a standby state. Also, the internal logic circuit 36
0a transmits / receives signals / data in one direction to / from the scan path SCP including the boundary scan register BSR. The scan path SCP may include a scan path for observing an internal node of the internal circuit.

The test controller 350 applies the test clock signal TCK applied in the test mode and the test mode select signal T for selecting and specifying the test mode.
A TAP (test access port) controller 350a for receiving an MS and a test reset signal TRST for resetting a test mode and generating an internal clock signal for a boundary scan test, and serially via a test data input terminal Instruction register 350b receiving test data TDI applied in units of 1 bit
And an instruction decoder 350c for decoding an instruction stored in the instruction register 350b to generate a control signal required for the test, and a control circuit 350d for generating a control signal required for the test in accordance with the decoded signal from the instruction decoder 350c. including. The control circuit 350d receives the signal / of the boundary scan register in the scan path SCP.
It controls data transfer / latch and activates gate tunnel current reduction mechanism 360b in the standby state.

The test controller shown in FIG.
The controller is compatible with the JTAG test and usually includes a bypass register for bypassing the test data TDI and a user-defined register group for defining the use by the user, but these are not shown in FIG.

The test controller 350 further includes a multiplexer (MUX) 350e for selecting one of an output signal / data of the scan path SCP and an output signal of a bypass register (not shown) according to an output signal of the instruction decoder 350c, and a TAP controller 350a.
A multiplexer (MUX) 350f for selecting one of the output signal / data of the instruction register 41 and the multiplexer 350e according to the output signal of the
A driver / buffer 350g for buffering the output signal / data of 0f and outputting it to the test data terminal is included.
In the normal operation mode, test data output terminal TDO is set to a high impedance state.

The test controller shown in FIG.
Although standardized in the IEEE standard, in the fourteenth embodiment, the instruction decoder 350c and / or
Alternatively, the control circuit 350 is further provided with an operation mode instruction OPC
And a function of generating a signal for controlling the latch of data in scan path SCP and activation of gate tunnel current reduction mechanism 360b in the standby state of the semiconductor device. This control circuit 350
As the configuration of d, the configuration shown in FIG. 87 can be used. The instruction decoder 350c causes the scan path SCP to latch the signal / data of the corresponding internal node during the transition to the standby state, and outputs the latched signal to the corresponding internal node at the next stage when the standby state is completed. According to the IEEE standard, the data / signal can be taken into the boundary scan register by the instruction “Capture-DR”, and the signal / data stored in the boundary scan register can be transferred to the next stage by “Update-DR”. It can be applied to internal nodes. According to the operation mode instruction OPC, the same states as those given by the instructions are generated in the coder by the instructions. This instruction decoder 35
Control circuit 350 according to the result of decoding from
d generates control signals necessary for data transfer / latch / update. Operation mode instruction OPC is applied to instruction decoder 350c and / or control circuit 350d, and gate tunnel current reduction mechanism 36 at the time of standby state is provided.
0b is activated to reduce the gate tunnel current of the internal logic circuit 360a. The operation of the scan path SCP is
This is the same as that described in FIG. The scan path SCP may include not only a boundary scan register provided corresponding to an external input / output terminal, but also a scan path register for making an internal node in an internal circuit externally observable.

The MIS transistor included in scan path SCP is formed of a MIS transistor having a high gate tunnel barrier so as to reduce the gate tunnel current, and internal logic circuit 360a is formed of a thin film transistor. Even in such a semiconductor device capable of performing the boundary scan test, the leakage current due to the gate tunnel current in the standby state can be reduced, and the current consumption can be reduced.

In the structure shown in FIG. 92, all the above-described structures of the fourteenth embodiment can be applied.

In the standby state, a sleep state in which a logic circuit stops operating for a long time, a self-refresh mode in which a self-refresh mode is performed in a DRAM or the like, and a refresh operation repeated a plurality of times in accordance with an external refresh instruction are executed. A standby state in an auto-refresh mode or the like, and also shows a standby cycle when an active cycle and a standby cycle in a normal operation are repeated.

[Embodiment 15] FIG. 93 schematically shows a whole structure of a semiconductor device according to an embodiment 15 of the invention. In FIG. 93, as a semiconductor device, a dynamic random access memory (DR)
AM) is shown as an example. In FIG. 93, this D
The RAM includes a memory cell array 400 in which memory cells are arranged in a matrix. This memory cell array 400
It is divided into a plurality of row blocks RB # 1-RB # m and a plurality of column blocks CB # 1-CB # n.

The DRAM further includes a row address input circuit 402 for receiving an external row address signal and generating an internal row address signal, and a row address input circuit 40.
Row decoder 404 performing a decoding operation in response to a row address signal (including a block address signal) from
And a word line drive circuit for driving a selected row of a selected row block to a selected state in accordance with a decode signal of a row decoder 404 and a sense control circuit for operating a sense amplifier for detecting and amplifying data of memory cells in the selected row. Word line drive / sense circuit 406, a column address input circuit 408 for receiving an external column address signal to generate an internal column address signal (including a block selection signal), and an internal column address from column address input circuit 408 Column decoder 41 that performs a decoding operation in accordance with a signal to generate a column selection signal designating a selected column
0, a data IO control circuit 412 for inputting / outputting data by coupling a selected column decode circuit of column decoders 410 to an internal data line in accordance with a block select address from column address input circuit 408, and an internal voltage generating circuit , Row-related control signals common to row blocks RB # 1-RB # m and column blocks CB # 1-DB # n
And a central control circuit for generating a common column-related control signal.

[0484] Row decoder 404 operates as row block RB #.
Including block row decoders provided corresponding to the respective 1-RB @ m, only the block row decoder provided corresponding to the selected row operates. The unselected block row decoder maintains the standby state. Similarly, in column decoder 410, a block column decoder provided corresponding to the selected column block performs a decoding operation, and data IO control circuit 412 also has an input / output circuit (write driver and preamplifier) provided corresponding to the selected column. Is activated and internal data lines and column decoder 4 are activated.
10 to the internal IO line selected. These are therefore performing a block dividing operation, and the row decoder 404, the word line drive / sense circuit 40
6, column decoder 410 and data IO control circuit 4
At 12, the gate tunnel current is controlled in block units.

FIG. 94 shows the row decoder 40 shown in FIG.
4 is a diagram schematically showing a configuration of a part corresponding to one row block RB # i (i = 1-m) of the word line drive / sense system circuit 406. FIG. Referring to FIG. 94, a block row decoder 404i, which is activated when a block selection signal BSi is activated for a row block RB # i and decodes an internal row address signal X, and a block row decoder 40
4i according to the decode signal of 4i.
A word line driver 406ia for driving the addressed word line WL to a selected state. Sense amplifier band SAB # i is provided adjacent to row block RB # i. In sense amplifier band SAB # i, sense amplifier circuits provided corresponding to respective columns of row block RB # i are arranged. Sense amplifier band SAB♯
The activation / inactivation of i is controlled by the sense system control circuit 406ib.

Block row decoder 404i, word line driver 406ia, and sense system control circuit 406ib
The gate tunnel current reducing mechanism 40 corresponds to each of them.
5i, 407i, and 409i are provided. These gate tunnel current reducing mechanisms 405i, 407i and 409i are activated when block select signal BSi is in a non-selected state, and block row decoder 404i, word line driver 406ia, and sense system control circuit 40
6ib gate tunnel current is reduced. These gate tunnel current reduction mechanisms 405i, 407i and 40
9i is arranged corresponding to the row block. Only for the selected row block, block decoder 404i and word line driver 406ia are activated, and sense control circuit 406ib is activated. For the non-selected row block, the gate tunnel current reduction mechanism 405i, 4
07i and 409i further reduce the gate tunnel current (same as in the standby cycle).

When the sense amplifier band is shared by adjacent row blocks, gate tunnel current reducing mechanism 409i
Are also supplied with a block selection signal for a row block sharing sense amplifier band SAB # i. In the case of a shared sense amplifier configuration in which a sense amplifier band is shared by adjacent row blocks, sense-related control circuit 406i
b also controls the operation of the bit line isolation gate, bit line precharge / equalize circuit and sense power supply node equalize circuit.

FIG. 95 shows an example of the structure of gate tunnel current reducing mechanisms 405i and 407i shown in FIG. In FIG. 95, block row decoder 40
4i is enabled when the block selection signal BS is activated, and the internal row decode signal X
NAND type decoding circuit 420a for decoding
An inverter 420b for inverting an output signal of the AND-type decode circuit 420a is included. Power supply nodes of NAND type decode circuit 420a and inverter circuit 420b are coupled to a power supply node via power supply transistor 422. Power supply transistor 422 is preferably formed of an ITR transistor and has a gate receiving complementary block select signal / BSi.

The word line driver is connected to the inverter circuit 42
0b to a signal having an amplitude of the high voltage VPP level, and a level shifter 4
An inverter circuit 424b for driving a corresponding word line WL according to the output signal of 24a is included. This gate tunnel current reducing mechanism is turned on in response to a complementary block select signal / BSi to supply an ITR for supplying high voltage VPP to level shifter 424a and inverter circuit 424b.
The power supply transistor 426 includes a transistor.

In the structure shown in FIG. 95, power supply transistor 422 is provided commonly to a unit row decode circuit included in block row decoder 404i, and power supply transistor 426 is connected to a word line drive circuit included in word line driver 406ia. Provided in common. Therefore, in the standby state, power supply transistors 422 and 426 are turned off, and the supply of the power supply voltage to the block row decoder and the word line driver is stopped.

In the structure shown in FIG. 95, word line WL is connected to main word line ZMWL and sub-word line SMW.
In the case of a hierarchical word line configuration including WL, the main word line Z
MWL is held at the high voltage VPP level when not selected.
Therefore, in the case of such a hierarchical word line configuration, a configuration in which a source bias or a well bias is deepened or a hierarchical power supply configuration is preferably used instead of the high voltage cutoff configuration.

FIG. 96 shows the column decoder 4 shown in FIG.
10 schematically shows a configuration of a portion corresponding to one column block CB # j of 10 and data IO control circuit 412. FIG. For column block CB # j, column block selection signal C
When Bj is activated, a block column decoder for decoding an internal column address signal from column address input circuit 408 shown in FIG. 93 and driving column selection signal CSL for selecting a corresponding column of column block CB # j to an active state 410j
And write driver / preamplifier 412j for writing / reading data to / from the selected column of column block CB # j.
including. This write driver / preamplifier 412j also has
Activated when column block select signal CBj is activated, it performs an amplification operation. Write driver / preamplifier 412j
Is a memory block of a column block CB # j (a block arranged corresponding to an intersection of a row block and a column block)
Are coupled to a global data bus GIO arranged in common. This write driver / preamplifier 412j is
It is coupled to internal data bus 434. A plurality of column blocks CB {1-CB} are shared by internal data bus 434.
The write driver / preamplifier provided corresponding to n is connected.

[0492] Gate tunnel current reduction mechanisms (ITRC) 430j and 432j are provided for block column decoder 410j and write driver / preamplifier 412j, respectively. Gate tunnel current reduction mechanisms (ITRC) 430j and 432j are activated when column block select signal CBj is not selected, and reduce the gate tunnel current of block column decoder 410j and write driver / preamplifier 412j.

In the structure shown in FIG. 96, a column selecting operation and data writing / reading are performed in a column block designated by column block selecting signal CBj. In an unselected column block, block column decoder 410
In addition, write driver / preamplifier 412 maintains a non-selected state (standby state). Therefore, by arranging gate tunnel current reducing mechanisms 430j and 432j for each column block, in the selected memory array, the gate tunnel current is reduced in the non-selected column blocks, and the operating current during the active period is reduced. be able to.

[Modification 1] FIG. 97 schematically shows a structure of a modification 1 of the fifteenth embodiment of the invention. In FIG. 97, a semiconductor device 440 includes a plurality of banks B #.
1-B # 4 and a gate tunnel current reducing mechanism (I) provided corresponding to each of these banks B # 1-B # 4.
TRC) 444a-444d and an external bank address signal BA # are decoded, and a bank designating signal BA1-
A bank decoder 440 for generating BA4 is included. Each of banks B # 1-B # 4 has a corresponding bank designating signal BA1.
-Activated when BA4 is activated to perform memory access (row selection or column selection). Gate tunnel current reduction mechanisms 444a-444d provide bank address signal BA1.
-Activated when BA4 is inactive, corresponding bank B # 1
-Reduce the gate tunnel current of B♯4. When bank designating signals BA1-BA4 are not selected, corresponding banks B # 1-B # 4 are in a standby state. Therefore, by activating the gate tunnel current reduction mechanism provided corresponding to the unselected bank in semiconductor device 440, it is possible to reduce the leak current caused by the gate tunnel current in semiconductor device 440, and to reduce the current consumption correspondingly. can do.

As described above, the fifteenth embodiment of the present invention is described.
According to the configuration, the gate tunnel current of the non-selected circuit block is reduced, and even when the circuit is activated, the gate tunnel current in the non-selected circuit block cannot be reduced and the consumption during the circuit operation is reduced. The current can be reduced (because the gate tunnel leak current can be suppressed).

[Embodiment 16] FIG. 98 schematically shows a structure of a main portion of a semiconductor memory device according to an embodiment 16 of the invention. In the sixteenth embodiment, the memory array is divided into a plurality of row blocks as in the configuration shown in FIG. FIG. 98 shows one row block RB # i. This row block RB # i includes a normal memory array N on which normal word lines NWL are arranged.
MA # i and spare memory array SMA # i in which spare word line SWL is arranged.

A normal row selection circuit 450 is provided for normal memory array NMA # i, and a spare row selection circuit 452 is provided for spare memory array SMAi. Normal row selection circuit 450 includes a normal row decoder and a normal word line driving circuit that drives normal word line NWL according to an output signal of normal row decoder. Similarly, spare row selection circuit 452 includes a spare row decoder and a spare word line drive circuit for driving spare word line SWL to a selected state according to an output signal of spare row decoder.

Gate tunnel current reduction mechanisms (ITRC) 454 and 456 are provided corresponding to normal row selection circuit 450 and spare row selection circuit 452, respectively. These gate tunnel current reduction mechanisms 454 and 456 reduce the gate tunnel current of the circuit corresponding to the activation.

A spare determining circuit 458 for determining which of normal word line NWL and spare word line SWL is selected for row block RB # i is provided.
The spare determination circuit 458 is provided for the normal memory array N
The address of the defective row in MA # i is stored, activated when block select signal BS is selected, and applied address signal X is compared with the address of the stored defective memory cell,
According to the determination result, the normal row enable signal N
Activate one of RE and spare row enable signal SRE. Normal row enable signal NRE controls activation / inactivation of normal row selection circuit 450, and spare row enable signal SRE controls spare row selection circuit 452.
Control the activation / deactivation of

This normal row enable signal NRE
Is normally given to the normal word line drive circuit,
This normal row selection circuit 450 outputs a block selection signal B
When L is in the selected state, the applied row address signal X is decoded. Normal row enable signal NRE
At the H level in the standby state. Spare row enable signal SRE is at the L level in the standby state, and spare word line is connected to spare row enable signal SR.
When E is in the active state, it is driven to the selected state. The gate tunnel current reducing mechanism (ITRC) 454 provided in the normal row selection circuit 450 receives the normal row enable signal NRE and the block selection signal BS.
0 is inactive when the output signal is at H level, and activated when at least one of the block selection signal BS and the normal row enable signal NRE is at L level in a non-selected state. Reduce tunnel current. Here, gate circuit 450 is shown as being constituted by a NAND circuit receiving block select signal BS and normal row enable signal NRE. This corresponds to the normal row enable signal NRE.
Is set to H level in the standby state.

On the other hand, gate tunnel current reduction mechanism (ITRC) 45 provided for spare row selection circuit 452
6 is activated when the spare row enable signal SRE is in an inactive state, and reduces the gate tunnel current of the spare row selection circuit 452. Spare row enable signal SRE is fixed at L level in the standby state and when not selected (when accessing a normal memory cell).

In the structure shown in FIG. 98, a spare determination circuit 458 is provided corresponding to each of row blocks RB # i, and a spare determination is performed in units of row blocks. When a spare word line is used in the selected row block, the gate tunnel current of normal row selection circuit 450 is reduced. On the other hand, when a normal word line NWL is used (accessed), spare row selection circuit 450 is used. The gate tunnel current of 452 is reduced. Therefore, in the selected row block, the gate tunnel current of the unselected circuit can be reduced, and the current consumption during the active period can be reduced. In an unselected row block, both gate tunnel current reduction mechanisms 454 and 456 are activated.

[Modification 1] FIG. 99 schematically shows a structure of a modification 1 of the sixteenth embodiment of the invention. In FIG. 99, memory array MA is divided into a plurality of row blocks RB # 1-RB # m. This memory array M
A is divided into a normal column block in which a normal column is arranged and a spare column block in which a spare column is arranged. Normal column blocks and spare column blocks are arranged corresponding to row blocks, and normal column blocks NC {1-NC}
m and spare column block SPC # 1-SPC # m
Is arranged. Row block RB # i includes normal column block NC # i and spare column block SPC #
i.

A word line is commonly arranged for normal column block NC # i and spare column block SPC # i. Therefore, when one row block is selected, a row of a normal column block and a spare column block is selected in a selected row block by a row decoder (not shown).

[0505] Normal column block NC {1-NC}
m, a normal column decoder 470 is provided, and a spare column decoder 471 is provided commonly to spare column blocks SPC # 1-SPC # m. Normal read / write circuit 472 is provided for performing data access to a column selected by normal column decoder 470, and spare column decoder 47 is provided.
A spare read / write circuit 473 is provided for performing data access to the spare column selected by 1.

A column spare determination circuit 474 is provided for determining which of the normal column and the spare column is accessed. The column spare determination circuit 474 activates one of the normal column enable signal NEC and the spare column enable signal SCE according to the match / mismatch between the applied column address signal Y and the stored defective column address. here,
Normally, normal column enable signal NEC is set to the H level during normal column access and in the standby state, similarly to normal row enable signal NRE. Spare column enable signal SCE is set to an active state of an H level only at the time of accessing a spare column.

For normal column decoder 470 and normal read / write circuit 472, gate tunnel current reduction mechanisms (ITRC) 475 and 476 are provided, respectively.
, And gate tunnel current reduction mechanisms (ITRC) 477 and 478 are provided for spare column decoder 471 and spare read / write circuit 473. Gate tunnel current reducing mechanisms 475 and 476 receive gate circuit 480 receiving column access activation signal CAS and normal column enable signal NEC.
Is active (H level), the gate tunnel current of normal column decoder 470 and normal read / write circuit 472 is reduced. Here, the case where the gate circuit 480 is configured by a NAND circuit is shown as an example. This corresponds to column access activation signal CA
It is assumed that S and normal column enable signal NEC are at the H level when they are active. Therefore, when column access in which column selection and data access (writing / reading) are performed is started and a normal column is addressed, the output signal of gate circuit 480 is rendered inactive (L level), and the gate is turned off. Tunnel current reduction mechanisms 475 and 476 are deactivated, and their normal column decoders 470 are deactivated.
Also, the gate tunnel current reducing operation of normal read / write circuit 472 is stopped.

On the other hand, gate tunnel current reduction mechanisms (ITRC) 477 and 4 provided for spare column decoder 471 and spare read / write circuit 473 are provided.
Reference numeral 78 is activated when the spare column enable signal SCE is inactive, and reduces the gate tunnel current of the spare column decoder 471 and the spare read / write circuit 473. Here, spare column enable signal SCE is held in an inactive state (L level) in a standby state and in a normal column access.

Therefore, at the time of column access,
By reducing the gate tunnel current for a circuit that does not operate, current consumption during this column access period can be reduced.

[Modification 2] FIG. 100 schematically shows a structure of a modification 2 of the sixteenth embodiment of the present invention.
In FIG. 100, the memory array is divided into a plurality of row blocks 504a-504m. Row block 504
Each of a-504m includes a normal row block 501 provided with a normal word line, and a spare row block 502 provided with a spare word line. That is, in the configuration shown in FIG. 100, repair of a defective row is performed in units of row blocks. Row block 504a-5
04m adjacent to each other in the column direction,
0a-500n are provided. These sense amplifier bands 500a to 500n are shared by adjacent row blocks. A row decoder (including a word line drive circuit) RD corresponding to the row blocks 504a to 504m
Is arranged. These row decoders RD include a normal row decoder (RD) arranged corresponding to normal row block 501 and a spare row decoder (RD) arranged corresponding to spare row block 502.

Also, sense amplifier bands 500a-500n
, A column decoder CD for generating a column selection signal
Is arranged. The column selection signal from column decoder CD is transmitted through sense amplifier bands 500a to 500n via column selection lines extending in the row direction. Therefore, column selection is simultaneously performed in parallel by the column decoder CD in the spare column block and the normal column block in the row block. No signal indicating the column spare determination result is applied to column decoder CD. When a corresponding block selection signal is active at the time of column access, a column decode operation is performed in accordance with a column access instruction (activation) signal.

A column gate tunnel current reducing mechanism CITRC is provided corresponding to column decoder CD, and a row gate tunnel current reducing mechanism RITRC is provided corresponding to row decoder RD. This row gate tunnel current reducing mechanism RITRC is composed of a normal row decoder (R
D) Normal gate tunnel current reduction mechanism NITRC and spare row decoder (RD) provided corresponding to D)
And a spare row gate tunnel current reduction mechanism SITRC provided corresponding to the above.

[0513] Row spare determination circuits 506a to 506m are provided corresponding to row decoder RD. These row spare determination circuits 506a to 506m are supplied with block selection signals corresponding to block selection signals BS <m: 1>, respectively. Also, the block selection signal BS <
m: 1> is also applied to a column gate tunnel current reducing mechanism CITRC provided corresponding to the column decoder CD.

A normal read / write circuit 508 is provided corresponding to a normal column block, and a spare read / write (R / W) corresponding to a spare column block.
A circuit 509 is provided. These normal read / write circuit 508 and spare read / write (R / W)
The circuit 509 operates concurrently with column access.

In this memory array, global data lines of a plurality of bits are connected to normal read / write circuit 5
08 in parallel with each other, and replaces a defective column in global data line units. That is, in order to repair a defective column, a column access instruction signal CACT is used.
Is activated when the row block address signal RB is activated.
A column redundancy control circuit 510 for decoding A and generating a data line selection signal SEL;
A multiplexer (MUX) 511 for selectively coupling the normal read / write circuit 508 and the spare read / write circuit 509 to the input / output circuit 512 in accordance with the data line selection signal SEL from the external device is provided. In column redundancy control circuit 510, a defective column address is programmed for each row block, and a global data line connected to a defective column in a selected row block is replaced with a spare global data line according to the row block address signal RBA. .

Therefore, since normal read / write circuit 508 and spare read / write circuit 509 operate in parallel, the gate tunnel current reducing mechanism (ITR)
C) 513 is the normal read / write circuit 50
8 and a spare read / write (R / W) circuit 509. This gate tunnel current reduction mechanism 5
13 reduces the gate tunnel current of the normal read / write circuit 508 and the spare read / write circuit 509 when the column access instruction signal CACT is inactive. When column access starts, the normal read / write circuit 508 and the spare read / write (R / W) circuit 509 stop the gate tunnel current reduction operation, and these normal read / write circuits 508
The spare read / write circuit 509 operates at high speed.

In the structure shown in FIG. 100, the gate tunnel current for column decoder CD and row decoder RD is controlled in accordance with both block selection signal BS <m: 1> and the determination results of row spare determination circuits 506a-506m. It is. When the normal row block is accessed in the selected row block, the corresponding spare gate tunnel current reducing mechanism SITRC is maintained in the same state as in the standby state, and the gate tunnel current of the corresponding spare row decoder (RD) is reduced. You. On the other hand, when a spare word line is accessed in the selected row block, normal gate tunnel current reducing mechanism NITRC maintains the standby state, and the gate tunnel current of the corresponding normal row decoder (RD) is reduced. . Therefore, in the configuration shown in FIG. 100, the gate tunnel current is controlled on a row block basis and on a normal / spare basis, and the gate tunnel current reduction operation is stopped only in the operating circuit. Current consumption during the cell selection operation) is reduced.

The activation / inactivation of the column gate tunnel current reducing mechanism CITRC for the column decoder CD is controlled in accordance with the block selection signal BS <m: 1> generated from the row block address signal RBA. However, to these column gate tunnel current reduction mechanisms CITRC, block select signals BS <m:
1> and column access instructing signal CACT may be applied, and the gate tunnel current reducing operation may be stopped only when both are in the selected state.

[Third Modification] FIG. 101A schematically shows a structure of a main part of a third modification of the sixteenth embodiment of the present invention. FIG. 101A shows a configuration of a row-related circuit for one row block.

In FIG. 101 (A), the row-related circuit
An address input buffer 552 for latching a word line address signal X in accordance with a row address latch enable signal RAL, and an internal word line address signal X from the address input buffer 552 are supplied to a row decoder enable signal R
A row decoder 554 for decoding according to the ADE, a word line drive timing signal RXT and a row decoder 554
, A normal word line driver 556 driving normal word line NWL to a selected state, a row block decoder 558 for decoding row block address signal RBA, and a block selection signal BSF from row block decoder 558 to be activated. , Row spare determination circuit 560 for determining whether word line address signal X at the time of activation specifies a defective row, and spare row enable signal SRE from row spare determination circuit 560.
A latch circuit 562 for latching F in accordance with a row decoder enable signal RADE, and a spare word line driver for driving a spare word line SWL to a selected state in response to a word line drive timing signal RXT in accordance with a spare row enable signal SRE from the latch circuit 562 564.

[0521] The row-related circuit further receives the block selection signal BSF from the row block decoder 558 and the normal row enable signal NREF from the row spare determination circuit 560, and outputs the row decoder enable signal RADE.
To generate a block select signal BS and a normal row enable signal NRE to generate a row decoder 5
And a latch circuit 566 to be provided to the control circuit 54. The normal row enable signal from latch circuit 566 may be applied to normal word line driver 556.

When row access activation signal RACT is activated, row-related control circuit 550 generates a row address latch enable signal RAL, a row address decoder enable signal RADE, and a word line drive timing signal RXT in a predetermined sequence. Row control circuit 550
And address input buffer 552 are provided commonly to a plurality of row blocks.

Next, the operation of FIG. 101A will be described with reference to FIG.
Description will be made with reference to a signal waveform diagram shown in FIG.

When row access activation signal RACT is driven to an active state of H level, row address latch enable signal RAL, row address decoder enable signal RADE and word line drive timing signal RXT are sequentially activated in a predetermined sequence. You. Before activation of row access activation signal RACT, word line address signal X and row block address signal RBA are applied. Row block decoder 558 and row spare determination circuit 560 operate in synchronization with row access activation signal RACT to perform a decoding operation and a determination operation.
That is, the row spare determination operation is performed using the setup period for the row access activation signal RACT of the address signal X and RBA. According to block select signal BSF from row block decoder 558,
A spare determination operation is performed in the selected row block.
According to the spare determination result, normal row enable signal NREF and spare row enable signal SREF
Is set to a state indicating a spare determination result. Therefore, normal row enable signal NREF and spare row enable signal SREF from row spare determination circuit 560 are settled before row access activation signal RACT is activated.

Then, according to activation of row address decoder enable signal RADE, latch circuits 566 and 562 fetch and latch the applied signals, respectively. Therefore, block select signal BS and normal row enable signal NRE are applied to row decoder 554, and row decoder 554 performs a decoding operation when a normal word line is designated in the selected row block, and then performs a normal word line operation. Driver 556
Drives normal word line NWL to the selected state. On the other hand, when a defective word line is addressed in the selected row block, row decoder 554 does not perform the decoding operation and maintains the standby state, and normal word line driver 556 also maintains the standby state. If this bad word line is addressed,
The spare row enable signal SREF from the row spare determination circuit 560 is activated, the latch circuit 562 is latched according to the row address decoder enable signal RADE, and the spare word line driver 564
Spare word line SWL is driven to a selected state according to word line drive timing signal RXT.

Therefore, these spare judgment results are:
Before the activation of the row access activation signal RACT or the activation of the row address decoder enable signal RADE, the state is determined at the latest. During this active period, the period required for spare determination can be shortened. Thus, the current consumption of a circuit held in a non-operating state in a normal / spare row decoder can be reduced accordingly (to drive a corresponding gate tunnel current reducing mechanism to an active state).

The row access activation signal RACT is
In the case of a standard DRAM, it is generated according to a row address strobe signal / RAS. In the case of a DRAM synchronized with a clock signal, an active command is given,
It remains active until the next precharge command is applied.

In the case of a clock synchronous DRAM, latch circuits 566 and 562 may be configured to transfer a corresponding signal in synchronization with clock signal CLK.

Also, word line address signal X is applied to row spare determination circuit 560 and row decoder 554, and block select signal BSF from row block decoder 558 is transferred in synchronization with a clock signal to activate the row decoder. And the transfer of the output signal of row spare determination circuit 560 may be performed.

In any case, row spare determination is performed using the setup period of the address signal.

In the structure shown in FIG. 101A, row block decoder 558 and row spare determination circuit 560 are shown to perform a static operation. However, these row block decoders 55
8 and the row spare determination circuit 560 may be configured to be reset once in response to the deactivation of the row access activation signal RACT.

FIG. 101A shows a structure in the case where the number of spare word lines SWL is one. However, when a plurality of spare word lines SWL are provided in the row block, a spare determination circuit is provided corresponding to each spare sub word line in row spare determination circuit 560, and each spare word line driver and spare determination circuit are provided. Are associated one-to-one. In this case, the normal row enable signal NREF is generated by NOR of the output signals of the plurality of spare determination circuits.

[Modification 4] FIG. 102 schematically shows a structure of a modification 4 of the sixteenth embodiment of the invention.
FIG. 102 shows a column circuit.

In FIG. 102, a column related circuit includes a column related control circuit 578 for generating a column address latch enable signal CAL and a column address decoder enable signal CADE in a predetermined sequence in response to activation of a column access instruction signal CACT. , Column address input buffer 570 which takes in and latches column address signal Y in response to column address latch enable signal CAL, and is activated when row access activating signal RACT is activated, and receives column address signal Y to determine column spare. And a normal column enable signal NEC from column spare determination circuit 572 are latched in response to activation of column address decoder enable signal CADE, and a column address input buffer is provided. A normal column decoder 574 decodes the column address signal from 70, the spare column enable signal SCE column address decoder enable signal CAD from column spare determining circuit 572
A spare column decoder 576 that latches in response to activation of E and generates spare column select signal CSL is included.

[0537] Spare column decoder 576 simply drives spare column select line SCSL to the selected state according to spare column enable signal SCE. If a plurality of spare column lines are provided, a plurality of program circuits for storing a plurality of defective column addresses are provided in column spare determination circuit 572, and the plurality of column program circuits are Corresponds to spare column select line SCSL.

Normal column decoder 574 and spare column decoder 576 drive normal column select line NCSL or spare column select line SCSL to the selected state according to column address decoder enable signal CADE. As shown in FIG. 103, column spare determination circuit 572 outputs column access activation signal CAC.
The spare determination operation is performed asynchronously with T. Therefore, at the start of the decoding operation of normal column decoder 574, the determination operation of column spare determination circuit 572 has been completed, and the internal column selection operation start timing can be advanced. Activation / inactivation can be controlled at an early timing of a gate tunnel current reduction mechanism provided corresponding to spare column decoder 576. Since the operation time of the switching of the gate tunnel reduction mechanism is not included in the active period, the current consumption required for the switching can be excluded from the active period, and the current consumption in the active period can be reduced.

In the structure shown in FIG. 102, column access instruction (activation) signal CACT may be generated in accordance with column address strobe signal / CAS, or may be generated by a column access command as in a clock synchronous DRAM. May be generated. In the case of a clock synchronous DRAM, the result of determination by the column spare determination circuit 572 may be transferred in synchronization with the clock signal CLK.

Note that FIG. 101 (A) and FIG.
In the structure shown in, internal operation is performed in accordance with access activation signals RACT and CACT, and the gate tunnel current reducing mechanism is selectively activated. However, in this case, switching of the gate tunnel current reduction mechanism is performed by these access activation signals RACT and CAC.
It may be configured to be performed asynchronously with T. That is, the row block decoder 5 shown in FIG.
The configuration may be such that the block selection signal BSF from the block 58 and the row enable signal SREF and the normal row enable signal NREF from the row spare determination circuit 560 are supplied to the corresponding gate tunnel current reduction mechanism.

In the structure shown in FIG. 100, a normal row block and a spare column block are arranged in a row block. However, one spare row block may be provided commonly to a plurality of normal row blocks. In this case, the active / inactive and gate tunnel current of the sense amplifier are separately controlled by the normal sense amplifier and the spare sense amplifier.

As described above, the sixteenth embodiment of the present invention is described.
According to the normal / spare memory cell redundant configuration, the gate tunnel current reducing mechanism is kept active for the access path which is in the non-selected state, and the gate tunnel during the active period of the semiconductor memory device is maintained. Leakage current due to current can be reduced, and accordingly, current consumption can be reduced.

[0541]

As described above, according to the present invention, the ITR
Since a transistor or a MIS transistor capable of increasing a gate tunnel barrier is used in a portion where a gate tunnel leak current is a problem, the gate tunnel leak current can be efficiently suppressed, and current consumption can be reduced.

That is, the ITR is provided on the power supply side of the logic gate.
A transistor is provided, and the ITR transistor is selectively set to a conductive state according to an operation mode, so that a gate tunnel current of a logic gate in a standby state can be effectively suppressed.

The MIS transistor of this logic gate is
A silicon oxide film having a thickness of 3 nm or less and an insulating film having a thickness equivalent to that of the gate tunnel barrier;
An exponentially increasing gate tunnel current can be efficiently suppressed by the ITR transistor.

In the case where the thickness of the gate insulating film of the MIS transistor of the logic gate is 3 nm, the reduced M
Gate tunnel current, which is a problem when an IS transistor is used as a component, is efficiently suppressed by an ITR transistor. Even if a logic circuit is manufactured with a minimum design size, a low power consumption is required in a standby state. Gate tunnel leak current can be suppressed.

[0545] Also, M which is turned on in the standby state
An IS transistor has an MI with a large gate tunnel barrier.
By using an S transistor, an MIS transistor with a small gate tunnel barrier is connected in series with the MIS transistor, and the MIS transistor with a small gate tunnel barrier is turned off in the standby state, thereby reducing the gate tunnel current in the standby state. And can be operated at high speed during an active cycle.

The size of the gate tunnel barrier is
By adjusting the thickness of the gate insulating film, an MIS transistor having a necessary gate tunnel barrier can be easily formed.

In a configuration in which CMOS inverter circuits are cascaded by cascading sets of MIS transistors having different gate tunnel barriers and increasing the gate tunnel barrier of the MIS transistors that are turned on in the standby state in each group. In addition, the gate tunnel current can be surely suppressed in the standby state.

In a device in which the logic level of an input signal in the standby state is predetermined, the first and second MIS transistors are connected in series, and the gates of the first and second MIS transistors are connected in the standby state. By reducing the tunnel current from that in the active cycle, it is possible to reliably suppress the current consumption in the standby state where low power consumption is required.

This control circuit is connected to the first and second MIS
With a circuit in which the back gate bias of the transistor is increased in the standby state, the gate tunnel current can be easily suppressed.

Alternatively, the control circuit can be easily constituted by a circuit for switching the voltage polarity of the power supply node connected to the first and second MIS transistors between a standby cycle and an active cycle. MI
A deep reverse bias state can be provided between the gate and the source of the S transistor, and the gate tunnel current can be effectively suppressed accordingly.

The operation of these control circuits allows M
The absolute value of the threshold voltage of the IS transistor can be effectively increased, and the off-leak current can be suppressed.

In the case where the gate insulating film of the MIS transistor has a gate tunnel barrier equivalent to that of a silicon oxide film having a thickness of 3 nm, the gate tunnel current can be surely suppressed even when a miniaturized transistor is used. Can be.

The first and second control circuits are
By switching the voltage of the power supply node connected to the MIS transistor between the active cycle and the standby cycle, the tunnel current and the off-leak current can be easily suppressed, and accordingly, the power consumption in the standby state can be reduced. it can.

Further, the main power supply line and the sub power supply line have a hierarchical structure, and the main power supply line and the sub power supply line are selectively turned on in the standby state according to the operation cycle of the active cycle and the standby cycle. By connecting the MIS transistor having a small gate tunnel barrier, which is turned off in the standby state, to the sub power supply line, the gate tunnel current and the off-leak current in the standby state can be reliably suppressed. The MIS transistor which is turned on in the standby state is a MIS transistor having a large gate tunnel barrier, and is connected to the main power supply node, thereby preventing the output signal from becoming uncertain during the transition to the active cycle. Can be.

Also, by increasing the absolute value of the threshold voltage of the switching transistor between the main power supply line and the sub-power supply line and turning off the transistor in the standby state, the gate tunnel current in the switching transistor can be effectively reduced. It can be prevented from occurring during the standby state,
By separating the sub power supply line and the main power supply line in the standby state, it is possible to reliably suppress the gate tunnel leak current of the MIS transistor in the logic circuit portion.

Further, the thickness of the gate insulating film of the first MIS transistor of the logic circuit is set to 3 nm or more,
By making the thickness of the gate insulating film of the transistor smaller than 3 nm, the logic circuit portion can be formed using the MIS transistor having the minimum size. In this case, the gate tunnel leak current is surely suppressed. be able to.

Also, by making the back gate potential of the switching transistor different from the MIS transistor of the logic circuit and the back gate potential, the MIS transistor having the same gate insulating film thickness can be used for the logic circuit and the switching transistor. Gate tunnel leakage current of the switching transistor can be reliably suppressed.

Further, by using a switching transistor for selectively connecting the main power supply line and the sub power supply line and a replica circuit of a CMOS circuit using the voltages of the main and sub power supply lines, the voltage of the sub power supply line is reduced. By adjusting, the voltage level of the sub power supply line can be driven to the balanced voltage level at high speed, the sub power supply line voltage can be stabilized at an early timing at the time of transition to the standby state, and the time of the standby state can be maintained. Irrespective of the length, the power supply voltage can be prevented from fluctuating when shifting from the standby cycle to the active cycle, and the internal circuit operation can be started at high speed when shifting from the standby cycle to the active cycle.

Also, the output of the replica circuit is transferred to the sub-power supply line using an amplifier circuit, and the sub-power supply line can be driven to a balanced voltage at high speed in accordance with the voltage level of the replica circuit.

Also, first and second switching transistors provided for the first and second main and sub power supply lines, respectively, and first and second switching transistors using these first and second sub power supply lines are provided. The gate ratio of the first gate circuit, the transistor size and the size of the first switching transistor, and the transistor size of the second gate circuit and the size ratio of the second switching transistor are equalized. , These first
And the second sub-power supply lines can have the same balanced voltage in the standby state, and the operation start timing can be made equal during the active cycle of the first and second gate circuits. Can be guaranteed.

By forming each of the first and second gate circuits as a unit gate circuit having a different gate insulating film thickness, it is ensured that these first and second gate circuits are in the standby state. The gate tunnel current of the gate circuit can be suppressed.

Further, third and fourth gate circuits cascade-connected to these first and second gate circuits, respectively, are provided, and the third and fourth sub-power supply lines are respectively connected to the third and fourth gate circuits. The third and fourth switching transistors connected to the third and fourth sub-power supply lines, the size ratio of the third gate circuit and the third switching transistor and the fourth By making the size ratio of the switching transistor and the transistor of the fourth gate circuit equal, the equilibrium voltage in the standby state of the power supply line can be made equal, and a hierarchical power supply configuration is used for both the power supply voltage and the ground voltage. In this case, the equilibrium voltages of the sub-ground lines in the standby state can be made equal to each other,
The internal circuit operation can be started at an early timing at the transition to the active cycle.

Further, by forming the third and fourth gate circuits with MIS transistors having different gate insulating film thicknesses, it is possible to reliably suppress the gate tunnel leak current in the standby state.

[0564] Further, by providing the switching circuit and the replica circuit of the gate circuit, the voltage of each sub-power supply line can be reliably driven to the balanced voltage, and the operation start timing at the time of the active cycle transition of the plurality of gate circuits can be set. Can be faster.

Further, by connecting the sub-power supply lines in the standby state, the balanced voltages of the sub-power supply lines can be surely made equal to each other.

Also, by providing a replica circuit with the third and fourth switching transistors for the third and fourth gate circuits, the third and fourth power supply lines are driven to a balanced voltage at high speed. be able to.

By transmitting the output voltage of the replica circuit to the sub power supply line using the differential amplifier,
The voltage of each sub-power supply line can be accurately driven to the output voltage level of the replica circuit.

By providing the replica circuit and the sub power supply line coupling to the third and fourth sub power supply lines, the voltages of these third and fourth sub power supply lines can be reliably increased at the same speed. It can be driven to a balanced voltage level.

The gate tunnel current can be easily suppressed by using MIS transistors having SOI structures having different gate insulating film thicknesses and increasing the bias applied to the body region of the MIS transistor having the SOI structure in the standby state. And an off-leak current can be suppressed.

[0570] By increasing the bias voltage applied to the body region to such an extent that the MIS transistor having the SOI structure is turned off, it is ensured that
Gate tunnel current can be suppressed.

Further, even when a plurality of gate circuits including MIS transistors having an SOI structure are connected in tandem,
By commonly controlling the voltages of the body regions of these MIS transistors, the gate tunnel current in the standby state can be easily suppressed.

Also, M which is turned on in the standby state
By using a buried channel MIS transistor as the IS transistor, the tunnel barrier can be increased, and the gate tunnel current can be suppressed accordingly.

Even if the gate insulating film thicknesses of these MIS transistors are made equal, the buried channel type MIS transistor has a structure in which the gate insulating film thickness is equivalently increased, and a complicated manufacturing process is added. It is possible to easily suppress the gate tunnel current without using.

Further, by forming this power supply line into a hierarchical power supply structure, it is possible to more accurately and reliably suppress gate tunnel current leakage.

Further, by using a buried channel type MIS transistor as the switching transistor connecting the main and sub power supply lines of the hierarchical power supply structure, the gate tunnel current can be surely suppressed.

[0576] Also, M which is turned on in the standby state
By using a gate depletion type MIS transistor as the IS transistor, a tunnel leak current can be easily suppressed.

Further, even if the thickness of the gate insulating film of the normal MIS transistor and that of the gate depletion MIS transistor are the same, it is possible to surely suppress the tunnel leak current in the gate depletion MIS transistor in the standby state.

Further, by making the thickness of the gate insulating film the same, the occurrence of a step in the gate circuit portion can be suppressed, and accurate patterning can be realized.

Further, by connecting the gate depletion type MIS transistor to a hierarchical power supply structure in which the main and sub power supply lines are used, the gate tunnel current can be surely suppressed.

Also, by using a gate depletion type MIS transistor as the switching transistor connecting the main and sub power supply lines, it is possible to reliably and easily suppress the gate tunnel current in this switching transistor.

Also, by using an MIS transistor having a large gate tunnel barrier for the latch circuit, even if the logic level of the latch signal in the standby state cannot be determined in advance, the gate tunnel of the latch circuit in the standby state can be surely ensured. The current can be suppressed. The gate circuit operates at high speed by setting the thickness of the gate insulating film of the MIS transistor of the gate circuit to a value equal to or less than the tunnel barrier provided by the silicon oxide film having a thickness of 3 nm. The signal of the latch circuit can be processed. Further, by blocking the voltage applied to the gate circuit in the standby state, the gate tunnel current in the gate circuit in the standby state can be suppressed.

Also, the MIS having a small gate tunnel barrier is used.
A first latch circuit composed of a transistor and a second latch circuit composed of an MIS transistor having a large gate tunnel barrier, and a signal is supplied to the first and second latch circuits in accordance with an operation cycle. By transferring, by holding the signal in the second latch circuit in the standby state, it is possible to hold the signal accurately while suppressing the gate tunnel current. Further, by taking measures such as shutting off the power supply of the first latch circuit in the standby state, current consumption in the standby state can be reduced.

[0583] During the active cycle, a signal is always transferred from the first latch circuit to the second latch circuit, so that it is not necessary to provide a new signal transfer period when shifting from the active cycle to the standby cycle.
A signal can be transferred from the first latch circuit to the second latch circuit without impairing high-speed operation.

Also, by activating the transfer circuit only in the cycle in which the signal processing relating to the first latch circuit is executed, it is possible to transfer the data to the second latch circuit accurately.

In the case where the first latch circuit is connected to the pipeline stage (synchronous design stage), the first latch circuit is operated in the cycle following the cycle in which the operation is performed on the first latch circuit. The signal is transferred from the first latch circuit to the second latch circuit without easily considering the margin of the signal transfer timing and without adversely affecting the high-speed operation of the pipeline stage. Signal can be transferred to the latch circuit of FIG.

By using a MIS transistor having a large gate tunnel barrier as the MIS transistor for precharging the precharge node to a predetermined voltage, it is possible to suppress the gate tunnel current of the MIS transistor for precharge in the precharge state. it can.

In addition, the precharge node is precharged in one shot by an MIS transistor having a small gate tunnel barrier separately from the precharge node, so that the voltage of the precharge node can be quickly increased to a predetermined precharge voltage level. Can be driven.

The precharge MIS transistor is activated in the sleep mode and turned off in the normal operation mode. In the normal operation mode, the precharge node is precharged by the MIS transistor having a small gate tunnel barrier. In the normal operation mode, the precharge node can be precharged to a predetermined voltage level at high speed. In the sleep mode, the precharge MIS transistor having a small gate tunnel barrier is turned off, so that the gate tunnel current in the sleep mode can be suppressed.
Accordingly, current consumption can be reduced.

Also, at the time of transition to the active cycle, by using a precharge MIS transistor having a small gate tunnel barrier in a one-shot form, the period during which the gate tunnel current flows through the precharge MIS transistor can be shortened. Current consumption can be reduced.

By providing an MIS transistor having a large gate tunnel barrier for holding the precharge node at a voltage level different from the precharge voltage during the standby period, the precharge node is reliably brought into a floating state during the standby period. Can be prevented.

In a configuration in which a precharge node is precharged by using a MIS transistor having a small gate tunnel barrier, the precharge M
By turning off the IS transistor, gate tunnel current flowing through the precharge MIS transistor can be suppressed, and current consumption can be reduced.

In a memory requiring a refresh operation, a circuit relating only to refresh is constituted by an MIS transistor having a large gate tunnel barrier, so that current consumption in the refresh mode can be reduced.

In the refresh operation, a refresh-related row circuit for performing a row selecting operation and a row-related circuit for selecting a row of the memory cell addressed in the normal operation mode are separately provided. By using MIS transistors having a large size, current consumption in the refresh mode can be significantly reduced. In a semiconductor memory device, a memory cell array occupies most of the area, and a large area penalty does not occur even if a refresh-related row circuit and a row-related circuit are provided in duplicate.

By activating the gate tunnel current suppressing mechanism of the MIS transistor of the refresh circuit during the standby period in the refresh mode, the average DC current in the refresh mode can be reduced.

Further, by configuring the gate tunnel current suppressing mechanism with a power supply MIS transistor having a large gate tunnel barrier which is turned off in the refresh standby cycle, the current consumption of the refresh circuit in the refresh standby can be easily reduced. can do.

In the refresh mode, the current consumption in the refresh mode can be reduced by activating the gate tunnel current suppressing mechanism of the circuit related to the column selection.

Further, since this gate tunnel current suppressing mechanism is constituted by a power supply MIS transistor having a large gate tunnel barrier which is turned off in the refresh mode, the supply of the power supply voltage to the column circuits in the refresh mode can be easily cut off. Thus, current consumption can be reduced.

When a logic circuit is mixedly mounted, the supply of the power supply voltage to the logic circuit in the refresh mode is cut off, so that the current consumption of the logic circuit and the entire memory in the refresh mode can be reduced.

Also, the MIS transistor for controlling the power supply to the logic circuit is provided with an MI transistor having a large gate tunnel barrier.
When the power supply voltage is supplied to the logic circuit, generation of a gate tunnel current in the power supply MIS transistor can be suppressed by using an S transistor.

If the register provided corresponding to the internal node of the logic circuit is configured to save the signal of the internal node corresponding to the standby state and reduce the gate tunnel current of the logic circuit, the consumption in the standby state is reduced. The current can be reduced.

Also, by configuring such that the gate tunnel current of this register is reduced at the time of standby,
The current consumption of this register during standby can be reduced, and the overall current consumption can be further reduced.

Further, since the transistor of the register is constituted by a transistor having a large gate tunnel barrier, it is not necessary to perform complicated power supply control on the register at the time of transition to the standby state, thereby easily reducing the current consumption at the time of standby. can do.

Also, by using a register constituting a scan path for observing or controlling the voltage of the internal node as this register, it is not necessary to newly provide an additional register. And the current consumption can be reduced.

Further, by configuring such that the gate tunnel current of the internal circuits other than the selected internal circuit among the plurality of internal circuits is reduced, the current consumption during the activation period can be reduced.

Also, by configuring the current control so as to reduce the gate tunnel currents of a plurality of internal circuits during standby, current consumption during standby can be further reduced.

In the normal / spare redundant configuration, the current consumption during the activation period can be reduced by reducing the gate tunnel current of the unselected normal / spare selection circuit.

In the case of the block division structure, the current consumption during the activation period is reduced by reducing the gate tunnel current of the selected spare / normal selection circuit among the spare / normal selection circuits of the selected block. It can be further reduced.

By performing the spare determination before the activation of the operation mode instruction signal, the activation period can be shortened, and both the spare / normal selection circuits are kept active until the determination is confirmed. It is not necessary, and the current consumption during the activation period can be reduced.

By performing the determination operation asynchronously with the operation mode instruction signal instructing the memory cell selection operation, the spare / normal determination result can be determined at an earlier timing, and the spare / normal selection circuit in the selected block can be determined. Need not be increased until the determination result is determined because of its high-speed operation, and the current consumption during the activation period can be reduced.

[Brief description of the drawings]

FIG. 1A shows a configuration of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a signal waveform diagram showing an operation of the semiconductor device shown in FIG. 1A.

2 (A) shows a configuration of a modification of the first embodiment of the present invention, and FIG. 2 (B) is a signal waveform diagram showing an operation of the device shown in FIG. 2 (A).

3 (A) shows a configuration of a semiconductor device according to a second embodiment of the present invention, and FIG. 3 (B) is a signal waveform diagram showing an operation of the device shown in FIG. 3 (A).

FIG. 4 is a diagram showing a leakage current path of the device shown in FIG.

FIG. 5 shows a structure of a semiconductor device according to a third embodiment of the present invention.

6 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG.

FIG. 7 is a drawing schematically showing a cross-sectional structure of the semiconductor device shown in FIG. 5;

FIG. 8A schematically shows a cross-sectional structure of a MIS transistor according to a third embodiment of the present invention, and FIG.
9 is a diagram showing the gate-substrate capacitance of the MIS transistor shown in FIG.

FIG. 9 is a diagram schematically showing a configuration of an N-well bias circuit shown in FIG. 7;

FIG. 10 is a diagram schematically showing a configuration of a P-well bias circuit shown in FIG. 7;

FIG. 11 schematically shows a configuration of a modification of the third embodiment of the present invention.

FIG. 12 is a signal waveform diagram showing an operation of the device shown in FIG.

FIG. 13 is a diagram showing a configuration of a second modification of the third embodiment of the present invention.

14 is a signal waveform diagram representing an operation of the device shown in FIG.

15 is a diagram schematically showing a cross-sectional structure of a MIS transistor of the semiconductor device shown in FIG. 13;

FIG. 16 schematically shows a structure of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 17 is a signal waveform diagram representing an operation of the device shown in FIG.

FIG. 18 schematically shows a modification of the fourth embodiment of the present invention.

FIG. 19 shows a structure of a semiconductor device according to a fifth embodiment of the present invention.

20 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG.

FIGS. 21A to 21C are diagrams respectively showing the structures of MIS transistors having a large gate tunnel barrier.

FIG. 22 shows a structure of a semiconductor device according to a sixth embodiment of the present invention.

23 is a signal waveform diagram representing an operation of the device shown in FIG.

24 is a diagram illustrating a configuration of a voltage adjustment circuit illustrated in FIG. 22;

FIG. 25A is a diagram showing a configuration of a first modification of the sixth embodiment of the present invention, and FIG. 25B is a signal waveform diagram showing an operation of the device shown in FIG. .

FIG. 26 is a diagram showing a configuration of a first modification of the sixth embodiment of the present invention.

FIG. 27 is a diagram showing a configuration of a second modification of the sixth embodiment of the present invention.

FIG. 28 is a diagram showing a configuration of a third modification of the sixth embodiment of the present invention.

FIG. 29 is a diagram showing a configuration of a fourth modification of the sixth embodiment of the present invention.

FIG. 30 schematically shows a cross-sectional structure of a semiconductor device according to a seventh embodiment of the present invention.

31A is a diagram schematically showing a planar layout of the MIS transistor shown in FIG. 30, and FIG.
FIG. 32 schematically shows a cross-sectional structure of the transistor shown in FIG.

32 is a diagram showing a modified example of the planar layout of the MIS transistor shown in FIG.

FIG. 33A shows a configuration of a semiconductor device according to a seventh embodiment of the present invention, and FIG. 33B is a signal waveform diagram showing an operation of the device shown in FIG.

34 (A) shows a modification of the seventh embodiment of the present invention, and FIG. 34 (B) is a signal waveform diagram showing an operation of the device shown in FIG. 34 (A).

FIG. 35 is a drawing illustrating roughly a cross-sectional structure of a MIS transistor used in Embodiment 8 of the present invention;

36A schematically shows a channel impurity concentration profile of a buried channel N-type MIS transistor when a P + gate is used, and FIG. 36B shows a surface channel type N type transistor when an N + gate is used. FIG. 4 is a diagram showing an impurity concentration profile of a channel region of a type MIS transistor.

37A shows an impurity concentration profile of a channel region of a buried channel P-type MIS transistor when an N + gate is used, and FIG. 37B shows a surface channel P-type when a P + gate is used. FIG. 4 is a diagram showing an impurity concentration profile of a channel region of a MIS transistor.

FIG. 38A shows a configuration of a semiconductor device according to an eighth embodiment of the present invention, and FIG. 38B is a signal waveform diagram showing an operation of the semiconductor device shown in FIG. 38A.

FIG. 39 (A) shows a modification of the eighth embodiment of the present invention, and FIG. 39 (B) is a signal waveform diagram showing an operation of the device shown in FIG. 39 (A).

FIGS. 40A and 40B schematically show a cross-sectional structure of a MIS transistor used in a ninth embodiment of the present invention.

FIG. 41 shows a structure of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 42 is a diagram showing a modification of the ninth embodiment of the present invention.

FIG. 43 shows a structure of a semiconductor device according to the tenth embodiment of the present invention.

FIG. 44 is a diagram showing a modification of the tenth embodiment of the present invention.

FIG. 45 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG. 44.

FIG. 46 is a diagram showing a configuration of a second modification of the tenth embodiment of the present invention.

FIG. 47 schematically shows a structure of a semiconductor device according to an eleventh embodiment of the present invention.

48 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG. 47.

FIG. 49A schematically shows a configuration of a portion for generating a control signal of the semiconductor device shown in FIG. 47, and FIG.
FIG. 50 is a signal waveform diagram representing an operation of the control signal generator shown in FIG. 49 (A).

FIG. 50 is a diagram showing a modified example of the operation of the semiconductor device shown in FIG.

FIG. 51A is a diagram showing a modification of the control signal generator for the semiconductor device shown in FIG. 47, and FIG.
FIG. 52 is a signal waveform diagram representing an operation of the control signal generator shown in FIG. 51 (A).

FIG. 52 is a view showing a modified example of the operation of the semiconductor device shown in FIG. 47;

FIG. 53 is a drawing illustrating roughly configuration of a portion that generates a control signal illustrated in FIG. 52;

FIG. 54 is a signal waveform diagram showing still another operation sequence of the semiconductor device shown in FIG. 47.

FIG. 55 is a drawing illustrating roughly configuration of a portion that generates a control signal illustrated in FIG. 54;

FIG. 56A is a diagram showing a modification of the semiconductor device according to the eleventh embodiment of the present invention, and FIG.
FIG. 3 is a signal waveform diagram illustrating an operation of the semiconductor device illustrated in FIG.

FIG. 57A shows a configuration of a transfer instruction signal generating portion of the semiconductor device shown in FIG. 56A, and FIG.
FIG. 3 is a signal waveform diagram illustrating an operation of the circuit illustrated in FIG.

FIG. 58 is a signal waveform diagram representing still another operation of the semiconductor device according to the eleventh embodiment of the present invention.

59 (A) shows a configuration of a semiconductor device according to a twelfth embodiment of the present invention, FIG. 59 (B) is a signal waveform diagram showing an operation of the device of FIG. 59 (A), and FIG. 59 (C) is FIG. FIG. 3A is a diagram showing a general form of the semiconductor device shown in FIG.

FIG. 60 (A) shows a configuration of a first modification of the twelfth embodiment of the present invention, and FIG. 60 (B) is a signal waveform diagram showing an operation of the device shown in FIG. 60 (A).

FIG. 61 shows a structure of a precharge instruction signal generation unit of the device shown in FIG.

FIG. 62 is a signal waveform diagram showing a modification of the operation of the semiconductor device according to the twelfth embodiment of the present invention.

FIG. 63 is a drawing illustrating roughly configuration of a precharge instructing signal generation unit in the operation sequence illustrated in FIG. 62;

FIG. 64 is a diagram showing a general configuration of a second modification of the twelfth embodiment of the present invention.

FIG. 65 is a signal waveform diagram representing a third operation sequence of the semiconductor device according to the twelfth embodiment of the present invention.

FIG. 66 shows a structure of a portion for generating a precharge instruction signal shown in FIG. 65.

FIG. 67A shows a configuration of a semiconductor device according to a fourth modification of the twelfth embodiment of the present invention, and FIG.
FIG. 7 is a signal waveform diagram illustrating an operation of the device illustrated in FIG.

FIG. 68 schematically shows a structure of a portion for generating a precharge instruction signal shown in FIG. 67 (A).

FIG. 69 is a diagram showing a configuration of a fifth modification of the twelfth embodiment of the present invention.

FIG. 70 shows a general configuration of Modifications 4 and 5 of Embodiment 12 of the present invention.

FIG. 71 is a diagram showing a configuration of a sixth modification of the twelfth embodiment of the present invention.

FIG. 72 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG. 71.

73 is a drawing illustrating roughly configuration of a portion that generates the control signal illustrated in FIG. 72;

FIG. 74A schematically shows a structure of a semiconductor device according to a thirteenth embodiment of the present invention, and FIG.
FIG. 74 shows a configuration of the refresh address counter shown in FIG.

FIG. 75 is a view schematically showing a configuration of a first modification of the thirteenth embodiment of the present invention;

FIG. 76 is a drawing illustrating roughly configuration of control of the semiconductor device illustrated in FIG. 75;

FIG. 77 schematically shows a structure of a modification 2 of the thirteenth embodiment of the present invention.

FIG. 78 is a signal waveform diagram representing an operation of the device shown in FIG. 77.

FIG. 79 is a diagram schematically showing a configuration of a portion for generating the signal shown in FIG. 78;

FIG. 80 schematically shows a structure of a third modification of the thirteenth embodiment of the present invention.

FIG. 81 is a diagram schematically showing a configuration of a control signal generator shown in FIG. 80;

FIG. 82 is a drawing illustrating roughly configuration of Modification 4 of Embodiment 13 of the present invention;

FIG. 83 schematically shows an entire structure of a semiconductor device according to a fourteenth embodiment of the present invention.

FIG. 84 is a view schematically showing a configuration of the test / power supply control circuit shown in FIG. 83;

FIG. 85 schematically shows a structure of the register circuit shown in FIG. 83.

86 is a signal waveform diagram representing an operation of the register circuit shown in FIG. 85.

87 is a diagram showing a more detailed configuration of the test / power supply control circuit shown in FIG. 83.

FIG. 88 is a diagram showing a configuration of a first modification of the fourteenth embodiment of the present invention.

FIG. 89 is a diagram showing a configuration of a second modification of the fourteenth embodiment of the present invention.

FIG. 90 is a diagram showing a configuration of a third modification of the fourteenth embodiment of the present invention.

FIG. 91 schematically shows a structure of a fourth modification of the fourteenth embodiment of the present invention.

FIG. 92 is a drawing schematically showing a configuration of the test controller shown in FIG. 91.

FIG. 93 schematically shows an entire structure of a semiconductor device according to a fifteenth embodiment of the present invention.

94 is a diagram schematically showing a configuration of a portion corresponding to one row block of the semiconductor device shown in FIG. 93;

FIG. 95 is a diagram schematically showing a configuration of a block row decoder and a word line driver shown in FIG. 94;

96 is a diagram schematically showing a configuration of a portion provided corresponding to one column block of the semiconductor device shown in FIG. 93;

FIG. 97 schematically shows a structure of a first modification of the fifteenth embodiment of the present invention.

FIG. 98 schematically shows a structure of a main portion of a semiconductor device according to a sixteenth embodiment of the present invention.

FIG. 99 schematically shows a configuration of a first modification of the sixteenth embodiment of the present invention.

FIG. 100 schematically shows a configuration of a second modification of the sixteenth embodiment of the present invention.

FIG. 101A schematically shows a configuration of a third modification of the sixteenth embodiment of the present invention, and FIG.
FIG. 3 is a signal waveform diagram illustrating an operation of the circuit illustrated in FIG.

FIG. 102 is a drawing illustrating roughly configuration of Modification 4 of Embodiment 16 of the present invention;

FIG. 103 is a signal waveform diagram representing an operation of the circuit shown in FIG. 102.

FIG. 104 illustrates an example of a configuration of a conventional semiconductor device.

105 is a signal waveform diagram representing an operation of the semiconductor device shown in FIG. 83.

FIGS. 106A to 106C are diagrams schematically showing structures of energy bands in an accumulation state, a depletion state, and an inversion state of an N-channel MIS transistor;

FIG. 107 is a diagram showing a gate tunnel current path of a conventional semiconductor device.

FIG. 108 is a diagram showing another path of the gate tunnel current path of the conventional semiconductor device.

[Explanation of symbols]

SW1, SW2 power switching transistor, 1
Power supply node, 2 ground node, 3 sub power supply line, 4 sub ground line, PQ, NQ, PQ1-PQ4, NQ1-NQ4
MIS transistor, 5 N well region, 6 P well region, 11 N well, 13 P well, 15 N well bias circuit, 20 P well bias circuit, 21
Power line, 22 power switching circuit, 23 ground line, 24 power switching circuit, 26, 28 power switching circuit, 30 main power line, 32 sub power line, 34 main ground line, 36 sub ground line, PQa-PQd, NQa- NQd MIS transistor, SWa, SWb power switching transistor, 42 voltage adjustment circuit, 42a replica circuit, RP
1, RP2, RN1, RN2 MIS transistor, S
W1r, SW2r Power transistors, 42b, 42c
Comparator, 42d, 42e transfer gate, SW
C-1 to SWC-n, SWS-1 to SWS-n power switching transistors, PX1-PXn, NX1-NX
n transfer gate, 52 voltage adjustment circuit, CTM
1-CTMn-1, STM1-STMn-1 transmission gate, 54 control clock signal generation circuit,
52a monitor circuit, 52b, 52c transmission gate, 62 semiconductor substrate, 61 buried oxide film, 63
a, 63b, 64a, 64b impurity regions, 65, 66
Body region, 67, 68 Gate electrode, 70, 73 Bias voltage application region, 75 P body region, 76 N body region, SPQ1-SPQ4, SNQ1-SNQ4
SOI structure MIS transistor, 81, 83 impurity region, 83 gate insulating film, 84 gate electrode, 85 inversion layer, 86, 87 depletion layer, BQ1-BQ4 buried channel type MIS transistor, 92, 97 gate electrode,
92a, 97a Depletion layer, DQ1-DQ4 Gate depletion MIS transistor, PTR1-PTR15 MIS transistor with large gate tunnel barrier, NTR1-
NTR16 ITR transistor, PT1, PT2, N
P1, NP2 MIS transistor, XF1, XF2
Transfer gate, 105 bidirectional transfer circuit, AL
Active latch circuit, SL standby latch circuit,
LG # 1-LG # n logic circuit, LT # 1-LT # n latch circuit, 150 precharge node, 155 logic circuit, 200 memory cell array, 201 refresh address counter, 202 refresh timer, 2
03 row address circuit, 204 word line drive circuit /
Sense circuits (row circuits), 205 Other peripheral circuits (column circuits), 206 Row address circuits, 207
Word line drive circuit / sense circuit (row circuit), PTR
20, PTR22 MIS with large gate tunnel barrier
Transistor, 250 semiconductor device, PTR24 MIS transistor having a large gate tunnel barrier, 270,
272, 274 Gate tunnel current reduction mechanism, 300
Semiconductor device, LK # 1-LK # 3 internal circuit, 302
Scan path, F1-F7 register circuit, 304
Test / power control circuit, 311 main power line, 312 test control circuit, 313 mode detection circuit, 314 power transistor, 321 flip-flop, 330 test / current control mechanism, 332 gate tunnel current reduction mechanism, PQRb, NQRb H-Vth MOS transistor , PQRc, NQRc High gate tunnel barrier transistor, BSR boundary scan register, SCP
Boundary scan path, 350 test controller, 360a internal logic circuit, 360b gate tunnel current reduction mechanism, 404 row decoder, 406 word line drive / sense circuit, 410 column decoder, 4
12 data IO control circuit, RB # 1-RB # m row block, CB # 1-CB # n column block, 405i,
407i, 409i Gate tunnel current reduction mechanism, 4
22,426 Power supply transistors 430j, 432j
Gate tunnel current reduction mechanism (ITRC), B 、 1-B
# 4 bank, 444a-444d Gate tunnel current reduction mechanism (ITRC), 450 normal row selection circuit, 452 spare row selection circuit, 454,456 Gate tunnel current reduction mechanism (ITRC), 458 spare determination circuit, 470 normal column decoder, 472
Normal read / write circuit, 471 spare column decoder, 473 spare read / write circuit, 474
Column spare determination circuit, 475-478 Gate tunnel current reduction mechanism (ITRC), 506a-506m Row spare determination circuit, CITRC, NITRC, SITR
C, RITRC Gate tunnel current reduction mechanism, CD
Column decoder, RD row decoder, 510 column redundancy control circuit, 550 row-related control circuit, 552 address input buffer, 554 row decoder, 556 normal word line driver, 558 row block decoder, 560 row spare determination circuit, 562,566 latch circuit, 564 spare word line driver, 570 column address input buffer, 572 column spare determination circuit, 574 normal column decoder, 576 spare column decoder.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/108 H01L 27/04 M 21/8242 27/08 321A 29/786 27/10 681F H03K 19/00 29/78 613A 614 F term (reference) 5F038 AV13 BG05 BG06 BG09 CD02 CD03 CD09 CD15 DF05 DF07 DF08 DF14 DT02 DT06 DT09 DT12 DT18 EZ06 EZ20 5F048 AA08 AB01 AB04 AC03 AC04 BA16 B03 BE01 BE03 BB01 BE03 BE03 BE01 GA06 HA02 LA04 LA06 LA10 NA03 ZA07 5F110 AA06 AA09 AA15 BB04 BB06 CC02 DD05 DD13 EE24 GG02 GG60 HM04 HM12 HM15 NN78 5J056 AA00 BB01 BB17 BB49 CC03 DD13 DD29 FF01 FF08 KK01 KK02

Claims (69)

[Claims] A first power supply node; an insulated gate field effect transistor having a first gate tunnel barrier as a component; receiving a voltage on the first power supply line as one operation power supply voltage; A logic gate for performing the following, and an insulated gate type field effect transistor connected between the first power supply node and the first power supply line and having a gate tunnel barrier larger than the first gate tunnel barrier. A first switching transistor which selectively conducts in response to an operation mode instruction signal instructing an operation mode of the logic gate. 2. The semiconductor device according to claim 1, wherein said first gate tunnel barrier is equivalent to a silicon oxide film having a thickness of 3 nm or less and a gate tunnel barrier. 3. The semiconductor device according to claim 1, wherein the insulated gate field effect transistor of the logic gate has a gate insulating film having a thickness of 3 nanometers or less. 4. A semiconductor device having a standby cycle and an active cycle, wherein a logic level of an input signal at the time of said standby cycle is predetermined, comprising: a first gate tunnel barrier; A first insulated gate field effect transistor that is connected between a power supply node and an output node and that receives the input signal at its gate and that is turned on during the standby cycle; and a gate smaller than the first gate tunnel barrier A second insulated gate field effect transistor that has a tunnel barrier, is connected between the output node and a second power supply node, and receives the input signal at its gate and is turned off during the standby cycle; Semiconductor device. 5. The semiconductor device according to claim 4, wherein said first insulated gate field effect transistor has a gate insulating film thicker than said second insulated gate field effect transistor. 6. The semiconductor device having the second gate tunnel barrier,
A third insulated gate field effect transistor connected between the first power supply node and the second output node and turned off in the standby cycle according to a signal from the first output node; A fourth insulated gate field effect having the first gate tunnel barrier connected between an output node and the second power supply node and being turned on during the standby cycle in accordance with a signal from the first output node; The semiconductor device according to claim 4, further comprising a transistor. 7. A semiconductor device having a standby cycle and an active cycle, wherein a logic level of an input signal at the time of the standby cycle is predetermined, wherein a logic level between a first power supply node and a first output node is provided. A first insulated-gate field-effect transistor connected to the gate and receiving the input signal at the gate; a second insulated-gate field-effect transistor connected between the output node and the second power supply node and receiving the input signal at the gate A field effect transistor coupled to the first and second insulated gate type field effect transistors, wherein a gate tunnel leakage amount of the first and second insulated gate type field effect transistors during the standby cycle is determined during the active cycle. A semiconductor device comprising a control circuit for reducing the power consumption. 8. The control circuit includes a circuit for making a bias of a back gate of the first and second insulated gate field effect transistors deeper in the standby cycle than in the active cycle. 13. The semiconductor device according to claim 1. 9. The semiconductor device according to claim 7, wherein said control circuit includes a circuit for switching a voltage polarity of said first and second power supply nodes between said standby cycle and said active cycle. 10. The first and second insulated gate field effect transistors include an insulating film having a gate tunnel barrier equal to or less than a gate tunnel barrier provided by a silicon oxide film having a thickness of 3 nanometers. 8. The semiconductor device according to 7. 11. The control circuit supplies first and second power supply voltages used during normal operation to the first and second power supply nodes during the active cycle, and supplies the first and second power supply voltages during the standby cycle. 1st and 2nd
8. A circuit for applying third and fourth voltages whose absolute values are smaller and larger than the power supply voltage of the first and second power supply voltages, respectively.
13. The semiconductor device according to claim 1. 12. A semiconductor device having a standby cycle and an active cycle, wherein a logic level of an input signal at the time of said standby cycle is predetermined, wherein a first power supply node and a first output node are connected to each other. A first insulated gate field effect transistor connected between the first output node and a sub-power supply node, the first insulated gate field effect transistor having the gate receiving the input signal and further having a first tunnel barrier; A second insulated gate field effect transistor that receives the input signal and conducts complementarily with the first insulated gate field effect transistor;
The insulated gate field effect transistor has a second gate tunnel barrier smaller than the first gate tunnel barrier, is connected between the sub power supply node and the second power supply node, and has an operation cycle designation signal. And a first switching transistor that selectively conducts in response to the first switching transistor. 13. The first switching transistor is turned off during the standby cycle, has a larger absolute value of a threshold voltage than the second insulated gate field effect transistor, and has a second insulated gate type. 13. The semiconductor device according to claim 12, wherein said field effect transistor is turned off in response to said input signal during said standby cycle. 14. The first insulated gate field effect transistor has a gate insulating film that provides a gate tunnel barrier larger than a gate oxide barrier provided by a silicon oxide film having a thickness of 3 nanometers. 13. The semiconductor device according to claim 12, wherein the gate type field effect transistor includes a gate insulating film that provides a gate tunnel barrier equal to or less than a gate tunnel barrier provided by the silicon oxide film having a thickness of 3 nanometers. 15. The semiconductor device according to claim 12, wherein the first switching transistor and the first insulated gate field effect transistor have different back gate voltages. 16. A power supply node, a power supply line, and a first power supply line connected between the power supply line and the power supply node, selectively turned on in response to an operation cycle instruction signal.
A switching transistor, and a gate circuit which receives the voltage of the power supply line as one operation power supply voltage, operates and performs a predetermined process, wherein the gate circuit includes a first insulated gate type electric field coupled to the power supply line. And a replica circuit including, as a component, an insulated gate field effect transistor in which an insulated gate type field effect transistor and the first switching transistor of the gate circuit are reduced in proportion. A replica circuit having an internal output node corresponding to the power supply line, a transmission circuit transmitting a voltage corresponding to an output voltage of the output node of the replica circuit to the power supply line in response to the operation cycle instruction signal; Wherein the transmission circuit and the first switching transistor are in a conducting state in phase. That, the semiconductor device. 17. The transmission circuit includes a comparison circuit for comparing the voltage of the output node of the replica circuit with the voltage of the power supply line when conducting, and driving the power supply line according to the comparison result. Item 17. The semiconductor device according to Item 16. 18. A first power supply node, a first power supply line, and is coupled between the first power supply node and the first power supply line, and selectively responding to an operation cycle instruction signal. A first switching transistor that conducts; and a first gate circuit that operates by receiving the voltage of the first power supply line as an operation power supply voltage, wherein the first gate circuit includes an insulated gate field effect transistor. A second power supply node that is included as a component, a second power supply line provided separately from the first power supply line, and is coupled between the second power supply node and the second power supply line; A second switching transistor selectively conducting in phase with the first switching transistor in response to a cycle instruction signal; a second gate circuit receiving the voltage of the second power supply line as an operation power supply voltage; Wherein the second gate circuit includes an insulated gate field effect transistor as a component, and a size of a transistor connected to the first power supply line of the first gate circuit and a size of the first switching transistor The ratio is substantially equal to a ratio of a size of a transistor connected to the second power supply line of the second gate circuit to a size of the second switching transistor, and the size is a ratio of a channel width to a channel length. Semiconductor device, given by 19. The first gate circuit is connected to the first power supply line, receives a first input signal at a gate, and receives a first input signal.
A first insulated gate field effect transistor having a gate insulating film thickness of A first unit gate circuit having a second insulated gate type field effect transistor having a gate insulating film thickness of, wherein the second gate circuit has a source connected to the second power supply line, and A third insulated gate field effect transistor having a first gate insulating film thickness while receiving a second input signal at a gate, and a source connected to a fourth power supply line, and a gate connected to the second input signal. 20. The semiconductor device according to claim 18, further comprising a second unit gate circuit having a second gate insulating film and a fourth insulated gate field effect transistor having said second gate insulating film thickness. 20. The semiconductor device further comprising a third gate circuit cascaded with the first gate circuit and receiving an output signal of the first gate circuit, wherein the third gate circuit is connected to the first power supply node. And an insulated gate field effect transistor as components, and cascade-connected to the second gate circuit, the second power supply node and a fourth power supply. A fourth gate circuit receiving the voltage of the line as both operation power supply voltages and including an insulated gate field effect transistor as a component, and being connected between the third power supply line and a third power supply node, and A third switching transistor which is turned on / off in the same phase as the first switching transistor in response to a cycle instruction signal; a fourth power supply line and a fourth power supply node; And a fourth switching transistor that is turned on / off in phase with the second switching transistor in response to the operation cycle instruction signal, and the size of the third switching transistor and the third switching transistor. The ratio of the size of the insulated gate field effect transistor connected to the third power supply line of the gate circuit is the size of the fourth switching transistor and the size of the fourth switching transistor connected to the fourth power supply line of the fourth gate circuit. 19. The semiconductor device according to claim 18, wherein the size ratio is equal to the size of the insulated gate field effect transistor. 21. An insulated gate field effect transistor connected to the first power supply node of the third gate circuit has a second gate insulating film thickness and is connected to the third power supply line. An insulated gate field effect transistor having a first gate insulating film thickness greater than the second gate insulating film thickness, and an insulated gate connected to the second power supply node of the fourth gate circuit The field-effect transistor has a thickness of the second gate insulating film, and the insulated gate field-effect transistor connected to the fourth power supply line has the thickness of the first gate insulating film. 21. The semiconductor device according to 20. 22. An insulated gate field effect transistor connected to the first power supply line of the first gate circuit or an insulated gate field effect transistor connected to the second power supply line of the second gate circuit The size of the first
Or a replica circuit including a replica switching transistor and a replica gate circuit having a size ratio equal to the ratio of the second switching transistor, wherein the replica switching transistor supplies an operation power supply voltage to the replica gate circuit, and the operation cycle instruction 19. The semiconductor device according to claim 18, further comprising a transmission circuit transmitting a voltage corresponding to an operation power supply voltage of said replica gate circuit to said first and second power supply lines in response to a signal. 23. A transfer circuit for comparing an operation power supply voltage of the replica gate circuit with a voltage of an output node, and adjusting a voltage of the output node according to a result of the comparison. 23. The semiconductor device according to claim 22, further comprising a switching circuit responsively coupling said output node to said first and second power supply lines, respectively. 24. The semiconductor device according to claim 18, further comprising a switching circuit for coupling said first and second power supply lines in response to said operation cycle instruction signal. 25. The ratio of the size of the insulated gate field effect transistor connected to the third or fourth power supply line of the third or fourth gate circuit to the size of the third or fourth switching transistor. A replica circuit including a replica switching transistor and a replica gate circuit having equal size ratios, wherein the replica switching transistor supplies an operating power supply voltage to the replica gate circuit; 21. The semiconductor device according to claim 20, further comprising a transmission circuit for transmitting a voltage corresponding to an operation power supply voltage of said replica gate circuit to a fourth power supply line. 26. A comparison circuit for comparing an operation power supply voltage of the replica gate circuit with a voltage of an output node, and adjusting a voltage of the output node according to a result of the comparison. 26. The semiconductor device according to claim 25, further comprising a switching circuit responsively coupling said output node to said third and fourth power supply lines, respectively. 27. The semiconductor device according to claim 20, further comprising a switching circuit for coupling said third and fourth power supply lines in response to said operation cycle instruction signal. 28. A semiconductor device having a standby cycle and an active cycle, comprising: a first and a second silicon-on-insulator structure.
A gate circuit that performs a predetermined process on an input signal and outputs the processed signal, a logic level of the input signal is predetermined in the standby cycle, and the first and second transistors are A bias voltage applying circuit for applying a bias voltage to a body region of the first and second transistors, comprising a gate insulating film having a gate tunnel barrier substantially equal to a silicon oxide film thickness of 3 nanometers or less. The bias voltage applying circuit includes a circuit that makes a bias of a body region of at least an on-state transistor of the first and second transistors in the standby cycle deeper than a bias in the active cycle. The silicon-on-insulator structure is a semiconductor substrate formed on an insulating film. It has an area, the first and second transistors are formed in the semiconductor substrate region,
Semiconductor device. 29. A semiconductor device having a standby cycle and an active cycle, comprising a first and a second silicon-on-insulator configuration.
A gate circuit that performs predetermined logic processing on an input signal and outputs the input signal; and a bias voltage application circuit that applies a bias voltage to a body region of the first and second transistors. The voltage applying circuit includes the first and second voltage applying circuits.
A circuit for making the bias of the body region of the transistor deeper than the bias during the standby cycle and the bias during the active cycle, wherein the silicon-on-insulator configuration includes a semiconductor substrate region formed on an insulating film; The first and second transistors are formed in a semiconductor substrate region;
Semiconductor device. 30. The semiconductor device further comprising a plurality of logic gates cascaded with the gate circuit, wherein each of the plurality of logic gates is
The semiconductor device includes third and fourth transistors having an insulator structure, wherein the third and fourth transistors are connected to the first transistor.
And a second power supply node connected between the first and second power supply nodes and receiving at respective gates an output signal of a preceding circuit, wherein the bias voltage applying circuit comprises a body region of a third and fourth transistor of each of the plurality of logic gates 30. The semiconductor device according to claim 29, wherein said bias is controlled in common with the bias of the body regions of said first and second transistors. 31. A semiconductor device having an active cycle and a standby cycle, wherein the first insulated gate field effect transistor is connected between a first power supply node and an output node and receives an input signal at its gate. Wherein the input signal has a predetermined logic level during the standby cycle, and
The insulated gate field effect transistor is turned on in response to the input signal during the standby cycle, and is constituted by a buried channel type insulated gate field effect transistor, and further comprises an output node and a second power supply node. And a second insulated gate field effect transistor connected between the second insulated gate field effect transistor and receiving the input signal at its gate and turned on complementarily with the first insulated gate field effect transistor. 32. The first and second insulated gate field effect transistors, wherein gate insulating films have the same thickness.
The semiconductor device according to claim 31. 33. The second power supply node is connected to a main power supply voltage supply line via a switching transistor that is turned off during the standby cycle.
2. The semiconductor device according to 1. 34. The semiconductor device according to claim 33, wherein said switching transistor comprises a buried channel type insulated gate field effect transistor. 35. A semiconductor device having an active cycle and a standby cycle, comprising: a first insulated gate field effect transistor connected between a first power supply node and an output node and having a gate receiving an input signal. , The input signal has a predetermined logic level during the standby cycle, and
The insulated gate field effect transistor is turned on in response to the input signal during the standby cycle, and is constituted by a gate depleted insulated gate field effect transistor. A semiconductor device, comprising: a second insulated gate field effect transistor connected to the gate and receiving the input signal at a gate and turned on complementarily with the first insulated gate field effect transistor. 36. The first and second insulated gate field effect transistors, wherein gate insulating films have the same thickness.
The semiconductor device according to claim 35. 37. The power supply node according to claim 35, wherein the second power supply node is coupled to a main power supply voltage line via a switching transistor that is turned off during the standby cycle.
13. The semiconductor device according to claim 1. 38. The switching transistor is a gate depletion type insulated gate field effect transistor,
The semiconductor device according to claim 37. 39. A latch circuit for latching a given signal, the latch circuit including an insulated gate field effect transistor having a first gate tunnel barrier as a component, and further coupled to the latch circuit. A gate circuit for performing a predetermined process on a latch output signal of the latch circuit, wherein the gate circuit forms an insulated gate field effect transistor having a second gate tunnel barrier smaller than the first gate tunnel barrier. A semiconductor device that is included as an element. 40. The semiconductor device according to claim 39, wherein the insulated gate field effect transistor of the gate circuit has a gate insulating film that provides a gate tunnel barrier equal to or less than a gate tunnel barrier provided by a silicon oxide film having a thickness of 3 nanometers. . 41. A first latch circuit for latching a given signal in an active cycle, wherein the first latch circuit comprises an insulated gate field effect transistor having a first gate tunnel barrier. A second latch circuit for latching a signal applied during a standby cycle, the second latch circuit comprising:
An insulated gate field effect transistor having a second gate tunnel barrier larger than the first gate tunnel barrier as a component, and further comprising the first gate tunnel barrier at the time of transition from the active cycle to the standby cycle.
Transferring the latch output signal of the second latch circuit to the second latch circuit and transferring the latch signal of the second latch circuit to the first latch circuit when the standby cycle shifts to the active cycle. A semiconductor device including a transfer circuit. 42. The transfer circuit, wherein the operation cycle instruction signal for instructing the active cycle and the standby cycle indicates the active cycle.
42. The semiconductor device according to claim 41, wherein a latch signal of said latch circuit is transferred to said second latch circuit. 43. The semiconductor device according to claim 41, wherein said transfer circuit is activated when an operation is performed on said first latch circuit. 44. The first latch circuit is coupled to a pipeline stage that operates according to a clock signal,
In response to an operation cycle instruction signal indicating a standby cycle and an active cycle of the first latch circuit, the first latch circuit by the transfer circuit in the next clock cycle in which the operation on the first latch circuit is performed 42. The semiconductor device according to claim 41, wherein a latch signal is transferred from said memory cell to said second latch circuit. 45. An insulated gate field effect transistor for precharging for precharging a precharge node to a predetermined voltage in response to activation of a precharge instruction signal, wherein said insulated gate field effect transistor for precharge is provided. Has a first gate tunnel barrier, is coupled to the precharge node, enters a standby state when the precharge instruction signal is activated, and operates in accordance with a signal applied when the precharge instruction signal is inactive. A semiconductor device, comprising: a gate circuit for driving a precharge node; wherein the gate circuit includes an insulated gate field effect transistor having a second gate tunnel barrier smaller than the first gate tunnel barrier as a component. . 46. A precharge for precharging the precharge node to the predetermined voltage level in response to a precharge auxiliary instruction signal activated when the precharge instruction signal shifts from inactivation to activation. 46. The semiconductor device according to claim 45, further comprising an auxiliary transistor, wherein the precharge auxiliary transistor comprises an insulated gate field effect transistor having the second gate tunnel barrier. 47. The semiconductor device, comprising: an active cycle in which the gate circuit operates and a standby cycle in which the gate circuit is in a standby state, wherein the precharge instruction signal is supplied when the standby cycle continues for a predetermined time or more. A standby mode signal activated in response to a sleep mode instruction signal given to the sleep mode instruction signal, activated during the standby cycle when the sleep mode instruction signal is inactivated, and deactivated when the sleep mode instruction signal is activated. And a standby precharge transistor for precharging the precharge node to the predetermined voltage when the standby instruction signal is activated, wherein the standby precharge transistor has a second gate. Perfect with tunnel barrier A gate-type field effect transistor, 45. The semiconductor device according. 48. A semiconductor device having a standby cycle and an active cycle, wherein the semiconductor device is activated for a predetermined period when shifting from the standby cycle to the active cycle, and is used for precharging a precharge node to a predetermined voltage level. A charging transistor; and a gate circuit for driving the precharge node in accordance with a given signal during the active cycle, wherein the gate circuit has the same gate tunnel barrier as the precharge transistor. Wherein the gate tunnel barrier is a gate tunnel barrier having a size equal to or smaller than a gate tunnel barrier provided by a silicon oxide film having a thickness of 3 nanometers. 49. An insulated gate field effect transistor for preventing floating for holding the precharge node at a voltage level having a polarity different from the predetermined voltage during the standby cycle, wherein the insulated gate type for preventing floating is further included. 49. The semiconductor device according to claim 48, wherein the field effect transistor has a larger gate tunnel barrier than the precharge transistor. 50. A semiconductor device having an active cycle and a standby cycle, wherein the semiconductor device is activated in response to a precharge instruction signal activated in the standby cycle to precharge a precharge node to a predetermined voltage. Wherein the precharging transistor comprises:
An insulated gate field effect transistor having a first gate tunnel barrier; and a gate circuit for driving the precharge node in accordance with a given signal during the active cycle, wherein the gate circuit comprises the first gate Including an insulated gate field effect transistor having a tunnel barrier as a component, further comprising a control circuit for activating the precharge transistor when releasing sleep mode, and maintaining the precharge transistor in an off state during the sleep mode, The sleep mode is set when the standby cycle continues for a predetermined time or more.
Semiconductor device. 51. A plurality of memory cells requiring storage data refresh, a timer circuit for outputting a refresh request instructing refresh of the plurality of memory cells at predetermined intervals, and a memory cell to be refreshed among the plurality of memory cells. A refresh address counter for generating a specified refresh address; and a refresh-related circuit for refreshing storage data of a memory cell specified by a refresh address of the plurality of memory cells in accordance with the refresh request and the refresh address. The timer circuit and the refresh address counter each include an insulated gate field effect transistor having a first gate tunnel barrier as a component, and the refresh circuit includes the first gate tunnel barrier. Comprising an insulated gate field effect transistor having a second gate tunnel barrier of magnitude below as components, a semiconductor device. 52. The first gate tunnel barrier and the second gate tunnel barrier have the same size, the plurality of memory cells are arranged in a matrix, and the refresh address is a memory cell row. Inactive, in a refresh mode in which the refresh is performed periodically, and enabled in a normal mode in which an access operation to the memory cell is performed, and a row of the plurality of memory cells in accordance with an applied address and control signal. Further comprising a row-related circuit for selecting the same, wherein the row-related circuit has substantially the same operation content as the refresh-related circuit, and has a gate tunnel barrier smaller than the first gate tunnel barrier. 6. A semiconductor device comprising a gate type field effect transistor as a component.
2. The semiconductor device according to 1. 53. The refresh mode includes a refresh active cycle in which refresh is performed in response to a refresh request from the timer circuit, and a refresh standby cycle for waiting for issuance of the refresh request. 52. The semiconductor device according to claim 51, further comprising a control circuit for activating a gate tunnel current suppressing mechanism of said refresh circuit. 54. The gate tunnel current suppressing mechanism,
A power supply transistor for supplying a power supply voltage to the refresh-related circuit, wherein the power supply transistor stops supplying the power supply voltage when activated and includes an insulated gate field effect transistor having the first gate tunnel barrier 54. The semiconductor device according to claim 53. 55. The plurality of memory cells are arranged in a matrix, the refresh address specifies a row of memory cells, and the semiconductor device further performs an operation related to column selection of the plurality of memory cells. 52. The semiconductor device according to claim 51, further comprising: a column-related circuit; and a control circuit for activating a column-related gate tunnel current suppressing mechanism of the column-related circuit in the refresh mode. 56. The column-related tunnel current suppressing mechanism includes a column-related power supply transistor for supplying a power-supply voltage to the column-related circuit, wherein the column-related power supply transistor activates a power supply voltage to the column-related circuit when activated. 56. The semiconductor device according to claim 55, further comprising an insulated gate field effect transistor that stops supplying power and has the first gate tunnel barrier. 57. A logic circuit for performing an arithmetic process using at least data stored in the plurality of memory cells during operation, and a logic power supply transistor for shutting off a power supply to the logic circuit in the refresh mode. 52. The semiconductor device according to claim 51, comprising: 58. The semiconductor device according to claim 57, wherein said logic power supply transistor comprises an insulated gate field effect transistor having said first gate tunnel barrier. 59. A logic circuit including an insulated gate field effect transistor as a component, a latch circuit provided corresponding to an internal node of the logic circuit, and latching a signal of the corresponding internal node, and the latch A semiconductor device, comprising: a test path coupled to a circuit, for transferring a signal of the latch circuit, wherein at least the logic circuit is set to a state in which a gate tunnel current is reduced in a standby state. 60. The latch circuit includes an insulated gate field effect transistor having a smaller leak current due to a gate tunnel current in the standby state than the insulated gate field effect transistor which is a component of the logic circuit. 60. The semiconductor device according to claim 59. 61. The latch circuit according to claim 59, wherein the latch circuit comprises an insulated gate field effect transistor having a gate tunnel barrier larger than a gate tunnel barrier of an insulated gate field effect transistor which is a component of the logic circuit. 13. The semiconductor device according to claim 1. 62. The semiconductor device according to claim 59, wherein said latch circuit is a scan register forming a scan path for enabling an internal state of said logic circuit to be observed externally. 63. The semiconductor device according to claim 59, wherein said latch circuit is a scan register forming a scan path for enabling an internal state of said logic circuit to be controlled from outside. 64. A plurality of internal circuits performing a predetermined operation when activated, each of said plurality of internal circuits includes an insulated gate field effect transistor as a constituent element, and further includes: An activation control circuit for generating an internal circuit activation signal for activating the designated internal circuit in response to an internal circuit designating signal designating an internal circuit to be activated, and an operation mode instruction signal; In response to the internal circuit activation signal, the gate tunnel current of the insulated gate field effect transistor of the inactive internal circuit of the plurality of internal circuits is changed to the insulated gate field effect transistor of the active internal circuit. A current control circuit for holding a state smaller than the gate tunnel current of the plurality of internal circuits. And a standby cycle in which the plurality of internal circuits stop operating. 65. The current control circuit, in response to the operation mode instruction signal, in the standby cycle,
Setting the gate tunnel current of the insulated gate field effect transistor of the plurality of internal circuits to the small state;
65. The semiconductor device according to claim 64. 66. A normal array having a plurality of normal memory cells, a redundant array having spare memory cells for repairing a defective normal memory cell having a defect of the normal array, and an insulated gate field effect transistor as components. A normal access circuit for accessing a selected memory cell of the normal array, a spare access circuit including an insulated gate field effect transistor as a constituent element, and a spare access circuit for accessing a spare memory cell of the redundant array And a power supply control circuit for making the gate tunnel current of the insulated gate field effect transistor of the inactive circuit of the normal access circuit larger than the gate tunnel current of the transistor of the active circuit.
Semiconductor device. 67. Each of the spare access circuit and the normal access circuit includes a plurality of selectively activated sub access circuits, and the power supply control circuit includes a non-operating state of the spare access circuit and the normal access circuit. 67. The semiconductor device according to claim 66, further comprising a circuit for setting a selected sub-access circuit to a state having a gate tunnel current smaller than a gate tunnel current of a transistor of the selected sub-access circuit. 68. A determination for activating one of the normal access circuit and the spare access circuit according to an address signal, and a determination for activating one of the normal access circuit and the spare access circuit according to a result of the determination. 7. The circuit according to claim 6, further comprising a circuit, wherein the determination circuit starts the determination operation before an operation mode instruction signal instructing a memory cell selection operation is activated.
7. The semiconductor device according to 6. 69. A determination for activating one of the normal access circuit and the spare access circuit according to an address signal, and a determination for activating one of the normal access circuit and the spare access circuit according to a result of the determination. 67. The semiconductor device according to claim 66, further comprising a circuit, wherein the determination circuit performs the determination operation asynchronously with an operation mode instruction signal instructing a memory cell selection operation.