JP2002064003A - Chip resistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip resistor that is equipped with an upper electrode layer which is never corroded even if a gap is formed between a protective layer and a plating layer, and reduced in manufacturing cost, by decreasing material conducive to a corrosion preventing effect in amount as much as possible, keeping a corrosion preventive effect high. SOLUTION: An upper electrode protective layer 23 is formed on the top surface of an upper electrode layer 22 under a part where a protective layer 40 comes into contact with a plating layer 26. The upper electrode protective layer 23 is formed of thick film of material of high sulfur resistance such as silver alloy containing 5.0% or above palladium.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a chip resistor used as a chip component.

[0002]

2. Description of the Related Art Conventional chip resistors include, for example,
It is formed by a configuration as shown in FIG. That is, the chip resistor X includes the insulating substrate 110 and the electrode unit 1.
20, a resistance layer 130, and a protective layer 140, and a pair of electrode portions 120 are provided on the left and right sides of the insulating substrate 110.
And a plating layer 126. This plating layer 12
6 is a nickel plating layer 127 and a solder plating layer 12
8 are formed by two layers. Here, the plating layer 12
The six ends are fixed so as to be in contact with the ends of the protective layer 140, and are formed such that the upper electrode layer 122, which is generally easily corroded, is not exposed.

[0003]

However, the upper electrode layer 1
22 and the upper electrode layer 12
2 at the boundary between the nickel plating layer 127 and the solder plating layer 128 deposited on the protective layer 140 and the upper electrode layer 122, and between the upper electrode layer 122 and the plating layer 126.
Are strongly adhered to each other. However, in comparison with this, the adhesive strength between the plating layer 126 deposited on the protective layer 140 and the protective layer 140 is lower. In other words, the protection layer 140, the nickel plating layer 127, and the solder plating
8, a gap is formed. This gap is the upper electrode layer 12
2, the upper electrode layer 122, which is generally formed of a silver-based thick film, loses silver contained in the upper electrode layer 122 and its sulfide when used in a corrosive atmosphere where a large amount of sulfide gas is present. The gas reacts with silver sulfide which is an insulator, and the upper electrode layer 122 is corroded. As the corrosion progresses, the upper electrode layer 122 cannot sufficiently function as a conductor. That is, the disconnection of the upper electrode layer 122 may cause a failure of the chip resistor X.

Further, silver of the upper electrode layer 122 is
In order to prevent the characteristics of the chip resistor from deteriorating by being diffused into the resistance layer 130 at the time of baking 0,
There is a case where a small amount of palladium of about 0.5 to 1.0% is contained therein, but it is insufficient as a measure against sulfidation of the upper electrode layer 122.

Accordingly, an object of the present invention is to provide a chip resistor which does not corrode the upper electrode layer even when a gap is formed between the protective layer and the plating layer.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. First, an insulating substrate and a pair of upper electrode layers provided on the insulating substrate are provided. A resistance layer formed between the pair of upper electrode layers, a protective layer formed to cover the resistance layer, at least an end surface of the insulating substrate on the upper electrode layer forming side and the upper electrode layer,
A chip resistor comprising: a side electrode layer formed on a back surface of the insulating substrate facing the upper electrode layer; and a plating layer formed so as to cover at least the side electrode layer; An upper electrode protection layer formed on the upper surface of the upper electrode layer, which is a lower layer below a portion where the upper electrode layer and the plating layer are in contact with each other;

In the chip resistor having the first configuration, since the upper electrode protection layer is provided, the upper electrode layer is exposed even if a gap is formed between the protection layer and the plating layer. There is no. In particular, even if a material having no sulfidation resistance is used for the upper electrode layer, the upper electrode layer is not sulfided, so that there is no danger of breaking the chip resistor such as disconnection. Further, since the upper surface electrode protective layer is formed below the portion where the protective layer and the plating layer are in contact with each other and is laminated on the upper surface of the upper surface electrode layer, it is formed only at the boundary between the protective layer and the plating layer. By doing so, it is possible to reduce the cost as compared with the case where the entire upper electrode layer is formed of a material having anti-sulfuration properties to prevent sulfidation.

Second, in the first structure, the area of the upper electrode protection layer is smaller than the area of the upper electrode layer. Therefore, the cost can be reduced as compared with the case where the entire upper electrode layer is formed of a material having anti-sulfuration characteristics to prevent sulfidation.

Third, an insulating substrate, a pair of upper electrode layers provided on the insulating substrate, a resistive layer formed between the pair of upper electrode layers, and a cover for covering the resistive layer. A formed protective layer, at least an end surface of the insulating substrate on the side where the upper electrode layer is formed, an upper electrode layer, a side electrode layer formed on the back surface of the insulating substrate facing the upper electrode layer, and at least the side electrode And a plating layer formed so as to cover the layer, a part of the upper electrode layer,
It is formed of an upper electrode protection layer having anti-sulfuration characteristics, and the upper electrode protection layer is provided below a portion where the protection layer and the plating layer are in contact with each other.

[0010] In the chip resistor of the third configuration, since the upper electrode protection layer is provided, even if a gap is formed between the protection layer and the plating layer, the upper electrode protection layer in the upper electrode layer is formed. The other parts are not exposed. In particular, even if a material having no sulfidation resistance is used for the upper electrode layer, the upper electrode layer is not sulfided, so that there is no danger of breaking the chip resistor such as disconnection. In addition, since the upper electrode protection layer is partially provided on the upper electrode layer, the cost can be reduced as compared with the case where the entire upper electrode layer is formed of a material having anti-sulfuration properties to prevent sulfuration. It becomes possible.

Fourthly, in the third configuration, the upper electrode layer has a first upper electrode layer in contact with the side electrode layer and a second upper electrode layer in contact with the resistance layer. And the upper electrode protection layer provided between the first upper electrode layer and the second upper electrode layer to connect the first upper electrode layer and the second upper electrode layer. Features.

Fifth, in any one of the first to fourth configurations, the upper electrode protective layer is a silver-based thick film having a palladium content of 5.0% or more. Features. Therefore, it is possible to obtain an upper electrode protection layer having excellent sulfuration resistance.

A sixth feature is that, in any one of the first to fourth configurations, the upper electrode protective layer is a gold-based thick film. Therefore, it is possible to obtain an upper electrode protection layer having excellent sulfuration resistance.

In a seventh aspect, there is provided a method of manufacturing the chip resistor having any one of the first to sixth aspects, wherein the resistance layer and the upper electrode protection layer are simultaneously fired. And Eighthly, the present invention provides a method of manufacturing a chip resistor having any one of the first to sixth configurations,
The resistance layer, the upper electrode layer, and the upper electrode protection layer are simultaneously fired. Thus, the number of manufacturing steps can be reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment
Embodiments will be described with reference to the drawings. A chip resistor A according to the present invention is, as shown in FIG.
, An electrode section 20, a resistance layer 30, and a protective layer 40.

The insulating substrate 10 has a substantially rectangular parallelepiped shape mainly made of alumina, and has a substantially rectangular shape when viewed in plan.

As shown in FIG. 1A, the electrode portions 20 are formed as a pair on the left and right sides, and as shown in FIG. 1A, an upper electrode layer 22, an upper electrode protection layer 23, a side electrode layer 24, and a plating layer 26.
And

Here, the upper electrode layers 22 are formed on the insulating substrate 10 so as to face each other. The upper electrode layer 22 is usually formed of a silver-based thick film.

The upper electrode protection layer 23 is formed as shown in FIG.
(A), (b) and FIG.
2 at a predetermined position on the upper surface. In addition, FIG.
It is a figure which shows arrangement | positioning of each part when the chip resistor A is visually recognized from above, and when the upper surface electrode layer 22, the resistance layer 30, the upper surface electrode protection layer 23, and the protection layer 40 are planarly viewed, the outermost contour is shown. It is illustrated. Actually, all components that are hidden and invisible are drawn with solid lines.

That is, the upper electrode protective layer 23 is provided below the portion where the protective layer 40 and the plating layer 26 are in contact with each other, that is, in contact with the lower side.
, That is, in contact with the upper surface of the upper electrode layer 22. The X direction of the upper electrode protection layer 23 (FIG. 2)
The width of the upper electrode layer 22 can be sufficiently protected even when a gap is formed between the protective layer 40 and the plating layer 26. Of 1
It is one third. As shown in FIG. 2, the width of the upper electrode protection layer 23 in the Y direction is larger than the upper electrode layer 22 and smaller than the protection layer 40. In FIG. 2, a region indicated by hatching is the upper surface electrode protection layer 23. The area of the upper electrode protection layer 23 in plan view is smaller than the area of the upper electrode layer 22 in plan view.

The upper electrode protection layer 23 is formed to prevent the upper electrode layer 22 from being corroded by a sulfide gas. That is, the upper electrode protection layer 23 is formed of a silver-based thick film having a palladium content of 5.0% or more. That is, the palladium content is higher than usual, and if the palladium content is 5.0% or more, the upper electrode layer 22 can be protected from sulfide gas. That is, the upper electrode protection layer 23 is formed of a material having excellent sulfuration resistance. Further, the upper surface electrode protection layer 23 is formed of a conductive film having good plating properties. In addition, this upper surface electrode protection layer 23 is
It may be formed of a gold-based thick film.

The upper electrode protection layer 23 is formed by, for example, screen printing followed by firing, and the upper electrode protection layer 23 may be fired at the same time as the resistance layer 30 is fired. The layer 22, the resistance layer 30, and the upper electrode protection layer 23 may be fired simultaneously.

The side electrode layer 24 is formed as shown in FIG.
As shown in FIG. 5, a part of the upper electrode layer 22, a side surface of the insulating substrate 10, and a part of the lower surface of the insulating substrate 10 are covered. The side electrode layer 24 is formed of a silver-based thick film or a mixture of a synthetic resin and a silver-based thick film. Here, the case of the silver-based thick film is a low-temperature sintering type in which about 80% is composed of silver, and the case of the synthetic resin and the silver-based thick film is about 70%. Fine silver particles and approximately 30% of the remaining synthetic resin are substantially uniformly dispersed.

The plating layer 26 is formed as shown in FIGS.
As shown in FIG. 1, the semiconductor device has a nickel plating layer 27 and a solder plating layer 28. This nickel plating layer 27
A substantially uniform film thickness is formed on the side electrode layer 24, and is applied by electroplating. The nickel plating layer 27 is formed by forming the upper electrode layer 22 on the solder plating layer 2.
This layer is formed in order to prevent elution to 8, and copper may be used other than nickel in some cases. Further, the solder plating layer 28 is formed with a substantially uniform thickness on the nickel plating layer 27, and is also applied by electroplating similarly to the nickel plating layer 27. This solder plating layer 28 is formed by the chip resistor A
Is a layer for improving soldering, and tin may be used in addition to solder.

As shown in FIG. 1A, the resistance layer 30 is formed so as to overlap with the insulating substrate 10 and a part of the pair of upper electrode layers 22. This resistance layer 30
Is, for example, a resistive paste such as ruthenium oxide,
It is formed by screen printing in the above-mentioned position with a substantially uniform film thickness in a substantially uniform shape, followed by baking.

As shown in FIGS. 1A and 1B, the protective layer 40 is formed so as to cover substantially the upper surface of the resistance layer 30. The protective layer 40 is provided at the end of the insulating substrate 10 in the longitudinal direction.
It is formed in a state of contacting with the like without any gap. The protective layer 40 is formed of lead borosilicate glass or a synthetic resin (epoxy, phenol, silicon, or the like).

According to the chip resistor A having the above-described structure, the upper electrode protection layer 23 is provided. Since the upper electrode protection layer 23 has excellent resistance to sulfuration, the upper electrode protection layer 23 has the same structure as the protection layer 40 and the plating layer 26. Even if there is a gap between the upper electrode layers 22, the upper electrode layer 22 is not exposed. In particular, even when an inexpensive material such as a silver-based thick film having a low palladium content or a silver-based thick film not containing palladium is used for the upper electrode layer 22, the upper electrode layer 22 may be sulfided. Therefore, the risk of causing a failure of the chip resistor such as disconnection can be eliminated.

The upper electrode protection layer 23 is formed of a protection layer 40
Is formed only near the boundary between the upper electrode layer 22 and the plating layer 26, so that the entire upper electrode layer 22 is formed of a silver-based thick film or a gold-based thick film having a high palladium content to prevent sulfuration. The amount of expensive noble metal materials such as palladium and gold can be reduced, and the cost can be reduced.

Next, a second embodiment will be described with reference to the drawings. A chip resistor B as a chip component according to the second embodiment of the present invention has substantially the same configuration as the chip resistor A in the first embodiment. However, in the first embodiment, a layer having a high palladium content is provided on the upper electrode layer, whereas in the present embodiment, the layer is provided in the upper electrode layer. .

As shown in FIG. 3A, the chip resistor B includes an insulating substrate 10, an electrode section 20, and a resistance layer 30.
And a protective layer 40.

Here, a pair of the electrode portions 20 is formed on the left and right, and as shown in FIGS. 3A and 3B, the upper electrode layer 21, the side electrode layer 24, and the plating layer 26 are formed. have. Here, the upper electrode layer 21 has a single plate shape as a whole, but includes a first upper electrode layer 21a, a second upper electrode layer 21b, and a third upper electrode layer (upper electrode protection layer) 21c.
And is formed from

The first upper electrode layer 21a, the second upper electrode layer 21b, and the third upper electrode layer 21c are formed as shown in FIG.
As shown in FIG. 4, they are formed on the insulating substrate 10 in substantially the same plane. That is, the third upper electrode layer 21c
Is provided below and in contact with the portion where the protective layer 40 and the plating layer 26 are in contact with each other, that is, on the lower side, and is substantially sandwiched between the first upper surface electrode layer 21a and the second upper surface electrode layer 21b. It is formed without gaps in the state. In other words, the third upper electrode layer 21c is formed in the central portion of the conventional upper electrode layer, that is, in the lower band-like region where the protective layer 40 and the plating layer 26 are in contact with each other. The width of the third upper electrode layer 21c in the X direction (see FIG. 4) is
Even when a gap is formed between the protective layer 40 and the plating layer 26, the first upper electrode layer 21a and the second upper electrode layer 21
b can be protected, specifically, the upper electrode layer 21
It is about 1/4 to 1/3. Further, the width of the third upper electrode layer 21c in the Y direction is the same as that of the first upper electrode layer 21a and the second upper electrode layer 21b, as shown in FIG. In FIG. 4, the area shown by hatching is the third upper electrode layer 21c.

FIG. 4 is a diagram showing the arrangement of each part when the chip resistor B is viewed from above, and when the top electrode layer 21, the resistance layer 30, and the protection layer 40 are viewed in plan, the outermost parts are shown. Is shown in the drawing. Actually, all components that are hidden and invisible are drawn with solid lines.

The first upper electrode layer 21a and the second upper electrode layer 21b are formed of a silver-based thick film substantially similar to the upper electrode layer 22 of the chip resistor A. On the other hand, the third upper electrode layer 21c is connected to the chip resistor A
Is formed of substantially the same material as that of the upper electrode protection layer 23. In other words, the third upper electrode layer 21c is a silver-based thick film having excellent resistance to sulfurization, that is, a silver-based thick film that protects the first upper electrode layer 21a and the second upper electrode layer 21b from corrosion by sulfide gas. It is formed of a silver-based thick film having a high palladium content. That is, specifically, it is formed of a silver-based thick film having a palladium content of 5.0% or more.
The third upper electrode layer 21c may be formed of a gold-based thick film.

The upper electrode layer 21 is formed by first printing the first upper electrode layer 21a, the second upper electrode layer 21b, and the third upper electrode layer 21c separately. The third upper electrode layer 21c and the resistive layer 30 are simultaneously fired, or the third upper electrode layer 21c, the first upper electrode layer 21a, and the second upper electrode layer 21b are simultaneously fired. The number of steps can be reduced.

The side electrode layer 2 in the electrode portion 20
4 and the configuration of the plating layer 26, and further, the configurations of the insulating substrate 10, the resistance layer 30, and the protective layer 40 are the same as those in the first embodiment, and therefore the description thereof is omitted.

According to the chip resistor B having the above structure, the third upper electrode layer 21c as the upper electrode protection layer is provided, and the third upper electrode layer 21c is a silver-based thick film having a high palladium content. And has excellent resistance to sulfuration. Therefore, even if a gap is formed between the protective layer 40 and the plating layer 26 and a sulfurizing gas or the like enters, the first upper electrode layer 21a and the second upper surface The electrode layer 21b is not exposed to the sulfide gas. In particular, inexpensive materials such as a silver-based thick film having a low palladium content and a silver-based thick film not containing palladium are used for the first upper electrode layer 21a and the second upper electrode layer 21b. Also, since the first upper electrode layer 21a and the second upper electrode layer 21b are not sulfided, there is no danger of causing a failure of the chip resistor such as disconnection.

The third upper electrode layer 21c is formed of the protective layer 4
Since it is formed only in the vicinity of the boundary between 0 and the plating layer 26, compared with the case where the entire upper electrode layer 21 is formed of a silver-based thick film or a gold-based thick film having a large palladium content to prevent sulfuration. In addition, the amount of noble metal material such as palladium or gold can be reduced, and the cost can be reduced.

[0039]

According to the chip resistor according to the present invention,
Since the upper electrode protection layer is provided, even if a gap is generated between the protection layer and the plating layer, the upper electrode layer is not exposed, and therefore, the upper electrode layer is not sulfided.
The risk of failure of the chip resistor such as disconnection can be reduced.

By forming the upper electrode protective layer only at the boundary between the protective layer and the plating layer, compared to the case where the entire upper electrode layer is formed of a material having excellent sulfuration resistance to prevent sulfuration. Costs can be reduced.

[Brief description of the drawings]

FIG. 1 is a view showing a chip resistor according to a first embodiment of the present invention, (a) is a longitudinal sectional view thereof, and (b)
Is an enlarged longitudinal sectional view of a main part thereof.

FIG. 2 is a plan view conceptually showing the arrangement of each part in the first embodiment.

3A and 3B are views showing a chip resistor according to a second embodiment of the present invention, wherein FIG. 3A is a longitudinal sectional view thereof, and FIG.
Is an enlarged longitudinal sectional view of a main part thereof.

FIG. 4 is a plan view conceptually showing an arrangement of each part in a second embodiment.

5A and 5B are diagrams showing a conventional example of a chip resistor according to the present invention, in which FIG. 5A is a longitudinal sectional view, and FIG.

[Explanation of symbols]

 A, B Chip resistor 10 Insulating substrate 20 Electrode part 21, 22 Upper electrode layer 21a First upper electrode layer 21b Second upper electrode layer 21c, 23 Upper electrode protection layer 24 Side electrode layer 26 Plating layer 27 Nickel plating layer 28 Solder Plating layer 30 Resistive layer 40 Protective layer

Claims (8)

[Claims] An insulating substrate; a pair of upper electrode layers provided on the insulating substrate; a resistance layer formed between the pair of upper electrode layers; and a protective layer formed to cover the resistance layer. And at least an end surface of the insulating substrate on the side where the upper electrode layer is formed, the upper electrode layer, a side electrode layer formed on the back surface of the insulating substrate facing the upper electrode layer, and at least the side electrode layer. A chip layer having a plating layer formed so as to cover the lower surface of a portion where the protective layer and the plating layer are in contact with each other, and an upper surface formed by being stacked on the upper surface of the upper electrode layer. A chip resistor comprising an upper electrode protection layer having an anti-sulfuration property as an electrode protection layer. 2. The chip resistor according to claim 1, wherein an area of the upper electrode protection layer is smaller than an area of the upper electrode layer. 3. An insulating substrate, a pair of upper electrode layers provided on the insulating substrate, a resistive layer formed between the pair of upper electrode layers, and a protective layer formed to cover the resistive layer. And at least an end surface of the insulating substrate on the side where the upper electrode layer is formed, the upper electrode layer, a side electrode layer formed on the back surface of the insulating substrate facing the upper electrode layer, and at least cover the side electrode layer. A chip resistor comprising: a formed plating layer; and a part of the upper electrode layer is formed by an upper electrode protection layer having anti-sulfuration characteristics. A chip resistor provided below a portion where the substrate and the plating layer are in contact with each other. 4. The upper electrode layer has a first upper electrode layer on a side in contact with the side electrode layer, a second upper electrode layer on a side in contact with the resistance layer, and the first upper electrode layer and the second upper surface. 4. The chip resistor according to claim 3, wherein the chip resistor is formed from the upper electrode protection layer provided between the electrode layers to connect the first upper electrode layer and the second upper electrode layer. . 5. The chip resistor according to claim 1, wherein the upper surface electrode protective layer is a silver-based thick film having a palladium content of 5.0% or more. 6. The chip resistor according to claim 1, wherein the upper electrode protection layer is a gold-based thick film. 7. The above-mentioned claim 1 or 2 or 3 or 4 or 5
Or the method of manufacturing a chip resistor according to 6, wherein the resistance layer and the upper electrode protection layer are simultaneously fired. 8. The above-mentioned claim 1 or 2 or 3 or 4 or 5
7. The method of manufacturing a chip resistor according to 6, wherein the resistance layer, the upper electrode layer, and the upper electrode protection layer are simultaneously fired. 8.