JP2002057132A - Method of chemical mechanical polishing of semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of reducing flaws generated in a chemical mechanical polishing process to prevent a short. SOLUTION: There is provided a semiconductor substrate having a first dielectric layer on a surface thereof. The first dielectric layer is subjected to a chemical mechanical polishing process. A second dielectric layer, of which material is the same as that of the first dielectric layer, is deposited on the wafer surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chemical mechanical polishing method for a semiconductor substrate, and more particularly to a method for reducing defects generated in a chemical mechanical polishing step.

[0002]

2. Description of the Related Art As the dimensions of semiconductor devices have shrunk, the demand for optical resolution of in-process optical light exposure (photolithography) has become increasingly stringent. In order to obtain a higher degree of optical resolution, it is necessary not only to improve the performance of the equipment, but also to eliminate possible causes of interference during the process. is there. Therefore, during the process of high-density integrated circuits, it is essential to further flatten the micro-surface of the material. For example, metal interconnection
The metal wiring dielectric layer deposited during the process is the first on the chip surface.
Since the surface unevenness occurs with the metal layer, the head problem is solved by the planarization treatment method, and the light exposure process of the second metal layer manufactured thereafter is performed by the exposure focus (exposure focus).
It is necessary to prevent the pattern from becoming difficult to transfer due to s).

[0003] Among various planarization methods, chemical-mechanical polishing (CMP) technology predominates and is currently an important process technology on a production line. trench iso
lation, STI), metal wiring process, etc., but it is necessary to improve some shortcomings of the technology.
FIG. 1 shows a cross-sectional view of a defect generated by a known CMP process. According to a known technique, when a metal wiring process is performed, first, a first metal layer 12 is formed on a semiconductor substrate 10, and the first metal layer 12 forms a plurality of first wirings 12 by light exposure and etching. Thereafter, a dielectric layer 14 is deposited on the substrate 10,
The groove between the first wiring 12 is covered. Further, the dielectric layer 14 is partially removed by a CMP process, and the dielectric layer 14 is planarized. Subsequently, a second metal layer 16 is formed on the dielectric layer 14,
The second metal layer 16 forms a plurality of second wirings 16 again by light exposure and etching.

However, if granules remain in the dielectric layer 14, voids are likely to occur after the CMP process.
The first metal layer 12 may be exposed. When the subsequent second metal layer 16 is manufactured, the second metal layer 16 comes into contact with the exposed first metal layer 12 to cause electrical connection, which affects the electrical characteristics of the device. In addition, if the slurry component used in the CMP process does not meet the appropriate process parameters, a pattern (ch) is formed on the surface of the first metal layer 12.
atter mark) or shallow trench
In addition to the occurrence of such defects, the effect of exposing the optical light thereafter is reduced, and a short circuit phenomenon occurs between the plurality of second wirings 16 due to electrical connection.

[0005]

SUMMARY OF THE INVENTION Based on the above facts,
An object of the present invention is to provide a method for reducing defects generated in a chemical mechanical polishing process, and to solve the above-mentioned short phenomenon.

[0006]

SUMMARY OF THE INVENTION The present invention provides a method for improving defects caused in a CMP process, comprising providing a semiconductor substrate, comprising a first dielectric layer on a surface of the semiconductor substrate, and Performing a chemical mechanical polishing process; then depositing a second dielectric layer on the substrate surface, wherein the material of the second dielectric layer is the same as the material of the first dielectric layer.

[0007] Preferably, the second dielectric layer is formed by chemical vapor deposition. Preferably, the thickness of the second dielectric layer is 100 to 250 nm. Preferably, a first conductive layer is provided on the semiconductor substrate surface, the first conductive layer being covered by the first dielectric layer. Preferably, the first and second dielectric layers insulate the first conductive layer from a second conductive layer formed on the second dielectric layer. Preferably, said first dielectric layer is formed by chemical vapor deposition.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION In order to further clarify the above-mentioned objects, features and advantages of the present invention, preferred embodiments of the present invention will be described below with reference to the drawings.

FIGS. 2 to 5 are schematic views showing a method of the present invention for improving defects generated in a CMP process. As shown in FIG. 2, when performing a metal wiring process, first, a first conductive layer 22 having a thickness of about 400 nm is formed on a semiconductor substrate 20, and the first conductive layer 22 is made of polysilicon or metal. By light exposure and etching, the first conductive layer 22 becomes a plurality of first conductive layers.
The wiring 22 is formed.

[0010] Then, chemical vapor deposition (chemical vapor deposition)
A first dielectric layer 24 is formed on the substrate 20 by deposition (CVD), and covers a groove between the first wirings 22.
The material of the first dielectric layer 24 is an oxide layer such as general silicon oxide, plasma enhanced tetraethoxy base silicide, nitric oxide silicide, and the like. Also, inappropriate steps or use of materials may leave granules 25 in the first dielectric layer 24.

Next, as shown in FIG. 3, a flattening process is performed by a CMP process to partially remove the first dielectric layer 24 to form a flattened surface.

However, even if the granules 25 remaining in the first dielectric layer 24 are removed, voids 26 remain on the surface of the first dielectric layer 24.
Not only occurs, but also the first metal layer 22 around the void 26.
Will be exposed. Also, under the influence of slurry components and process parameters used during the CMP process,
During the polishing process, a pattern (chattermar) is formed on the surface of the first dielectric layer 24.
k) or a defect such as a shallow trench 28 occurs.

Subsequently, as shown in FIG.
In order to prevent defects such as shallow trenches 28 from affecting the electrical properties of the device, the present invention uses CVD to form a layer having a thickness of about 100 to 25 on the surface of the first dielectric layer 24.
The second dielectric layer 30 having a thickness of 0 nm is uniformly deposited, and the material thereof is the same as the material of the first dielectric layer 24, and the exposed first metal layer 22 is formed.
To compensate for the defects on the surface of the first dielectric layer 24, and further flatten the entire surface of the substrate 20.

Subsequently, as shown in FIG. 5, the second dielectric layer 3
A second conductive layer 32 having a thickness of about 400 nm is formed on the zero surface. The second dielectric layer 32 is made of polysilicon or metal.
The second conductive layer 32 forms a plurality of second wirings 32 by light exposure and etching. In the present invention, the second dielectric layer 30
The first dielectric layer 24 and the second dielectric layer 3
0 effectively insulates the first conductive layer 22 from the second conductive layer 32 and prevents the electrical connection between the exposed first conductive layer 22 and the second conductive layer 32. In addition, the second dielectric layer 30 is
Filling voids on the surface of the dielectric layer 24 and effectively insulating a plurality of second interconnections 32 formed thereafter;
An electrical connection between the second wirings 32 is prevented.

Although the preferred embodiments of the present invention have been disclosed above, they are not intended to limit the invention in any way, and anyone skilled in the art will be aware of the scope and spirit of the present invention. Thus, various variations and colors can be added, and the protection scope of the present invention is based on the contents specified in the claims.

[0016]

As described above, according to the present invention, defects generated in the chemical mechanical polishing step can be reduced, and occurrence of a short phenomenon can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a defect generated in a known CMP process.

FIG. 2 is a cross-sectional view illustrating a method of the present invention for improving defects generated in a CMP process.

FIG. 3 is a cross-sectional view showing a method of the present invention for improving a defect generated in a CMP process and continuing from FIG. 2;

FIG. 4 is a cross-sectional view showing a method of the present invention for improving a defect generated in a CMP process and showing a continuation of FIG. 3;

FIG. 5 is a cross-sectional view showing a method of the present invention for improving a defect generated in a CMP step and continuing from FIG. 4;

[Explanation of symbols]

20 ... substrate, 22 ... first conductive layer, first wiring, 24 ... first dielectric layer, 25 ... granule, 26 ... void, 28 ... shallow trench, 30
... second dielectric layer, 32 ... second conductive layer, second wiring.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Xiao Jianjun No. 50, No. 95, 213 Alley, Kangshan Forest Grove, Hsinchu City, Taiwan F-term (reference) 5F043 AA33 DD16 FF07 GG03

Claims (6)

[Claims] 1. A chemical mechanical polishing method for a semiconductor substrate, comprising: providing a semiconductor substrate having a first dielectric layer on a surface thereof; performing a chemical mechanical polishing step on the first dielectric layer; A second dielectric layer made of the same material as the first dielectric layer;
A chemical mechanical polishing method comprising depositing a dielectric layer. 2. The method according to claim 1, wherein the second dielectric layer is formed by chemical vapor deposition. 3. The chemical mechanical polishing method according to claim 1, wherein the thickness of the second dielectric layer is 100 to 250 nm. 4. The chemical mechanical polishing method according to claim 1, further comprising a first conductive layer on the surface of the semiconductor substrate, the first conductive layer being covered with the first dielectric layer. 5. The first dielectric layer and the second dielectric layer include a first conductive layer and a second dielectric layer formed on the second dielectric layer.
The chemical mechanical polishing method according to claim 4, wherein the conductive layer is insulated from the conductive layer. 6. The chemical mechanical polishing method according to claim 1, wherein the first dielectric layer is formed by chemical vapor deposition.