JP2002057085A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can form a resist pattern having small linewidth fluctuations on a transparent film. SOLUTION: In the method for manufacturing a semiconductor device, a resist film 14 is coated on a silicon substrate 11 through a pad oxide film 12 and a silicon nitride film 13, and then the resist film 14 is subjected to a lithography process to form a resist pattern. In an allowable thickness range of the flat-surfaced silicon nitride film 13 and in an allowable thickness range of the flat-surfaced resist film 14, optimum values of the thicknesses of the films 13 and 14 are selected so that the resist pattern have optimal film thickness.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for optimizing the thickness of a transparent film and a resist film when a resist pattern is formed on a transparent film having a planarized surface. It relates to a manufacturing method.

[0002]

2. Description of the Related Art In lithography for forming a resist pattern on an interlayer insulating film on a highly reflective substrate,
Since the interlayer insulating film has transparency to exposure light,
Exposure light is reflected on the surface of the substrate or at the interface between the interlayer insulating film and the resist film to easily cause multiple interference. For this reason, variation (so-called standing wave effect) easily occurs in the line width of the resist pattern. In particular, a resist film applied on an interlayer insulating film having a large surface step has a large thickness variation, so that a standing wave effect is likely to occur partially, and a line width variation of the resist pattern occurs even in the substrate surface. become.

Therefore, an antireflection film is provided on the interface between the substrate and the interlayer insulating film, the interface between the interlayer insulating film and the resist film, the surface of the resist film, or the like. By stacking a film, the reflection of exposure light is prevented, and the occurrence of the standing wave effect is suppressed.

[0004]

However, such a method of providing an antireflection film having a plurality of layers or a laminated film of an antireflection film and a high-absorbing film causes an increase in the number of steps and an increase in manufacturing cost. Has become. In recent years, the level difference on the surface of the interlayer insulating film has been reduced due to the development of the planarization technology, and the variation in the thickness of the resist film applied thereon has also been reduced. Therefore, as described above, instead of the above-described manufacturing method on the assumption that the thickness variation of the resist film is large, a process optimization method corresponding to the case where the thickness variation of the resist film is small is required. .

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a resist pattern having a small line width variation on a transparent film having a flat surface.

[0006]

In order to achieve the above object, the present invention provides a method for forming a transparent film on a substrate, applying a resist film on the transparent film, and subjecting the resist film to lithographic processing. This is a method of manufacturing a semiconductor device in which a resist pattern is formed on a transparent film by performing the resist pattern in an allowable range of the thickness of the resist film so as to minimize the line width variation of the resist pattern on the transparent film having a flat surface. It is characterized in that the optimum value of the film thickness is selected. Here, the transparent film includes a translucent film, and specific examples include a silicon nitride film, a silicon oxide film,
It is a silicon nitride oxide film, a polysilicon film, an amorphous silicon film, a titanium nitride film, or the like.

The above-described manufacturing method aims at optimizing the thickness of a resist film having a small thickness variation (uniform thickness) applied on a transparent film having a flat surface, and aims at optimizing the line width of the resist pattern. The optimum value of the thickness of the resist film is selected so as to minimize the variation. For this reason, on the transparent film,
A resist film having a small variation with respect to the selected optimum value is applied. Therefore, on the transparent film,
Without providing an anti-reflection film or a high light absorption film for preventing the occurrence of the standing wave effect, a resist pattern in which the line width variation is suppressed to be small relative to the initial line width is formed.

At this time, when the thickness of the resist film is optimized so that the line width variation of the resist pattern is minimized with respect to a predetermined film thickness of the transparent film, the line width variation of the resist pattern is reduced. The thickness of the resist film may be selected within the allowable range of the thickness so as to minimize the thickness.

In the case where an anti-reflection film is provided on at least one of the resist film and the resist film, after setting the thickness of the anti-reflection film, the thickness of the anti-reflection film is set within the allowable range of the resist film. The optimum value of the thickness of the antireflection film is selected so that the line width variation of the resist pattern is minimized. At this time, the optimum value of the thickness of the resist film is selected so that the line width variation of the resist pattern with respect to the thickness variation of the transparent film is minimized.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a cross-sectional view for explaining a step of forming an element isolation on the front surface side of a substrate. In the first embodiment, FIG. A method for optimizing the film thickness of each film in the case where element isolation is formed will be described.

Here, when forming the element isolation, first, an extremely thin pad oxide film (made of silicon oxide) 12 having a thickness of about 10 nm is formed on a silicon substrate 11, and then this pad oxide film 12 is formed. A silicon nitride film 13 is formed thereon. Next, a resist film 14 is applied on the silicon nitride film 13, and the resist film 14 is lithographically processed to form a resist pattern. Then, using the resist pattern as a mask, the silicon nitride film 14 is etched, and further, the pad oxide film 12 and the silicon substrate 11 are etched to form trenches for element isolation on the surface side of the silicon substrate 11.

In the above steps, a pad oxide film 1 as a transparent film is formed on a silicon substrate 11 as a highly reflective substrate.
2 and a resist film 14 are provided via the silicon nitride film 13. Therefore, during pattern exposure in the lithography process, the exposure light h at the surface of the silicon substrate 11 and at the interface between the silicon nitride film 13 and the resist film 14 is exposed.
Reflection may cause multiple interference, and a standing wave effect may occur. However, since the resist film 14 is applied on the silicon nitride film 13 having a flat surface, the thickness variation thereof is suppressed to 1% or less.

Therefore, the thicknesses of the resist film 14 and the silicon nitride film 13 are optimized as follows. Here, from the allowable range of the thickness of the silicon nitride film 13 defined by the process, the thickness that minimizes the dimensional variation of the resist pattern formed by the resist processing is selected. At the same time, a film thickness that minimizes the dimensional variation of the resist pattern formed by the resist processing is selected from the allowable thickness range of the resist film 14 defined by the process. Although the pad oxide film 12 is also a transparent film, its thickness is as thin as 10 nm.
Here, only the thickness of the silicon nitride film 14 may be optimized.

First, the thickness of the silicon nitride film 13 and other conditions are fixed, and a sample is formed using the thickness of the resist film 14 as a factor to form a resist pattern. At this time, the thickness of the silicon nitride film 13 is fixed to a constant value (for example, a median value, here, 148 nm) within an allowable thickness range defined by the process. Then, the line widths of these resist patterns are measured, and the film thickness having the smallest variation is selected as the optimum value of the film thickness of the resist film 14.

FIG. 2 is a graph showing the relationship between the thickness of the resist film 14 and the line width variation (3σ) of the resist pattern. Here, the allowable range of the thickness of the resist film 14 defined by the process is assumed to be 500 nm to 580 nm, and a sample in which the resist film 14 is applied in steps of 10 nm in the allowable range of the thickness is prepared to form a resist pattern. Was measured. From this graph, it was confirmed that when the film thickness of the resist film 14 was in the range of 500 nm to 580 nm, the variation in the line width of the resist pattern was the smallest and the smallest at the film thickness of 540 nm. 540n as value
Select m.

Next, the thickness of the silicon nitride film 13 is optimized so that the line width variation of the resist pattern is minimized at the optimum value of the resist film 14 selected as described above. Here, the resist pattern is formed by fixing the film thickness of the resist film 14 and other conditions and fabricating a sample using the allowable thickness range of the silicon nitride film 13 as a factor. Then, the line widths of these resist patterns are measured, and the film thickness with the smallest variation is selected as the optimum value of the film thickness of the silicon nitride film 13.

FIG. 3 is a graph showing the relationship between the thickness of the silicon nitride film 13 and the line width (Critical Dimension) of the resist pattern. Here, the allowable thickness range of the silicon nitride film 13 specified by the process is 125 nm to
It was 165 nm. The thickness of the resist film 14 was fixed at 540 nm, which was selected as the optimum value. From this graph, it can be seen that the thickness of the silicon nitride film 13 is 1
In the range of 25 nm to 165 nm, the film thickness is 148 nm.
It is confirmed that the variation in the line width of the resist pattern is smallest in the above, and 148 nm is selected as the optimum value of the thickness of the silicon nitride film 13.

After selecting the optimum values of the thicknesses of the silicon nitride film 13 and the resist film 14 as described above, the respective films are laminated in the configuration described with reference to FIG. And perform lithography processing. Thus, a resist pattern for device isolation trench processing is formed on the silicon nitride film 13.

According to such a manufacturing method, since the resist film 14 is formed on the silicon nitride film 13 having a flat surface, the resist film 14 having a small thickness variation (uniform thickness) is targeted. The thicknesses of the resist film 14 and the silicon nitride film 13 are optimized so that the width variation is minimized. Therefore, a resist having a small thickness variation with respect to the initial line width is not provided on each part on the silicon nitride film 13 without providing an anti-reflection film or a high light absorption film for preventing the standing wave effect from occurring. It becomes possible to form a pattern. Therefore, it is possible to omit the manufacturing process of the antireflection film and the high light absorption film, and to reduce the number of manufacturing processes of the semiconductor device.

In the first embodiment, after selecting the optimum value of the thickness of the resist film 14, the silicon nitride film 13
Although the optimum value of the film thickness is selected, the optimum film thickness of the resist film 14 may be selected at a predetermined film thickness of the silicon nitride film 13. By adopting such a procedure, the present invention can be applied even when the thickness of the silicon nitride film 13 is severely restricted.

(Second Embodiment) FIG. 4 is a cross-sectional view for explaining a step of forming a gate wiring having a polycide structure on a substrate. In the second embodiment, FIG. A method of optimizing the thickness of each film when forming a gate wiring will be described.

Here, when forming the gate wiring, first, the silicon substrate 1 having the element isolation 11a formed on the surface thereof is used.
A polycide film 22 is formed on 1 through a gate oxide film 21. The polycide film 22 is formed, for example, by stacking a silicide film made of tungsten silicide (WSi) on a polysilicon film. Next, a silicon oxide film 23 serving as an offset film is formed on the polycide film 22, and a resist film 25 is further interposed via an antireflection film 24.
To form Then, a resist pattern composed of the resist film 25 is formed by lithography, and the antireflection film 24 is formed by using the resist pattern as a mask.
The silicon oxide film 23 and the polycide film 22 are etched. Thus, a gate wiring having a polycide structure having an offset film made of silicon oxide on the silicon substrate 11 is formed.

In the above steps, the silicon oxide film 23 as a transparent film is formed on the polycide film 22 as a highly reflective surface.
A resist film 25 is provided through the substrate. Although an antireflection film 24 (so-called BARC) is provided between the silicon oxide film 23 and the resist film 25, the thickness of the antireflection film 24 has process restrictions. For this reason,
During pattern exposure in the lithography process, a standing wave effect due to multiple interference may occur. However, the resist film 25 is a silicon oxide film 23 having a flat surface.
Since it is applied on top, its thickness variation is suppressed to 1% or less.

Therefore, the thicknesses of the resist film 25 and the silicon oxide film 23 are optimized as follows. First, the film thickness of the antireflection film 24 is set in consideration of the process conditions. Here, for example, the film thickness of the antireflection film 24 is set to 65 nm in consideration of workability thereafter.

Next, as shown in FIG. 5, in pattern exposure at the time of lithography, the energy (energy absorption rate) absorbed by the resist film is changed by the silicon oxide film 2.
3 and the thickness of the resist film 25. At this time, the thickness of the silicon oxide film 23 and the resist film 2
The film thickness of 5 is changed in a film thickness allowable range defined by the process. Here, for example, the allowable thickness of the silicon oxide film 23 is 0.12 μm to 0.20 μm, and the allowable thickness of the resist film 25 is 0.39 μm to
It is assumed to be 0.54 μm. The real component n and the imaginary component k of the complex refractive index of each film used the values shown in Table 1 below.

[Table 1]

From FIG. 5, it can be seen from FIG. 5 that the silicon oxide shows the region where the energy absorption rate in the resist film 25 is most stable, that is, the area where the line width of the resist pattern is stable because the energy absorption rate shows a stable value. The film thickness of the film 23 and the film thickness of the resist film 25 are selected as optimal values. Here, for example, it is assumed that the thickness variation of the silicon oxide film 23 is about ± 15%, and the thickness of the silicon oxide film 23 and the thickness of the resist film 25 indicating a region capable of absorbing the thickness variation are optimized. Select as a value. Therefore, the optimum value of the thickness of the resist film 25 is 0.46 μm.
m was selected. If the thickness of the resist film 25 is 0.46 μm, the thickness of the silicon oxide film 23 is 0.12 μm or less.
Even if it varies in the range of 0.20 μm, pattern exposure with a stable energy absorption rate is performed. The optimum thickness of the silicon oxide film 23 is 0.12 μm to 0.20 μm when the thickness variation is about ± 15%.
0.15 μm was selected to be in the range of μm.

After setting the film thicknesses of the silicon oxide film 23 and the resist film 25 as described above, the respective films are stacked according to the film thicknesses set in this manner and described with reference to FIG. Perform processing. As a result, a resist pattern for processing a gate wiring is formed on the silicon oxide film 23 serving as an offset film of the gate wiring.

According to such a manufacturing method, similarly to the first embodiment, the resist film 25 on the silicon oxide film 23 having a flat surface is targeted, and the resist film is formed so that the line width variation of the resist pattern is minimized. Since the thicknesses of the silicon oxide film 25 and the silicon oxide film 23 are selected, it is possible to form a resist pattern having an initial line width on each part on the substrate. Therefore, when providing an anti-reflection film or a high light absorption film to prevent the occurrence of the standing wave effect, a smaller film thickness or a smaller number of films is sufficient, and the film formation time and the number of processes are reduced. Can be achieved.

(Third Embodiment) FIG. 6 is a cross-sectional view for explaining a step of forming a connection hole in an insulating film covering a metal wiring on a substrate. In the third embodiment, FIG. A method of optimizing the thickness of each film when forming a connection hole on a metal wiring will be described.

Here, when forming the connection hole, first, a silicon oxide film 32 is formed on a substrate (not shown) in a state of covering the metal wiring 31 whose surface is covered with a titanium nitride film (TiN). The surface of the silicon oxide film 32 is
(Chemical Mechanical Polishing) Flatten by polishing. Thereafter, a resist film 33 is applied on the silicon oxide film 32, and an antireflection film 34 is formed on the resist film 33. Then, a resist pattern composed of the resist film 33 is formed by lithography, and the silicon oxide film 32 is etched using the resist pattern as a mask. As a result, a connection hole reaching the metal wiring 31 is formed in the silicon oxide film 32.

In the above steps, the resist film 3 is formed on the metal wiring 31 via the transparent silicon oxide film 32.
3 are provided. The anti-reflection film 3 is formed on the resist film 33.
Although 4 (so-called TARC) is provided, the thickness of the antireflection film 34 has process restrictions. Therefore, at the time of pattern exposure in the lithography process, the exposure light h is reflected on the surface of the metal wiring 31 and the interface between the silicon oxide film 32 and the resist film 33, and a standing wave effect due to multiple interference may occur. is there. Further, the surface of the silicon oxide film 32 after the CMP polishing has a step depending on the variation of the polishing rate due to the density of the underlying metal wiring. For this reason, the metal wiring 31 after the CMP is polished.
The thickness of the upper silicon oxide film 32 is one cycle with respect to the exposure wavelength λ (however, one cycle is λ / 2 × n, where n is the refractive index of the silicon oxide film, even though it is flattened). The above-mentioned variation occurs.

Therefore, the thicknesses of the resist film 33 and the silicon oxide film 32 are optimized as follows. First, the film thickness of the antireflection film 34 is set in consideration of the process conditions. Here, for example, an HDP film as the antireflection film 34, that is, HDP (high density plasma) -CVD (chemical vap) is used.
or a silicon oxide film formed by the deposition method, the anti-reflection film 3 is used in consideration of workability thereafter.
4 is set to 46 nm.

Next, as shown in FIG. 7, the relationship between the exposure amount variation with respect to the thickness variation of the silicon oxide film 32 and the film thickness of the resist film 33 is obtained. At this time, the silicon oxide film 32 is set to 750 nm due to process restrictions, and has a variation in the range of ± 250 nm. The thickness of the resist film 33 is 0.70 μm or more within the allowable thickness range defined by the process.
Vary between 0.80 μm. Table 2 below shows the real component n and the imaginary component k of the complex refractive index of each film and the film thickness d. The TiN film on the surface of the metal film wiring 31 has a thickness of 70 nm.
Therefore, in the metal wiring 31, this Ti
The N film is used as a bulk material.

[Table 2]

FIG. 7 shows that the silicon oxide film 3
As the optimum value of the resist film 33 in the case where the film thickness of No. 2 varies in the range of 750 nm ± 250 nm, 0.775 μm with the smallest variation in the exposure dose is selected.

After setting the film thicknesses of the silicon oxide film 32 and the resist film 33 as described above, the respective films are laminated according to the film thicknesses set in this manner with the configuration described with reference to FIG. Perform processing.

According to such a manufacturing method, the optimum value of the thickness of the resist film 33 is selected within the range of the variation of the silicon oxide film 32 so that the variation in the line width of the resist pattern is minimized. Even if the thickness of the underlying transparent film (silicon oxide film 32) varies, the metal wiring 3
It is possible to form a resist pattern having an initial line width on each part on the first line. Therefore, when an anti-reflection film or a high light absorption film is provided to prevent the occurrence of the standing wave effect, a smaller number of films is required, and the number of steps can be reduced.

[0038]

As described above, according to the method of manufacturing a semiconductor device of the present invention, by optimizing the resist film on the transparent film having a flat surface together with the thickness of the transparent film, each part on the substrate can be formed. It becomes possible to form a resist pattern having an initial line width. Therefore, it is not necessary to provide an antireflection film or a high light absorption film for preventing the occurrence of the standing wave effect, and when it is provided, a smaller film thickness or a smaller number of films may be used. It is possible to reduce the number of processes and the number of steps and thereby reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a first embodiment.

FIG. 2 is a diagram showing a relationship between a resist film thickness and a line width variation of a resist pattern.

FIG. 3 is a diagram showing the relationship between the thickness of a silicon nitride film and the line width of a resist pattern.

FIG. 4 is a sectional view illustrating a second embodiment.

FIG. 5 is a distribution diagram of an energy absorptivity of the resist film with the thickness of the silicon oxide film and the resist film as factors.

FIG. 6 is a sectional view illustrating a third embodiment.

FIG. 7 is a diagram showing a relationship between a resist film thickness and a variation in exposure amount with respect to a variation in a silicon oxide film.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Substrate, 12 ... Pad oxide film, 13 ... Silicon nitride film, 14, 25, 33 ... Resist film, 22 ... Polycide film, 23, 32 ... Silicon oxide film, 31 ... Metal wiring, 2
4,34 ... Anti-reflective coating

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Sato Politics 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture F-term in Fujitsu Limited (reference) 2H025 AA03 AB16 BJ00 DA03 DA18 DA34 DA40 5F033 HH04 HH26 KK33 QQ01 QQ04 QQ08 QQ09 QQ37 RR04 XX00 XX33 XX34 5F046 JA21

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: forming a transparent film on a substrate, applying a resist film on the transparent film, and performing lithography on the resist film to form a resist pattern on the transparent film. An optimal value of the thickness of the resist film is selected within an allowable range of the thickness of the resist film so that a line width variation of the resist pattern is minimized on the transparent film having a flat surface. A method for manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein an optimum value of the thickness of the resist film is selected, and the optimum value of the thickness of the transparent film is set within an allowable range of the thickness of the transparent film. A method for manufacturing a semiconductor device, comprising: selecting a semiconductor device; 3. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the resist film is set so that a line width variation of the resist pattern is minimized with respect to a predetermined thickness of the transparent film. A method of manufacturing a semiconductor device, comprising selecting an optimum value of 4. The method for manufacturing a semiconductor device according to claim 1, wherein an antireflection film is provided on at least one of the resist film and the resist film, and the thickness of the antireflection film is set. And a method of manufacturing the semiconductor device, wherein an optimum value of the resist film is selected within an allowable thickness range of the resist film so that a line width variation of the resist pattern is minimized. 5. The method for manufacturing a semiconductor device according to claim 4, wherein an optimum value of the thickness of the resist film is selected such that a variation in line width of the resist pattern with respect to a variation in thickness of the transparent film is minimized. A method for manufacturing a semiconductor device, comprising: