JP2002055667A - Device and method for outputting image - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image output device, in which display of image data is periodically updated and are also immediately updated by an absolute minimum data transfer. SOLUTION: A video processing section 104 in an image output device is provided with a data transfer request control circuit 107, which includes a frame rate register 108 that determines the data transfer request issuing period and a data transfer request issuing section 109. When an update flag is set in the register 108, a data transfer request is issued, regardless of the periodic transfer period set in the register 108, so as to make the display image data stored in a frame memory 106 updated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image output apparatus and an image output control method.

[0002]

2. Description of the Related Art In recent years, as the number of portable terminals using a liquid crystal display device has increased and the importance of image display has increased, low power consumption has become an important issue. Liquid crystal devices typically require high display refresh rates and require 60 Hz updates. However, since image generation is performed at 30 Hz or less, the difference in the rate is absorbed by having a frame buffer or the like. An electronic drawing apparatus having such a frame buffer is disclosed in JP-A-07-7795.
No. 8 is disclosed and will be described with reference to FIG.

FIG. 15 is a block diagram showing a configuration of the electronic drawing apparatus 1. In FIG. 15, the data supply unit 10
Includes an intermediate data generation unit 11 for generating intermediate data from graphic element data, and a glyph data generation unit 12 for generating glyph data from the intermediate data generated by the intermediate data generation unit 11. The data is converted into the image data, which is a dot data string in the scanning order of the image forming device, and supplied to the output selection unit 30 and the superimposition control unit 60. The frame memories 20 and 21 store the second internal glyph data that is the glyph data for one frame supplied from the output selection unit 30. By inputting the R / W control signal from the control unit 50, 1
A writing mode for writing frame-shaped figure data,
And a reading mode for reading stored one-frame image data. The output selection unit 30 includes a first internal symbol data supplied from the data supply unit 10, a third internal symbol data supplied from the frame memories 20 and 21, a fourth internal symbol data supplied from the superimposition control unit 60, Select one of The data display unit 40 displays the output glyph data supplied from the output selection unit 60. The control unit 50 controls the entire device.
The superimposition control unit 60 sequentially merges a plurality of frames of the figure data.

[0004] The operation of the electronic drawing apparatus 1 configured as described above will be described. When a unit timing signal for designating a time-series position of the output glyph data supplied to the data display unit 40 is input to the control unit 50, the control unit 50 performs internal processing of the data supply unit 10 or the like. The local timing signal is generated based on a unit timing signal or a signal obtained by adjusting the phase of the unit timing signal, and further supplies graphic element data that needs to be controlled asynchronously with the local timing signal. A control signal is applied.

Further, the control unit 50 generates a drawing section designation signal for specifying one drawing section in one frame, and outputs the signal to the intermediate data generation unit 11. Intermediate data generator 11
Outputs the coordinates of the intersection between the pattern boundary line and the drawing line existing in the designated drawing section to the glyph data generation unit 12 with reference to the input graphic element data.
Generates first internal symbol data.

The first internal symbol data is input to the output selection unit 30 and the overlap control unit 60. The superimposition control unit 60 stores the supplied first internal symbol data and the frame memories 20 and 2
The third internal symbol data supplied from 1 is superimposed (combined) with the third internal symbol data and output to the output selection unit 30 as fourth internal symbol data.

[0007] The output selection unit 30 selects one of the first internal symbol data and the fourth internal symbol data,
The data is output to the data display unit 40 and the frame memories 20 and 21 or to the data display unit 40 and the frame memories 20 and 21. Note that this selection process is performed based on an output control signal supplied from the control unit 50, and the glyph data supplied from the output selection unit 30 to the data display unit 40 is referred to as output glyph data. Frame memory 2
The figure data supplied to 0 and 21 is called second internal figure data. The number of the frame memories 20 and 21 is two in the conventional example, but may be two or more.

[0008] The data display section 40, when supplied with the output glyph data, performs data display and displays the frame memory 20,
When the second glyph data is supplied, the 21 outputs it to the output selection unit 30 and the overlap control unit 60 as third internal glyph data.

When the first internal symbol data cannot be output to the data display unit 40 in real time, that is, when the frame rate is low, the data supply unit 1
0 are stored in the frame memories 20, 2
1 and the control unit 50 controls the frame memories 20 and 2
The output selection unit 30 is controlled so that the third internal glyph data output from any one of the first and second data items is supplied to the data display unit 40.

On the other hand, IEICE technical report Vo
In l.100 No. 42 "Integrated Circuits", an architecture for outputting data from a single DRAM is disclosed in "Development of DMA Controller in MPEG-4 Codec LSI". , May1999,
“A MPEG4 Programmable Codec DSP with an Embedded
The “Pre / Post-processing Engine” indicates the power consumption of the LSI.
(352 x 288) at 15Hz codec
The F-related data transfer amount occupies 41% or more of the whole, indicating that the DMA bus operation rate and the VIF operation rate are high. This will be described below with reference to FIG.

FIG. 16 shows an MPEG-4 codec LSI.
1 is a block diagram showing the configuration of an LSI.
63, and the image data stored in the SDRAM 162 corresponds to an image in the NTSC format at a rate of 6 per second.
The image data of the 0 field is output to the NTSC encoder (DAC) 166 via the VIF 164. The power consumption at this time is about 640 mW for the entire chip excluding the SDRAM 162.

Japanese Patent Application Laid-Open No. Hei 9-93578 discloses that
An image transmitting device and an image receiving device capable of easily performing resolution conversion of an image to be encoded or decoded are disclosed. Among them, the image transmission device discloses a frame rate setting register, and the image reception device discloses a technique related to write control and read control of a frame memory, which will be described with reference to FIG. 17 and FIG.

In the image transmitting apparatus shown in FIG. 17, a video signal is digitized by an A / D converter 19, and a switch is switched for each frame to change the image frame memory 2
Input to 2 and 23. The read / write control means 21
From the signal processing time of the QCIF image obtained by dividing the image of the IR 601 level, a pixel sampling method is determined so as to fall within the frame rate specified by the target frame rate setting unit 26. That is, here, in order to lower the resolution from the input image, downsampling is performed from the CCIR 601 to a plurality of QCIF images having different sampling positions. Then, the read address is set to the image frame memory 2
Give to 2,23. QCIF encoding means 25
The level image is encoded by DCT and quantization, and transmitted to the receiving device via the communication network 28 together with the QCIF number.

In the image receiving apparatus shown in FIG. 18, the video signal decoded by the decoding means 31 is written in the image frame memory 34 or 35. Which to write to,
The read / write control means 33 selects. This is to prevent reading and writing from accessing the same memory at the same time. The switches 32 and 36 are alternately switched in opposite phases. The QCIF decoding means 31 detects that decoding of the last number of QCIFs constituting one frame (QCIF3 in the case of division into four frames, QCIF15 in the case of division into sixteen frames) is completed. To the read / write control means 33. That is, switching of the switches 32 and 36 is instructed. When the QCIF decoding unit 31 notifies that the decoding process of all the QCIFs constituting one frame has been completed, the read / write control unit 33 starts reading the video signal from the image frame memory 34 or 35. , CCIR 601 image.

[0015]

However, in the above-described conventional electronic drawing apparatus, when synthesizing an image, the image is temporarily stored in a frame memory and then synthesized with the next frame data to be transferred. There is a problem that a delay of at least one frame is required for displaying the composite image for outputting to the image display device. Also, when the frame rate of the generated image is lower than the display rate of the data display unit, if there is a need to update the display image immediately, there is no updating means. Therefore, a delay of one frame always occurs.

Further, even when the images to be updated immediately are two composite images having different frame rates, the composite image cannot be immediately reflected. Further, in addition to the fact that two frame memories are always required, which causes an increase in circuit scale, it is necessary to read out from the frame memory again in order to combine data once stored, thereby increasing the number of data transfers. This has led to an increase in power consumption.

On the other hand, IEICE technical report Vo
l.100 No.42 “Integrated Circuits” describes “Development of DMA Controller in MPEG-4 Codec LSI” and
rocof CICC'99, pp69-72, May1999, “A MPEG4 Programm
able Codec DSP with an Embedded Pre / Post-processin
In the “g Engine”, as the operation rate of the DMA bus and the VIF increases, the power consumption of the logic and the memory increases.
Since it is necessary to output an image at 60 fields per second, it is conceivable that the cause is an increase in access to the memory or an increase in the operation rate of the logic.

In Japanese Patent Application Laid-Open No. 9-93578, a frame rate register is provided in the transmitting device, but the receiving device is provided with only a decoding end notification. There is no disclosure of a method for displaying an image asynchronously with the cycle and a technique related to data transfer control therefor.

When it is desired to apply a video processing unit for performing various video processing such as image enlargement / reduction and noise removal to the decoded image, it is necessary to insert a video processing unit between the selector and the DA converter. The video processing unit operates every output frame. This leads to an increase in power consumption.

Further, when the video processing unit does not have scheduling for data transfer, when it is desired to issue a data transfer request at one place, when the display schedule changes depending on the image display device, or when hardware If data transfer is requested at the determined timing, it is not possible to flexibly cope with various devices. Further, if a configuration is adopted in which two frames are provided and the switches are switched, when processing a plurality of images such as moving images and graphics, four frame memories are required, which increases the circuit scale.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide an image output apparatus and an image output control method capable of immediately updating a display screen with a minimum necessary data transfer. And

[0022]

According to a first aspect of the present invention, there is provided an image output apparatus, comprising: a data memory for storing image data; A video processing unit that generates display image data, a data transfer control unit that controls data transfer between the data memory and the video processing unit, and temporarily stores the display image data, and displays an image at a fixed cycle. An image output device comprising: an output data storage unit that outputs to the device; and a system control unit that controls the entire device, wherein the system control unit stores the display image data stored in the output data storage unit. A data transfer request control circuit for issuing a data transfer request to execute the data transfer in a fixed data unit only when an update instruction for updating is provided. It is an butterfly. This allows
Data transfer is performed only when the update flag is set in the frame update register, so that the minimum necessary data update is performed, unnecessary transfer is omitted, and as a result, power consumption can be reduced. By setting the update flag, data transfer can be started automatically and immediately, so that complicated control by the system control unit is no longer necessary as in the past, and image data can be immediately transferred without delay. Can be updated.

According to a second aspect of the present invention, in the image output apparatus according to the first aspect, the data transfer request control circuit periodically issues the data transfer request. And a frame rate register for determining an issuance cycle of the data transfer request. The data transfer request issuance unit is configured to set the frame rate when the system control unit sets an update flag in the frame rate register. Irrespective of the issuance cycle set in the register, the issuance of the data transfer request is started immediately at the issuance start determination timing of the data transfer request. As a result, an irregular data transfer request can be immediately issued while maintaining the period for issuing the regular data transfer request.

In the image output device according to a third aspect of the present invention, in the image output device according to the second aspect, the frame rate register includes a counter that counts each time the data transfer request issuance start determination timing. The uppermost bit is a bit representing an update flag, and the lower bits excluding the most significant bit determine the issue period. When the update flag is valid, the counter is reset and the next data At the transfer request issue start determination timing, the update flag is reset to an invalid value, and the counter again counts the issue cycle determined by the lower bits excluding the most significant bit. It is a feature. This allows
The settings of the frame rate register and the counter can be automated, and the transfer cycle and transfer can be easily set, eliminating the need for resetting.

In the image output device according to a fourth aspect of the present invention, in the image output device according to the third aspect, the frame rate register stores the data in any frame during an image output cycle to the image display device. A transfer cycle indicating whether a transfer request is issued is determined, and the data transfer request issuing unit determines whether to enable or disable the transfer of the moving image data, and a transfer register for the graphics data that is enabled. And a graphics transfer register to determine whether to invalidate, and, when the system control unit sets an update flag in the frame rate register,
Only when the moving image register or the graphics register is valid, the data transfer request corresponding to each is issued. As a result, the displayed image can be updated immediately, the delay between the user's operation and the display of the data is reduced, a video without a sense of incongruity can be provided, and unnecessary video data transfer can be performed. Therefore, power consumption when data transfer is not performed can be reduced.

According to a fifth aspect of the present invention, in the image output apparatus according to the fourth aspect, the data transfer request issuing unit transmits the data transfer request to the image display device in a frame in which the data transfer is valid. Of the image output periodic signals of
A line data transfer request is issued at the timing of a horizontal synchronization signal. This allows
The data transfer request issue start timing can be easily controlled without requiring a special timing generator, and the data transfer issue request can be controlled at a regular transfer cycle. This facilitates the realization of the transfer request issuance in hardware.

According to a sixth aspect of the present invention, in the image output apparatus according to the fifth aspect, when the data transfer request issuing unit sets an update flag in the frame rate register, Determining that the update flag is valid at the next vertical synchronizing signal timing among the image output periodic signals to the image display device, and issuing a data transfer request for transferring the frame. It is. This makes it possible to determine the issuance of a data transfer request on a frame-by-frame basis, so that system control can be easily and accurately controlled, and as a result, image disturbance and the like are less likely to occur.

According to a seventh aspect of the present invention, in the image output device, a data memory for storing image data, a video processing unit for performing image processing on the image data and generating display image data, and the data memory A data transfer control section for controlling data transfer between the video processing section and the video processing section, an output data storage section for temporarily storing the display image data, and outputting the display image data to the image display device at a constant period, and controlling the entire apparatus. An image output device comprising: a fixed period interrupt generation unit that outputs an interrupt signal to the system control unit at fixed intervals according to an image output period signal to the image display device. The system control unit determines whether to perform the data transfer based on the input of the interrupt signal, and determines that it is the interrupt timing to be transferred. In this case, a data transfer request for performing the data transfer is issued to the data transfer control unit, and if it is determined that it is not an interrupt timing to be transferred, the data transfer request is not issued. . Thus, the transfer pattern can be changed by the system control unit at any phase of development, and in particular, the transfer pattern can be changed even after the system is completed.

According to the image output device of the present invention, in the image output device of the present invention, the system control unit may include a moving image data for transferring moving image data stored in the data memory. Issuing a transfer request and a graphics transfer request for transferring graphics data stored in the data memory,
It is characterized by the following. Thereby, the transfer of the moving image data and the graphics data can be separately controlled, and the power consumption can be reduced.

[0030] In the image output device according to a ninth aspect of the present invention, in the image output device according to the first aspect, the video processing unit performs a scaling process on the moving image data transferred from the data memory. A scaling processing unit that generates display moving image data, and a graphics generation processing unit that performs graphics generation processing on graphics data transferred from the data memory to generate display graphics image data, The display moving image data and the display graphics image data are combined and output. Thereby, the processing of the moving image data and the processing of the graphics data can be controlled separately.

According to a tenth aspect of the present invention, in the image output device according to the ninth aspect, the output data storage unit stores one of the output data of the video processing unit.
It comprises a line buffer for temporarily storing lines, and a frame memory for storing one frame of output data of the line buffer.
This makes it easy to control the timing of writing the display image data to the frame memory, and realizes the synthesis and display of the image with one frame memory. Further, since the image is stored in the frame memory in frame units, In addition, the image is not disturbed, and the image can be displayed with a small number of circuits.

[0032] In the image output device according to claim 11 of the present invention, in the image output device according to claim 9, the output data storage unit stores the output data of the video processing unit as one.
It is characterized by comprising a frame memory for storing frames and sequentially outputting the stored data on a line-by-line basis, and a line buffer for storing output data of the frame memory. Thus, when display image data is output to the image display device, it is not necessary to control by RAS and CAS unlike the frame memory, so that it is easier to control the output timing of the display image data than directly from the frame memory.

According to a twelfth aspect of the present invention, in the image output apparatus according to the first or seventh aspect, the video processing unit performs processing on the moving image data transferred from the data memory. A scaling processing unit that performs scaling processing to generate display moving image data; and a graphics generation processing unit that performs graphics generation processing to the graphics data transferred from the data memory to generate display graphics image data. ,
And outputting each of the display moving image data and the display graphics image data to the output data storage unit. Thus, the processing of the moving image data and the processing of the graphics data can be controlled separately, and the power consumption can be reduced.

According to a thirteenth aspect of the present invention, in the image output device of the twelfth aspect, the output data storage unit temporarily stores one line of the display moving image data. A moving image line buffer, a moving image frame memory for temporarily storing output data of the moving image line buffer for one frame, and a graphics line buffer for temporarily storing one line of the display graphics image data. A graphics frame memory for temporarily storing output data of the graphics line buffer for one frame, and combining the storage data of the moving picture frame memory and the storage data of the graphics frame memory to display the image. Output to a device.
Thereby, the display moving image data and the display graphics image data can be stored separately, and the disturbance such as disappearance of the video does not occur. Further, the display moving image data and the display graphics image data can be updated separately. Therefore, it is not necessary to perform useless data transfer, and power consumption can be reduced.

According to a fourteenth aspect of the present invention, in the image output device according to the twelfth aspect, the output data storage unit temporarily stores the display moving image data in one.
A moving image frame memory that stores frames of the moving image data and sequentially outputs the stored display moving image data line by line; a moving image line buffer that temporarily stores output data of the moving image frame memory; A graphics frame memory for sequentially storing one frame and sequentially outputting the stored display graphics image data in units of one line; a graphics line buffer for temporarily storing output data of the graphics frame memory; Wherein the data stored in the moving image line buffer and the data stored in the graphics line buffer are combined or separately output to the image display device. This allows
Even if the video format differs between the video data and the graphics data, the data can be output separately in synchronization with the display lines, and the number of display lines does not always match, such as repeatedly outputting the same display graphics image data Even when not performed, it is not necessary to always read data from the frame memory for each display line, and power consumption can be greatly reduced.

[0036] In the image output apparatus according to the present invention, the output data storage section may store the display moving image data temporarily in one.
A moving image frame memory for storing frames of the displayed moving image data and sequentially outputting the stored display moving image data in units of one line, and temporarily storing the display graphics image data for one frame, and A graphics frame memory for sequentially outputting in line units, and a line buffer for combining output data of the moving image frame memory and output data of the graphics frame memory and temporarily storing the combined data. It is. As a result, the display moving image data and the display graphics data can be updated separately. As a result, useless data transfer is eliminated, and power consumption can be reduced.

[0037] In the image output device according to the present invention, the output data storage section may store one line of the display moving image data temporarily. A line buffer, a moving image frame memory for temporarily storing output data of the moving image line buffer for one frame, and outputting the stored display moving image data in units of one line, and a moving image frame memory for storing one line of the display graphics image data. A graphics line buffer for temporarily storing data, and output data for the graphics line buffer for one frame temporarily,
A graphics frame memory that outputs the stored display graphics image data in units of one line, and combines the output data of the moving image frame memory and the output data of the graphics frame memory and temporarily stores the combined data as display image data And a line buffer for outputting to the image display device. As a result, the display moving image data and the display graphics data can be separately updated, and furthermore, the operation of each circuit can be reduced. As a result, useless data transfer is eliminated, and power consumption can be reduced.

According to a seventeenth aspect of the present invention, in the image output device of the twelfth aspect, the output data storage section temporarily stores one line of the display moving image data. A moving image line buffer, a moving image frame memory for temporarily storing output data of the first moving image line buffer for one frame, and sequentially outputting the stored display moving image data in line units; A second moving image line buffer for temporarily storing the output data of the image data, a first graphics line buffer for temporarily storing one line of the display graphics image data, and the first graphics line buffer. Temporarily stores the output data for one frame,
A graphics frame memory for sequentially outputting the stored display graphics image data in units of one line, and a second graphics line buffer for temporarily storing output data of the graphics frame memory. And storing the data stored in the second moving image line buffer and the data stored in the second graphic line buffer and outputting the combined data to the image display device. As a result, the operation of a large-capacity frame memory storing one frame of image can be minimized for image display when there is no image update, and power consumption can be significantly reduced. Data can be updated separately for moving image data and display graphics image data, and even when the video format differs between moving image data and graphics data, the data is individually displayed on the display line to the image display device. Synchronous output is possible.

In the image output device according to claim 18 of the present invention, when the data transfer or the data processing is not performed in the image output device according to claim 1 or 7, the operation clock in the device is changed. An operation clock stop control unit for controlling to stop the operation is provided. Thereby, the operation clocks of the moving image data processing system and the graphics image data processing system can be separately controlled according to the data transfer of the moving image data or the graphics image data, and the power consumption can be greatly reduced.

According to a nineteenth aspect of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device. In a period other than the blanking period of the horizontal synchronizing signal in the image output periodic signal to the display device,
The display image data is stored in the line buffer, and during the blanking period of the horizontal synchronization signal, the display image data is transferred from the line buffer to the frame memory, and during a period other than the blanking period of the horizontal synchronization signal, Outputting the display image data from the frame memory to the image display device. This makes it possible to use the effective period of the horizontal sync signal,
The data is stored in the frame memory and controlled so that the stored data is output immediately, reducing the frame delay and
It is also possible to respond to repeated display in the next frame,
Access competition for the frame memory can also be prevented, and system control becomes easy. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to a twentieth aspect of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device. In the image output periodic signal to the display device, during a period other than the blanking period of the horizontal synchronization signal,
The display image data is stored in the frame memory, and during the blanking period of the horizontal synchronization signal, the display image data is transferred from the frame memory to the line buffer, and during a period other than the blanking period of the horizontal synchronization signal, Outputting the display image data from the line buffer to the image display device. This makes it possible to use the effective period of the horizontal sync signal,
The data is stored in the frame memory and controlled so that the stored data is output immediately, reducing the frame delay and
It is also possible to respond to repeated display in the next frame,
Access competition for the frame memory can also be prevented, and system control becomes easy. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to a twenty-first aspect of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to the thirteenth aspect. In a period other than the blanking period of the horizontal synchronizing signal in the image output periodic signal to the display device,
The display moving image data and the display graphics image data are stored in the moving image line buffer and the graphics line buffer, respectively, and during the blanking period of the horizontal synchronization signal, the display moving image data and the display graphics image data are stored. Each of them is transferred from the moving image line buffer and the graphics line buffer to the moving image frame memory and the graphics frame memory, and the display moving image data and the display graphics are displayed during a period other than the blanking period of the horizontal synchronization signal. The image data is synthesized and output to the image display device. This makes it possible to use the effective period of the horizontal synchronizing signal to store the data in the frame memory and output the stored data immediately, thereby reducing the frame delay and simultaneously responding to repeated display in the next frame. Also, access competition for the frame memory can be prevented, and system control becomes easy. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to a second aspect of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to the fourteenth aspect. In the image output periodic signal to the display device, during a period other than the blanking period of the horizontal synchronization signal,
The display moving image data and the display graphics image data are stored in the moving image frame memory and the graphics frame memory, respectively, and during the blanking period of the horizontal synchronization signal, the display moving image data and the display graphics image data are stored. Are transferred from the moving image frame memory and the graphic frame memory to the moving image line buffer and the graphics line buffer, and during a period other than a blanking period of the horizontal synchronization signal, the display moving image data and the display graphic are Image data is synthesized or separately output to the image display device. This allows
Using the effective period of the horizontal synchronizing signal, the data stored in the frame memory is controlled to be output to the line buffer, and the data of the line generated by the video processing unit can be output in the next line. There is no contention for data access to, and the frame delay can be reduced. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to a twenty-third aspect of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to the fifteenth aspect. Of the image output periodic signal to the display device, during a period other than the blanking period of the horizontal synchronization signal,
Each of the display moving image data and the display graphics image data is stored in the moving image frame memory and the graphics frame memory, and during a blanking period of a horizontal synchronization signal, the output data of the moving image frame memory and the graphics Combining the output data of the frame memory and transferring it to the line buffer, and outputting the data stored in the line buffer to the image display device during a period other than the blanking period of the horizontal synchronization signal. It is. This makes it possible to use the effective period of the horizontal synchronizing signal to store the data in the frame memory and output the stored data immediately, thereby reducing the frame delay and simultaneously responding to repeated display in the next frame. Also, access competition for the frame memory can be prevented, and system control becomes easy. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to a twenty-fourth aspect of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to the sixteenth aspect. The blanking period of the horizontal synchronizing signal in the image output periodic signal to the display device is divided into a first period and a second period. In the first period, the data stored in the moving image line buffer and the graphics line are stored. Transferring each of the data stored in the buffer to the video frame memory and the graphics frame memory,
In the second period, the output data of the moving picture frame memory and the output data of the graphics frame memory are combined and transferred to the line buffer. This makes it possible to use the effective period of the horizontal synchronizing signal to store the data in the frame memory and output the stored data immediately, thereby reducing the frame delay and simultaneously responding to repeated display in the next frame. Also, access competition for the frame memory can be prevented, and system control becomes easy. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to a twenty-fifth aspect of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device. In the image output periodic signal to the display device, the blanking period of the horizontal synchronizing signal is divided into a first period and a second period, and in the first period, the data stored in the first moving image line buffer and the Each of the data stored in the first graphics line buffer is transferred to the video frame memory and the graphics frame memory. During the second period, the data stored in the video frame memory and the graphics frame memory are transferred. Transferring each of the stored data to the second video line buffer and the second graphics line buffer. It is an. This makes it possible to store the data in the moving image frame memory and the graphics frame memory using the effective period of the horizontal synchronization signal and output the stored data immediately. As a result, the frame delay can be reduced and It is possible to cope with repeated display, and it is also possible to prevent contention for access to the moving image frame memory and the graphics frame memory, thereby facilitating system control. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

[0047]

Embodiments of the present invention will be described below with reference to the drawings. The embodiment described here is merely an example, and the present invention is not necessarily limited to this embodiment.

(Embodiment 1) Hereinafter, Embodiment 1 will be described.
Will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the image output device according to the first embodiment. In FIG. 1, reference numeral 1001 denotes a processor unit, which controls the entire apparatus and performs decoding processing on input moving image encoded data. A data memory 1002 stores image data. A data transfer control unit 1003 controls data transfer between the data memory 1002 and the video processing unit 1004. A video processing unit 1004 performs image processing on image data stored in the data memory 1002 to generate display image data. A frame memory 1006 temporarily stores display image data for one frame. Reference numeral 1007 denotes a data transfer request control circuit, which includes a frame update register 1008 for determining a data transfer request issuance cycle, and a data transfer request issuing unit 1 for periodically issuing a data transfer request.
009 to control the data transfer request.

Next, the operation of the image output apparatus having the above configuration will be described. The processor unit 1001 decodes the bit stream (encoded moving image data) transferred from the host CPU and stores the decoded data as image data in the data memory 1.
002. When generating image data of a new frame, the processor unit 1001 sets 1 to the frame update register 1008. Then, the data transfer request issuing unit 1009 starts from the start of the next frame.
The data transfer request is sent to the data transfer control unit 10 in line units.
Issue to 03. The data transfer control unit 1003 controls the data memory 1002 to transfer the image data from the data memory 1002 to the video processing unit 1004 in line units according to the data transfer request.

The image data transferred from the data memory 1002 is stored in the video processing unit 1004 by an image display device,
For example, scaling processing is performed to fit the screen size of a liquid crystal display device (LCD), and the data is sequentially written as display image data to a frame memory 1006.
Output to CD. When the data transfer for one frame is completed, the frame rate update register 1008 becomes 0, and the data transfer request issuing unit 1009 stops issuing the data transfer request to the data transfer control unit 1003.

In the image output device according to the first embodiment, the processor unit 1001 operates only when the image data to be updated is generated.
, And the data transfer request control unit 1007 automatically issues a data transfer request for transferring one frame of image data, so that the processor unit 1001 does not perform detailed transfer control. Image data can be transferred with the minimum necessary control. As a result, the operating rates of the data transfer control unit 1003, the video processing unit 1004, and the data transfer bus are reduced, and the display image is stored in the frame memory 1006. Therefore, image display on the liquid crystal display device can be output every frame, and power consumption can be reduced.

Note that a video processing unit 100 is used by using a liquid crystal display device having a frame memory as an image display device.
If the output data of No. 4 is directly input to the image display device, it is not necessary to provide the frame memory 1006 in the image output device, and a higher effect can be exhibited.

(Embodiment 2) The following describes Embodiment 2 of the present invention.
Will be described with reference to FIG. 2, FIG. 3, FIG. 4, and FIG. FIG. 2 is a block diagram showing a configuration of the image output device according to the second embodiment. In FIG. 2, reference numeral 101 denotes a processor unit, which controls the entire apparatus. A data memory 102 stores image data such as data for decoding, moving image data obtained by decoding compressed moving image encoded data, and graphics table data. A data transfer control unit 103 controls data transfer between the data memory 102 and the video processing unit 104. Reference numeral 104 denotes a video processing unit which includes a scaling processing unit that enlarges or reduces moving image data to generate display moving image data, and a graphics generation processing unit that generates display graphics image data from graphics table data. Yes, image processing of image data transferred from the data memory 102 is performed. A line buffer 105 temporarily stores one line of display image data obtained by combining display moving image data and display graphics image data. Reference numeral 106 denotes a frame memory, which outputs data at 60 Hz to an image display device, for example, a liquid crystal display device (LCD) while storing output data of the line buffer 105 for each line. A data transfer request control circuit 107 includes a frame rate register 108 for determining a cycle for issuing a data transfer request and a data transfer request issuing unit 109 for periodically issuing a data transfer request.

FIG. 3 is a diagram showing the configuration of the frame rate register 108. In FIG. 3, lower bits 201 except the most significant bit are frame rate registers, which determine a transfer cycle. The most significant bit 202 is an update flag. A counter 203 counts at each start determination timing for issuing a data transfer request. 204 is a cycle coincidence detector, 205 is an update flag 2
Reference numeral 206 denotes a logical sum of a match detection result and a logical product (all-zero detection unit) 206 that outputs enable as an effective frame when the counter value becomes all zero. Reference numeral 207 denotes a clock stop control unit that controls stop of a clock for operating the entire video processing unit 104.

When the most significant bit is valid, the frame rate register 108 having the above-mentioned configuration
Are reset, at the timing of the start of issuing the next data transfer request, the update graph 202, which is the most significant bit, is reset to an invalid value, and the counter 203 again counts the period determined by the lower bit. Thus, the setting of the frame register and the counter is automated, and the transfer cycle and the update can be easily set.

FIG. 4 is a diagram showing the relationship between the vertical synchronizing signal of the LCD, the data transfer timing from the data memory 102 to the frame memory 106, and the display data output timing from the data memory 102. As shown in FIG. 4, when the processor unit 101 sets the update flag 202 in the frame rate register 108, the data transfer request issuing unit 109 sets the image display device A data transfer request is issued at the next image output frame timing.

That is, it is determined that the update flag 202 is valid at the timing of the next vertical synchronizing signal in the image output periodic signal to the image display device, and that frame is set as an image transfer frame. This makes it possible to determine the issuance of a data transfer request on a frame-by-frame basis, eliminating the need for resetting. Then, the data transfer request issuing unit 1
09 is an update flag 2 in the frame rate register 108.
When 02 is set, a data transfer request is issued immediately at the issuance start determination timing regardless of the transfer cycle set in the frame rate register 201. This allows
Irregular data transfer requests can be issued immediately while maintaining the regular data transfer request issuance cycle, and the system can be controlled easily and accurately. As a result, disturbance of the image and the like hardly occur.

FIG. 5 shows a horizontal synchronizing signal of the LCD, data transfer timing from the data memory 102 to the video processing unit 104, storage timing to the line buffer 105, data transfer timing from the line buffer 105 to the frame memory 106, and The relationship of the image output timing from the frame memory 106 is shown. In addition, LCD
Is referred to as a blanking period.

Next, the operation of the image output apparatus according to the second embodiment will be described. When moving image coded data is transferred from the host CPU, the processor unit 101 performs a decoding process on the moving image coded data using the data memory 102, and the data memory 10
2 is stored. When the graphics table data is transferred from the host CPU, the graphics table data is stored in the data memory 102 as it is.

Next, the processor unit 101 stores the decoded image rate of 15 Hz in the frame rate register 108.
Set a value that represents. Here, as shown in FIG. 4, 15 Hz means one transfer every four frames with reference to the vertical synchronizing signal of the LCD. In other words, in four frames
Once, data transfer is valid. Therefore, 3 is set in the frame rate register 201.

When the frame for which the transfer is valid is reached, the data transfer request issuance unit 109, as shown in FIG.
A data transfer request is issued to the data transfer control unit 103 in synchronization with the timing of the horizontal synchronization signal from the timing immediately before the vertical synchronization signal of the LCD becomes valid. As a result, the timing of issuing a data transfer request can be easily controlled without using a special timing generator, and the issuance of a data transfer request can be controlled at a regular transfer cycle. This facilitates the issuance of a transfer request by hardware. When the data transfer request is issued, the data transfer control unit 103 controls the data memory 102 to transfer the moving image data and the graphics table data to the video processing unit 104.

Each of the moving image data and the graphics table data transferred in this way is subjected to scaling processing and graphics generation processing in the video processing unit 104, so that display video data and display graphics image data and the like are processed. Display image data is generated. Here, the scaling process means that the moving image data is stored in the QCIF (1
76 × 144) to a CIF (352 × 288) size, and the graphics generation processing generates a luminance signal and a color difference signal from the graphics table data in pixel units according to the table value. That is.

In the generated display image data, either one of the display moving image data and the display graphics image data is selected to be synthesized for each pixel. One line of display image data is stored. Next, the line buffer 105 outputs the image output synchronization signal to the image display device.
During the blanking period of the horizontal synchronizing signal, the stored display image data is stored in the frame memory 10 at the subsequent stage in units of one line.
6 is burst-transferred.

The frame memory 106 stores the stored display image for one frame from the time when the blanking period of the horizontal synchronizing signal ends (the time when the effective period of the horizontal synchronizing signal starts) at the pixel clock timing of the LCD. Output data. In a period other than the transfer cycle of 15 Hz, writing to the frame memory 106 is not performed.
From 06, the display image data is repeatedly output to the LCD. At this time, the operation clock of the video processing unit 104 is stopped by the clock stop control unit 207 in FIG.

Next, a case where a graphics update command is issued together with graphics table data from the host CPU will be described. The processor unit 101
1 is set in the update flag 202 of the frame rate register 108.
Is set. That is, the frame rate register 201
When the most significant bit of the update flag 202 is set to 1, the counter 203 is reset at the next falling edge of the vertical synchronization signal (at the start of the frame). Counter 20
When 3 becomes all 0, the logical product 206 outputs an enable indicating that the data transfer is valid to the data transfer request issuing unit 109. At this time, the clock stop control unit 207 controls to supply the operation clock.
The update flag 202 is configured to automatically return to 0. After the frame is updated, the data transfer is repeated at the set issue cycle again.

In the image output device according to the second embodiment, a data transfer request is issued at a cycle set in the frame register 108 to update the display image data stored in the frame memory 106. When an image to be updated immediately, such as graphics image data, occurs, an update flag is set in the frame rate register 108, and the next image output to the image display device is performed regardless of the issuance cycle set in the frame rate register 108. Since the data transfer request is issued at the frame timing, the display image can be updated immediately, the delay between the user's operation and the data display is reduced, and a video without a sense of incongruity can be provided. .

Further, a line buffer 105 is provided in a stage preceding the frame memory 106, and display image data is transferred to the line buffer 105 during a blanking period of the horizontal synchronizing signal.
To the frame memory 106 and output to the LCD during the effective period of the horizontal synchronizing signal, so that the timing of writing the display image data to the frame memory can be easily controlled, and the display image data can be stored in one frame memory. Can be realized and display can be realized, and further, a delay of a frame until the transferred image data is displayed can be eliminated.

In the second embodiment, the image display device is realized by a liquid crystal display device.
If the memory 06 and the data memory 102 are realized by a DRAM, a small space and low power consumption can be achieved while retaining a large amount of image data. Further, the second embodiment includes an operation clock control unit, and the line buffer 105, the video processing unit 104, and the
By controlling the operation clock of the frame memory 106 to stop, power consumption can be reduced.

(Embodiment 3) Hereinafter, Embodiment 3
Will be described with reference to FIGS. 6 and 7. FIG. The difference from the second embodiment is that the line buffer is provided in the preceding stage of the frame memory in the second embodiment, whereas the line buffer is provided in the subsequent stage of the frame memory in the third embodiment. is there.

FIG. 6 is a block diagram of an image output device according to the third embodiment. In FIG. 6, the same or corresponding components as those in FIG. A frame memory 501 sequentially stores one frame of display image data obtained by combining display moving image data and display graphics image data. 5
Numeral 02 denotes a line buffer, which is composed of, for example, an SRAM, and transfers 60 display image data per second in units of one line from the frame memory 501 in synchronization with a horizontal synchronization signal, and sequentially stores the display image data.

FIG. 7 shows the horizontal synchronization signal of the LCD, the data transfer timing from the data memory 102 to the video processing unit 104, the storage timing to the frame memory 501, the data transfer timing from the frame memory 501 to the line buffer 502, and Line buffer 50
2 shows the relationship between image output timings. LC
The “L” period of the D horizontal synchronization signal is called a blanking period.

Next, the operation of the image output apparatus according to the third embodiment will be described. As described in the second embodiment, the moving image data and the graphics table data transferred from the data memory 102 are each subjected to image processing by the video processing unit 104. As a result, display moving image data and display graphics image data are generated.

The display image data thus generated is
Either the display moving image data or the display graphics image data is selected to combine for each pixel, and one line of display image data is stored in the frame memory 501 within the valid period of one horizontal synchronization signal. . By repeating this process, display image data for one frame is stored in the frame memory 501.

The frame memory 501 transfers the stored data for one line to the subsequent line buffer 502 during the blanking period of the next horizontal synchronizing signal. The line buffer 502 outputs image data one pixel at a time in accordance with the horizontal synchronization signal and the display pixel period from the timing of line start after the blanking period ends.

Here, similarly to the second embodiment, when the processor unit 101 sets the frame rate register 108, that is, the update flag 202, the update flag 202 is determined at the start of the next vertical synchronization signal. Then, the counter 203 is reset, and the valid frame enable is output. In response to this, the data transfer request issuing unit 107 issues a data transfer request to the data transfer control unit 103 in the next frame period. In this way, data can be displayed immediately. In addition, as in the second embodiment, the clock stop control of the video processing unit 104 and the line buffer 502 is controlled by the clock stop control unit 207, so that power consumption can be reduced.

In the image output device according to the third embodiment, at the cycle set in the frame register 108,
By issuing a data transfer request and updating the display image data stored in the frame memory 106, and when an image such as graphics image data to be updated immediately occurs, the processor unit 101 stores the image data in the frame rate register 108. When the update flag is set, the data transfer request is issued at the next image output frame timing to the image display device regardless of the issuance cycle set in the frame rate register 108, so that the display image is immediately updated. Thus, the delay between the user's operation and the display of the data is reduced, and it is possible to provide an image that does not cause any discomfort.

Further, a line buffer 502 is provided at the subsequent stage of the frame memory 501 to transfer data from the frame memory 501 to the line buffer during the blanking period of the horizontal synchronizing signal of the image output period signal to the image display device. During periods other than the blanking period of the horizontal sync signal,
Since one line of image data is output from the line buffer 502, when data is output to the image display device, there is no need to control by RAS and CAS unlike a frame memory. It is easier than performing directly from the frame memory, and during the period when data transfer from the data memory 102 is not executed,
Since there is no data writing to the frame memory 501,
The operation time of the frame memory 501 can be significantly reduced.

(Embodiment 4) The following describes Embodiment 4 of the present invention.
Will be described with reference to FIGS. 8 and 10. FIG. FIG. 8 shows the configuration of the image output device according to the fourth embodiment. In FIG. 8, the same or corresponding components as those in FIG. Reference numeral 701 denotes a video processing unit that enlarges / enlarges moving image data transferred from the data memory 102.
A scaling process for generating reduced display moving image data and a graphics generation process for generating display graphics image data from the graphics table data transferred from the data memory 102 are performed.

Reference numeral 702 denotes a moving image line buffer for temporarily storing one line of display moving image data. Reference numeral 703 denotes a graphics line buffer for temporarily storing one line of display graphics image data, and is constituted by, for example, an SRAM. 70
Reference numeral 4 denotes a moving image frame memory for storing the output data of the moving image line buffer 702 for one frame (for 288 lines) during the blanking period of the horizontal synchronization signal.
Reference numeral 705 denotes a graphics frame memory for storing output data of the graphics line buffer 703 for one frame during a blanking period of the horizontal synchronization signal.

A data transfer request control circuit 706 includes a frame rate register 707 and a data transfer request issuing unit 708. Frame rate register 7
Reference numeral 07 denotes a cycle for issuing a data transfer request, which is configured as shown in FIG. 10 and includes an update flag 202 for immediately updating an image frame.

The data transfer request issuing section 708 receives a valid frame enable from the frame rate register 707 and issues a data transfer request to the data transfer control section 103. The data transfer request issuing unit 708 includes a moving image transfer register that determines whether to enable or disable moving image data transfer, and a graphics transfer register that determines whether to enable or disable transfer of graphics data. Only when the update flag 202 is set in the frame rate register 706 by the processor unit 101 and the moving image transfer register or the graphics transfer register is valid, a corresponding data transfer request is issued. Note that each of the moving image transfer and the graphics transfer is controlled to be ON / OFF by the processor unit 101, and does not issue a data transfer request when the transfer is OFF. FIG. 10 is a configuration diagram of the frame rate register. 10, the same or corresponding components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

Reference numeral 801 denotes a moving image processing system clock stop control unit which stops and controls a moving image processing system circuit in the video processing unit 701 and a clock for operating the moving image line buffer 702. Also, the clock is stopped when the moving image transfer of the data transfer request issuing unit 708 is OFF.

Reference numeral 802 denotes a graphics processing system clock stop control unit, which includes a graphics processing system circuit in the video processing unit 701 and a graphics line buffer 703.
Stop the clock for operating The graphics transfer of the data transfer request issuing unit 708 is
At the time of F, the clock is stopped.

Next, the operation of the image output device according to the fourth embodiment will be described. The processor unit 101 performs a decoding process on an image using the data memory 102, and stores the decoded image in the data memory 102. Also, graphics table data is transferred from the host CPU and stored in the data memory 102. The processor unit 101 sets a value indicating 15 Hz which is the decoded image rate in the frame rate register 707. 15Hz
This means, as shown in FIG. 4, that transfer is performed once in four frames with reference to the vertical synchronization signal of the LCD. That is, data transfer is effective once every four frames. Therefore, 3 is set in the frame rate register 201. Further, the data transfer request issuing unit 708 is set so that only the data to be transferred is turned on. Here, normally, it is assumed that only a decoded image (moving image) is displayed, and moving image transfer ON and graphics transfer OFF are set.

Further, the data transfer request issuing unit 708, as shown in FIG.
A data transfer request is issued in accordance with the timing of the horizontal synchronization signal from the timing immediately before the vertical synchronization signal of the LCD becomes valid. At this time, the transfer request is made only for the moving image data, and not for the graphics data.

The moving image data for one line transferred in this way is subjected to scaling processing in the video processing unit 701 during an effective period other than the blanking period of the horizontal synchronizing signal, and is subjected to QCIF (176 × 144). CIF (35
2 × 288). Further, the processed moving image data is stored in the moving image line buffer 702 as display moving image data.

The 1 stored in the moving image line buffer 702
The display image data for the line is transferred to the moving image frame memory 704 at a stretch during the blanking period of the horizontal synchronization signal, and is output to the external LCD during the effective period other than the blanking period of the horizontal synchronization signal. It is output according to the timing.

Further, except for the transfer cycle of 15 Hz, writing to the moving image frame memory 704 is not performed, and the display image data is repeatedly output from the moving image frame memory 704 to the LCD. In addition, when the transfer cycle is other than the transfer cycle of 15 Hz and the transfer
The operation clock of the video processing unit and the line buffer of the graphics transfer system which is an FF is stopped by the graphics processing system clock stop control unit 802 in FIG.

Next, a case where a graphics update instruction is issued together with graphics table data from the host CPU will be described. The processor unit 101
Graphics transfer ON to data transfer request issuing unit 708
Is set, and 1 is set to the update flag 202 of the frame rate register 707. At this time, if there is no need to update the display moving image data and only the display graphics image data needs to be changed, the data transfer request issuing unit 708 may be set to OFF for moving image transfer.

The data transfer request issuing unit 708 checks the update flag 202 at the start of the next frame, that is, at the fall of the vertical synchronizing signal, and indicates that graphics transfer is ON and moving image transfer is OFF. Therefore, the data transfer request issuing unit 708 requests transfer of only graphics table data in the next frame.

Therefore, in the next frame, the decoded image (moving image) data is not transferred from the data memory 702 to the video processing unit 701, but only the graphics table data is transferred. The transferred graphics table data is generated into display graphics image data in the video processing unit 701, and is sequentially stored in the graphics line buffer 703. The graphics line buffer 703 transfers the stored data to the graphics frame memory 705 at a stretch during the blanking period of the next horizontal synchronization signal.

Then, when a valid period other than the blanking period of the horizontal synchronizing signal is reached, data is sequentially read from the moving image frame memory 704 and the graphics frame memory 705, and is passed through a selection circuit for synthesizing image data. It is output in accordance with the display timing of the LCD.
At this time, since the moving image transfer is OFF, the moving image processing system in the video processing unit 701 and the moving image line buffer 702
The operation clock is stopped by the moving image processing system clock stop control unit 801 in the frame rate register 707.

In the image output device according to the fourth embodiment, a data transfer request is issued at a fixed period, and the display image data stored in the moving image frame memory 704 and the graphics frame memory 705 is updated. When an image to be updated immediately such as display graphics image data occurs, the processor unit 101 sets an update flag in the frame rate register 707, and only when the moving image register or the graphics register is valid, Since the data transfer request is issued, the delay between the user's operation and the data display is reduced, providing a video that is not uncomfortable.
The operation clocks of the moving image processing system and the graphics processing system can be separately controlled without unnecessary transfer of moving image data, so that power consumption can be reduced when data transfer is not performed.

A moving image line buffer 702 and a graphics line buffer 703 are provided before the moving image frame memory 704 and the graphics frame memory 705.
Since the display moving image data and the display graphics image data are stored separately from each other, disturbance such as disappearing of the video does not occur, and the moving image line buffer 702 and the graphics line buffer 703 are provided.
Is stored in the blanking period of the horizontal synchronization signal in the image output periodic signal to the image display device.
Data is transferred from the moving image line buffer 702 and the graphics line buffer 703 to the moving image frame memory 704 and the graphics frame memory 705 at the subsequent stage, and during a period other than the blanking period of the horizontal synchronization signal,
Since one line of image data obtained by combining the output data from the moving image frame memory 704 and the graphics frame memory 705 is output to the subsequent image display device, the timing of writing to the frame memory can be easily controlled, and It is possible to combine and display images with one frame memory. Further, it is possible to eliminate a frame delay until the transferred data is displayed.

(Embodiment 5) Hereinafter, Embodiment 5 will be described.
Will be described with reference to FIGS. 9 and 10. FIG. FIG. 9 shows a configuration of an image output device according to the fifth embodiment. In FIG. 9, the same or corresponding components as those in FIG. 711 is a moving image frame memory,
The display moving image data is temporarily stored for one frame, and the stored display moving image data is output for each line. 712
A graphics frame memory temporarily stores display graphics image data for one frame, and outputs the stored display graphics image data in units of one line. A moving image line buffer 713 temporarily stores output data of the moving image frame memory 711.
A graphics line buffer 714 temporarily stores output data of the graphics frame memory 712.

Next, the operation of the image output apparatus according to the fifth embodiment will be described. The processor unit 101 performs a decoding process on an image using the data memory 102, and stores the decoded image in the data memory 102. The graphics data transferred from the host CPU is also stored in the data memory 102. The processor unit 101 stores the decoded image rate of 15 in the frame rate register 707.
Set a value representing Hz. As shown in FIG. 4, 15 Hz means one transfer every four frames on the basis of the vertical synchronization signal of the LCD. That is, 1 in 4 frames
Times, data transfer is enabled. Therefore, 3 is set in the frame rate register 201. Further, the data transfer request issuing unit 708 stores only the data to be transferred O
N is set. Here, normally, it is assumed that only a decoded image (moving image) is displayed, and moving image transfer ON and graphics transfer OFF are set.

Further, the data transfer request issuance unit 708, when the transfer becomes valid frame, as shown in FIG.
A data transfer request is issued in accordance with the timing of the horizontal synchronization signal from the timing immediately before the vertical synchronization signal of the LCD becomes valid. At this time, the transfer request is only for moving image transfer, not for graphics transfer.

The moving image data for one line transferred in this manner is subjected to scaling processing in the video processing unit 701 during an effective period other than the blanking period of the horizontal synchronizing signal, and is converted from QCIF (176 × 144). The moving image data enlarged and processed to the CIF (352 × 288) size is sequentially stored in the moving image frame memory 711 as display moving image data. The moving image frame memory 711 stores one frame (2
(88 lines) of moving image data. And
The stored display moving image data is transferred to the moving image line buffer 713 in one line at a time during the blanking period of the next horizontal synchronization signal.

The moving image line buffer 713 outputs the external LC during the valid period other than the blanking period of the horizontal synchronizing signal.
D is output in synchronization with the synchronization signal and the pixel output timing. For example, the luminance data is read out every line from the moving image frame memory 711 to the moving image line buffer 713 and output to the LCD. However, only the even-numbered lines of the color difference data
The data for the line is read out and the moving image line buffer 713 is read.
To the moving image line buffer 71 for odd lines.
3 is output. By doing so, the moving image frame memory 711
The image in the 4: 2: 0 format stored therein is converted into 4: 2: 2 and output to the LCD.

Then, except for the transfer cycle of 15 Hz, writing to the moving image frame memory 711 is not performed, and image data is repeatedly output from the moving image frame memory 711 to the LCD via the moving image line buffer 713.
In addition, the operation clock of the video processing unit 701 of the graphics transfer system which is turned off by the data transfer request issuing unit 708 except for the transfer cycle of 15 Hz is stopped by the graphics clock stop control unit of FIG. .

Next, a case where a graphics update command is issued together with graphics table data from the host CPU will be described. The processor unit 101
Data transfer request issuing unit 708 in video processing unit 701
Is set to graphics transfer ON, and 1 is set to the update flag 202 of the frame rate register 707. At this time, if there is no need to update the display moving image data and only the display graphics image data needs to be changed, the data transfer request issuing unit 708 may turn off the moving image transfer.

Therefore, in the next frame, moving image data is not transferred from the data memory 102 to the video processing unit 701, but only graphics table data is transferred. The transferred graphics data is generated as display graphics image data in the video processing unit 701, and is sequentially stored in the graphics frame memory 712. One line of data is read from the moving image frame memory 711 and the graphics frame memory 712 during the blanking period of the next horizontal synchronization signal, and is read to the moving image line buffer 713 and the graphics line buffer 714, respectively. , Will be transferred all at once.

Here, when the format of the moving image data is the same as the format of the graphics image data (for example, Y, C
b, Cr, R, G, B, etc.), when the effective period of the horizontal synchronizing signal is reached, data is sequentially read from the moving image line buffer 713 and the graphics line buffer 714, and is passed through the selection circuit for synthesis to the LCD. Is output according to the display timing of.

If the formats do not match,
The image data is separately output to the subsequent processing circuit without passing through the selection circuit. At this time, since the moving image transfer is OFF, the operation clock of the moving image processing system in the video processing unit 701 is stopped by the moving image processing system clock stop control unit 801 in the frame rate register unit 707.

In the image output apparatus according to the fifth embodiment, a data transfer request is issued at regular intervals, and the display image data stored in the moving image frame memory 704 and the graphics frame memory 705 is updated. When an image to be updated immediately such as graphics image data is generated, the processor unit 101 sets an update flag in the frame rate register 707, and only when the moving image register or the graphics register is valid, the corresponding data is set. Since the transfer request is issued, the delay between the user's operation and the data display is reduced, providing a video that is not uncomfortable, and a video processing system and graphics processing without transferring unnecessary video data. System operation clocks can be controlled separately, When you do not line it is possible to reduce the power consumption.

The moving image frame memory 711 and the graphics frame memory 712 are followed by a moving image line buffer 713 and a graphics line buffer 714.
, It is easy to control the read timing from the frame memory and output control in accordance with the display timing of the LCD. Since the display moving image data and the display graphics image data are stored separately, the image disappears. In addition, when the same data as the previous line is repeatedly output, there is no need to access the frame memories 711 and 712 each time, and the power consumption of the frame memories 711 and 712 can be reduced. . During the valid period of the horizontal synchronization signal of the previous line, the frame memories 711 and 71 of the display image data for one line are used.
2 during the blanking period of the horizontal synchronizing signal, one line of data is transferred to the line buffers 713 and 714 at a stretch,
By outputting the image data to the CD, the frame delay until displaying the transferred data can be reduced.

(Embodiment 6) The following describes Embodiment 6 of the present invention.
Will be described with reference to FIGS. 4 and 11. FIG. FIG. 11 is a block diagram of an image output device according to the sixth embodiment. In FIG. 11, the same reference numerals are used for the same or corresponding components as those in FIG.
The description is omitted.

Reference numeral 901 denotes a moving image frame memory which stores one line of display moving image data for one frame (288 lines) during an effective period other than the blanking period of the horizontal synchronizing signal. A graphics frame memory 902 stores display graphics image data for one line for one frame (288 lines) in an effective period other than the blanking period of the horizontal synchronization signal. Reference numeral 903 denotes a moving image frame memory 901 and a graphics frame memory 902
A line buffer that combines output data from the frame memory and stores data for one line. During a blanking period of the horizontal synchronization signal, data is read from each frame memory and passed through a selection circuit for combination. And stored in the line buffer 903. In addition, data is output from the line buffer 903 during an effective period other than the blanking period of the horizontal synchronization signal in accordance with the LCD synchronization signal and the pixel display timing. Since the sixth embodiment is almost the same as the fourth embodiment, the description of the common parts will be omitted.

Next, the operation of the image output apparatus according to the sixth embodiment will be described. As described in the fourth embodiment, the moving image data and the graphics table data transferred from the data memory 102 are processed by the video processing unit 701, respectively. The processor unit 101 stores the decoded image rate of 15H in the frame rate register 707.
Set a value representing z. Further, the data transfer request issuing unit 708 is set so that only the data to be transferred is turned on. Here, normally, only moving images are displayed, and moving image transfer ON and graphics transfer OFF are set.

When the frame for which the transfer is valid is reached, the data transfer request issuing unit 708, as shown in FIG.
A data transfer request is issued in accordance with the timing of the horizontal synchronization signal from the timing immediately before the vertical synchronization signal of the LCD becomes valid. At this time, a data transfer request is made only for moving image data, and no graphics data is transferred.

The moving image data for one line transferred in this way is subjected to scaling processing in the video processing unit 701 during an effective period other than the blanking period of the horizontal synchronizing signal, and is subjected to QCIF (176 × 144). CIF (35
2 × 288). Then, the processed moving image data is sequentially stored in the moving image frame memory 901 as display moving image data. Then, the moving image data for one frame (288 lines) stored in the moving image frame memory 901 is transferred to the line buffer 903 at a stretch during the blanking period of the next horizontal synchronization signal.
From the line buffer 903, during a valid period other than the blanking period of the horizontal synchronizing signal, it is output to the external LCD in synchronization with the synchronizing signal and the pixel output timing.

Further, except for the transfer cycle of 15 Hz, writing to the moving picture frame memory 901 is not performed.
Image data is repeatedly output to the LCD. As in the fourth embodiment, the operation clock of the video processing unit 701 is the graphics processing system clock stop control unit 8.
02 is stopped.

Next, a case where a graphics update instruction is issued together with graphics table data from the host CPU will be described. The processor unit 101
The graphics transfer ON is set in the data transfer request issuing unit 708, and the update flag 2 of the frame rate register 707 is set.
Set 1 to 02. At this time, if there is no need to update the display moving image data and only the display graphics image data needs to be changed, the data transfer request issuing unit 708 may turn off the moving image transfer.

Therefore, in the next frame, the moving image data is not transferred from the data memory 102 to the video processing unit 704, but only the graphics table data is transferred. Then, the transferred graphics table data is generated as display graphics image data in the video processing unit 701, and is sequentially stored in the graphics frame memory 902. Since the display moving image data and the display graphics image data are stored separately, there is no disturbance such as disappearance of the video.

From the moving picture frame memory 901 and the graphics frame memory 902, display image data for one line is displayed during the blanking period of the next horizontal synchronization signal.
Each is read out and transferred to the line buffer 903 via a selection circuit for synthesizing data. Then, when a valid period other than the blanking period of the horizontal synchronizing signal comes, data is sequentially read from the line buffer 903 and output in accordance with the display timing of the LCD. During this time, since the moving image transfer is OFF, the video processing unit 70
1 is the moving image processing system clock stop control unit 801 in the frame rate register 707.
Stops the clock.

In the image output device according to the sixth embodiment, a data transfer request is issued at regular intervals to update the display image data stored in the moving image frame memory 704 and the graphics frame memory 705. When an image to be updated immediately such as graphics image data occurs, the processor unit 101 sets an update flag in the frame rate register 707, and only when the moving image register or the graphics register is valid, Since the data transfer request is issued, the delay between the user's operation and the data display is reduced, providing a video that is not uncomfortable, and a video processing system and graphics without unnecessary video data transfer. Since the operating clock of the processing system can be controlled separately, data transfer When you do not want to run it is possible to reduce power consumption.

Further, by providing one line buffer 903 at the subsequent stage of the moving image frame memory 901 and the graphics frame memory 902, of the image output periodic signals to the image display device, other than the blanking period of the horizontal synchronizing signal. , Image data is written into the moving image frame memory 901 and the graphics frame memory 902, and during the blanking period of the horizontal synchronization signal, the moving image frame memory 901 and the graphics frame memory 902 are written.
The output data is combined for one line and transferred to the line buffer 903, and the image data is output from the line buffer 903 to the subsequent LCD during a period other than the blanking period of the horizontal synchronization signal. The frame delay until the displayed image data is displayed can be eliminated, the readout timing from the frame memory,
Further, the display timing on the image display device can be easily controlled, and the operation time of the frame memories 901 and 902 can be minimized to reduce the power consumption.

(Embodiment 7) The following describes Embodiment 7 of the present invention.
Will be described with reference to FIG. 4 and FIG. FIG. 12 is a block diagram illustrating a configuration of an image output device according to the seventh embodiment. In FIG. 12, FIG.
The same reference numerals are used for components that are the same as or correspond to 1, and the description thereof is omitted. A moving image line buffer 904 temporarily stores one line of the display moving image data. 905 is a graphics line buffer,
One line of display graphics image data is temporarily stored. A moving image frame memory 906 temporarily stores output data of the moving image line buffer 904 for one frame. A graphics frame memory 907 includes a graphics line buffer 905.
Is temporarily stored for one frame.

Next, the operation of the image output apparatus according to the seventh embodiment will be described. The processor unit 101 performs a decoding process on an image using the data memory 102, and stores the decoded image in the data memory 102. Host C
Graphics table data transferred from PU also
The data is stored in the data memory 102.

The processor section 101 sets a value representing 15 Hz which is the decoded image rate in the frame rate register 707. 15 Hz is, as shown in FIG.
When the vertical synchronization signal of D is used as a reference, the transfer is performed once every four frames. That is, data transfer is effective once every four frames. Therefore, the frame rate register 20
1 is set to 3. Further, the data transfer request issuing unit 7
08 is set so that only the data to be transferred is turned on. Here, usually, it is assumed that only the decoded image (moving image) is displayed, and that the moving image transfer is ON and the graphics transfer OF is performed.
Set F.

Further, when the data transfer request issuing unit 708 becomes a frame in which the transfer is valid, as shown in FIG.
A data transfer request is issued from the timing immediately before the vertical synchronization signal of the LCD becomes valid, to the start timing of the horizontal synchronization signal. At this time, the transfer request is made only for the moving image data, and not for the graphics data.

The moving image data for one line transferred in this manner is subjected to scaling processing in the video processing unit 701 during an effective period other than the blanking period of the horizontal synchronizing signal, and is converted from QCIF (176 × 144). Expanded to CIF (352 x 288) size. The processed moving image data is sequentially stored in the moving image line buffer 904 as display moving image data. The display moving image data for one line stored in the moving image line buffer 904 is stored in the moving image frame memory 906 at a stretch in the first half of the blanking period of the horizontal synchronization signal.

In the latter half of the blanking period of the horizontal synchronizing signal, the display moving image data stored in the moving image frame memory 906 is transferred to the subsequent line buffer 903 at a stretch. From the line buffer 903, during a valid period other than the blanking period of the horizontal synchronizing signal, it is output to the external LCD in synchronization with the synchronizing signal and the pixel output timing.

Note that writing to the moving picture frame memory 906 is not performed except for the transfer cycle of 15 Hz, and the display image stored in the moving picture frame memory 906 is repeatedly output to the LCD via the line buffer 903. Is done. In addition, other than the transfer cycle of 15 Hz,
The operation clock of the video processing unit 701 and the line buffer 903 of the graphics transfer system that is turned off by the data transfer request issuing unit 708 is stopped by the graphics clock stop control unit 802.

Next, a case where a graphics update command is issued together with graphics table data from the host CPU will be described. The processor unit 101
The graphics transfer ON is set in the data transfer request issuing unit 708, and the update flag 2 of the frame rate register 707 is set.
Set 1 to 02. At this time, if there is no need to update the display moving image data and only the display graphics image data needs to be changed, the data transfer request issuing unit 708 may turn off the moving image transfer. At this time, it is assumed that graphics transfer remains ON.

The data transfer request issuing unit 708 checks the update flag at the start of the next frame when the vertical synchronizing signal falls, and determines that the graphics transfer is ON and the moving image transfer is ON. From, in the next frame,
Request transfer of both video data and graphics table data. Therefore, in the next frame, moving image data and graphics data are transferred from the data memory 102 to the video processing unit 701.

The moving image data for one line transferred in this manner is subjected to scaling processing in the video processing section 701 during an effective period other than the blanking period of the horizontal synchronizing signal, and is converted from QCIF (176 × 144). The data is enlarged to a CIF (352 × 288) size and sequentially stored as moving image data in the moving image line buffer 904. Further, the graphics table data is generated into graphics image data in the video processing unit 701, and is sequentially stored in the graphics line buffer 905.

In the first half of the blanking period of the horizontal synchronizing signal, the data is transferred from the moving image line buffer 904 and the graphics line buffer 905 to the moving image frame memory 906 and the graphics frame memory 907 at a stretch. At this time, since the display moving image data and the display graphics image data are stored separately, no disturbance such as disappearance of the video occurs. Further, in the latter half of the horizontal synchronizing signal blanking period, the moving image frame memory 90
6 and the graphics frame memory 907 to the line buffer 903 to store display image data obtained by combining display moving image data and display graphics image data. When the effective period of the horizontal synchronizing signal comes, the combined display image data is sequentially output from the line buffer 903 line by line in accordance with the display timing of the LCD.

In the image output device according to the seventh embodiment, a data transfer request is issued at regular intervals, and the display image data stored in the moving image frame memory 704 and the graphics frame memory 705 is updated. When an image to be updated immediately such as graphics image data occurs, the processor unit 101 sets an update flag in the frame rate register 707, and only when the moving image register or the graphics register is valid, Since the transfer request is issued, the delay between the user's operation and the data display is reduced, providing a video that is not uncomfortable, and a video processing system and graphics processing without unnecessary video data transfer. System operation clocks can be controlled separately, When you do not line it is possible to reduce the power consumption.

A moving image line buffer 904 and a graphics line buffer 905 precede the moving image frame memory 906 and the graphics frame memory 907.
, The writing timing control to the frame memories 906 and 907 becomes easy, and the synthesis and display of the image can be realized with one frame memory.
One line buffer 903 is also provided at the subsequent stage, and during the blanking period of the horizontal synchronizing signal, the display moving image data and the display graphics
3, each frame memory 906, 9
07 operation time can be minimized, and power consumption can be reduced.

In the first half of the horizontal synchronizing signal blanking period, display image data for one line is stored in the frame memories 906 and 907 at a stretch, and is transferred to the line buffer in the latter half of the horizontal synchronizing signal blanking period. By transferring the data, the frame delay until displaying the transferred data can be reduced.

In the seventh embodiment, display image data is written to the frame memory in the first half of the blanking period of the horizontal synchronization signal, and from the frame memory to the line buffer in the second half of the blanking period of the horizontal synchronization signal. In contrast, the data transfer to the line buffer is performed in the first half of the blanking period of the horizontal synchronization signal, and the data transfer to the frame memory is performed in the second half of the blanking period of the horizontal synchronization signal. The data is written, the display image data is input to the frame memory at the timing one line before, and the display image data one line after the display image data is output from the frame memory at the timing of the next line. Embodiment 7
The same effect can be obtained.

Embodiment 8 Hereinafter, an image output apparatus according to Embodiment 8 will be described with reference to FIG. FIG. 13 is a block diagram showing a configuration of an image output device according to the eighth embodiment. In FIG. 13, reference numeral 131 denotes a processor, which controls the entire apparatus. A data memory 132 stores image data such as moving image data and graphics table data. Reference numeral 133 denotes a data transfer control unit, which includes a data memory 132 and a video processing unit 134.
Controls data transfer to and from A video processing unit 134 performs image processing such as scaling processing and graphics generation processing on the image data transferred from the data memory 132 to generate display image data such as display moving image data and display graphics image data. .

A first moving image line buffer 135 temporarily stores one line of moving image data. 13
Reference numeral 6 denotes a first graphics line buffer, which temporarily stores one line of graphics image data. A moving image frame memory 137 temporarily stores output data of the first moving image line buffer. 138
Is a graphics frame memory for temporarily storing output data of the first graphics line buffer. Reference numeral 139 denotes a second moving image line buffer, which temporarily stores output data of the moving image frame memory 137.
130 is a second graphics line buffer;
The output data of the graphics frame memory 138 is temporarily stored. Reference numeral 140 denotes a constant cycle interrupt generation unit which outputs an interrupt signal to the processor unit 131 at regular intervals according to an image output cycle signal to the image display device, and a horizontal synchronization signal generator 141 for generating an Hsync interrupt signal. And a vertical synchronization signal generator 142 for generating a Vsync interrupt signal.

Next, the operation of the image output apparatus having the above configuration will be described. The processor unit 131 is a host CP
The encoded video data transferred from U is stored in data memory 1
The decoding process is performed using the data 32 and the moving image data is stored in the data memory 132. The graphics table data transferred from the host CPU is also stored in the data memory 132. The horizontal synchronizing signal generator 141 and the vertical synchronizing signal generator 142 send the Hsync interrupt signal and Vsy to the processor 131 at the timing of the synchronizing signal.
An nc interrupt signal has been generated.

In response to the input of the Vsync interrupt signal, the processor unit 131 resets the measurement (line count) of the number of occurrences of the Hsync interrupt signal in order to reset the data transfer request generation interval. Thereafter, each time the Hsync interrupt signal is generated, the number of occurrences is counted up. Then, the processor unit 131
Issues a data transfer request to the data transfer control unit 133 when the Hsync interrupt signal of the line 8 is input as shown in FIG. Here, the data transfer request is
If only moving image data is to be displayed, a request for only moving image data is made, and if only graphics image data is to be displayed, only a request for graphics table data is made. Also, in order to combine and output at the final stage,
When both data are required, a data transfer request for transferring moving image data and graphic table data is issued.

The processor unit 131 sets the H of the line 297 to H.
The data transfer request continues to be issued until the sync interrupt signal is input. When the Hsync interrupt signal on line 298 is input, the data transfer request is not issued. When the Vsync interrupt signal is input again, the line count is reset. If the decoding processing of the encoded video data has been completed or the graphics data needs to be updated in the next frame period, the line count is reset. The number of occurrences of the Hsync interrupt signal is counted up, and a data transfer request is issued. However, when the image data is not transferred in the next frame period (when there is no moving image data or when there is no graphics data to be updated), H
It does not count up the number of times a sync interrupt signal is generated and does not issue a data transfer request.

The transferred moving image data and graphics table data are transferred to the video processing unit 134 in the next line.
As required, image processing such as scaling processing, graphics generation processing, noise removal processing, image format conversion (RGB conversion, 4: 2: 2 conversion) is performed, and display moving image data and display graphics image data At any time, the first moving image line buffer 135 and the first
Is written to the graphics line buffer 136. Then, in the first half of the blanking period of the horizontal synchronization signal of the next line, burst transfer is performed to the moving image frame memory 137 and the graphics frame memory 138.

Subsequently, in the latter half of the blanking period of the same horizontal synchronizing signal, the data is transferred from the moving picture frame memory 137 and the graphics frame memory 138 to the second moving picture line buffer 139 and the second graphics line buffer 130, After the ranking period ends, the display moving image data and the display graphics image data are combined, and L
Output to CD. By doing so, it is possible to reduce delay until image display.

In a frame in which the processor unit 131 does not issue an image data transfer request, during a previous frame period,
The display image data stored in the moving image frame memory 137 and the graphics frame memory 138 are output to the LCD via the second line buffer 139 and the second graphics line buffer 130, respectively.

In the image output apparatus according to the eighth embodiment, the processor unit 131 uses the synchronization signal interrupt signal periodically generated from the fixed period interrupt generation unit 140 to switch the data memory 132 from the video processing unit 134.
By controlling the transfer of image data to the CPU, the data transfer can be collectively managed by the processor unit 131, and the transfer pattern can be changed in any phase of development. In particular, the transfer pattern can be changed even after the system is completed. The rate can be programmed freely, increasing the degree of freedom of the update pattern. In addition, since the updating of the image frame is controlled by the program, the updating can be performed even after the hardware design is completed, so that the easiness of the design and the degree of freedom are improved.

Further, a first moving image line buffer 135 and a first graphics line buffer 136 are provided at the preceding stage of the moving image frame memory 137 and the graphics frame memory 138, and the second moving image line buffer 139 and the second Graphics line buffer 130
Is provided, the image data stored in the frame memories 137 and 138 can be displayed immediately, so that image display with less delay can be realized, and at the same time, data of the next frame is stored. be able to.

The large-capacity frame memory operates only during data input / output with the first and second line buffers during the blanking period.
By stopping the operation, power consumption can be reduced. When image data transfer does not occur (when the video processing unit does not operate), the first line buffer is stopped and a large-capacity frame memory is used. Is required to operate only during the blanking period of the horizontal synchronizing signal to be transferred to the second line buffer.
Only the line buffer needs to operate at the time of outputting image data, and by stopping the clocks of the line buffer and the frame memory, low power consumption output can be realized.

In the eighth embodiment, when an image display device such as a liquid crystal display device having a frame memory is used, the output of the video processing unit 134 or the output of the first line buffers 135 and 136 is used. It is possible to adopt a configuration in which input is directly made to the image display device, and a higher effect can be exhibited.

In the eighth embodiment, display image data is written to the frame memory in the first half of the blanking period of the horizontal synchronizing signal, and from the frame memory to the line buffer in the second half of the blanking period of the horizontal synchronizing signal. In contrast, the data transfer to the line buffer is performed in the first half of the blanking period of the horizontal synchronization signal, and the data transfer to the frame memory is performed in the second half of the blanking period of the horizontal synchronization signal. The data is written, the display image data is input to the frame memory at the timing one line before, and the display image data one line after the display image data is output from the frame memory at the timing of the next line. Embodiment 8
The same effect can be obtained.

[0146]

According to the image output device of the first aspect of the present invention, a data memory for storing image data, and a video processing unit for performing image processing on the image data and generating display image data. A data transfer control unit that controls data transfer between the data memory and the video processing unit, and an output data storage unit that temporarily stores the display image data and outputs the image data to the image display device at regular intervals. A system control unit that controls the entire apparatus, wherein the system control unit issues an update instruction for updating the display image data stored in the output data storage unit. Only because a data transfer request control circuit that issues a data transfer request to execute the data transfer in a fixed data unit is provided, the update flag is set in the frame update register. Data transfer is performed only when the data is set, the minimum required data update is performed, unnecessary transfer is reduced, and as a result, power consumption can be reduced, and an update flag must be set. In this way, data transfer can be started automatically and immediately, eliminating the need for complicated control by the system controller as in the past.
In addition, the image data can be updated immediately without delay.

According to the image output device of the present invention, in the image output device of the first aspect, the data transfer request control circuit periodically issues the data transfer request. A request issuing unit, a frame rate register for determining an issuance cycle of the data transfer request,
The data transfer request issuance unit is configured to issue the data transfer request when the system control unit sets an update flag in the frame rate register, regardless of the issuance cycle set in the frame rate register. Since the issuance of the data transfer request is immediately started at the start determination timing, an irregular data transfer request can be immediately issued while maintaining the period for issuing the periodic data transfer request. it can.

According to the image output device of the present invention, in the image output device of the present invention, the frame rate register counts each time the data transfer request issuance start determination timing. A counter is provided, the most significant bit is a bit representing an update flag, and the lower bits excluding the most significant bit determine the issuance cycle. When the update flag is valid, the counter is reset, and The update flag is reset to an invalid value at the data transfer request issuance start determination timing, and the counter again counts the issuance cycle determined by the lower bits excluding the most significant bit. Since the setting of the frame rate register and counter can be automated, the transfer cycle and transfer can be easily set. The need for reconfiguration is eliminated.

According to the image output device of the fourth aspect of the present invention, in the image output device of the third aspect, the frame rate register stores which frame in the image output cycle to the image display device. A transfer cycle indicating whether a data transfer request is to be issued, and the data transfer request issuing unit determines whether to enable or disable the transfer of the moving image data, and a transfer of the graphics data. And a graphics transfer register for determining whether to enable or disable the video register. If the system control unit sets an update flag in the frame rate register, the video register or the graphics register is valid. Only in such cases, the data transfer requests corresponding to each are issued, so that the displayed image can be updated immediately. In addition, the delay between the user operation and the data display is reduced, providing a video that is not uncomfortable, and the power consumption when data transfer is not performed because unnecessary video data is not transferred. Can be reduced.

According to the image output device of the present invention, in the image output device of the present invention, the data transfer request issuance unit may be configured to execute the image display in a frame in which the data transfer is valid. Since the line transfer request is issued for each line at the timing of the horizontal synchronization signal in the image output periodic signal to the device, the start timing of the data transfer request is easily controlled without the need for a special timing generator. It is possible to control a data transfer issue request at a regular transfer cycle. This facilitates the realization of the transfer request issuance in hardware.

According to the image output device of the sixth aspect of the present invention, in the image output device of the fifth aspect, the data transfer request issuance unit may be configured so that an update flag is set in the frame rate register. Of the image output periodic signals to the image display device, the update flag is determined to be valid at the next vertical synchronization signal timing, and a data transfer request for transferring the frame is issued. It is possible to determine the issuance of a data transfer request on a frame-by-frame basis, so that system control can be easily and accurately controlled, and as a result, image disturbances and the like are less likely to occur.

According to the image output device of the present invention, a data memory for storing image data, a video processing unit for performing image processing on the image data and generating display image data, A data transfer control unit that controls data transfer between a data memory and the video processing unit; an output data storage unit that temporarily stores the display image data and outputs the display image data to an image display device at regular intervals; And a system control unit for controlling the image output device, wherein a fixed cycle interrupt generation unit that outputs an interrupt signal to the system control unit at fixed intervals in accordance with the image output cycle signal to the image display device. The system control unit determines whether to perform the data transfer based on the input of the interrupt signal, and determines that it is the interrupt timing to be transferred. If the data transfer request for performing said data transfer by issuing to the data transfer control unit,
When it is determined that it is not the interrupt timing to transfer, the above data transfer request is not issued.
The transfer pattern can be changed by the system control unit at any phase of the development, particularly after the system is completed, so that the transfer pattern can be freely programmed and the degree of freedom of the update pattern increases.

According to the image output device of the present invention, in the image output device of the present invention, the system control unit transfers the moving image data stored in the data memory. Moving image transfer request, and a graphics transfer request for transferring the graphics data stored in the data memory, so that the moving image data and the graphics data can be separately transferred, Power consumption can be reduced.

According to the image output device of the ninth aspect of the present invention, in the image output device of the first aspect, the video processing unit performs scaling processing on the moving image data transferred from the data memory. And a graphics generation processing unit for performing graphics generation processing on the graphics data transferred from the data memory to generate display graphics image data. Since the display moving image data and the display graphics image data are combined and output, the processing of the moving image data and the processing of the graphics data can be controlled separately.

According to the image output device of the present invention, in the image output device of the ninth aspect, the output data storage unit temporarily stores one line of output data of the video processing unit. And a frame memory for storing one frame of output data of the line buffer, so that the timing of writing the display image data to the frame memory can be easily controlled and one Image synthesis and display can be realized by the frame memory. Further, since the image is stored in the frame memory in frame units, the image is not disturbed, and the image display can be realized with a small number of circuits.

According to the image output device of the present invention, in the image output device of the ninth aspect, the output data storage section stores the output data of the video processing section for one frame. A frame memory that sequentially outputs the stored data in units of one line, and a line buffer that stores the output data of the frame memory, when outputting display image data to the image display device,
Since there is no need to perform control by RAS and CAS unlike the frame memory, it is easier to control the output timing of the display image data than directly from the frame memory.

According to the image output device of the present invention, in the image output device of the first or seventh aspect, the video processing unit may be configured to convert the moving image data transferred from the data memory. A scaling processing unit that performs scaling processing on the data to generate display moving image data;
A graphics generation processing unit that performs graphics generation processing on the graphics data transferred from the data memory to generate display graphics image data, and the display video data and the display graphics image data Since each is output to the output data storage unit, processing of moving image data and graphics data can be controlled separately, and power consumption can be reduced.

According to the image output device of the present invention, in the image output device of the present invention,
The output data storage unit is configured to temporarily store one line of data of the display moving image data in a moving image line buffer, and temporarily stores output data of the moving image line buffer in one line.
A moving image frame memory for storing frames, a graphics line buffer for temporarily storing one line of the display graphics image data, and a frame for temporarily storing output data of the graphics line buffer. A graphics frame memory, wherein the storage data of the moving image frame memory and the storage data of the graphics frame memory are combined and output to the image display device, so that the display moving image data and the display graphics image data Can be stored separately, so that disturbances such as disappearance of video do not occur.In addition, since they can be updated separately, it is not necessary to perform both image data, so there is no need to perform useless data transfer. Power consumption can be reduced.

According to the image output apparatus of the present invention, in the image output apparatus of the present invention,
The output data storage unit temporarily stores the display moving image data for one frame, and stores the stored display moving image data in one frame.
A moving image frame memory for sequentially outputting line by line, a moving image line buffer for temporarily storing output data of the moving image frame memory, and a frame for temporarily storing the display graphics image data for one frame; A graphics frame memory for sequentially outputting graphics image data in units of one line, and a graphics line buffer for temporarily storing output data of the graphics frame memory. Since the data stored in the line buffer is combined or separately output to the image display device, even when the video format differs between the moving image data and the graphics data, the data is individually synchronized with the display line. Output and the same display graph Ikkusu image repeatedly even if not always display the number of lines such as the output does not match the data, it is not necessary to read out the data from each display line always frame memory is largely possible reduce power consumption.

According to the image output device of the present invention, in the image output device of the present invention,
The output data storage unit temporarily stores the display moving image data for one frame, and stores the stored display moving image data in one frame.
A moving image frame memory for sequentially outputting the display graphics image data for one frame, and temporarily storing the display graphics image data for one frame;
The display frame data and the frame data that are sequentially output in line units, and the line buffer that temporarily combines the output data of the graphics frame memory and the output data of the graphics frame memory, thereby displaying the display video data and Display graphics data can be updated separately, and as a result, useless data transfer is eliminated, and power consumption can be reduced.

According to the image output device of the present invention, in the image output device of the present invention,
The output data storage unit includes a moving image line buffer for temporarily storing one line of the display moving image data, and temporarily stores one frame of output data of the moving image line buffer, and stores the stored display moving image data. A moving image frame memory for outputting one line at a time, a graphics line buffer for temporarily storing one line of the display graphics image data, and one frame for temporarily storing output data of the graphics line buffer. A graphics frame memory that stores and outputs the stored display graphics image data in units of one line, and combines the output data of the moving image frame memory and the output data of the graphics frame memory to temporarily generate display image data. Line buffer for temporarily storing and outputting to the image display device , From the consisting of a updatable display moving image data and the display graphics data separately, further, since it is possible to reduce the respective circuit operation, the result, there is no useless data transfer, power consumption can be reduced.

According to the image output apparatus of the present invention, in the image output apparatus of the present invention,
A first moving image line buffer for temporarily storing one line of the display moving image data;
A moving image frame memory for temporarily storing output data of the first moving image line buffer for one frame, and sequentially outputting the stored display moving image data in units of one line, and temporarily storing output data of the moving image frame memory. Second to store
Moving image line buffer, a first graphics line buffer for temporarily storing one line of the display graphics image data, and an output data of the first graphics line buffer for one frame temporarily A graphics frame memory for sequentially outputting the stored display graphics image data in units of one line, and a second graphics line buffer for temporarily storing output data of the graphics frame memory; The data stored in the second moving image line buffer and the data stored in the second graphic line buffer are combined and output to the image display device. Minimize the operation of large-capacity frame memory that stores images for frames, Cost power is capable of significantly reducing the,
Furthermore, data can be updated separately for the display moving image data and the display graphics image data, and even when the video format differs between the moving image data and the graphics data, the data is individually transmitted to the image display device. Output is possible in synchronization with the display line.

According to the image output apparatus of the present invention, when the data transfer or the data processing is not performed in the image output apparatus of the first or seventh aspect, the operation in the apparatus is performed. An operation clock stop control unit that controls the clock to be stopped provides separate control of the operation clocks for the video data processing system and the graphics image data processing system according to the data transfer of video data or graphics image data. Power consumption can be greatly reduced.

According to an image output control method according to claim 19 of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to claim 10. In the image output periodic signal to the image display device, the display image data is stored in the line buffer during a period other than the blanking period of the horizontal synchronization signal, and the display image data is stored in the blanking period of the horizontal synchronization signal. Is transferred from the line buffer to the frame memory, and during a period other than the blanking period of the horizontal synchronization signal, the display image data is output from the frame memory to the image display device. Using the validity period, control the data to be stored in the frame memory and output the stored data immediately to reduce the frame delay. In a possible response to the repeated display in the next frame, the access contention to the frame memory can be prevented, thereby facilitating the system control. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to a twentieth aspect of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device. In the image output periodic signal to the image display device, the display image data is stored in the frame memory during a period other than the blanking period of the horizontal synchronization signal, and the display image data is stored in the blanking period of the horizontal synchronization signal. Is transferred from the frame memory to the line buffer, and during the period other than the blanking period of the horizontal synchronization signal, the display image data is output from the line buffer to the image display device. Using the validity period, control the data to be stored in the frame memory and output the stored data immediately to reduce the frame delay. In a possible response to the repeated display in the next frame, the access contention to the frame memory can be prevented, thereby facilitating the system control. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to an image output control method according to claim 21 of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to claim 13. In the image output period signal to the image display device, during the period other than the blanking period of the horizontal synchronization signal, the display moving image data and the display graphics image data are respectively transferred to the moving image line buffer and the graphics line buffer. And during the blanking period of the horizontal synchronizing signal, the display moving image data and the display graphics image data are transferred from the moving image line buffer and the graphics line buffer to the moving image frame memory and the graphics frame memory, respectively. During the period other than the horizontal synchronization signal blanking period, Since the display moving image data and the display graphics image data are combined and output to the image display device, the data is stored in the frame memory using the effective period of the horizontal synchronization signal, and the stored data is output immediately. To reduce the frame delay, and at the same time, it is possible to respond to repeated display in the next frame.
System control becomes easy. Also, 1 is stored in the frame memory.
By accumulating data for frames, the operating time can be reduced, and power consumption can be reduced.

According to an image output control method according to claim 22 of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to claim 14, In the period other than the blanking period of the horizontal synchronizing signal in the image output periodic signal to the image display device, the display moving image data and the display graphics image data are stored in the moving image frame memory and the graphics frame memory, respectively. During the blanking period of the horizontal synchronization signal, the display moving image data and the display graphics image data are transferred from the moving image frame memory and the graphic frame memory to the moving image line buffer and the graphics line buffer, respectively. During the period other than the horizontal synchronization signal blanking period, Since the display moving image data and the display graphics image data are combined or separately output to the image display device, the data stored in the frame memory is output to the line buffer using the valid period of the horizontal synchronization signal. With this control, the data of the line generated by the video processing unit can be output on the next line. As a result, there is no contention for data access to the frame memory, and the frame delay can be reduced. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to an image output control method according to claim 23 of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to claim 15, In the period other than the blanking period of the horizontal synchronizing signal in the image output periodic signal to the image display device, the display moving image data and the display graphics image data are stored in the moving image frame memory and the graphics frame memory, respectively. During the blanking period of the horizontal synchronization signal, the output data of the moving picture frame memory and the output data of the graphics frame memory are combined and transferred to the line buffer, except for the blanking period of the horizontal synchronization signal. Since the data stored in the line buffer is output to the image display device during the period of By using the valid period of the initial signal, the data is stored in the frame memory and is controlled so as to output the stored data immediately, so that the frame delay can be reduced and at the same time, it is possible to cope with the repeated display in the next frame. Access conflicts can also be prevented, and system control becomes easier. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to an image output control method according to claim 24 of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to claim 16, In the image output periodic signal to the image display device, a blanking period of the horizontal synchronizing signal is divided into a first period and a second period. In the first period, the data stored in the moving image line buffer and the graphic data are stored. Transferring each of the data stored in the line buffer to the video frame memory and the graphics frame memory, and in the second period, the output data of the video frame memory and the output data of the graphics frame memory are Since they are combined and transferred to the line buffer, they are stored in the frame memory using the effective period of the horizontal synchronization signal. Controls to output the immediately accumulated data, and at the same time reducing the frame delay is also available to repeatedly display the next frame, the access contention to the frame memory can be prevented, thereby facilitating the system control. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

According to an image output control method according to claim 25 of the present invention, there is provided an image output control method for controlling output of image data from an image output device to an image display device according to claim 17, The blanking period of the horizontal synchronizing signal of the image output periodic signal to the image display device is divided into a first period and a second period.
Transfer each of the storage data of the moving image line buffer and the storage data of the first graphics line buffer to the moving image frame memory and the graphics frame memory, and in the second period, Since each of the storage data and the storage data of the graphics frame memory is transferred to the second moving image line buffer and the second graphics line buffer, the effective period of the horizontal synchronization signal is used. It is possible to store the data in the moving picture frame memory and the graphics frame memory and output the stored data immediately. As a result, it is possible to reduce the frame delay and at the same time to cope with the repeated display in the next frame. Access to graphics frame memory Conflict can be prevented, thereby facilitating the system control. Further, by storing data for one frame in the frame memory, the operation time can be reduced, and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image output device according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of an image output device according to a second embodiment.

FIG. 3 is a diagram illustrating an example of a configuration of a frame rate register.

FIG. 4 is a diagram illustrating a relationship between an image output frame cycle and an update flag.

FIG. 5 is a diagram showing a relationship between a horizontal synchronization signal of the LCD and data transfer timing.

FIG. 6 is a block diagram illustrating a configuration of an image output device according to a third embodiment.

FIG. 7 is a diagram illustrating a relationship between a horizontal synchronization signal of the LCD and data transfer timing.

FIG. 8 is a block diagram illustrating a configuration of an image output device according to a fourth embodiment.

FIG. 9 is a block diagram illustrating a configuration of an image output device according to a fifth embodiment.

FIG. 10 is a diagram illustrating an example of a configuration of a frame rate register.

FIG. 11 is a block diagram showing a configuration of an image output device according to a sixth embodiment.

FIG. 12 is a block diagram illustrating a configuration of an image output device according to a seventh embodiment.

FIG. 13 is a block diagram showing a configuration of an image output device according to an eighth embodiment.

FIG. 14 is a diagram showing a relationship between a horizontal synchronization signal of the LCD and data transfer timing.

FIG. 15 is a diagram showing a configuration of a conventional electronic drawing apparatus.

FIG. 16 is a diagram illustrating an example of a conventional image output device.

FIG. 17 is a diagram illustrating a configuration of a conventional image transmission device.

FIG. 18 is a diagram illustrating a configuration of a conventional image receiving device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Electronic drawing apparatus 10 Data supply part 11 Intermediate data generation part 12 Hierarchical data generation part 20, 21 Frame memory 30 Output selection part 40 Data display part 50 Control part 60 Overlay control part 1001 Processor part 1002 Data memory 1003 Data transfer control part 1004 Video processing unit 1006 Frame memory 1007 Data transfer request control circuit 1008 Frame update register 1009 Data transfer request issuing unit 101 Processor unit 102 Data memory 103 Data transfer control unit 104 Video processing unit 105 Line buffer 106 Frame memory 107 Data transfer request control circuit 108 Frame rate register 109 Data transfer request issuing unit 201 Frame rate register 202 Update flag 203 Counter 204 Period match detector 205 Logic Sum 206 Logical product (all 0 detection unit) 207 Clock stop control unit 501 Frame memory 502 Line buffer 701 Video processing unit 702 Video line buffer 703 Graphics line buffer 704 Video frame memory 705 Graphics frame memory 706 Data transfer request control circuit 707 Frame rate register 708 Data transfer request issuing unit 711 Video frame memory 712 Graphics frame memory 713 Video line buffer 714 Graphics line buffer 801 Video processing system clock stop control unit 802 Graphics processing system clock stop control unit 901 Video frame memory 902 Graphics Frame memory 903 Line buffer 904 Video line buffer 905 Graphics line bar Buffer 906 Video frame memory 907 Graphics frame memory 131 Processor unit 132 Data memory 133 Data transfer control unit 134 Video processing unit 135 First video line buffer 136 First graphics line buffer 137 Video frame memory 138 Graphics frame memory 139 Second moving image line buffer 130 Second graphics line buffer 140 Fixed period interrupt generation unit 141 Horizontal synchronization signal generator 142 Vertical synchronization signal generator 160 Host IF 161 Processor 162 SDRAM 163 DMA controller 164 Video IF 165 NTSC ADC 166 NTSC DAC

 ────────────────────────────────────────────────── ─── Continued from the front page (72) Inventor Masatoshi Matsuo 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5B069 BC02 LA16 5C082 AA00 BA12 BB22 BB25 BB26 BB53 BD02 BD09 DA42 DA63 DA73 DA76 DA89 EA15 MM02

Claims (25)

[Claims] 1. A data memory for storing image data,
A video processing unit that performs image processing on the image data to generate display image data, a data transfer control unit that controls data transfer between the data memory and the video processing unit, and temporarily stores the display image data. An image output device comprising: an output data storage unit that stores the output data and outputs the image data to the image display device at a fixed period; and a system control unit that controls the entire device. A data transfer request control circuit that issues a data transfer request to execute the data transfer in a fixed data unit only when an update instruction for updating the display image data stored in the storage device is issued. Characteristic image output device. 2. The image output device according to claim 1, wherein the data transfer request control circuit determines a data transfer request issuing unit for periodically issuing the data transfer request, and an issue cycle of the data transfer request. The data transfer request issuing unit, when an update flag is set in the frame rate register by the system control unit, regardless of the issuance cycle set in the frame rate register. An image output device, wherein the issuance of the data transfer request is started immediately at the timing of the start of issuing the data transfer request. 3. The image output device according to claim 2, wherein the frame rate register includes a counter that counts each time the data transfer request issuance start determination timing, and the most significant bit is a bit representing an update flag. Yes,
The lower bits excluding the most significant bit determine the issuance cycle, and when the update flag is valid, the counter is reset, and at the timing of the start of issuing the next data transfer request, the update flag is set to: The image output apparatus, wherein the counter is reset to an invalid value, and the counter counts again the issuance cycle determined by lower bits excluding the most significant bit. 4. The image output device according to claim 3, wherein the frame rate register determines a transfer cycle indicating in which frame a data transfer request is issued during an image output cycle to the image display device. The data transfer request issuance unit includes a moving image transfer register that determines whether transfer of moving image data is enabled or disabled, and a graphics unit that determines whether transfer of graphics data is enabled or disabled. A transfer register, and when the system control unit sets an update flag in the frame rate register, issues the corresponding data transfer request only when the moving image register or the graphics register is valid. An image output device characterized by the above-mentioned. 5. The image output device according to claim 4, wherein said data transfer request issuing unit is configured to output a horizontal synchronization signal of a horizontal synchronization signal among image output periodic signals to said image display device in a frame in which said data transfer is valid. An image output device for issuing a line data transfer request at a timing. 6. The image output device according to claim 5, wherein the data transfer request issuing unit, when an update flag is set in the frame rate register, among the image output cycle signals to the image display device.
An image output device that determines that the update flag is valid at the next vertical synchronization signal timing, and issues a data transfer request for transferring the frame. 7. A data memory for storing image data,
A video processing unit that performs image processing on the image data to generate display image data, a data transfer control unit that controls data transfer between the data memory and the video processing unit, and temporarily stores the display image data. An image output device comprising: an output data storage unit for temporarily storing and outputting the image data to the image display device at a constant period; and a system control unit for controlling the entire device. A constant-period interrupt generating unit that outputs an interrupt signal to the system control unit at a constant interval according to the following. The system control unit determines whether to perform the data transfer based on the input of the interrupt signal, If it is determined that the interrupt timing should be performed, a data transfer request for performing the data transfer is issued to the data transfer control unit, and the transfer should be performed. If it is determined that the interrupt is not time, it does not issue the data transfer request, that the image output apparatus according to claim. 8. The image output device according to claim 7, wherein the system control unit is a moving image transfer request for transferring moving image data stored in the data memory, and is stored in the data memory. Issue a graphics transfer request for transferring graphics data. 9. The image output device according to claim 1, wherein the video processing unit performs a scaling process on the moving image data transferred from the data memory to generate display moving image data; A graphics generation processing unit that performs graphics generation processing on the graphics data transferred from the data memory to generate display graphics image data, and the display moving image data and the display graphics image data An image output device comprising: 10. The image output device according to claim 9, wherein said output data storage unit temporarily stores one line of output data of said video processing unit, and output data of said line buffer. And a frame memory for storing one frame. 11. The image output device according to claim 9, wherein the output data storage unit stores output data of the video processing unit for one frame,
An image output device, comprising: a frame memory for sequentially outputting the stored data in units of one line; and a line buffer for storing output data of the frame memory. 12. The image output device according to claim 1, wherein the video processing unit performs scaling processing on the moving image data transferred from the data memory to generate display moving image data. A processing unit, and a graphics generation processing unit for performing graphics generation processing on the graphics data transferred from the data memory to generate display graphics image data, wherein the display moving image data and the display graphics are displayed. An image output device for outputting each of the image data to the output data storage unit. 13. The image output device according to claim 12, wherein the output data storage unit includes a moving image line buffer for temporarily storing one line of the display moving image data, and an output of the moving image line buffer. A moving image frame memory for temporarily storing data for one frame;
A graphics line buffer for temporarily storing data for a line; and a graphics frame memory for temporarily storing output data of the graphics line buffer for one frame. An image output device comprising: combining data stored in the graphics frame memory; and outputting the synthesized data to the image display device. 14. The image output device according to claim 12, wherein the output data storage unit temporarily stores the display moving image data for one frame, and sequentially outputs the stored display moving image data in line units. A moving image frame memory, a moving image line buffer for temporarily storing output data of the moving image frame memory, and a frame for temporarily storing the display graphics image data for one frame.
A graphics frame memory for sequentially outputting in line units, a graphics line buffer for temporarily storing output data of the graphics frame memory,
An image output device comprising: combining the storage data of the moving image line buffer and the storage data of the graphics line buffer with each other or separately outputting the combined data to the image display device. 15. The image output device according to claim 12, wherein the output data storage unit temporarily stores the display moving image data for one frame, and sequentially outputs the stored display moving image data in units of one line. A moving image frame memory, a graphics frame memory for temporarily storing the display graphics image data for one frame, and sequentially outputting the stored display graphics image data for each line, and an output of the moving image frame memory. An image output device comprising: a line buffer that combines data and output data of the graphics frame memory and temporarily stores the data. 16. The image output device according to claim 12, wherein the output data storage unit stores a moving image line buffer for temporarily storing one line of the display moving image data and an output data of the moving image line buffer. A moving image frame memory for temporarily storing one frame and outputting the stored display moving image data in units of one line; and a graphics line buffer for temporarily storing one line of the display graphics image data. A graphics frame memory for temporarily storing output data of the graphics line buffer for one frame, and outputting the stored display graphics image data in units of one line; Combines the output data of the frame memory with the display data Time to store the line buffer to be output to the image display device, consisting of, that the image output apparatus according to claim. 17. The image output device according to claim 12, wherein the output data storage unit comprises: a first moving image line buffer for temporarily storing one line of the display moving image data; and the first moving image buffer. A moving image frame memory for temporarily storing the output data of the line buffer for one frame and sequentially outputting the stored display moving image data in units of one line; and a second memory for temporarily storing the output data of the moving image frame memory. A video line buffer,
A first graphics line buffer for temporarily storing one line of the display graphics image data;
A graphics frame memory for temporarily storing output data of the first graphics line buffer for one frame, and sequentially outputting the stored display graphics image data in units of one line; and an output of the graphics frame memory. A second graphics line buffer for temporarily storing data, wherein the data stored in the second moving image line buffer and the data stored in the second graphic line buffer are combined and output to the image display device. An image output device. 18. The image output device according to claim 1, further comprising an operation clock stop control unit that controls to stop an operation clock in the device when the data transfer or the data processing is not performed. An image output device, characterized in that: 19. An image output control method for controlling the output of image data from an image output device to an image display device according to claim 10, wherein, among the image output cycle signals to the image display device, horizontal synchronization Storing the display image data in the line buffer during a period other than the signal blanking period; transferring the display image data from the line buffer to the frame memory during the blanking period of the horizontal synchronization signal; An image output control method, comprising: outputting the display image data from the frame memory to the image display device during a period other than a signal blanking period. 20. An image output control method for controlling the output of image data from an image output device to an image display device according to claim 11, wherein the image output control device controls the horizontal synchronization among the image output cycle signals to the image display device. The display image data is stored in the frame memory during a period other than the signal blanking period, and the display image data is transferred from the frame memory to the line buffer during the horizontal synchronization signal blanking period. An image output control method, wherein the display image data is output from the line buffer to the image display device during a period other than a signal blanking period. 21. An image output control method for controlling the output of image data from an image output device to an image display device according to claim 13, wherein, among the image output cycle signals to the image display device, horizontal synchronization During the period other than the signal blanking period, the display moving image data and the display graphics image data are stored in the moving image line buffer and the graphics line buffer, respectively. Transferring each of the moving image data and the display graphics image data from the moving image line buffer and the graphics line buffer to the moving image frame memory and the graphics frame memory, and a period other than a blanking period of the horizontal synchronization signal; The display moving image data and the display graphics image data And outputting the combined data to the image display device. 22. An image output control method for controlling the output of image data from an image output device to an image display device according to claim 14, wherein: among the image output period signals to the image display device, horizontal synchronization During the period other than the signal blanking period, the display moving image data and the display graphics image data are stored in the moving image frame memory and the graphics frame memory, respectively. Transferring the display moving image data and the display graphics image data from the moving image frame memory and the graphic frame memory to the moving image line buffer and the graphics line buffer, respectively, for a period other than a blanking period of the horizontal synchronization signal; The display moving image data and the display graphics image data And outputting the data to the image display device separately or separately. 23. An image output control method for controlling the output of image data from an image output device to an image display device according to claim 15, wherein: During the period other than the signal blanking period, the display moving image data and the display graphics image data are stored in the moving image frame memory and the graphics frame memory, respectively. The output data of the video frame memory and the output data of the graphics frame memory are combined and transferred to the line buffer, and the data stored in the line buffer is stored in the image display device during a period other than the blanking period of the horizontal synchronization signal. Output to an image output control method. 24. An image output control method for controlling the output of image data from an image output device to an image display device according to claim 16, wherein a horizontal synchronization among the image output cycle signals to the image display device is controlled. The signal blanking period is divided into a first period and a second period. In the first period, each of the data stored in the video line buffer and the data stored in the graphics line buffer is stored in the video frame memory and Transferring to the graphics frame memory, and in the second period, combining output data of the moving picture frame memory and output data of the graphics frame memory and transferring the combined data to the line buffer. Image output control method. 25. An image output control method for controlling the output of image data from an image output device to an image display device according to claim 17, wherein: The signal blanking period is divided into a first period and a second period. In the first period, each of the data stored in the first moving image line buffer and the data stored in the first graphics line buffer is divided. Transferring the data stored in the moving image frame memory and the data stored in the graphics frame memory to the second moving image line buffer during the second period. And transferring to the second graphics line buffer.