JP2002042427A - Reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that control for matching thresholds is complicated, convergence to stably equalize a waveform takes much time and also convergence itself is not obtained since a run length and a PR characteristic desired to be equalized, etc., differ according to the property of a signal to be reproduced in a unit to which a plurality of kinds of signals are inputted in a conventional manner. SOLUTION: Point information to be supplied to a tap delay circuit 23 by a characteristic mode is selected from ether of zero point information and peak point information, the tap delay circuit 23 delays point information from an interpolation DPLL 19, a temporary judgement circuit 24 receives a PR mode signal, an RLL mode signal, plural kinds of point information and a reproduction signal after equalization as an input and, then, a difference value between a temporary judgement value and the reproduction signal after waveform equalization, which are calculated based on state transition fixed by the PR mode signal and the RLL mode signal and on the patterns of plural kinds of point information, is outputted as an error signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus, and more particularly to a reproducing apparatus having a waveform equalizing circuit for waveform equalizing a run-length limited code reproduced from a recording medium such as an optical disk.

[0002]

2. Description of the Related Art In a reproducing apparatus for reproducing a run-length limited code from a recording medium such as an optical disk on which a run-length restricted code is recorded at a high density, a partial response (hereinafter referred to as PR) is required to remove waveform distortion of a reproduced signal. A device using a waveform equalization circuit having equalization characteristics has been conventionally known (Japanese Patent Laid-Open No. 10-106161). FIG. 24 is a block diagram showing an example of the conventional reproducing apparatus. In FIG. 1, a run-length limiting code reproduced from an optical disc 1 by a recording / reproducing system 2 is supplied to a transversal filter 3 where a tap coefficient input from a tap coefficient determiner 6 in a parameter setter 5 is converted to a tap coefficient. Based on this, PR equalization is performed.

An X value selector 10 selects an X value, which is an intersymbol interference value in, for example, PR (1, X, X, 1) equalization in the transversal filter 3 based on characteristics of a reproduced waveform. Then, X is sequentially determined from the determination result of the error rate determination unit 9.
i is obtained, and finally a value of X whose error rate satisfies an allowable value is selected. The equalization target waveform generator 8 stores the binary data supplied from the parameter setting binary data memory 7 and the X value of the intersymbol interference imparting value in PR equalization selected by the X value selector 10. Then, a target waveform after the equalization is created and given to the tap coefficient determiner 6.

[0004] Bits corresponding to the parameter setting binary data memory 7 are recorded on the optical disc 1 in advance. The tap coefficient determiner 6 obtains tap coefficients from the reproduced waveform corresponding to these bits and the equalized target waveform so that the reproduced waveform matches the equalized target waveform, and inputs the coefficients to the transversal filter 3. Discrimination point signal level determiner 11
Calculates the discrimination point signal level based on the value of X given from the X value selector 10 and supplies this to the ML decoder 4. The ML decoder 4 decodes the equalized reproduced waveform extracted from the transversal filter 3 into binary data based on the above-mentioned identification point signal level, and outputs the binary data.

[0005] The decoded data extracted from the ML decoder 4 is supplied to an error rate determiner 9 where it is compared with the parameter setting binary data from the parameter setting binary data memory 7 to determine the error rate. The X-value selector 10 obtains the obtained error rate and determines whether or not the error rate satisfies an allowable value. When the error rate determination unit 9 determines that the error rate satisfies the allowable value, the PR (1, X, X, 1) ML method using the tap coefficient and the discrimination point signal level at that time is used for PR or the like. And maximum likelihood decoding are performed. Conventionally, an optical disc signal reproducing method for performing maximum likelihood detection using a run length limited code whose minimum code inversion interval is limited to a constant equal to or greater than 2 and then performing maximum likelihood detection with the code inversion interval as a constraint condition. A reproducing apparatus that performs ternary equalization only on the amplitude of the points immediately before or after the sign inversion position except for the point corresponding to the data sequence having the minimum sign inversion interval and the amplitude of the sign inversion position. Is also known (JP-A-7-192270).

[0006]

However, the above-mentioned conventional reproducing apparatus can equalize a typical integral characteristic reproduced from an optical disk, but can perform equalization on a signal having a differential characteristic. Cannot be converted to, for example, TPP
(Tangential push-pull) method cannot respond to the signal read. (The pre-embossed signal recorded in the read-only area of a shallow groove rewritable disc, which is extremely strictly readable in principle, can hardly be reproduced by normal reproduction, but the TP
When the data is read out by the P method and Viterbi decoding is performed, a good error rate can be obtained. That is, two types of equalization systems must be prepared, which is a problem in terms of circuit size and cost.

Further, since the PR equalization performed by the reproducing apparatus has a multi-valued target value, a fine threshold comparison is required in the error rate judgment unit 9, and there is a problem that the judgment becomes difficult due to noise or distortion. Therefore, in a device to which a plurality of types of signals are input (for example, a reproducing apparatus such as a CD and a DVD), since the run-length and the PR characteristic to be equalized differ depending on the characteristics of the reproduced signal, the control for adjusting the threshold is complicated. Thus, there is a possibility that the convergence time for performing the waveform equalization stably is long.

[0008] The present invention has been made in view of the above points,
PR for a reproduced signal having the characteristics of an integral system and a differential system
Equalization to the characteristic represented by (a, b, b, a) and PR
(A, b, -b, -a) to achieve equalization to the characteristics shown in FIG.
It is an object of the present invention to provide a reproducing apparatus capable of performing waveform equalization by equalization. Another object of the present invention is to provide a reproducing apparatus capable of realizing expansion of a convergence range and reduction of a convergence time.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention reproduces a run-length limited code recorded on a recording medium and converts the reproduced signal using a transversal filter to a partial response or the like. In the reproducing apparatus for decoding after the conversion, the output signal of the transversal filter is supplied, and based on the output error signal of the temporary discriminating circuit for estimating the equalization target value, the tap coefficient of the transversal filter is reduced to the minimum value. And a coefficient generation means for variably controlling so as to obtain an equality to a characteristic represented by PR (a, b, b, a) by switching an algorithm of the temporary discrimination circuit having a small circuit load; Provided is a reproducing apparatus characterized by achieving equalization to characteristics represented by PR (a, b, -b, -a). Further, in order to solve the above-described problems, the present invention provides a playback device that decodes a playback signal obtained by playing back a run-length limited code recorded on a recording medium after performing partial response equalization using a transversal filter, Zero detection means for outputting, in synchronization with a bit clock, zero-point information indicating whether or not the signal is a zero crossing point from a reproduced signal after waveform equalization input to the transversal filter, and a waveform input to the transversal filter. Peak detection means for outputting peak point information indicating whether or not the signal is a peak from the reproduced signal in synchronization with the bit clock; inputting the zero point information and the peak point information; selecting one of the points; Selecting means for outputting as information, and the point information output from the selecting means A delay circuit that outputs as at least three delay signals delayed by only a period, a plurality of pieces of point information from the delay circuit, and a waveform-equalized reproduction signal output from the transversal filter as inputs, Based on a state transition determined by the type of response equalization and the type of the run-length limiting code of the reproduced signal and the pattern of the plurality of point information, a temporary determination value of the waveform equalization signal is calculated, and the temporary determination value and the waveform A provisional discrimination circuit that outputs a difference value from the equalized reproduction signal as an error signal, and a tap coefficient of the transversal filter is varied based on an output error signal of the provisional discrimination circuit so that the error signal is minimized. A coefficient generating means for controlling, wherein equalization to a characteristic represented by PR (a, b, b, a) and PR (a, b, -b, -a) Possible to achieve both the equalization of the characteristics that are to provide a reproducing apparatus according to claim. In order to solve the above-described problems, the present invention is to reproduce a run-length limited code recorded on a recording medium, a reproduction device that decodes the reproduced signal after partial response equalization using a transversal filter, Zero detection means for outputting, in synchronization with a bit clock, zero-point information indicating whether or not the signal is a zero crossing point from the reproduced signal after waveform equalization output from the transversal filter, a waveform output from the transversal filter, etc. Peak detection means for outputting peak point information indicating whether or not the signal is a peak from the reproduced signal in synchronization with the bit clock; inputting the zero point information and the peak point information; selecting one of the points; Selecting means for outputting as information, and the point information output from the detecting means. A delay circuit that outputs at least three delay signals delayed by a time, a plurality of pieces of point information from the delay circuit, and a waveform-equalized reproduction signal output from the transversal filter as inputs, Based on a state transition determined by the type of response equalization and the type of the run-length limiting code of the reproduced signal and the pattern of the plurality of point information, a temporary determination value of the waveform equalization signal is calculated, and the temporary determination value and the waveform A provisional discrimination circuit that outputs a difference value from the equalized reproduction signal as an error signal, and a tap coefficient of the transversal filter is varied based on an output error signal of the provisional discrimination circuit so that the error signal is minimized. A coefficient generating means for controlling, and equalizing to a characteristic represented by PR (a, b, b, a), and PR (a, b, -b, -a) Possible to achieve both the equalization of the characteristic shown to provide a reproducing apparatus according to claim. In the present invention, a tentative judgment value of a waveform equalized signal is calculated based on a state transition determined by a PR mode signal and an RLL mode signal by a tentative judgment circuit and a plurality of peak point information patterns. Since the difference value from the reproduced signal after the equalization is output as an error signal, an error signal that is an error from the convergence target value is generated and output without depending on the level of the current sampling point. By variably controlling the tap coefficient of the transversal filter based on the signal, it is possible to control the partial response waveform equalization characteristics of the transversal filter so that the error signal becomes zero. Furthermore, in the present invention, PR (a, PR, a) is provided by providing a selection circuit that selects one of them according to a characteristic mode signal indicating the type of the equalization characteristic (integral system / differential system) and outputs it as point information. b, b, a)
And the PR (a, b, -b,-
The equalization to the characteristic shown in a) can be achieved with a small circuit load.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the reproducing apparatus according to the present invention. In the figure, a DC component of a run-length limiting code (digital signal), which is photoelectrically converted and amplified by a PD head amplifier 16 from an optical disc 15 on which a run-length limiting code is recorded at high density, is blocked by a DC blocking circuit 16. AGC circuit 1 through an A / D converter for digital-to-analog conversion (not shown)
7, after automatic gain control (AGC) is performed so that the amplitude becomes constant, resampling / DPLL (digital PL
L) 19. The position where the A / D converter is provided may be any position before the resampling / DPLL 19.

[0011] The resampling / DPLL 19 is a digital P / L converter in which a loop is completed in its own block.
The LL circuit generates digital data obtained by resampling the input signal sampled by the A / D converter at a fixed system clock at a desired bit rate, and automatically generates a digital data to be described later which constitutes a main part of the present embodiment. It is supplied to the equalization circuit 20. Here, resampling refers to obtaining sampling data at the timing of the bit clock by performing a thinning-out interpolation operation from data that has been A / D converted at the timing of the system clock. In addition, the resampling / DPLL 19 performs a phase pull-in operation in accordance with an integral or differential signal in accordance with the input characteristic mode signal. For the signal of the integration system, the zero cross of the resampling data is detected, and the obtained point information is supplied to the automatic equalization circuit 20. Further, the peak of the resampling data is detected for the signal of the differential system, and the obtained point information is supplied to the automatic equalization circuit 20.

When the signal of the integration system is input, the point information indicates a point at which the bit sampling data crosses the zero level in bit clock units. Further, the resampling / DPLL 19 outputs the phase 1 corresponding to the zero cross point indicated by the point information.
Based on the value of the resampling data at 80 °, the resampling timing, that is, the frequency and the phase are locked so that it becomes zero.

When a differential signal is input, the point information indicates a positive or negative peak level in bit sampling data in bit clock units. Further, the resampling / DPLL 19 performs resampling based on the value of the resampling data corresponding to the peak indicated by the peak point information so that it becomes maximum at the bit sampling position (minimum in the negative direction). , That is, the frequency and phase are locked. The automatic equalization circuit 20 selects a characteristic to be equalized according to the characteristic mode signal, and performs a target PR equalization.

The reproduced waveform after the equalization, to which the PR characteristic has been added by the automatic equalization circuit 20, is supplied to a decoding circuit 38, and is subjected to, for example, Viterbi decoding. The circuit configuration of this Viterbi decoding is known. For example, a branch metric operation circuit that calculates a branch metric from a sample value of a reproduced waveform after equalization, and a path metric is calculated by cumulatively adding the branch metric every clock. It comprises a path metric calculation circuit and a path memory for storing a signal for selecting the most probable data sequence with the smallest path metric. The path memory stores a plurality of candidate sequences, and outputs a candidate sequence selected according to a selection signal from the path metric operation circuit as a decoded data sequence. Since the state transition determined from the signal and the equalization characteristic changes according to the characteristic mode signal, the Viterbi decoding also switches the processing accordingly and performs appropriate decoding.

The ECC circuit 39 uses the error correction code in the decoded data sequence from the decoding circuit 38 to correct a code error of a generation element of the error correction code. Is output. In the above configuration, the present embodiment is characterized by the configuration of the automatic equalization circuit 20. Hereinafter, the automatic equalization circuit 20 will be described in further detail.

FIG. 2 is a block diagram showing a first embodiment of an automatic equalizing circuit as a main part of the apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 2, the automatic equalization circuit 20a of the first embodiment of FIG. 2 corresponding to the automatic equalization circuit 20 of FIG.
P for resampling data from DPLL 19
Transversal filter 21 providing R equalization characteristics
And a multiplier / low-pass filter (LPF) that varies the coefficient of the transversal filter 21 according to an error signal.
22, a tap delay circuit 23 for delaying point information from the resampling / DPLL 19, and a provisional decision circuit 24 for generating the error signal based on an output signal of the transversal filter 21 and a delay signal from the tap delay circuit 23. And a multiplier L
And an inverter (INV) 25 to be supplied to the PF 22. For example, the tap delay circuit 23 sets a plurality of predetermined delay times, and is configured to output three or more delay signals from different taps.

The resampling / DPLL 19 is supplied with a characteristic mode signal which is a main part of the present embodiment. According to the characteristics (integral system / differential system) of the input signal, the object whose phase is to be locked is: The input signal is switched to zero crossing when the signal is an integral signal, and is switched to a peak when the signal is a differential signal. In addition, point information (0 point information when the signal is an integral signal, peak point information when the signal is a differential signal) is output. .

Similarly, the characteristic mode signal is input to the tentative determination circuit 24, and the tentative determination algorithm is switched according to the characteristics (integration system / differential system) of the input signal. The above-described tap delay circuit 23 and temporary determination circuit 24
Is a circuit part which is another essential part of this embodiment, and has a circuit configuration as shown in FIG. 3, for example. In the figure, a waveform equalized reproduction signal from the transversal filter 21 is input to a temporary discriminator 51 via a terminal 41. The temporary discriminator 51, the subtractor 52, and the D-type flip-flop 53 constitute the above-described provisional discriminant circuit 24. The temporary discriminator 51 receives data from the transversal filter 21 input via the terminal 41, output data of the tap delay circuit 23, a PR mode signal input via the terminal 43, , And the characteristic mode signal input via the terminal 47.

The temporary discriminator 51 is constituted by a logic circuit, and performs a temporary discriminating operation using a property of a partial response characteristic skillfully in accordance with an algorithm described later, based on an input signal. The subtracter 52 generates an error signal by subtracting the tentative judgment result from the tentative discriminator 51 from the input data D3 from the terminal 41. The D-type flip-flop 53 synchronizes the error signal from the subtractor 52 input to the data input terminal with the master clock from the terminal 45 input to the clock terminal, and outputs the error signal when the bit clock is at a high level. Latched from the Q output terminal via the terminal 54 and the INV 25 of FIG.
Output to PF22.

A bit clock is input to each enable terminal (not shown) of the D-type flip-flop 47 or the D-type flip-flop in the tap delay circuit 23 via a terminal 40. , A system clock is input via a terminal 45, and a reset signal is input via a terminal 46 to each clear terminal. As described above, since both the tap delay circuit 23 and the provisional determination circuit 24 are constituted by digital circuits, they are not affected by the aging and parameter variation peculiar to analog, have high reliability, and have a large circuit scale. This is a configuration that hardly increases.

Here, the partial response (PR) characteristic of the integration system will be described. For example, PR (a,
When the characteristics of (b, b, a) are added to the solitary wave shown in FIG. 4A and equalized, the equalized waveform becomes as shown in FIG. 4B as is well known. Further, for a continuous wave, this equalized waveform is 0, a, a + b, 2a, 2b, a + 2b,
Takes 7 values of 2a + 2b. When these seven values are input to the Viterbi decoder, the original data (input value) and the reproduced signal after PR equalization (output value) are constrained by the past signal, and are input by this and (1,7) RLL. It is known that the use of the fact that the signal "1" does not continue more than twice can be represented by a state transition diagram as shown in FIG.

In FIG. 4C, S0 to S5 indicate states determined by the immediately preceding output values. From this state transition diagram, for example, when in the state S2, when the input value is a + 2b, the output value becomes 1 and the state transits to the state S3. When the input value is 2b, the output value becomes 1 and the state transits to the state S4. However, it can be seen that no other input value is input, and that if it is, it is an error.

FIG. 4D shows a state transition diagram when the run-length limit of the input signal is (2, X).
It can be seen that there is no transition from S1 to S1 and from S2 to S4.

Next, the partial response (P
To explain the R) characteristic, for example, PR (a, b,-
When the characteristics of (b, -a) are added to the solitary wave shown in FIG. 5A and equalized, the equalized waveform becomes as shown in FIG. 5B as is well known. Further, in a continuous wave, this equalized waveform takes five values of-(a + b), -a, 0, a, a + b. When these five values are input to the Viterbi decoder, the original data (input value) and the reproduced signal after PR equalization (output value) are
By utilizing the fact that the past signal is restricted and the input signal "1" does not continue more than twice by this and (1, X) RLL, it can be represented by a state transition diagram as shown in FIG. It is known that it can be done.

In FIG. 5C, S0 to S5 indicate states determined by the immediately preceding output values. From this state transition diagram, for example, when in the state S2, when the input value is a + 2b, the output value becomes 1 and the state transits to the state S3. When the input value is 2b, the output value becomes 1 and the state transits to the state S4. However, it can be seen that no other input value is input, and that if it is, it is an error.

FIG. 5D shows a state transition diagram when the run length limit of the signal is (2, X).
It can be seen that there is no transition from S1 to S1 and from S2 to S4.

FIG. 6 shows the PR (a, b, b,
FIG. 7A is a diagram illustrating a relationship between the characteristic of FIG. 7A, a run-length restriction rule RLL mode, and a tentative determination value output from a tentative classifier 51.
In the figure, the PR mode in the top row indicates the value of the signal input to the provisional determination circuit 24 via the terminal 43, and the RLL mode in the leftmost column indicates the value via the terminal 44. The signal input to the temporary discriminator 51 of the temporary discriminating circuit 24 is shown, and here, RLL (1, X) and RLL (2, X) are shown.

PR mode values are PR (1, 1), PR (1, 1, 1, 1), PR
(1, 2, 2, 1), PR (1, 3, 3, 1), PR
(2, 3, 3, 2) or PR (3, 4, 4, 3). RLL (1, X) indicates a run length restriction rule of a predetermined value X whose minimum inversion interval is “2” and whose maximum inversion interval differs depending on the modulation method.
(2, X) indicates a run length restriction rule of a predetermined value X in which the minimum inversion interval is "3" and the maximum inversion interval differs depending on the modulation method.

As described with reference to FIG. 4, in the case of RLL (1, X), the equalized waveform is 0, a, a + b, 2a, 2b, a + 2b, 2a + 2b in PR (a, b, b, a).
FIG. 5 shows the provisional determination values in the respective partial response characteristics corresponding to these seven values. Among the tentative determination values, the value on the right side of the arrow indicates a value when the median value of the seven values, “a + b”, is offset to “0”. RLL (2, X) indicates the same tentative judgment value as RLL (1, X), but there are no values in two rows indicated by 2a and 2b of RLL (1, X). This is because there is no transition of S5 → S1, S2 → S4 in the state transition diagram of FIG. 4C (because values 2a and 2b are not taken).

In FIG. 6, PR (1,1) is P
This is the case where a = 0 and b = 1 in R (a, b, b, a).
Further, in FIG. 6, a gain G is a multiplication coefficient for normalizing the maximum value (a + b) * of the absolute value after offset, and is represented by A / (a + b) * (where A is an arbitrary level). ).

FIG. 7 shows the PR (a, b,-) of the above differential system.
FIG. 7 is a diagram showing a relationship between the characteristics of (b, −a) and the tentative judgment value output from the tentative classifier 51. In the figure, P in the top row
The R mode indicates the value of the signal input to the temporary discriminating circuit 24 via the terminal 43, and the RLL mode in the leftmost column indicates to the temporary discriminator 51 of the temporary discriminating circuit 24 via the terminal 44. This shows an input signal.

The PR mode value is such that the partial response characteristics are PR (1, -1), PR (1, 1, -1, -1),
PR (1,2, -2, -1), PR (1,3, -3,-
1), PR (2, 3, -3, -2) and PR (3, 4,
-4, -3). Especially PR (1,
-1) is a well-known PR4 (PartialRe
sponse Class IV) and PR (1, 1,
-1, -1) is a well-known EPR4 (Exten
ded Partial ResponseClass
IV).

In FIG. 7, PR (1, -1) is the case where a = 0 and b = 1 in PR (a, b, -b, -a). Further, in FIG. 5, the gain G is a multiplication coefficient for normalizing the maximum value (a + b) of the absolute value, and A / A
(A + b) (where A is an arbitrary level).

Next, returning to FIG. 3, the operation of the circuit shown in FIG. 3 will be described. The waveform equalized reproduction signal from the transversal filter 21 input through the terminal 41 is the signal D3 at the current time. Is treated as On the other hand, the peak point information from the resampling / DPLL 19 is supplied to the tap delay circuit 23 via the terminal 42, and the tap delay output is input to the temporary discriminator 51.
The provisional discriminator 51 performs provisional discrimination based on partial response equalization according to an algorithm described later (convergence target setting).
I do.

The subtractor 52 calculates an error signal by subtracting the discrimination result obtained by the provisional discriminator 51 from the current time signal D3 from the terminal 41, latches the error signal by a D-type flip-flop 53, and outputs the error signal. FIG. 2 through terminal 54
After the polarity is inverted by the inverter 25, the multiplier / LPF
22. The error signal whose polarity has been inverted by the inverter 25 is multiplied by the tap output from the transversal filter 21 by the multiplier / LPF 22, after which the high frequency components are removed, and then the tap is set so that the error signal becomes 0. It is output to the transversal filter 21 as a coefficient (filter coefficient).

Next, the operation of the integrating system temporary discriminator 51 will be described in more detail with reference to the flowchart of FIG. Here, when the value Z of the zero point information is "1", it indicates a zero cross point, which is shown in FIG.
In the state transition diagram of PR (a, b, b, a) shown in (C), it is represented by a value “a + b”, and the state S1 → S
2 or during the transition from state S4 to S5.

In this case, the state S in the right half in FIG.
2, S3 and S4 are paths having positive values (a + 2b, 2a as described with reference to FIG. 5 when normalized to a + b = 0).
+ 2b, 2b), and the left half state S5,
S0 and S1 refer to values before or after the zero crossing point to follow a path of negative value (when normalized to a + b = 0, either 0, a, or 2a as described with reference to FIG. 5). By doing so, it is possible to determine whether the route is a positive route or a negative route.

Moreover, if the interval from a certain zero cross point to the next zero cross point is known, that is, from the state S2 to the state S5, or from the state S5 to the state S5
If the number of transitions up to 2 is known, the path is determined, and possible values become clear for each sample point.

When the value other than "a + b" is not a zero cross point in the above state transition diagram, the value Z of the zero point information is "0". From this state transition diagram, two zero cross points (Z = 1) are not taken out in succession, and in the case of RLL (1, X), at least one zero cross point is present between adjacent Z = 1. 0 "exists (when the value Z of the 0 point information changes from 1 → 0 → 1,
That is, state S2 → S4 → S5 or state S5 →
When the transition is made from S1 to S2). Note that RLL (2, X)
In the case of, there are at least two “0” s between adjacent Z = 1. This is because the values of 2a and 2b do not exist.

In an actual signal, due to the influence of noise and the like,
It is fully expected that the zero cross point itself will be erroneously detected, but in the case of feedback control, if the probability of making a correct decision exceeds the probability of making a mistake, it should converge in the correct direction. For the integration process,
It is considered that a single noise is not a problem in practical use.

Focusing on the above points, the provisional discriminator 51 first identifies the value Z of the point information input at each bit clock cycle via the terminal 42 and the tap delay circuit 23, Whether the five values of the cycle are all “0” (step 61 in FIG. 8), whether only the last value of the five values is “1” (step 62 in FIG. 8), Whether only the first of the five values is "1" (step 63 in FIG. 8), the first and last values of the above five values are "1" and the remaining three values are "0". Is determined (step 64 in FIG. 6).

In these patterns, when the central value of the value Z of the point information of interest is "0", the values Z of the 0 point information on both front and rear sides are both "0". Is the case where the signal waveform is stuck on the positive side or the negative side. Therefore, when any of these patterns is satisfied, the large value P is obtained by the equation P = (a + b) * × G (1) Is calculated (step 65 in FIG. 8). In the expression (1) and the expressions (2) and (3) described later, G is the gain shown in FIG. 6, and a * and b * are PR (a,
b, b, a), the values of a and b are calculated as the median (a + b)
Is a value after offset so that it becomes 0. These values of a *, b * and G are known values obtained from the PR mode signal input via the terminal 43 and the RLL mode signal input via the terminal 44.

When none of the above patterns is used,
Five zero point information values Z for five consecutive clock cycles
Is "01010" (step 66 in FIG. 8). In this pattern, it is determined based on the RLL mode signal whether or not RLL (1, X) partial response equalization is performed (FIG. 6). Step 67). In this pattern, the value Z of the zero point information of the median of interest is set to “0”.
Is the case where the two values of Z adjacent on both sides before and after the median are both “1”, which is, as described above,
Since it may occur only in the case of RLL (1, X), when RLL (1, X), the value P is calculated by the equation P = (ba) * × G (2) ( Step 6 in FIG.
8). In this case, since the polarity instantaneously changes at the second clock, a small value P is calculated by the equation (2).

When the values Z of the five point information in the successive five clock cycles are not "01010", the values Z of the five point information are "01001" and "1001".
It is determined whether the pattern is any one of “0”, “00010” and “01000” (Step 6 in FIG. 8).
9-72). These four patterns are obtained when the median of the five consecutive zero-point information does not indicate the zero-crossing point and one of the two pieces of point information adjacent before and after the median indicates the zero-crossing point. is there.

When any of the above four patterns is selected, or in step 67, the RLL mode is set to (1, X)
If not, the value P is calculated by the equation P = b * × G (3) (step 7 in FIG. 6).
3). In this case, since the signal waveform has the same polarity for a short period of time, the value P of the intermediate level between the equations (1) and (2) is calculated by the equation (3).

When the value P is calculated in any of the steps 65, 68 and 73, the waveform equalization signal D3 at the current time taken out from the D-type flip-flop 47 is set to 0.
It is determined whether or not this is the case (step 74 in FIG. 8).
When the waveform equalization signal D3 at the current time is 0 or more, the final provisional judgment level Q is set to the value of P (step 75 in FIG. 8),
When the value is negative, the final provisional judgment level Q is set to a value of -P (step 76 in FIG. 8).

In step 72, the value Z of the point information
Is not "01000", the final provisional judgment level Q is set to "0" (step 77 in FIG. 8). For example, a case where the median of five consecutive points Z is "1" corresponds to this case.

The tentative judgment level Q obtained by the above tentative judgment processing is supplied to the subtractor 52 in FIG. 3 and is subtracted from the waveform equalization signal D3 at the current time to obtain an error signal.
As described above, after being latched by the D-type flip-flop 53, the output terminal 54 and the INV 25 of FIG.
, And after multiplication, the high-frequency component is removed, and the result is output to the transversal filter 21 as a tap coefficient. In this way, the error signal extracted from the subtractor 52 in FIG.
By variably controlling the tap coefficient of the transversal filter 21 such that the following equation is satisfied, the waveform equalization by the transversal filter 21 can be suitably performed by expanding the convergence range.

Next, the operation of the temporary discriminator 51 in the differential system will be described in more detail with reference to the flowchart of FIG. Here, for the sake of simplicity, a case where the signal run-length limit is (2, X) will be described. Here, when the value PK of the above point information is “1”, it indicates a peak, which corresponds to the PR shown in FIG.
In the state transition diagram of (a, b, -b, -a), it is represented by the value "a + b" or "-(a + b)", and the state S
It occurs during the transition from 1 → S2 or state S4 → S5.

In this case, in FIG. 5C, the polarity of the peak can be determined by the polarity of the sample point. Moreover, if the interval from one peak to the next peak is known, that is, the state S
2 to state S5, or from state S5 to state S2
If the number of transitions up to is known, the path is determined, and possible values become clear for each sample point.

In the above state transition diagram, when the value is not a value other than "a + b" or "-(a + b)", that is, when it is not a peak, the value PK of the point information is "0". From this state transition diagram, two consecutive peaks (PK = 1) are not taken out, and in the case of (2, X), the adjacent P
There are at least two "0" s between K = 1.

In an actual signal, due to the influence of noise and the like,
It is fully expected that the peak itself will be erroneously detected, but in the case of feedback control, if the probability of making a correct decision exceeds the probability of making a mistake, it should converge in the correct direction. Due to the processing, the single noise is considered to be practically acceptable.

Focusing on the above points, the provisional discriminator 51 first identifies the value PK of the point information input at each cycle of the bit clock via the terminal 42 and the tap delay circuit 23, and Whether the five values of the cycle are all “0” (step 61 in FIG. 9), whether only the last value of the five values is “1” (step 62 in FIG. 9), Whether only the first of the five values is "1" (step 63 in FIG. 9), the first and last values of the above five values are "1" and the remaining three values are "0". Is determined (step 64 in FIG. 9).

In these patterns, when the center value of the point value PK of the point information of interest is “0”, the values PK of the point information on both front and rear sides are both “0”.
In this case, since the signal waveform is stuck to the signal waveform 0, when any of these patterns is satisfied, the tentative discrimination value Q is calculated by the equation Q = 0 (1) (step 65 in FIG. 9). ).

When none of the above patterns is used,
The values PK of the five peak point information in five consecutive clock cycles are “01010”, “01001”, and “1001”.
It is determined whether the pattern is any one of “0”, “00010” and “01000” (Step 6 in FIG. 9).
6, 69-72). These four patterns are obtained when the median value of the five consecutive peak point information does not indicate a peak point, and any of two adjacent point information before and after the median value indicates the peak point. It is.

If any of the above five patterns, the value P is calculated by the following equation: P = a × G (2) (step 7 in FIG. 9).
3). Here, in the expression (2) and the expression (3) described later, G indicates the gain shown in FIG. 7, and a and b indicate the values of a and b in PR (a, b, b, a). These values of a, b and G are:
A PR mode signal input through a terminal 43;
Is a known value obtained from the RLL mode signal input through

In step 72, the value P of the point information
If K is determined to be other than the above, the value P is calculated by the equation P = (a + b) × G (2) (step 7 in FIG. 9).
7). For example, the median value of five consecutive peak PKs is "
The case of "1" corresponds to this case.

When the value P is calculated in either of the above steps 73 and 77, it is then determined whether or not the waveform equalization signal D3 at the current time extracted from the D-type flip-flop 47 is 0 or more (FIG. 9). Step 74). When the waveform equalization signal D3 at the current time is 0 or more, the final provisional judgment level Q is set to the value of P (step 75 in FIG. 9), and when negative, the final provisional judgment level Q is set to the value of -P. (Step 76 in FIG. 9)

The tentative judgment level Q obtained by the above-described tentative judgment processing is supplied to the subtractor 52 shown in FIG.
As described above, after being latched by the D-type flip-flop 53, the output terminal 54 and the INV 25 of FIG.
, And after multiplication, the high-frequency component is removed, and the result is output to the transversal filter 21 as a tap coefficient. In this way, the error signal extracted from the subtractor 52 in FIG.
By variably controlling the tap coefficient of the transversal filter 21 such that the following equation is satisfied, the waveform equalization by the transversal filter 21 can be suitably performed by expanding the convergence range.

Next, the waveform equalization of the integral system by the above-described provisional determination processing will be described more specifically. For example, FIG.
The reproduced signal after the equalization of the waveform shown by the solid line in FIG.
4, the zero point information of the value Z as shown in the lower part of the waveform of FIG. Here, in FIG. 10A, the circles indicate the original data points of the run-length limited code recorded on the recording medium. In addition, crosses indicate sample points for equalization when partial response equalization is performed by the transversal filter 21, which is shifted from the original data point by 180 ° (see FIGS. 10B to 10D). , FIG. 11 and FIG. 12).

In FIG. 10A, five consecutive 0s
When the value Z of the point information is all "0" and "10000"
10 and “00001” are equalized based on the above equation (1) (steps 61 to 63 and 65 in FIG. 8), and FIG.
As shown in (B), the reproduced signal is obtained with the same waveform as the original. Note that the waveform equalization based on the calculation results of the above equations (1) to (3) is based on the value Z of five consecutive 0-point information.
As shown in FIG. 8, the operation is performed at the third timing according to the polarity of the waveform equalization signal D3.

FIG. 10C shows a resampling / DPLL.
19 shows an example of the output-equalized reproduction signal waveform of the transversal filter 21 when the value Z of five consecutive 0-point information extracted from No. 19 is "10001". In this case, since the value of the waveform equalization signal D3 at the third timing of the value Z of the five consecutive 0-point information is positive, the waveform equalization is performed by the equation (1) at this time (see FIG. 8). Steps 64, 65, 74, and 75), and the equalized reproduced signal shown in FIG. 10D is obtained from the transversal filter 21.

FIG. 11A shows a resampling / DPLL.
When the value Z of five consecutive 0-point information extracted from No. 19 is “01010” and RLL (1, X), the value Z of five consecutive 0-point information is “01”.
11 shows an example of a reproduced signal waveform after output equalization of the transversal filter 21 when the value is "001". In this case, the value of the waveform equalized signal D3 when the five consecutive zero-point information values Z are "01010" Is positive, the waveform equalization of the positive value by the equation (2) is performed (steps 66 to 6 in FIG. 8).
8, 74, 75) and the value of the waveform equalization signal D3 at the time of "01001" is negative, so that the waveform equalization of a negative value is performed by the equation (3) (steps 69, 73, FIG. 74, 7
6), the equalized reproduction signal shown in FIG. 11B is obtained from the transversal filter 21.

FIG. 12A shows a resampling / DPLL.
Output equalization of the transversal filter 21 when the value Z of the five consecutive 0-point information extracted from 19 is "01000" and when the value Z of the five consecutive 0-point information is "00010" An example of a post-reproduction signal waveform is shown. In this case, the value of the waveform equalization signal D3 is positive when the five consecutive zero point information values Z are "01000" and "00010". (Steps 71, 73 to 7 in FIG. 8)
5, or steps 72 to 75), and the equalized reproduction signal shown in FIG. 12B is obtained from the transversal filter 21.

FIG. 12C shows the resampling and D
Output equalization of the transversal filter 21 when the value Z of five consecutive 0-point information extracted from the PLL 19 is "01001" and when the value Z of five consecutive 0-point information is "10010" An example of a post-reproduction signal waveform is shown. In this case, when the value Z of the five consecutive 0-point information is "01001" or "10010", the value of the waveform equalization signal D3 is positive. (Steps 69 and 7 in FIG. 8)
3 to 75, or steps 70, 73 to 75), FIG.
The post-equalization reproduction signal shown in (D) is obtained from the transversal filter 21.

As described above, in the present embodiment, the value Z of the zero point information is referred to and equalized to the value determined as the self from the state transition diagram, so that it does not depend on the level of the current sample point. Accurate waveform equalization (which is not affected even if it is close to other target values) can be performed. In addition, it is possible to cope with different partial response equalizations, and furthermore, the probability of erroneous determination is smaller than that of a conventional device having a fixed threshold, so that the convergence time can be shortened. In this embodiment, the RLL
The same can be applied to (2, X). This is because, as described with reference to FIG. 6, a state transition substantially similar to that of RLL (1, X) is performed.

Next, the waveform equalization by the above-described provisional discrimination processing of the differential system will be described more specifically. For example, FIG.
3 (A), the reproduced signal after the equalization of the waveform shown by the solid line is taken out from the transversal filter 21 and
4, the peak point information of the value PK as shown in the lower part of the waveform of FIG.
Here, in FIG. 13 (A), circles indicate sample points for equalization when partial response equalization is performed by the transversal filter 21 (see FIG. 13).
(B) and FIGS. 14 and 15).

In FIG. 13A, when the values PK of the five consecutive peak point information are all “0” and “10”
000 "and" 00001 "are equalized based on the above equation (1) (steps 61 to 63, 6 in FIG. 9).
5) When the PK is "01000" and when the PK is "00010", equalization is performed based on the above equation (2) (step 7 in FIG. 9).
1 to 72, 73, 74, and 75), and when PK is "00100", equalization is performed based on the above equation (3) (steps 77, 74, and 75 in FIG. 9), and as shown in FIG. In addition, a reproduced signal is obtained with the same waveform as the original. The waveform equalization based on the calculation results of the above equations (1) to (3) is performed at the third timing of the value PK of the five consecutive peak point information according to the polarity of the waveform equalization signal D3. What is done is as shown in FIG.

In FIG. 14A, the values of five consecutive peak point information are resampling and DPLL1.
9 shows an example of a reproduced signal waveform after output equalization of the transversal filter 21 when the value PK of five consecutive peak point information extracted from No. 9 is “10001”. In this case, the value PK of five consecutive zero point information
Since the value of the waveform equalization signal D3 at the third timing is positive, at this time, the waveform equalization by the equation (1) is performed (steps 64 and 65 in FIG. 9), and shown in FIG. 14B. The reproduced signal after the equalization is obtained from the transversal filter 21.

FIG. 15A shows the resampling and D
When the value PK of the five consecutive peak point information extracted from the PLL 19 is “01001”, the value PK of the five consecutive zero peak point information is “10010”.
4 shows an example of a reproduced signal waveform after output equalization of the transversal filter 21 when. In this case, the values PK of five consecutive 0 point information are “01001”, “1001”.
Since the value of the waveform equalization signal D3 is positive when the value is "0", the waveform equalization of a positive value is performed by the equation (3) (FIG. 9).
Steps 69, 73-75, or steps 70, 73
74, 76) and the equalized reproduced signal shown in FIG. 15B are obtained from the transversal filter 21.

As described above, in this embodiment, the value PK of the peak point information is referred to and equalized to the value determined as the self from the state transition diagram, so that it does not depend on the level of the current sample point. Accurate waveform equalization (which is not affected even if it is close to other target values) can be performed. In addition, since it is possible to cope with different partial response equalizations, and the probability of erroneous determination is smaller than that of a conventional device having a fixed threshold,
The convergence time can be shortened. In this embodiment, R
The same can be applied to LL (1, X). This is because, as described with reference to FIG. 7, a state transition substantially similar to that of RLL (2, X) is performed.

FIG. 16 shows an example of an eye pattern of an output signal of the decoding circuit of the reproducing apparatus. In the figure, the vertical axis indicates the quantization level, and the horizontal axis indicates time. In the example shown in FIG. 16A, the value of the PR mode signal is “6”, that is, PR (3,
4,4,3) and in the example of RLL (2, X), 2a
It can be seen that the values + 2b, a + 2b, a + b, a and 0 converge in a short time. The example shown in FIG.
When the value of the mode signal is “1”, that is, PR (1, 1),
And RLL (2, X), where a + 2b, a +
It can be seen that the values b and a converge in a short time.

FIG. 17 shows an example of an eye pattern of an output signal with respect to an input signal of a differentiation system of the reproducing apparatus. In the figure, the vertical axis indicates the quantization level, and the horizontal axis indicates time. Figure 1
In the example shown in FIG. 6, the value of the PR mode signal is "2", that is, P
R (1,1, -1, -1) and RLL (2, X)
In the example, it can be seen that the values converge to the values of a + b, a, 0, -a, and-(a + b) in a short time.

Next, another embodiment of the present invention will be described. FIG. 18 shows a block diagram of a second embodiment of the automatic equalization circuit of the main part of the device of the present invention. 2, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted.
As shown in FIG. 18, the automatic equalization circuit 20b of the second embodiment corresponding to the automatic equalization circuit 20 of FIG. 1 has a PR equalization characteristic with respect to the resampling data from the resampling / DPLL 19a. A transversal filter 21 to be applied, a multiplier / low-pass filter (LPF) 22 that varies the coefficient of the transversal filter 21 according to an error signal, a tap delay circuit 23, an output signal of the transversal filter 21, and a tap. A provisional determination circuit 24 that generates the error signal based on the delay signal from the delay circuit 23 and supplies the error signal to the multiplier / LPF 22; and a peak detector that detects a peak of the resampling data and outputs peak point information. 100 and 0 point information output by the resampling / DPLL 19a (not the point information) Receiving the peak point information,
It comprises a point selection circuit 101 which selects one of them according to the input characteristic mode, outputs point information, and supplies it to the tap delay circuit 23.

When, for example, the polarity of the reproduced signal after input equalization is inverted, the peak detector 100 supplies, to the point selection circuit 23, the one closer to 0 out of the two neighboring sample points as peak point information. . As a result, this embodiment performs the same operation as the embodiment in FIG.

By the way, resampling / DPLL1
9 and 19a are provided with an AGC circuit or an ATC circuit on the input side, and the automatic equalization circuit 20 (20) on the output side.
a, 20b) are provided. However, since the loop is completed by itself, reliable convergence can be expected. Further, since no external circuit is required, the configuration is simple. Therefore, there is an advantage that the reliability is high. However, the present invention is not limited to this, and can be applied to a configuration that does not use a resampling / DPLL as in the following embodiments.

Next, a third embodiment of the present invention will be described. FIG. 19 shows a block diagram of a third embodiment of the automatic equalization circuit of the main part of the apparatus of the present invention. 2, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. As shown in FIG. 11, the automatic equalization circuit 20b of the second embodiment corresponding to the automatic equalization circuit 20 of FIG. 1 has a PR equalization characteristic with respect to the resampling data from the resampling / DPLL 19a. A transversal filter 21 to be applied, a multiplier / low-pass filter (LPF) 22 that varies the coefficient of the transversal filter 21 according to an error signal, a tap delay circuit 23, an output signal of the transversal filter 21, and a tap. Delay circuit 23
A temporary discriminating circuit 24 that generates the error signal based on the delay signal from the first and second signals and supplies the error signal to the multiplier / LPF 22;
3, a peak detector 102 for detecting a peak point of the output signal of the transversal filter 21 and supplying peak point information to a point selection circuit 103, and the zero detector 26 according to the characteristic mode. A point selection circuit 103 selects one of the point information and the peak point and supplies it to the tap delay circuit 23 as the point information. The characteristic mode is
It is also input to the temporary determination circuit 24, and switches the temporary determination algorithm.

For example, when the polarity of the reproduced signal after the input equalization is inverted, the zero detector 26 supplies, to the point selection circuit 23, the point closer to 0 among the two neighboring sample points as 0 point information. . As a result, this embodiment performs the same operation as the embodiment in FIG.

FIG. 20 is a block diagram showing a fourth embodiment of the automatic equalizing circuit as a main part of the apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 20, the automatic equalization circuit 20c of the third embodiment corresponding to the automatic equalization circuit 20 of FIG. 1 performs A / D conversion on a reproduced signal instead of a signal from the resampling / DPLL 19. And automatic gain control, and further receives a signal subjected to DC control (ATC control) as an input signal,
The zero-crossing detection / peak detection / phase comparator 31 to which the reproduction signal after the equalization of the transversal filter 21 is input, converts the point information corresponding to the zero point information or the peak point information into a tap delay circuit according to the characteristic mode signal. 23 is supplied.

The peak detection / phase comparator 31 performs zero-cross detection or peak detection on the reproduced signal after equalization of the transversal filter 21, and detects the phase of the detected zero-cross point or detected peak point and the phase from the voltage-controlled oscillator (VCO) 33. A phase error signal is generated by comparing the phase of the bit clock with the phase of the bit clock. This phase error signal is supplied to the loop filter 32
The control voltage is applied as a control voltage to a voltage controlled oscillator (VCO) 33 through the controller, and the output system clock frequency is variably controlled. The system clock of the VCO 33 includes the above-described bit clock, and is applied to each block that requires the device clock.

The loop filter 32 and the VCO 33 can be constituted by digital or analog. In the case of analog, an interface for performing D / A conversion is required.
This embodiment also has the same features as the above embodiments.

FIG. 21 is a block diagram showing a fifth embodiment of the automatic equalizing circuit as a main part of the apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 21, the automatic equalization circuit 20d of the fifth embodiment corresponding to the automatic equalization circuit 20 of FIG. 1 is not a signal from the resampling / DPLL 19, but is pre-equalized as necessary. A digital signal obtained by A / D conversion of the reproduced signal by the A / D converter 34 is input to the zero detector 27 and the peak detector 104 together with the transversal filter 21, and according to the characteristic mode signal, the zero detector It is characterized in that any one of the 0 point information output from 27 and the peak point information output from the peak detector 104 is selected and supplied to the tap delay circuit 23 as point information.

The input reproduction signal of the A / D converter 34 is supplied to a phase comparator 35, where the phase of the peak point is compared with the phase of the bit clock from the voltage controlled oscillator (VCO) 37 to obtain a phase error. After being converted into a signal, it is applied as a control voltage to a voltage controlled oscillator (VCO) 37 through a loop filter 36 to variably control the output system clock frequency. The loop filter 36 and the VCO 37 can be configured by digital or analog. In the case of analog, an interface for performing D / A conversion is required. The system clock of the VCO 37 includes the above-described bit clock, and is applied to each block that requires the device clock. Delay adjustment is performed as needed.

On the other hand, the peak detector 104 supplies the immediately preceding timing to the tap delay circuit 23 as peak point information, for example, when the polarity of the gradient (differential) of the signal is inverted. This embodiment also has the same features as the above embodiments.

In the above embodiment, the provisional classifier 5
As described with reference to the flowcharts of FIGS. 8 and 9, 1 is based on the value Z or PK of five consecutive pieces of point information input at each bit clock cycle via the terminal 42 and the tap delay circuit 23. Although the provisional determination result is obtained, the provisional determination result may be obtained based on the values PK of three consecutive peak point information. FIG. 22 and FIG.
3 shows a flowchart in this case. Here, the description of the operation is omitted.

The present invention is not limited to the above embodiment. For example, the provisional decision circuit 24 generates an error signal by making both the PR mode signal and the RLL mode signal variable. One or both may be fixed to generate an error signal.

The INV 25 is inserted for the purpose of providing negative feedback (negative feedback) when updating the coefficient of the transversal filter 21, and there are many other methods for achieving the purpose. The typical method is as follows. The tap output of the transversal filter 21 is inverted by INV.
The output of the multiplier / LPF 22 is inverted by INV. The polarity of the main signal inside the transversal filter 21 is changed to make the same. The polarity inversion is performed in any of the blocks in the lube. At this time, it is needless to say that the polarity of D3 and the polarity of the error output used in the flowcharts shown in FIGS.

[0088]

As described above, according to the present invention,
By switching the characteristic mode, it is possible to respond to both signals having the characteristics of the integral system and the differential system without increasing the circuit scale, and to make the state transition of the peak sample without depending on the level of the current sample point. By generating and outputting an error signal that is an error from the convergence target value determined from, the tap coefficient of the transversal filter is variably controlled based on the error signal, so that the error deviating from the partial response waveform equalization characteristic is obtained. Since the control for minimizing the signal is performed, it is possible to cope with different partial response characteristics, and to expand the convergence range as compared with a conventional waveform equalizing circuit having a fixed tap coefficient value.

Further, according to the present invention, the probability of erroneous determination is lower than that of the conventional waveform equalization circuit having a fixed tap coefficient, so that the convergence time can be reduced as compared with the conventional case. Further, according to the present invention, it is possible to cope with any of the run-length limiting codes of the minimum inversion interval 2 and 3, and it is possible to constitute a digital circuit, so that the reliability is higher than the analog circuit and the circuit scale is almost increased. Configuration that does not require

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a reproducing apparatus according to the present invention.

FIG. 2 is a block diagram of a first embodiment of an automatic equalization circuit as a main part of the apparatus of the present invention.

FIG. 3 is a circuit diagram of an embodiment of a tap delay circuit and a provisional determination circuit in FIG. 2;

FIG. 4 is an explanatory diagram of a partial response characteristic of an integration system.

FIG. 5 is an explanatory diagram of a partial response characteristic of a differential system.

FIG. 6 is a diagram showing the relationship between the characteristics of PR (a, b, b, a), the run-length limiting rule RLL mode, and the tentative judgment value of the tentative classifier.

FIG. 7 is a diagram showing the relationship between the characteristics of PR (a, b, -b, -a), the run-length restriction rule RLL mode, and the tentative judgment value of the tentative classifier.

FIG. 8 is a flowchart illustrating an example of an operation of the temporary discriminator in FIG. 3 with respect to the integration system.

9 is a flowchart illustrating an example of an operation of the temporary discriminator in FIG. 3 with respect to a differential system.

FIG. 10 is a diagram (part 1) illustrating a waveform example before and after waveform equalization with respect to the integration system according to the present invention.

FIG. 11 is a diagram (part 2) illustrating a waveform example before and after waveform equalization for the integration system according to the present invention.

FIG. 12 is a diagram (part 3) illustrating a waveform example before and after waveform equalization for the integration system according to the present invention.

FIG. 13 is a diagram (part 1) illustrating a waveform example before and after waveform equalization with respect to the differential system according to the present invention.

FIG. 14 is a diagram (part 2) illustrating waveform examples before and after waveform equalization with respect to the differential system according to the present invention.

FIG. 15 is a diagram (part 3) illustrating a waveform example before and after waveform equalization for the differential system according to the present invention.

FIG. 16 is a diagram showing an example of an eye pattern of an output signal of a decoding circuit of the playback device according to the present invention.

FIG. 17 is a diagram showing an example of an eye pattern of an output signal of a decoding circuit of the playback device according to the present invention.

FIG. 18 is a block diagram of a second embodiment of the automatic equalization circuit of the main part of the device of the present invention.

FIG. 19 is a block diagram of a third embodiment of the automatic equalization circuit of the main part of the device of the present invention.

FIG. 20 is a block diagram of a fourth embodiment of the automatic equalization circuit of the main part of the device of the present invention.

FIG. 21 is a block diagram of a fourth embodiment of the automatic equalization circuit of the main part of the device of the present invention.

FIG. 22 is a flowchart for explaining an operation of another example of the integration system of the provisional classifier in FIG. 3;

FIG. 23 is a flowchart for explaining an operation of another example of the differentiation system of the temporary discriminator in FIG. 3;

FIG. 24 is a block diagram of an example of a conventional reproducing apparatus.

[Explanation of symbols]

Reference Signs List 15 optical disk 19 resampling / DPLL 20, 20a, 20b, 20c, 20d, 20e automatic equalization circuit 21 decoding circuit 21 transversal filter 22 multiplier / low-pass filter (LPF) 23 tap delay circuit 23a main part of tap delay circuit 24 Temporary determination circuit 26, 27, 28 Peak detector 31 Peak detector / phase comparator 33, 37 Voltage controlled oscillator (VCO) 35 Phase comparator 100, 102, 104 Peak detector 101, 103, 105 Point selection circuit

Claims (7)

[Claims] 1. A reproducing apparatus for reproducing a run-length limited code recorded on a recording medium, performing partial response equalization on the reproduced signal using a transversal filter, and then decoding the reproduced signal, wherein an output signal of the transversal filter is Supplied,
Coefficient generating means for variably controlling a tap coefficient of the transversal filter based on an output error signal of a temporary discriminating circuit for estimating an equalization target value so that the error signal is minimized. By switching the algorithm of the temporary discriminating circuit, equalization to the characteristic indicated by PR (a, b, b, a) and equalization to the characteristic indicated by PR (a, b, -b, -a) A reproducing device characterized by satisfying both. 2. A reproducing apparatus for decoding a reproduced signal obtained by reproducing a run-length limited code recorded on a recording medium, after performing partial response equalization using a transversal filter, and decoding the signal input to the transversal filter. Zero detection means for outputting, in synchronization with the bit clock, zero-point information indicating whether or not the reproduced signal is a zero cross point, and whether or not a peak is detected from the reproduced signal after the waveform equalization input to the transversal filter. A peak detecting unit that outputs peak point information indicating the peak point information in synchronization with a bit clock; a selecting unit that inputs the zero point information and the peak point information, selects one of them, and outputs it as point information; At least 3 points obtained by delaying the point information output from the means by a predetermined time. A delay circuit that outputs as a delay signal, a plurality of the point information from the delay circuit, and a reproduced signal after waveform equalization output from the transversal filter as an input, and a type of partial response equalization. Based on the state transition determined by the type of the run-length limiting code of the reproduction signal and the pattern of the plurality of point information, a provisional determination value of the waveform equalized signal is calculated, and the provisional determination value and the reproduction signal after the waveform equalization are calculated. A temporary discriminating circuit that outputs a difference value of the error signal as an error signal, and a coefficient generating unit that variably controls a tap coefficient of the transversal filter based on an output error signal of the temporary discriminating circuit so that the error signal is minimized. And P
Equalization to the characteristic indicated by R (a, b, b, a) and PR
A reproducing apparatus characterized in that equalization to the characteristics represented by (a, b, -b, -a) is compatible. 3. The detecting means receives, as an input signal, a digital signal obtained by sampling the run-length limited code reproduced from the recording medium by an A / D converter with a system clock, and receives the digital signal at a desired bit rate. A resampling / DPLL for generating and supplying resampled digital data to the transversal filter, detecting whether or not the input digital signal is at a zero crossing point, and outputting the zero point information; 3. The reproducing apparatus according to claim 2, further comprising a resampling / DPLL for detecting whether or not the peak point information is output. 4. A reproduction apparatus for reproducing a run-length limited code recorded on a recording medium, decoding the reproduced signal after performing a partial response equalization using a transversal filter, and then decoding the reproduced signal. Zero detection means for outputting, in synchronization with the bit clock, zero-point information indicating whether or not the reproduced signal after waveform equalization is a zero crossing point; and determining whether a peak is detected from the reproduced signal after waveform equalization output from the transversal filter. Peak detection means for outputting peak point information indicating whether or not the peak point information is synchronized with the bit clock; and input means for inputting the zero point information and the peak point information, selecting one of them, and outputting as the point information, The point information output from the detection means is delayed by a predetermined time. A delay circuit that outputs as three delay signals, a plurality of point information from the delay circuit, and a reproduced signal after waveform equalization output from the transversal filter as inputs, and a partial response equalization Based on the type and the state transition determined by the type of the run-length limiting code of the reproduced signal and the pattern of the plurality of point information, a temporary discriminant value of the waveform equalized signal is calculated, and the temporary discriminant value and the waveform discriminated signal after the waveform equalization are calculated. A provisional determination circuit that outputs a difference value from a reproduction signal as an error signal; and a coefficient generation that variably controls a tap coefficient of the transversal filter based on an output error signal of the provisional determination circuit so that the error signal is minimized. Means, and P
Equalization to the characteristic indicated by R (a, b, b, a) and PR
A reproducing apparatus characterized in that equalization to characteristics shown by (a, b, -b, -a) is compatible. 5. A Viterbi decoder is used for decoding, and the processing of the Viterbi decoder is switched in response to switching of the partial response equalization. The playback device according to any one of the above. 6. The reproducing apparatus according to claim 1, wherein the reproducing apparatus makes equalization reproduction compatible with characteristics of a plurality of signals existing in the same recording medium. apparatus. 7. The reproducing apparatus according to claim 1, wherein at least one of the reproduced signals is a signal reproduced from an optical disk medium by a TPP method.