JP2002007321A - Bus transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method, by which bus agents having different transfer speeds can be mixed on the same bus. SOLUTION: In a computer system, an interface between plural bus agents connected to a synchronizing bus 102 is provided with a dedicated signal line for confirming that operation is enabled at both the rising edge and falling edge of a synchronizing clock and inside the bus agent capable of transfer at both the edges, a means, namely, an edge transfer switching control part 107 is provided for switching both single-edge transfer using a single edge and double-edge transfer using both the edges corresponding to a relevant dedicated signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus transfer system in a computer system, and more particularly to a bus transfer system in which bus agents having different transfer capabilities coexist on the same bus.
The present invention relates to a bus transfer system for performing connection without reducing the bus transfer capability of a bus agent having a high-speed bus transfer capability.

[0002]

2. Description of the Related Art In a synchronous bus transfer system in a computer device, data is generally exchanged between bus agents using a synchronous clock. Therefore, as one method for improving the bus transfer performance, the frequency of the synchronous clock is increased. There is a method of raising. 2. Description of the Related Art In recent years, as the amount of processed data in a computer device has increased, there has been a demand for an improvement in transfer performance to an IO device such as a file device or a communication device.

In order to meet this demand, for example, PCI (Peripheral) which is one of standard IO buses is used.
In the Component Interconnect) bus, the frequency of the synchronous clock is changed from 33 MHz to 66M.
Hz to improve performance.
It has been proposed to improve the transfer performance by further increasing the clock frequency. The method disclosed in this PCI bus is a method of determining the bus operation clock by confirming that all agents on the bus can operate at the same clock frequency (for example, 66 MHz) at the time of reset release of the bus. In order to change the frequency of the bus clock, for example, if a bus agent operating at 33 MHz and a bus agent operating at 66 MHz coexist on the same bus, the bus agent capable of transferring in synchronization with the 66 MHz frequency is 33
It will operate at MHz.

[0004]

As a result, 66 MHz
A bus agent capable of transferring data synchronously with the above has a drawback that the original performance cannot be obtained. Furthermore, if you want to operate the bus agent at 66 MHz,
A low-speed bus agent that cannot operate at 66 MHz
There is also a disadvantage that it cannot be connected to the bus.

A main object of the present invention is to provide a method in which bus agents having different transfer speeds can be mixed on the same bus. It is an object of the present invention to make it possible to use low-speed devices and to mix new high-speed devices on the same bus, and to provide a wider range of computer systems.

The bus transfer method according to the present invention is configured so that bus agents having different transfer performances connected on a synchronous bus can be mixed particularly in a computer device.

[0007]

According to a first aspect of the present invention, there is provided a bus transfer system in a synchronous bus transfer system using a clock, in which a transfer mode using a rising edge of a clock and both a rising edge and a falling edge are used. An edge transfer switching control unit for switching the transfer mode to be used is provided in the bus agent.

[0008] The bus transfer system of the second invention of the present application is the first bus transfer system.
In the invention of the above, at the start of communication of the bus master having the edge transfer switching control unit, the bus master sends a DEREQ signal requesting a transfer mode using both edges to a communication partner agent, and sends a permission response to the signal. When receiving as a DEACK signal, the transfer switching control unit is set to a transfer mode using both edges,
When there is no response from the agent by the DEACK signal, the transfer mode is set to a rising edge.

The bus transfer method according to the third invention of the present application is the first transfer method.
In the invention, when the agent of the communication partner responds to the bus master with the DEACK signal, the agent of the communication partner switches an edge switching control unit of the agent to a transfer mode using both edges.

The bus transfer method according to the fourth invention of the present application is the first transfer method.
In the invention, the agent having the edge transfer switching control unit is connected by two signal lines of a signal line for transmitting the DEREQ signal and a signal line for transmitting the DEACK signal.

The bus transfer method according to the fifth invention of the present application is the first transfer method.
In the invention, the transfer is performed in a transfer mode using both a rising edge and a falling edge between the bus master and the agent having the edge transfer switching control unit.

The bus transfer method according to the sixth invention of the present application is the first transfer method.
In the invention, when the transfer in the transfer mode using both the rising edge and the falling edge is completed, the edge transfer switching control unit is set to the transfer mode using the rising edge.

The bus transfer method according to a seventh invention of the present application is the first transfer method.
In the invention, a bus master having the edge transfer switching control unit and a bus master not having the edge transfer switching control unit are mixed on the same bus.

The bus transfer method according to an eighth aspect of the present invention is the
In the invention, an agent having the edge transfer switching control unit with one open collector signal line that sets the valid time of the signal to low instead of the signal line for transmitting the DEREQ signal and the signal line for transmitting the DEACK signal And controlling the switching of the transfer mode by connecting between them.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

As an embodiment of the present invention, FIG. 1 shows a connection example centered on a synchronous bus 102 in a computer device. In the present embodiment, an upper bus 108 such as a system bus connected to a CPU and a main memory, a synchronous bus 102 such as a PCI bus as a lower bus, a bus bridge 101 having a bridge function between the two buses, It has an agent A 103 and an agent B 104 connected to the synchronization bus 102.

Each agent and the bus bridge 101
The operation is performed using clocks of the same frequency output from a bus clock control / generation circuit (not shown). For example, as this bus capability, the clock frequency is
It is assumed that 33 MHz is applied, and transfer performance equivalent to a 66 MHz clock can be exhibited between devices that can use both edges of this clock. The bus bridge 101 has an arbitration function as a bus arbiter.

Agent A 103 of the synchronous bus 102
Operates using one of the rising edges of the bus clock. Bus bridge 101 and agent B10
4 can operate using the rising edge of the bus clock similarly to the agent A, but can also operate using both the rising and falling edges of the bus clock. Therefore, the bus bridge 101 and the agent B 104 have a transfer mode using one edge using a rising edge and a transfer mode using both rising and falling edges in data transmission and reception, and switch between the two transfer modes. An edge transfer switching control unit 107 is provided. The default transfer mode of the edge transfer switching control unit 107 is a transfer mode using a rising edge.

Further, after acquiring the right to use the bus, the bus master capable of using both edges receives a request signal for requesting transfer on the bus using both edges of the clock, and sends a DEREQ to the agent of the transfer partner. (Doub
The agent that outputs the edge request (le Edge Request) signal 105 and receives the DEREQ signal 105 receives a DEACK (Double Edge A) for responding to the bus master with permission to start transfer using both edges.
A cknowledgment signal 106 is provided, and the above two signal lines are provided between all agents capable of transferring using both edges.

As described above, the transfer using both edges is performed between the agents capable of using both edges, and the transfer between the agents of other combinations (between the agents having only the rising edge, the agent having the rising edge and the use of both edges is not possible). (Between possible agents), the transfer by the rising edge is performed. 2
When the transfer using both edges is completed between the two agents, both agents transfer the edge transfer switching control unit 1
07 is switched to the transfer mode using the rising edge.

In FIG. 1, the signal line DEREQ and the signal line DE
The ACK signal line is set between the bus bridge 101 provided with the edge transfer switching control unit 107 and the agent B 104, and is not provided between the agent A 103 not provided with the edge transfer switching control unit 107 and another agent. .

Here, it is assumed that the bus bridge 101 becomes a bus master and intends to issue an IO transaction to the agent A103. The bus bridge 101 including the edge transfer switching control unit 107
Although the REQ signal 105 is asserted (activated) to the agent A 103, the DEREQ signal line is not provided between the agent A 103 and the DEACK signal from the agent A 103 to the bus bridge 101 even if monitoring is performed for a certain period of time. There is no response by the signal 106. Accordingly, the bus bridge 101 knows that the agent A 103 does not include the edge transfer switching control unit 107, and
The transaction will be performed using the rising edge of the clock. The bus bridge 101 sets its own edge transfer switching unit 107 to the transfer mode based on the rising edge.

Next, a case where the bus bridge 101 becomes a bus master and intends to issue an IO transaction to the agent B 104 will be described. The bus bridge 101 including the edge transfer switching control unit 107
The agent B 103, which asserts the EREQ signal 105 and also includes the edge transfer switching control unit 107,
In response to the assertion of the DEREQ signal 105, the DEACK signal
The bus bridge 101 is asserted and responded to, and notifies the bus bridge 101 that both-edge transfer is possible. Thereby, the edge transfer switching control unit 10 of the bus bridge 101
7 and the edge transfer switching control unit 107 of the agent B 104 switch to transfer using both edges of the clock. As a result, it is possible to execute both-edge transfer between the bus bridge 101 and the agent A103. At the end of the transfer, each transfer switching unit 107
Returns to the transfer mode by the rising edge of the clock.

Further, when the agent A 103 becomes a bus master and intends to issue an IO transaction to the bus bridge 101, the agent A 103
Since the DEREQ signal 105 is not asserted, the IO transaction is performed using the rising edge of the clock.

Finally, when the agent B 104 becomes the bus master and intends to issue an IO transaction to the bus bridge 101, the DEREQ signal 105
, And the bus bridge 101 including the edge transfer switching control unit 107
Assert the DEACK signal 106 in response to the EREQ signal 105 and notify the agent B 104. As a result, in the transfer from the agent B 104 to the bus bridge 101, transfer using both edges becomes possible.

Hereinafter, the operation of the present embodiment will be described based on the configuration shown in FIG.

FIG. 2 shows the edge transfer switching operation.
This will be described with reference to the IO transfer timing chart of FIG. Here, the bus bridge 101 becomes the bus master of the bus 102,
Issue an O transaction. A DEREQ signal 105 which is a transfer request signal using both edges and a permission signal DEACK signal 1 for a transfer request using both edges
06 is a bidirectional signal on a signal line connected to the bus bridge 101 and the agent B104. FIG.
In the state of the clock, R indicates the rising timing and F indicates the falling timing.

From the bus bridge 101 to the agent A1
In the IO transaction corresponding to the clock T03, the bus bridge 101 outputs the time T1-
At R, the address is sent to the agent A 103 and the DEREQ signal 105 is asserted. On the other hand, DE between the agent A 103 and the bus bridge 101
The signal line for transmitting the REQ signal 105 is not connected,
The DEACK signal 106 from the agent A is not asserted, and the data D1 and D2 are output using rising edges at time T3-R and time T4-R, respectively.

Next, in the IO transaction from the bus bridge 101 to the agent B104, the bus bridge 101 transmits the agent B1
04 is issued at time T
Address and DE for Agent B104 in 6-R
The REQ signal is asserted to the agent B104.

The agent B 104 having the edge transfer switching control unit 107 asserts the DEACK signal at time T6-F to notify the bus bridge 101 that both-edge transfer is possible. The data D1 and D2 between the bus bridge 101 and the agent B104 are at the time T
8-R, output at time T8-F. It can be seen that the data transfer time between the bus bridge 101 and the agent B 104 is half the time required for the agent A 103.
Since the bus bridge 101 is a bus master and a bus arbitrator, there is no arbitration signal in FIG.

Conversely, the transfer operation of the IO transaction from the agent A 103 and the agent B 104 to the bus bridge 101 is executed according to the timing chart of FIG. In FIG. 3, as in FIG.
In the clock state, R indicates the rising timing and F indicates the falling timing.

That is, the agent A 103 asserts the bus use right acquisition request signal BREQA to the bus bridge 101 having the bus arbitration function at the time T1-R,
The bus use permission signal BACKKA corresponding thereto is asserted by the bus bridge 101 at time T2-R. As a result, the agent A103, which has become the bus master,
At time T3 without asserting EREQ signal 105
-R outputs an address, and data D1 and D2 are transferred
This is performed using the time T5-R and the time T6-R.

Next, the agent B104 asserts the bus acquisition request signal BREQB at time T7-R, and the bus use permission signal BACKKB corresponding thereto is asserted by the bus bridge 101.
Is asserted at time T8-R. Agent B 104 provided with edge transfer switching control section 107
Asserts the DEREQ signal 105 to the bus bridge 101 at time T8-F and makes a double edge transfer request to the bus bridge 101. Agent B104,
At time T9-R, the address is output. A permission signal DEACK 106 for the DEREQ signal 105 is output at time T9-
When asserted at R by the bus bridge 101 having the edge transfer switching control unit 107, the transfer of the data D1 and D2 is performed using the time T10-F and the time T11-R, and between the bus bridge 101 and the agent B104. The data transfer time in the DMA transfer depends on the bus bridge 1
It can be seen that half of the data transfer time in the IO transaction transfer between Agent 01 and Agent A 103 is sufficient.

In the above embodiment, two control signals, ie, DEREQ, are used as the transfer control signals for both edges.
In the above description, the signal 105 and the DEACK signal 106 are provided.
TEN (Double Edge Transacti
on ENable) signal. For example, this signal is a bidirectional signal. When the signal is valid, the signal is a low (Low) open collector signal. The bus bridge 101 performs DETE at the address output timing.
N signal goes low, but agent A has DETEN
No signal is transmitted. Even when agent A outputs data, the DETEN signal never goes low.
This transfer is not performed on both edges. In the transfer from the bus bridge 101 to the agent B (or from the agent B to the bus bridge 101), both signals can be used for both-edge transfer.

As described above, an object of the present invention is to selectively use a transfer using one edge of a clock and a transfer using both edges on the same bus, and specialize the type and number of control signals. Not something.

[0036]

As described above, by adding a dedicated control signal according to the present invention, it becomes possible to mix devices having different transfer speeds on the same bus. Therefore, conventionally, for example, 3
In the case where a device capable of operating at 66 MHz is connected to a bus operating at 3 MHz, the operation of a device capable of operating at 66 MHz must be adjusted to a low-speed device of 33 MHz.
Although it was not possible to connect devices operating at 30 Hz, the present invention makes it possible to construct a connection configuration in which only exclusive connections could be made by using the 33 MHz clock edge between devices. . Also,
By applying the present invention to an extended IO slot typified by a PCI expansion slot, a user of a computer device can configure a more free system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of the first exemplary embodiment of the present invention.

FIG. 3 is a block diagram illustrating a detailed configuration of the first exemplary embodiment of the present invention.

[Explanation of symbols]

 101 Bus Bridge 102 Synchronous Bus 103 Agent A 104 Agent B 105 DEREQ Signal 106 DEACK Signal 107 Edge Transfer Switching Control Unit 108 Upper Bus

Claims (8)

[Claims] In a synchronous bus transfer method using a clock, an edge transfer switching control unit that switches between a transfer mode using a rising edge of a clock and a transfer mode using both rising and falling edges is provided to a bus agent. A bus transfer method comprising: 2. When a bus master having the edge transfer switching control unit starts communication, the bus master sends a DEREQ signal requesting a transfer mode using both edges to a communication partner agent, and a permission response to the signal is sent. 2. The transfer mode according to claim 1, wherein the transfer switching control unit is set to a transfer mode using both edges when receiving the DEACK signal as a DEACK signal, and is set to a transfer mode based on a rising edge when there is no response from the agent by the DEACK signal. Bus transfer method. 3. The agent of the communication partner includes the D
2. The bus transfer method according to claim 1, wherein, when responding to the bus master with an EACK signal, the edge switching control unit of the agent switches to a transfer mode using both edges. 4. An agent having the edge transfer switching control unit is connected by two signal lines, a signal line for transmitting the DEREQ signal and a signal line for transmitting the DEACK signal. 2. The bus transfer method according to 1. 5. The bus transfer according to claim 1, wherein the transfer is performed in a transfer mode using both a rising edge and a falling edge between the bus master and the agent having the edge transfer switching control unit. method. 6. The transfer mode according to claim 1, wherein when the transfer in the transfer mode using both the rising edge and the falling edge between the bus masters is completed, the edge transfer switching control unit is set to the transfer mode based on the rising edge. Bus transfer method described. 7. The bus transfer method according to claim 1, wherein a bus master having the edge transfer switching control section and a bus master not having the edge transfer switching control section coexist on the same bus. 8. The edge transfer switching control unit is replaced with a signal line for transmitting the DEREQ signal and a signal line for transmitting the DEACK signal. 2. The bus transfer method according to claim 1, wherein the switching between transfer modes is controlled by connecting the agents having the buses.