JP2001345773A - Burst frame transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a burst frame transmission system for simplified supplying of clock signal which is used to prevent near-end crosstalk when a metallic cable is used in a fast communication environment. SOLUTION: In order to prevent near-end crosstalk at a metallic cable 102 connecting interface conversion devices 1031-103M to respective VDSL modems 101, a data transmission is required which uses 2 kHz clock source synchronous in phase between the interface conversion devices. A cross connect device 104 builds a phase information for clock signal taken out of the 2 kHz clock source (not shown) and a discrimination information ('H4' byte) for reproducing a frequency identical with the clock signal into an STM-1 frame, which are transmitted to the devices 1031-103M. ON the interface conversion devices 1031-103M sides, clock signal is reproduced from the discrimination information while its phase is corrected using the phase information for synchronizing clock. Thus, clock is not required to be received from a common clock source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst frame transfer system used for a VDSL system or the like, and particularly to a case where a burst frame is transferred using a pair cable used for a telephone line or the like as a transmission path. The present invention relates to a burst frame transfer system for preventing near-end crosstalk.

[0002]

2. Description of the Related Art With the spread of the Internet, communication of not only text information but also large-capacity information such as images, sounds, and images from various servers has been actively performed. Under these circumstances, VDSL
(Very high-bit-rate Digital Subscriber Line, Very
Development of a high-speed communication environment such as a high-speed Digital Subscriber Line (Ultra High-Speed Digital Subscriber Line) system is regarded as important. In particular, existing telecommunications carriers have a huge asset of an access line using an existing metallic cable called a so-called twisted pair. Therefore, it is a big issue to provide an advanced service by effectively using the service.

FIG. 9 shows such a conventionally proposed VDS.
1 shows an outline of a communication system using the L system. VDSL modem 201 by-N units arranged on the terminal side in the communication system, connected to one each corresponding one of the first to M interface converter 203 ₁ ～203 _M of the metallic cable 202 to 1 Have been. The first to Mth interface converters 203 _{1 to} 203 _M are based on SDH (synchronous digital hierarchy) as an international standard for a high-speed relay speed system.
TM (synchronous transfer mode) -1 signal and VDS
This device performs interface conversion with the L signal. The first to Mth interface converters 203 _{1 to} 203 _M
The lower limit of each metallic cable 202 is 64 Kbps, and when the upper limit is symmetrical transmission, 2
6 Mbps, 52 Mbps downstream for asymmetric transmission,
Data can be transferred at a transfer rate in the range of 6 Mbps upstream. N metallic cables 202 can be connected to each of the _first to M-th interface converters 203 _{1 to} 203 _M (one cable is illustrated in the figure).
Therefore, the total transfer rate of these N metallic cables 202 ranges from 64 Kbps to 156 Mbps. Here, a 2KHz ping-pong transmission method (TDD; Ti
me Division Duplexed).

[0004] First to M-th interface converter 20
3 ₁ ~203 _M is between N number of cross-connect device 204, STM-1 by SDH with an optical cable 205
It is designed to transfer frames. Each optical cable 205 can transfer data at a transfer rate of 156 Mbps. Cross-connect device 204
And the SDH communication network 207,
8 and repeaters 209 are arranged in L sets. Here, an optical cable 21 is connected between the cross-connect device 204 and the terminal multiplex repeater 208, between the terminal multiplex repeater 208 and the repeater 209, and between the repeater 209 and the SDH communication network 207.
1, 212 and 213 are arranged. These optical cables 211, 212, and 213 transfer STM-1 frames by SDH at a transfer rate of 156 Mbps. The first to M-th interface converters 203 _{1 to} 203 _M are respectively connected to the optical cable 20.
5 and a 2 KHz clock source 222 by a separate line 221.
, And a clock signal 223 of 2 KHz is supplied. 2 kHz clock source 222
Is located in some higher-level device.

In this communication system, the first to Mth interface converters 203 _{1 to} 203 _M convert the signal format between the STM-1 frame and the VDSL signal. The clock signal 223 is used to prevent near-end crosstalk between metallic cables during burst frame transfer.

FIG. 10 shows a main part of a VDSL system in this communication system. Here, in order to simplify the description, the first interface converter 203 ₁
The part related to is shown. The first interface converter 203 ₁ is connected to the first to Nth V through a real line 225.
DSL modems 201 _{1 to} 201 _N are connected.

FIG. 11 shows a case where the phases of burst frames as transmission signals and reception signals output from the first and second VDSL modems in the VDSL system shown in FIG. 10 do not match. 12 is FIG.
First and second VDSL in the VDSL system shown in FIG.
This shows a case where the phases of a burst frame as a transmission signal and a reception signal output from a modem are in phase. In the example shown in FIG. 11, the actual line 2 shown in FIG.
25 in the transmission signal 231 ₁ from the first VDSL modems 201 ₁ is transmitted first to the interface converter 203 ₁
And the first interface conversion device 203 ₁ to the first
A transmission timing of the received signal 232 ₁ is transmitted to the VDSL modem 201 _1, transmission signals 231 ₂ and the first interface conversion device 2 transmitted from the second VDSL modem 201 ₂ to the first interface conversion unit 203 ₁
03 ₁ , the transmission timing of the received signal 232 ₂ sent to the second VDSL modem 2012 ₂ is shifted. Therefore, transmission signals 231 _1, 231 ₂ and the reception signal 232 _1, 2
32 ₂ time zone 235 that overlap in time will occur. Near-end crosstalk occurs during this time period.

[0008] In the timing of the example shown in FIG.
Of the transmission signal 231 ₁ transmitted from the VDSL modem 201 ₁ to the first interface conversion device 203 ₁ and the transmission signal 231 ₂ transmitted from the _first VDSL modem 201 ₁ to the second interface conversion device 203 ₂ And the transmission timing of the reception signal 232 ₁ similarly sent from the first interface converter 203 ₁ to the first VDSL modem 201 ₁ and the transmission timing of the received signal 232 ₁ from the _first interface converter 203 ₁ to the second VDSL modem 201 ₁ 201 ₂
And the transmission timing of the received signal 232 ₂ sent to the receiver. Since the transmission signal and the transmission signal and the reception signal and the reception signal completely match in the respective time zones 236, far-end crosstalk does not occur in these time zones.

It has been known that when near-end crosstalk as shown in FIG. 11 occurs, the line quality is greatly deteriorated. FIG.
The far-end crosstalk shown in FIG. 2 has less influence on the line quality than the near-end crosstalk. For this reason, the first to Mth shown in FIG.
Interface converters 203 _{1 to} 203 _M are 2KH
2 KHz clock signal 223 from z clock source 222
The clock signal 223 is used to make the burst frame timings of 2 KHz coincide with each other.

FIG. 13 shows the configuration of an interface conversion device in this conventional system. FIG.
1 to M-th interface converter 203 ₁ shown in FIG.
～203 _M, since identical in circuit configuration will be described of the circuit the first interface conversion unit 203 ₁ as an example here. The first interface conversion unit 203 _1, the first to N of VDSL modems 201 ₁ ～201 _N and one by one the first to VDSL line card 241 ₁ ～241 _N of the N corresponding shown in FIG. 9 And they are connected one-to-one. These VDSL line cards 241 ₁ ~241 _N of the first to N may, SDH
STM-1 interface block 242 and 2KHz
It is connected to the clock receiving unit 243. The 2 KHz clock receiving unit 243 receives the 2 KHz clock signal 223 and uses it as the clock signal 251 to output the first to Nth V-th signals.
And supplies it to the DSL line card 241 ₁ ~241 _N.

[0011] SDH STM-1 interface block
242 is connected to the cross-connect device 204 shown in FIG.
Connected, the first to Nth VDSL line cards 2
41 ₁~ 241_NRead in synchronization with the clock signal 251
The outgoing transmission signal 231 is transmitted to the SDH STM-1 interface.
STM- by SDH
Sent to the cross-connect device 204 as one frame 261
Out or conversely sent from the cross-connect device 204
Received data 232 from the received STM-1 frame 261
And the first to Nth VDSL line cards 241₁
~ 241_NOutput to the corresponding one of
ing.

[0012]

In such a conventional apparatus for burst frame transfer, each interface converter 203 obtains a common 2 kHz clock signal from an external 2 kHz clock source 222. . For this reason, each interface converter 203 needs to arrange a separate line 221 from the optical cable 205 to receive a clock signal between the interface converter 203 and the common 2 KHz clock source 222, and a communication system using the VDSL system is required. There was a problem that a large amount of money was required for construction.

It is an object of the present invention to provide a burst frame transfer system which simplifies the supply of a clock signal used to prevent near-end crosstalk when using a metallic cable in a high-speed communication environment. It is in.

[0014]

According to the first aspect of the present invention, (a) communication terminals divided into a plurality of groups;
(B) a cross-connect device; and (c) a signal terminal disposed between a communication terminal and a cross-connect device for converting the format of signals handled by the cross-connect device and the format of signals handled by the cross-connect device for each group of communication terminals. (D) a cable for individually connecting each communication terminal of a group corresponding to each signal format converter, and (e) a cable provided for each signal format converter, and a predetermined A data transmission means for transmitting high-speed data in synchronization with a reference clock signal having a frequency, a clock signal supply source for supplying a reference clock signal to the cross-connect device, and a clock signal supply source from the clock signal supply source. Identification information indicating the timing of the same cycle as the supplied reference clock signal, and the position of the frame with respect to the reference clock signal. Cross-connect device-side clock information transmitting means for incorporating the phase information representing the difference and transmitting to the signal format converting means of each group at a cycle shorter than the cycle of the reference clock signal; and (h) respective signal format converting means. The identification information is extracted from the signal sent from the clock information sending means on the side of the cross-connect device provided on the side, and the clock signal having the same frequency as the reference clock signal is reproduced, and the phase information is extracted to extract the phase information. The burst frame transfer system includes a signal format conversion unit and a clock signal generation unit that corrects the phase of the clock signal.

That is, according to the first aspect of the present invention, the signal transmitted between the cross-connect device and the signal format conversion means for each group includes a signal having the same frequency as the reference clock signal supplied to the cross-connect device. And the phase information with respect to the reference clock signal for reconstructing the reference clock signal are transmitted to each signal format converter. By extracting the identification information on the signal format conversion means side, a signal having the same frequency as the reference clock signal is obtained, and the phase can be adjusted using the phase information. Therefore, if communication is performed with the communication terminals of each group using the clock signal reproduced on the side of each signal format converter, the timing of the frame of the signal transmitted through each cable can be adjusted, and near-end crosstalk is prevented. be able to.

According to the second aspect of the present invention, (a) communication terminals divided into a plurality of groups, (b) a cross-connect device, and (c) a communication terminal disposed between the communication terminal and the cross-connect device. Signal format conversion means provided for each group, which converts the format of the signals handled by these and the signals handled by the cross-connect device for each group,
(D) a cable for individually connecting each signal format converting means to each communication terminal of the corresponding group; and (e) a cable provided for each signal format converting means, which synchronizes the cable with a reference clock signal of a predetermined frequency. Data transmission means for transmitting high-speed data, a clock signal supply source for supplying a reference clock signal provided in any of (f) signal format conversion means, and (g) a clock signal supply source supplied from this clock signal supply source. The identification information indicating the timing of the same cycle as the reference clock signal and the phase information indicating the phase difference of the frame with respect to the reference clock signal are incorporated and transmitted to the cross-connect device at a cycle shorter than the cycle of the reference clock signal. And (h) the clock information transmitting means on the signal format converter side. Clock information transmitting means on the cross-connect device side, which incorporates the identification information and phase information, and transmits to the signal format converting means of each group at a cycle shorter than the cycle of the reference clock signal; The identification information is extracted from the signal sent from the clock information sending means provided on the cross-connect device side provided on each signal format conversion means side without sending means, and a clock signal having the same frequency as the reference clock signal is reproduced and the phase information is reproduced. The burst frame transfer system is provided with a signal format conversion means side clock signal generation means for correcting the phase of the clock signal having the same frequency as the reference clock signal.

That is, according to the second aspect of the present invention, the signal transmitted between the cross-connect device and the signal format conversion means for each group includes the same frequency as the reference clock signal prepared for one of the signal format conversion means. The identification information for reproducing the signal and the phase information for the reference clock signal are incorporated, and the signal format conversion means transmits the signal to the cross-connect device. The cross-connect device transfers this to a signal to be transmitted with each signal format conversion means. Therefore, each signal format converter can obtain a signal having the same frequency as the reference clock signal by extracting identification information, and can adjust the phase using the phase information. Therefore, if communication is performed with the communication terminals of each group using the clock signal reproduced on the side of each signal format converter, the timing of the frame of the signal transmitted through each cable can be adjusted, and near-end crosstalk is prevented. be able to.

According to a third aspect of the present invention, in the burst frame transfer system according to the first or second aspect, the cable is a metallic cable, the reference clock signal is a 2 KHz signal, and the data transmission means is a 2 KHz burst. It is characterized in that the frame is transmitted to a metallic cable.

That is, according to the third aspect of the present invention, when transmitting a 2 KHz burst frame to an existing metallic cable, near-end crosstalk is prevented.

According to a fourth aspect of the present invention, in the burst frame transfer system according to the first aspect, a clock signal supply source for supplying a reference clock signal is built in the cross-connect device.

That is, the invention according to claim 4 indicates that not only the reference clock signal is externally supplied to the cross-connect device but also the cross-connect device may be built therein.

According to a fifth aspect of the present invention, in the burst frame transfer system according to the first or second aspect, the signal format conversion means and the cross-connect device are connected to each other by the SDH.
It is characterized by transmitting a TM-1 signal.

According to a sixth aspect of the present invention, in the burst frame transfer system according to the first or second aspect, the signal format conversion means and the communication terminal transmit a VDSL signal.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows an outline of an example of a communication system using a burst frame transfer system according to an embodiment of the present invention. In this communication system, each of N VDSL modems 1 arranged on the terminal side
01 denotes the first to M-th interface converters 103 ₁ to 103 ₁ through a pair of metallic cables 102, respectively.
It is connected to corresponding ones are of 103 _M. First
~ M-th interface converters 103 _{1 to} 103 _M are S
STM by DH (synchronous digital hierarchy)
(Synchronous transfer mode) -1 signal and VDSL (V
ery high-bit-rate Digital Subscriber Line, Very hi
gh-speed Digital Subscriber Line) is a device that performs interface conversion with a signal. The metallic cable 102 connected to the _first to M-th interface converters 103 _{1 to} 103 _M has a lower limit of 64 Kbps, and an upper limit of 26 Mbps for symmetric transmission, 52 Mbps for asymmetric transmission, and 6 Mbps for uplink. Data can be transferred at a range of transfer rates. Since N metallic cables 102 can be connected to each of the _first to M-th interface converters 103 _{1 to} 103 _M (one by one in the figure), these N metallic cables 1
02 total transfer rate from 64Kbps to 156Mbp
s. Here, a 2 KHz ping-pong transmission system (TDD; Time Division Duplexed) is adopted.

First to Mth interface converters 10
3 ₁ 10 @ 2 to 10 @ 3 _M of between the cross-connect device 104 of N number, STM-1 by SDH with an optical cable 105
It is designed to transfer frames. Each optical cable 105 can transfer data at a transfer rate of 156 Mbps. Cross connect device 104
And the SDH communication network 107,
8 and L repeaters 109 are arranged. The terminal station multiplex relay device 108 is provided for performing long-distance and large-capacity data transmission. Between the cross-connect device 104 and the terminal multiplex repeater 108, between the terminal multiplex repeater 108 and the repeater 109, and between the repeater 109 and the SDH communication network 107.
The optical cables 111, 112, and 113 are disposed between them. These optical cables 111, 112, 113
Are 156 STM-1 frames by SDH, respectively.
The data is transferred at a transfer rate of Mbps.

In this communication system, the VDSL modem 101 is located, for example, in an office or each home.
The interface converters 103 _{1 to} 103 _M are arranged in, for example, a pillar or a machine room of a building. The cross-connect device 104 is located in the telephone company.

FIG. 2 shows the configuration of the interface conversion device of this embodiment. 1 to M shown in FIG.
Since the interface converters 103 _{1 to} 103 _M have the same circuit configuration, the circuit will be described using the first interface converter 103 ₁ as an example. FIG. 1 shows the first interface conversion device 103 ₁ .
VDSL modems 101 ₁ to 101 _N of the first to N shown in
The first to N-th VDSL line cards 141 _{1 to} 141 _N are provided one by one, and these are connected one-to-one. These first to N-th VDSL line cards 141 _{1 to} 141 _N include an SDH STM-1 interface block 142 and a 2 kHz clock recovery unit 143.
It is connected to the. The 2 KHz clock reproducing unit 143
The phase data 144 is received from the DHSTM-1 interface block 142 to reproduce a 2 KHz clock signal. The reproduced 2 KHz clock signal 146 is supplied to the _{first to} Nth VDSL line cards 141 _{1 to} 141 _N.

SDH STM-1 interface block
142 is connected to the cross-connect device 104 shown in FIG.
Connected, first to Nth VDSL line cards 1
41 ₁~ 141_NRead in synchronization with the clock signal 146
The transmitted transmission signal 151 is transmitted to the SDH STM-1 interface.
STM by SDH
Sent to the cross-connect device 104 as one frame 152
Out or conversely sent from the cross-connect device 104
Received data obtained from the received STM-1 frame 152
To the first to Nth VDSL line cards 141₁
~ 141_NOutput to the corresponding one of
ing.

FIGS. 3 and 4 show the STM-1 frame 2.
One frame format is shown. The STM-1 frame 152A shown in FIG.
Like the one frame 152B, it is repeated at a transfer rate of 156 Mbps at a cycle of 8 KHz, and is also called an SDH super frame. STM- shown in FIG.
One frame 152A includes an SOH (Sect) as a management area.
ion over head) 161A and a payload 162A containing actual data. STM-
As shown, three VC-3 units 163 are accommodated in the payload 162A of one frame 152A. Path overhead (POH) 1 of each VC-3 unit 163
64 holds an “H4” byte 165 that sequentially repeats a value from “0” to “3”. This "H4"
Byte 165 is a pointer (position information) used to indicate “0” to “3” as a multiframe number of a TU (Tributary Unit), and the signal state is “0”.
0, “01,” “10,” and “11.” Therefore, the STM-1 frame 152
A specific one of the “H4” bytes 165 in A is extracted in order, and a cycle in which the same value (for example, the value “0”) is obtained is 2 KHz.

The STM-1 frame 152B shown in FIG.
Is configured by an SOH 161B as a management area and a payload 162B containing actual data. The payload 162B has a V
One C-3 unit 163 is accommodated. VC-3 part 16
The path overhead (POH) 164 of “3” contains “H4” bytes 165 that sequentially repeat values from “0” to “3”. Therefore, the "H4" byte 165 in the STM-1 frame 152B is sequentially extracted, and the cycle at which the "H4" byte 165 takes the same value (for example, the value "0") is 2 KHz. That is, the STM-1 frames 152A and 152B shown in FIG. 3 and FIG.
Thus, a clock signal similar to the 2 KHz clock signal 223 obtained from 22 can be extracted.

FIG. 5 shows the configuration of the phase information generation circuit arranged on the cross-connect device side. The phase information generation circuit 171 includes a 2 KHz component detection circuit 172.
And a counter 173 disposed at the subsequent stage, and a 2 KHz phase detection unit 174 disposed at a further subsequent stage. The “H4” byte 165 described with reference to FIGS. 3 and 4 is input to the 2 KHz component detection circuit 172. 2K
The Hz component detection circuit 172 receives the input “H4” byte 1
65 are "00", "01", "10", "1".
When it becomes "00" of "1", the frame zero phase detection signal 175 is outputted to the counter 173. The counter 173 outputs "0" to "4095" by a clock signal (not shown) of 8.192 MHz. The SDH superframe (8KH) is counted.
The count value is reset to “0” by the frame timing signal 176 output at the beginning timing of z), and the counting is restarted from this point. Counter 17
The 12-bit count value information 177 representing the count value output from 3 is input to the 2 KHz phase detector 174.

The 2 KHz phase detection section 174 receives a 2 KHz burst frame timing signal 178 received from a clock supply device (not shown) on the network side, and generates 12-bit count value information 177 at this input timing. And outputs the same as 12-bit phase information 179. This phase information 179 is the SOH 161A shown in FIG.
It is incorporated into a specific vacant area in H161B and is transmitted to the first to Mth interface converters 103 _{1 to} 103 _M together with data.

FIG. 6 shows the configuration of the 2 KHz clock recovery unit on the first interface converter side. Second to Mth interface converters 103 ₂ to 1
Since 03 _M also has exactly the same circuit for 2KHz clock reproducing unit 143, these drawings and explanations are omitted.

The SDH STM-1 interface block 142 in the _first interface converter 103 ₁ shown in FIG. 2 stores the 12-bit phase information 1 described in FIG.
79, and this is used as phase data 144 as 2KH
The signal is supplied to the first 2 KHz phase detector 181 in the z clock reproducer 143. The “H4” obtained based on the STM-1 frame 152 is stored in the 2 kHz clock recovery unit 143.
2KH for detecting 2KHz component from byte 165
A z-component detection circuit 182 is also provided. This is a circuit having the same configuration as the 2 KHz component detection circuit 172 in FIG. Output from the 2 KHz component detection circuit 182,
The frame zero phase detection signal 183 indicating that the signal state of the "H4" byte 165 is "00" is a counter 184.
Is output to The counter 184 has a frequency of 8.192 MHz similarly to the counter 173 shown in FIG.
From “0” to “409” by a clock signal (not shown).
The counter 184 counts a value up to 5 ″. The counter 184 outputs a frame timing signal 18 output at the start timing of the SDH superframe (8 KHz).
5 is input. The 12-bit count value information 186 representing the count value output from the counter 184 is supplied to the second 2 kHz phase detector 187. These first and second 2 KHz phase detectors 1
A phase comparator 188 is provided on the output side of 81 and 187, and a 2 KHz burst frame signal generation circuit 189 is provided on the output side. 1st and 2nd
The KHz phase detectors 181 and 187 receive the 2 KHz clock signal 191 output from the 2 KHz burst frame signal generation circuit 189 as a latch signal.

The 2 KHz clock reproducing unit 143
The 2KHz component detection circuit 182 uses the “H4” byte 16
When the signal state of No. 5 becomes “00”, a frame zero phase detection signal 183 indicating this is output to the counter 184. The counter 184 has an SDH super frame (8KH
The frame timing signal 185 output at the first timing of z) is input. At the timing when the frame timing signal 185 is input, the counter 184 resets its count value to “0” and repeats the operation of restarting the count from this point. Then, when the frame zero phase detection signal 183 is input, 12-bit count value information 186 representing the count value at that time is supplied to the second 2 KHz phase detection unit 187. The 12-bit count value information 186 is latched at the rising edge of the 2 KHz clock signal 191 generated by the 2 KHz burst frame signal generation circuit 189, and its output is converted to 12-bit count value data 193 by the phase comparator 188.
Supplied to The first 2 KHz phase detector 181 similarly fetches the current phase data 144 sent from the cross-connect device 104 by the 2 KHz clock signal 191, and uses this as the 12-bit phase data 194. To the vessel 188.

The phase comparator 188 has the 12-bit count value data 193 and the 12-bit phase data 194.
Is subtracted. For example, if the count value data 193 on the _first interface converter 103 ₁ side is “00000”
000101 ", the cross-connect device 1
The phase data 194 on the 04 side is “00000000100
The phase comparator 188 performs these subtractions, and outputs the calculation result “0x03” to the 2 KHz burst frame signal generation circuit 189 as the calculation result data 19.
Supplied as 5. The 2 KHz burst frame signal generation circuit 189 generates the first
The phase of the 2 KHz burst frame signal on the side of the interface converter 103 ₁ is adjusted to the phase of the 2 KHz burst signal on the side of the cross connect device 104, and the 2 KHz clock signal
Will be output.

In this example, the phase of the 2 KHz clock signal between the cross-connect device 104 and the first interface converter 103 ₁ is adjusted using the 2 KHz clock recovery unit 143 on the _first interface converter 103 ₁ side. An example of doing this has been described. Similarly, the second to M-th interface converters 103 _{2 to} 103 _M adjust the phase of the 2 KHz clock signal with the cross-connect device 104. Therefore, these devices 104, 103 ₁ to 1
A clock signal common 2KHz it is possible to obtain the same effect as if you are using between 03 _M.

FIG. 7 shows these cross-connect devices and
9 shows the relationship of the M-th interface conversion device. Here, using a common SDH communication network, the cross connect device 104 is used as a master station, and a common 2 kHz is used among the _first to Mth interface converters 103 _{1 to} 103 _M.
This means that the clock signal can be used. The first to M-th interface converters 103 _{1 use} these cross-connect devices 104 as master stations for clock signals.
Since an STM-1 frame is transmitted between 10 and 103 _M , any device provided with a clock signal source can be a master station. One example will be described in the following modified example.

Modification

FIG. 8 shows a basic configuration of a burst frame transfer system in which a master station of a clock signal is used as a first interface converter. The system of this modification is useful, for example, when there is no clock signal source of 2 KHz on the network side. In this example, the 2KH of the _first interface conversion device 103 ₁
The phase of the 2 KHz clock signal is synchronized with respect to the z clock signal source.

In the case of this example, 2K is added to the STM-1 frame transmitted from the _first interface converter 103 _1.
The phase information of the Hz burst frame and the identification information relating to the frequency corresponding to the “H4” byte 165 shown in the embodiment are incorporated and transmitted to the cross-connect device 104. The cross-connect device 104 similarly incorporates and transmits the phase information and the identification information of the frequency when transmitting the STM-1 frame to the _{second to Mth} interface converters 103 _{2 to} 103 _M. As a result, the common 2 KHz between these devices 104, 103 _{1 to} 103 _M
The same effect as in the case where the clock signal is used can be obtained.

In the embodiment, the frequency of 2 KHz is reproduced by extracting the special signal state of the "H4" byte 165 using the STM-1 frame 152A repeated at 8 KHz. Similarly, by incorporating identification information such as “H4” byte 165 into a signal having a frequency higher than
A desired frequency can be reproduced. Therefore, it is natural that the present invention is not limited to reproducing the clock signal of the frequency of 2 KHz or adjusting the phase thereof.

[0045]

According to the first and third aspects of the present invention, as described above.
According to the present invention, a signal having the same frequency as the reference clock signal supplied to the cross-connect device is added to the signal transmitted between the cross-connect device and the signal format converter for each group. The identification information for reproduction and the phase information for the reference clock signal are incorporated and transmitted to each signal format conversion means, and the signal format conversion means extracts the identification information to obtain the same frequency as the reference clock signal. And the phase is adjusted using the phase information. Therefore, it is not only possible to prevent near-end crosstalk, but it is not necessary to provide a line for transmitting a clock signal from one clock supply source to each signal format conversion means, and the cost and time required for system construction are reduced. Can save money. Moreover, since the clock signal is reproduced using the existing signal, there is an advantage that the traffic of the signal is not increased.

According to the second, third, fifth and sixth aspects of the present invention, any one of the signals transmitted between the cross-connect device and the signal format conversion means for each group is added to The identification information for reproducing a signal having the same frequency as the reference clock signal prepared on the format conversion means side and the phase information for the reference clock signal are incorporated and transmitted from the signal format conversion means to the cross-connect device. The connecting device transfers the signal to each signal format converter and the signal to be transmitted, so that each signal format converter extracts the identification information to obtain a signal having the same frequency as the reference clock signal, and uses the phase information. The phase can be adjusted. Therefore,
Not only can the near-end crosstalk be prevented, but there is no need to provide a line for transmitting a clock signal from one clock supply to each signal format converter, thereby saving the cost and time required for system construction. be able to. Moreover, since the clock signal is reproduced using the existing signal, there is an advantage that the traffic of the signal is not increased.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing an outline of an example of a communication system using a burst frame transfer system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an interface conversion device according to the present embodiment.

FIG. 3 is an explanatory diagram showing a first frame format of an STM-1 frame.

FIG. 4 is an explanatory diagram showing a second frame format of an STM-1 frame.

FIG. 5 is a block diagram showing a configuration of a phase information generation circuit arranged on the cross-connect device side in the embodiment.

FIG. 6 is a block diagram showing a configuration of a 2 KHz clock recovery unit on the first interface converter side in the embodiment.

FIG. 7 is a cross-connect device according to the present embodiment and
FIG. 9 is an explanatory diagram showing a relationship of an Mth interface conversion device.

FIG. 8 is a system configuration diagram showing a principle configuration of a burst frame transfer system in which a master station of a clock signal is used as a first interface converter as a modification of the present invention.

FIG. 9 is a system configuration diagram showing an outline of a communication system using a conventionally proposed VDSL system.

FIG. 10 is a schematic configuration diagram showing a main part of a VDSL system in a conventional communication system.

FIG. 11 is a timing chart showing a case where the phases of burst frames as transmission signals and reception signals output from the first and second VDSL modems in the VDSL system shown in FIG. 10 do not match.

FIG. 12 is a timing chart showing a case where burst signals as transmission signals and reception signals output from the first and second VDSL modems have the same phase in the VDSL system shown in FIG. 10;

FIG. 13 is a block diagram showing a configuration of the conventional interface conversion device shown in FIG.

[Description of Signs] 101 VDSL modem 102 Metallic cable 103 Interface conversion device 104 Cross-connect device 107 SDH communication network 108 Terminal station multiplex repeater 142 SDH STM-1 interface block 143 2 KHz clock recovery unit 144 Phase data 146, 191 2 KHz clock signal 152 STM-1 frame 161 SOH (Section Over Head) 162 Payload 165 “H4” byte 171 Phase information generation circuit 172, 182 2 KHz component detection circuit 173, 184 counter 174 2 KHz phase detection section 179 Phase information 181 First 2 KHz phase detection Unit 187 second 2 kHz phase detecting unit 188 phase comparator

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H04Q 11/04 304 H04L 11/20 BF term (Reference) 5K028 AA02 AA06 DD04 KK05 KK33 MM12 MM16 NN01 NN33 NN41 5K030 GA04 GA12 HB15 HB25 JA11 JA12 JL10 KA21 LA15 5K047 AA13 AA15 BB18 CC02 GG03 GG09 GG11 HH01 JJ02 5K069 AA01 CB04 EA18 FD04 GA08 GA10 GA12

Claims (6)

[Claims] A communication terminal divided into a plurality of groups, a cross-connect device, a signal disposed between the communication terminal and the cross-connect device, and a signal handled by the communication terminal and a signal handled by the cross-connect device. A signal format conversion means provided for each group, a cable for individually connecting each communication terminal of each group corresponding to each signal format conversion means, and a signal format conversion means provided for each signal format conversion means. Data transmission means for transmitting high-speed data to a cable in synchronization with a reference clock signal of a predetermined frequency; a clock signal supply source for supplying the reference clock signal to the cross-connect device; and a clock signal supply source. Identification information indicating timing having the same period as the reference clock signal supplied from
Cross-connect device-side clock information transmitting means for incorporating the phase information representing the phase difference of the frame with respect to the reference clock signal and transmitting the signal to the signal format conversion means of each group at a cycle shorter than the cycle of the reference clock signal; The identification information is extracted from the signal transmitted from the clock information transmission means on the side of the cross-connect device provided on each signal format conversion means side, and a clock signal having the same frequency as the reference clock signal is reproduced, and the phase information is reproduced. And a signal format converting means-side clock signal generating means for correcting the phase of the clock signal having the same frequency as the reference clock signal. 2. A communication terminal divided into a plurality of groups, a cross-connect device, a signal disposed between the communication terminal and the cross-connect device, and a signal handled by the group of communication terminals and a signal handled by the cross-connect device. A signal format conversion means provided for each group, a cable for individually connecting each communication terminal of each group corresponding to each signal format conversion means, and a signal format conversion means provided for each signal format conversion means. A data transmission means for transmitting high-speed data in synchronization with a reference clock signal of a predetermined frequency to a cable, a clock signal supply source for supplying the reference clock signal prepared in any of the signal format conversion means, Identification information indicating a timing having the same period as the reference clock signal supplied from the clock signal supply source; ,
A clock information transmitting means on the signal format conversion means side, which incorporates phase information indicating the phase difference of the frame with respect to the reference clock signal and transmits the signal to the cross-connect device at a cycle shorter than the cycle of the reference clock signal; A cross-connect device-side clock that incorporates the identification information and the phase information sent from the conversion-unit-side clock information sending unit and sends it to the signal format conversion unit in each group at a cycle shorter than the cycle of the reference clock signal. Information transmitting means, and extracting the identification information from a signal transmitted from the cross-connect device-side clock information transmitting means provided on each of the signal format converting means without the signal format converting means-side clock information transmitting means. When a clock signal having the same frequency as the reference clock signal is reproduced, The burst frame transfer system, characterized in that an extracted phase information and a signal format conversion means side clock signal generating means for correcting the phase of the clock signal of the reference clock signal and the same frequency. 3. The cable according to claim 1, wherein the cable is a metallic cable, the reference clock signal is a 2 KHz signal, and the data transmission unit transmits a 2 KHz burst frame to the metallic cable.
Or a burst frame transfer system according to claim 2. 4. The burst frame transfer system according to claim 1, wherein a clock signal supply source for supplying the reference clock signal is built in the cross-connect device. 5. The burst frame transfer system according to claim 1, wherein the signal format conversion means and the cross-connect device transmit an STM-1 signal by SDH. 6. The burst frame transfer system according to claim 1, wherein said signal format conversion means and said communication terminal transmit a VDSL signal.