JP2001344979A - Semiconductor memory, semiconductor integrated circuit device, and portable device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current consumption at standby. SOLUTION: In a standby mode, word drivers 8, 9 supply negative voltage Vng to word lines WL0, WL1. Pre-charge circuits 6, 7 turn off P channel MOS transistors PT61-PT63, PT71-PT73 and separate pairs of bit lines (BL0, /BL0), (BL1, /BL1) electrically from a power source node for receiving power source voltage VDD. Therefore, the voltage between the source and the drain of an access transistor connected to the data holding node of an L level and an access transistor connected to a data holding node of a H level can be reduced to a level at which the problem of a GIDL current is not caused. Consequently, current consumption in a standby mode can be reduced without causing the problem of a GIDL current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
More particularly, the present invention relates to a semiconductor memory device having a normal mode and a standby mode, a semiconductor integrated circuit device, and a portable device.

[0002]

2. Description of the Related Art A semiconductor memory device called an SRAM (Static Random Access Memory) has a feature that refresh is not required and easy to use since it has a basic structure of a flip-flop circuit. Another feature is that high-speed operation is possible and the operation margin is large. For this reason, it is frequently used in memories for portable devices. Furthermore, in recent years, portable devices have also been reduced in size with the miniaturization of transistors.

[0003]

The transistor has a feature that the withstand voltage decreases as the size becomes smaller. Therefore, when a fine transistor is used, it is necessary to lower the operating voltage of the transistor. Further, in order to operate at a low voltage without impairing the operation speed, the threshold value of the transistor must be lowered. Therefore, a low threshold transistor is used in a small portable device that is driven by a battery. However, if the threshold value is lowered too much, the transistor cannot be cut off sufficiently and a leak current flows.
This leakage current increases current consumption during standby.

[0004] In a small portable device that is driven by a battery,
Low voltage and low power operation is required. In particular, how long the standby time can be extended for a mobile phone is one of the decisive factors. To increase the standby time, it is necessary to reduce the current consumption during standby, that is, during standby.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of reducing current consumption during standby.

[0006]

According to one aspect of the present invention, a semiconductor memory device has a normal mode and a standby mode, and includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines, A plurality of access transistors and a potential difference supply unit are provided. The plurality of memory cells are arranged in rows and columns in a matrix. The plurality of word lines are arranged corresponding to each row of the plurality of memory cells. The plurality of bit lines are arranged corresponding to each column of the plurality of memory cells. The plurality of access transistors are provided corresponding to each of the plurality of memory cells, are connected between a data holding node of the corresponding memory cell and a bit line corresponding to the memory cell, and have a word corresponding to the memory cell. The line voltage is applied to the gate. In the standby mode, the potential difference supply unit is configured to access the access transistor connected to the data holding node holding the logic high level data or the access connected to the data holding node holding the logic low level data among the plurality of access transistors. A negative potential difference is applied between the gate and the source of the transistor.

Preferably, in the plurality of access transistors, a current of 100 pA / μm or more flows between the drain and the source when the potential difference between the gate and the source is 0 V.

In the above-described semiconductor memory device, in the standby mode, the access transistor connected to the data holding node holding the logic high level data or the data holding node holding the logic low level data among the plurality of access transistors. A negative potential difference is applied between the gate and the source of the connected access transistor. Accordingly, a leak current flowing from the data holding node holding logic high level data to the bit line via the access transistor or a leak current flowing from the bit line to the data holding node holding logic low level data via the access transistor Can be reduced.

Preferably, the potential difference supply means includes a potential holding means. When the potential holding means is in the standby mode,
The potentials of the plurality of bit lines are held at a predetermined positive level.

In the semiconductor memory device, in the standby mode, the potentials of the plurality of bit lines are higher than the potentials of the plurality of word lines. Therefore, a negative potential difference is applied between the gate and the source of the access transistor connected to the data holding node that holds the logic high level data among the plurality of access transistors. Thus, it is possible to reduce a leak current flowing from the data holding node that holds the logic high level data to the bit line via the access transistor. The GIDL current (G
ate Induced Drain Leakage
By maintaining the potentials of the plurality of bit lines at a level at which the current problem does not occur, the problem of the GIDL current can be avoided.

Preferably, the potential holding means includes means for floating a plurality of bit lines in a standby mode.

In the above-mentioned semiconductor memory device, in the standby mode, the bit line is precharged by a leak current flowing from the data holding node holding the data of the logic high level via the access transistor to the bit line. Thus, the potentials of the plurality of bit lines are maintained at a positive level.

Preferably, the potential difference supply means includes a word line drive means. The word line driving means supplies a negative voltage to the plurality of word lines in the standby mode.

In the above-mentioned semiconductor memory device, in the standby mode, the potentials of the plurality of word lines are lower than the potential of the data holding node that holds the logic low level data. Therefore, a negative potential difference is applied between the gate and the source of the access transistor connected to the data holding node that holds logic low level data among the plurality of access transistors. Thereby, a leak current flowing from the bit line to the data holding node holding the data of the logic low level via the access transistor can be reduced.

According to another aspect of the present invention, a semiconductor memory device has a normal mode and a standby mode, and includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of access transistors. , Word line driving means, and precharge means. The plurality of memory cells are arranged in rows and columns in a matrix. The plurality of word lines are arranged corresponding to each row of the plurality of memory cells. The plurality of bit lines are arranged corresponding to each column of the plurality of memory cells. The plurality of access transistors are provided corresponding to each of the plurality of memory cells, are connected between a data holding node of the corresponding memory cell and a bit line corresponding to the memory cell, and have a word corresponding to the memory cell. The line voltage is applied to the gate. The word line driving means activates a word line corresponding to a memory cell to be accessed among a plurality of word lines. The precharge means
The potentials of the plurality of bit lines are precharged to the power supply voltage level for a predetermined period before accessing the memory cell. In the standby mode, the word line driving means supplies a negative voltage to the plurality of word lines, and the precharge means electrically disconnects the plurality of bit lines from a power supply node receiving the power supply voltage.

In the above semiconductor memory device, in the standby mode, the potentials of the plurality of bit lines electrically disconnected from the power supply node are lower than the power supply voltage level because there is no supply from the power supply node. Normally, the voltage is stabilized at a level near the intermediate potential which is half the power supply voltage level. Thus, the voltage between the source and the drain of the access transistor connected to the data holding node can be reduced to a level at which the problem of the GIDL current does not occur.

As described above, according to the semiconductor memory device, in the standby mode, a negative voltage is supplied to the plurality of word lines and the plurality of bit lines are electrically disconnected from the power supply node. , The current consumption in the standby mode can be reduced.

Preferably, the semiconductor memory device further includes level holding means. The level holding means holds the potentials of the plurality of bit lines at a predetermined level in the standby mode.

Preferably, the predetermined level is a level lower than the intermediate potential.

In the semiconductor memory device, since the potentials of the plurality of bit lines are held at a predetermined level in the standby mode, the precharge period for returning from the standby mode to the normal mode may be set to a fixed period. it can.

Preferably, the word line driving means includes a ground voltage supply means and a negative voltage supply means. The ground voltage supply means supplies a ground voltage to the plurality of word lines in the standby mode. The negative voltage supply means supplies a negative voltage to the plurality of word lines after the ground voltage is supplied.

In the above-mentioned semiconductor memory device, the plurality of word lines are once pulled up to the ground voltage level by the ground voltage supply means at a high speed, so that the power consumption of the negative voltage supply means can be reduced.

According to still another aspect of the present invention, a semiconductor integrated circuit device includes the above-mentioned semiconductor memory device.

Preferably, the semiconductor integrated circuit device further includes a logic circuit section and supply switching means. The supply switching unit supplies the power supply voltage to the logic circuit unit in the normal mode, but does not supply the power supply voltage to the logic circuit unit in the standby mode. The precharge means in the semiconductor memory device further precharges the potentials of the plurality of bit lines to a power supply voltage level in response to switching from the standby mode to the normal mode.

According to still another aspect of the present invention, a portable device includes the above semiconductor integrated circuit device.

Preferably, the portable device further comprises mode switching signal supply means. The mode signal switching means includes:
A mode switching signal for instructing switching between the normal mode and the standby mode is supplied to the semiconductor integrated circuit.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

(First Embodiment) [Regarding the Configuration of the SRAM] FIG. 1 shows an SRAM according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating an overall configuration of an M (static random access memory). The SRAM shown in FIG. 1 includes a memory cell array 1, a row decoder 2, and a column decoder 3.
, A column selection circuit 4, an input / output circuit 5, precharge circuits 6 and 7, word drivers 8 and 9, a negative voltage generation circuit 10, and a NAND circuit 11.

The memory cell array 1 includes a memory cell MC1
-4, word lines WL0 and WL1, and a bit line pair (BL
0, / BL0), (BL1, / BL1), and access transistors NT1a-NT4a, NT1b-NT4b. Memory cells MC1-MC4 are arranged in rows and columns in a matrix. Word line WL0 is arranged corresponding to memory cells MC1 and MC3. Word line WL
1 is arranged corresponding to memory cells MC2 and MC4. Bit line pair BL0, / BL0 is connected to memory cell MC
1, MC2. Bit line pair BL1,
/ BL1 is arranged corresponding to memory cells MC3 and MC4. Access transistors NT1a-NT4a, N
T1b-NT4b is a low threshold transistor. Specifically, access transistors NT1a-NT
4a, when the potential difference between the gate and the source of NT1b-NT4b is 0 V, 100 pA / μm between the drain and the source.
The above current flows. Access transistor NT1a
Is a data holding node (not shown) of the memory cell MC1
And the bit line BL0, the gate of which receives the voltage of the word line WL0. Access transistor NT1b
Is a data holding node (not shown) of the memory cell MC1
And a bit line / BL0, and a word line WL0
To the gate. Access transistor NT2
a is connected between a data holding node (not shown) of the memory cell MC2 and the bit line BL0,
A voltage of 1 is applied to the gate. Access transistor NT
2b is connected between a data holding node (not shown) of memory cell MC2 and bit line / BL0, and word line W
The gate receives the voltage of L1. Access transistor N
T3a is connected between a data holding node (not shown) of memory cell MC3 and bit line BL1, and word line W3 is connected to bit line BL1.
The gate receives the voltage of L0. Access transistor N
T3b is connected between a data holding node (not shown) of memory cell MC3 and bit line / BL1, and receives the voltage of word line WL0 at its gate. Access transistor NT4a is connected between a data holding node (not shown) of memory cell MC4 and bit line BL1, and receives the voltage of word line WL1 at its gate. Access transistor NT4b is connected between a data holding node (not shown) of memory cell MC4 and bit line / BL1, and receives the voltage of word line WL1 at its gate.

The NAND circuit 11 outputs a NAND of the mode signal MD and the precharge control signal PR0. N
The output of the AND circuit 11 becomes the precharge signal PR1.

The row decoder 2 includes an inverter IV21,
NAND circuits ND21 and ND22. Inverter IV21 inverts address signal A1. NAND circuit ND21 outputs NAND of precharge signal PR1 and address signal A1. The output of the NAND circuit ND21 becomes the word line selection signal SW0. The NAND circuit ND22 includes a precharge signal PR1 and an inverter IV.
The NAND with the output of 21 is output. NAND circuit ND
The output of 22 becomes a word line selection signal SW1.

The negative voltage generating circuit 10 generates a negative voltage Vng.

The word drivers 8 and 9 constitute word line driving means. Word drivers 8 and 9 respond to word line selection signals SW0 and SW1 to supply power supply voltage VDD, ground voltage Vss or negative voltage Vng to word lines WL0 and Wng.
L1.

The column decoder 3 includes an inverter IV31,
AND circuits AD31 and AD32. Inverter I
V31 inverts the address signal A0. AND circuit A
D31 outputs an AND of the address signal A0 and the access signal R / W. AND circuit AD32 outputs AND of the output of inverter IV31 and access signal R / W.

The column selection circuit 4 includes inverters IV41, I41
V42 and transfer gates TG41-TG44. Inverters IV41 and IV42 are connected to AND circuit A
The outputs of D31 and AD32 are inverted. Transfer gates TG41 and TG42 are connected between bit lines BL0 and / BL and input / output lines IO and / IO. The transfer gates TG41, TG42 connect / disconnect the bit line pair BL0, / BL0 and the input / output line pair IO, / IO in response to the output of the AND circuit AD31. The transfer gates TG43, TG44 connect / disconnect the bit line pair BL1, / BL1 and the input / output line pair IO, / IO in response to the output of the AND circuit AD32.

The input / output circuit 5 transmits data read to the input / output line pair IO, / IO to the input / output terminal D in response to the access signal R / W, or transmits the data to the input / output terminal D from outside. The input data is transmitted to the input / output line pair IO, / IO.

The precharge circuit 6 is a P-channel MOS
Includes transistors PT61-PT63. P channel M
The OS transistors PT61 and PT62 are connected to the power supply voltage VD
D is connected between a power supply node receiving D and bit lines BL0 and / BL0, and is turned on / off in response to precharge signal PR1. P channel MOS transistor PT63
Is connected between bit line BL0 and bit line / BL0, and is turned on / off in response to precharge signal PR1.

The precharge circuit 7 is a P-channel MOS
Includes transistors PT71-PT73. P channel M
The OS transistors PT71 and PT72 are connected to the power supply voltage VD
D is connected between a power supply node receiving D and bit lines BL1 and / BL1, and is turned on / off in response to precharge signal PR1. P channel MOS transistor PT73
Is connected between the bit line BL1 and the bit line / BL1, and is turned on / off in response to the precharge signal PR1.

FIG. 2 is a circuit diagram of the memory cell MC1- shown in FIG.
FIG. 3 is a diagram showing a specific configuration of MC4. Memory cell MCi shown in FIG. 2 is a P-channel MOS transistor MPi
a, MPib and N-channel MOS transistor MNi
a, MNib (i = 1-4).

P channel MOS transistor MPia
Is connected between a power supply node receiving power supply voltage VDD and data holding node Nia. N-channel MOS transistor MNia is connected between data holding node Nia and a ground node receiving ground voltage Vss. P channel MOS transistor MPia and N channel M
The gate of the OS transistor MNia is connected to the data holding node Nib. P-channel MOS transistor MPib is connected between a power supply node and data holding node Nib. N-channel MOS transistor MNi
b is connected between the data holding node Nib and the ground node. The gates of the P-channel MOS transistor MPib and the N-channel MOS transistor MNib are
Connected to data holding node Nia.

The memory cell MCi configured as described above
Then, the 1-bit complementary data signal is held in the data holding nodes Nia and Nib.

Access transistor NTia (i = 1-4) shown in FIG. 1 is connected between bit lines BL0 and BL1 and data holding node Nia, and access transistor NTib is connected to bit lines / BL0 and / BL0. It is connected between BL1 and the data holding node Nib.

FIG. 3 is a circuit diagram of the negative voltage generating circuit 10 shown in FIG.
FIG. 3 is a diagram showing a specific configuration of FIG. 3 includes a ring oscillator 101 and an inverter 102.
, Capacitors C101-C104, and P-channel MO
And S transistors PT101 to PT106.

Ring oscillator 101 includes odd-numbered stages of inverters (not shown) connected in a ring shape, and outputs a signal having a predetermined oscillation frequency. Inverter 10
2 inverts the signal from the ring oscillator 101.
Capacitor C101 is connected between an output node of inverter IV102 and node N102. Capacitor C102 is connected between an output node of inverter IV102 and node N104. Capacitor C103
Is the output node of the ring oscillator 101 and the node 10
3 is connected. Capacitor C104 is connected between the output node of ring oscillator 101 and node N105.

P channel MOS transistor PT101
Is connected between the node N101 and the node N102. P-channel MOS transistor PT102 is connected between node N102 and a ground node receiving ground voltage Vss. P channel MOS transistor PT10
3 is connected between the nodes N101 and N103. P-channel MOS transistor PT104 is connected between node N103 and a ground node. P-channel MOS transistor PT105 is connected to node N104
And a ground node. P-channel MOS transistor PT106 is connected between node N105 and a ground node. P channel MOS transistor P
The gates of T101 and PT104 are connected to each other and to the node N104. P channel MO
The gates of S transistors PT102 and PT103 are connected to each other and to node N105. The gate of P-channel MOS transistor PT105 is connected to node N105. P channel MOS transistor PT106 has its gate connected to node N104.

In the negative voltage generating circuit configured as described above, the rising / lowering of the signal from ring oscillator 101
Charge pumping is performed in response to the fall, and a negative voltage Vng is generated at the node N101.

When generating the negative voltage Vng, the node N1
The electric charge supplied to 01 is stored in the capacitor 104 shown in FIG. Components of the capacitor 104 include a capacitance using a gate oxide film, a capacitance between wirings, a coupling capacitance with a word line, and the like.

The level (potential) of negative voltage Vng is clamped by PN junction diode 103 shown in FIG. 4 to an intermediate level between the built-in voltage level and the ground voltage Vss level. This potential is determined using existing analog technology, such as a combination of monitor and reference circuits.
It can be controlled to a desired level. GID described later
It is expected that the current is often set in the range of -0.3 V to -0.5 V according to the characteristics of the L current.

FIG. 5 shows the word driver 8 shown in FIG.
FIG. 9 is a diagram showing a specific configuration of No. 9; Word driver 8, 9
Have the same configuration, FIG. 5 shows the configuration of the word driver 8. The word driver shown in FIG. 5 includes inverters IV81 to IV92 and a NAND circuit N
D81, level shift circuits LS1, LS2, P-channel MOS transistor PT81, N-channel MOS
It includes transistors NT81 and NT82.

Inverters IV81-IV85 are connected in series. The word line selection signal SW0 is supplied to the input of the inverter IV81. The output of inverter IV85 is connected to one input of NAND circuit ND81. Inverters IV81-IV85 delay the word line selection signal SW0 by a predetermined time and supply it to one input of NAND circuit ND81. The NAND circuit ND81 outputs an N signal between the output of the inverter IV85 and the word line selection signal SW0.
Outputs AND. Inverter IV86 inverts the output of NAND circuit ND81. Inverter IV87
The word line selection signal SW0 is inverted. Inverter IV8
8 inverts the output of the inverter IV87. Inverters IV89-IV92 are connected in series. A word line selection signal SW0 is supplied to an input of the inverter IV89. Inverters IV89-IV92 delay word line select signal SW0 by a predetermined time and output.

The level shift circuit LS1 is a P-channel M
OS transistors PT91, PT92 and N-channel M
OS transistors NT91 and NT92 and inverter I
V93.

P channel MOS transistor PT91
Are the nodes N80 and N8 receiving the power supply voltage VDD.
2 and receives at its gate the output of inverter IV86. N-channel MOS transistor NT91
Is a node N81 receiving the node N82 and the negative voltage Vng.
Connected between N channel MOS transistor N
The gate of T91 is connected to node N83. Inverter IV93 inverts the output of inverter IV86. P-channel MOS transistor PT92 is connected between nodes N80 and N83, and is connected to inverter I
The output of V93 is received at the gate. N-channel MOS transistor NT92 is connected between nodes N83 and N81. N-channel MOS transistor NT9
The gate of 2 is connected to node N82.

The level shift circuit LS2 is a P-channel M
OS transistors PT93 and PT94 and N-channel M
OS transistors NT93 and NT94 and inverter I
V94.

P channel MOS transistor PT93
Are the nodes N90 and N9 receiving the power supply voltage VDD.
2 and receives at its gate the output of inverter IV92. N-channel MOS transistor NT93
Is a node N91 receiving the node N92 and the negative voltage Vng.
Connected between N channel MOS transistor N
The gate of T93 is connected to node N93. Inverter IV94 inverts the output of inverter IV92. P-channel MOS transistor PT94 is connected between nodes N90 and N93, and is connected to inverter I
The output of V94 is received at the gate. N-channel MOS transistor NT94 is connected between nodes N93 and N91. N-channel MOS transistor NT9
The gate of No. 4 is connected to node N92.

P channel MOS transistor PT81 and N channel MOS transistor NT81 are connected in series between a power supply node receiving power supply voltage VDD and a ground node receiving ground voltage Vss. P channel M
The gate of the OS transistor PT81 is connected to the inverter IV.
88 output is received. N channel MOS transistor N
The gate of T81 receives voltage Va of node N83.
P-channel MOS transistor PT81 and N-channel M
The voltage of interconnection node N84 with OS transistor NT81 is supplied to word line WL0.

N-channel MOS transistor NT82
Is connected between interconnection node N84 and a node receiving negative voltage Vng. The gate of N-channel MOS transistor N82 receives the voltage of node N93.

The word driver 8 configured as described above
Will be described with reference to FIG.

When word line select signal SW0 is at H level (logic high level), voltage Va at node N83 is at the negative voltage Vng level, and voltage Vb at node N93 is at the power supply voltage VDD level. Therefore, the N-channel MO
The S transistor NT81 is off, the N channel MOS transistor NT82 is on, and the P channel MOS transistor PT81 is off.

When word line select signal SW0 falls from H level (logic high level) to L level (logic low level), P channel MOS transistor PT81 is turned on in response to this. Also, the voltage V of the node N93
b falls to the negative voltage Vng level, and the N-channel MO
The S transistor NT82 turns off. As a result, the voltage of the node N84, that is, the voltage of the word line WL0 changes from the negative voltage Vng level to the power supply voltage VDD level.

The word line selection signal SW0 is changed from L level to H level.
When rising to the level, the P-channel MOS transistor PT81 is turned off. Also, the voltage Va of the node N83
Is a one-shot pulse in response to the rise of the word line selection signal SW0. Upon receiving this one-shot pulse, N-channel MOS transistor NT81 is turned on for a certain period, and node N84 is discharged. That is,
The voltage of word line WL0 goes from power supply voltage VDD level to ground voltage Vss level. After the voltage Va of the node N83 rises, the voltage of the node N93 is changed to the power supply voltage VDD.
Level and the N-channel MOS transistor NT82
Turns on. As a result, the voltage of the word line WL0 becomes
The level changes from the ground level Vss to the negative voltage Vng level.

As described above, in the word driver 8, the word line W is controlled by the N-channel MOS transistor NT81.
By temporarily pulling L0 to the level of the ground voltage Vss and then turning on the N-channel MOS transistor NT82, the charge accumulated in the capacitor 104 shown in FIG. The potential drops to the voltage Vng level. As a result, it is possible to realize high-speed pull-down of the word line and not to wasteful charges. That is, the power consumption of the negative voltage generation circuit 10 can be reduced.

[Operation of SRAM] Next, the operation of the SRAM configured as described above will be described with reference to the overall configuration diagram shown in FIG. 1 and the timing chart shown in FIG. Here, (1) normal mode,
(2) Standby mode will be described separately.

(1) Normal Mode When the mode signal MD is at the H level, the SRAM enters the normal mode. The normal mode refers to a period during which the memory cell MCi is accessed. This SRAM is controlled in the order of accessing in the first half of one cycle of the precharge signal PR0, performing precharge in the second half, and preparing for the next cycle. The precharge signal PR0 supplied from outside the SRAM is a signal synchronized with the external clock signal CLK. External clock signal CLK
Is a signal serving as a reference for operation.

At time t1, precharge signal PR
0 changes from H level to L level. In response, precharge signal PR1 attains H level. The access signal R / W changes from L level to H level. In order to access memory cell MC1 shown in FIG. 1, both address signals A0 and A1 attain H level. Address signal A
1 and the word line selection signal SW0 attains an L level in response to the precharge signal PR1. In response to this, word line WL0 is activated by word driver 8, and the voltage of word line WL0 attains the level of power supply voltage VDD. Then, N-channel MOS transistors NT1a, NT1
is turned on, and the data holding nodes N1a and N1b of the memory cell MC1 are connected to the bit line pair BL0 and / BL0.

On the other hand, in response to the address signal A0 and the access signal R / W, the transfer gates TG41, TG41, T
G42 turns on. Thereby, the bit line pair BL0, BL0,
/ BL0 is connected to input / output line pair IO, / IO.

When data is read from memory cell MC1, the complementary data of data holding nodes Nia and Nib are stored in bit line pair BL0 and / BL0, data input / output line pair IO and
/ IO, and transmitted to the input / output terminal D by the input / output circuit 5.

When writing data to memory cell MC1, data supplied to input / output terminal D is transmitted to bit line pair BL, / BL0 via data input / output line pair IO, / IO by data input / output circuit 5. Is done. Thus, the data signal read from memory cell MC1 to bit line pair BL0, / BL0 is rewritten.

At time t2, precharge signal PR
0 becomes H level. In response, the precharge signal PR1, the access signal R / W, and the address signals A0, A
1, becomes L level. Further, the transfer gate T
G41 and TG42 are turned off. Further, the word line selection signal SW0 becomes H level, and the voltage of the word line WL0 becomes negative voltage level. In response, an N-channel MOS
The transistors NT1a and NT1b are turned off.

In response to the precharge signal PR1 going low, the P-channel MOS transistors PT61-PT63 and PT71 in the precharge circuits 6 and 7 respond.
-PT73 is turned on. Thereby, the bit line BL
0, / BL0, BL1, / BL1 are connected to a power supply node receiving power supply voltage VDD, and are precharged to the power supply voltage VDD level. Further, a pair of bit lines BL0, / BL0 is provided by P-channel MOS transistor PT63.
However, bit line pair BL1 and / BL1 are equalized by P channel MOS transistor PT73, respectively. Thus, the preparation for the access at the subsequent time t3 to t4 is completed. Then, access and precharge are similarly performed in the cycle from time t3 to t5.

(2) Standby Mode When the mode signal MD is at L level, the SRAM enters the standby mode. Here, the standby mode refers to a period in which the access frequency to the memory cell is 10% or less of the access frequency in the normal mode.

At time t5, mode signal MD changes from H level to L level, and the SRAM enters the standby mode.

When mode signal MD goes low, precharge signal PR1 goes high regardless of the value of precharge signal PR0. In response, P-channel MOS transistors P in precharge circuits 6 and 7
T61-PT63 and PT71-PT73 are turned off.
As a result, the bit line pair BL0, / BL0, BL1, / B
L1 is electrically disconnected from the power supply node receiving power supply voltage VDD. That is, the precharge is stopped.

The word line selection signals SW0 and SW1 attain the H level, and the voltages of the word lines WL0 and WL1 attain the level of the negative voltage Vng.

Access signal R / W attains an L level, and transfer gates TG41-TG44 are turned off. Thereby, the bit line pair BL0, / BL0, BL
1, / BL1 and the input / output line pair IO, / IO are electrically disconnected.

Thereafter, the state of the standby mode continues until time t6.

Normally, the SRAM is controlled in the order of performing an access operation in the first half of one cycle, performing precharge in the second half, and preparing for the next cycle. Therefore, when the precharge operation is stopped in the standby mode, it is not possible to directly enter the normal mode, that is, the access operation in the first half of the cycle. However, in a portable device using an SRAM, it usually takes several milliseconds to return from a standby state (standby mode) to a normal operation state (normal mode) (power supply stabilization period described later). If a plurality of dummy cycles enter during that time, all bit lines can be returned to the precharged state, which is no problem. From such a viewpoint, the time t
A dummy cycle is provided between 6 and t7.

If such a dummy cycle cannot be provided, the above problem can be avoided by converting the control into a memory in which a precharge is performed at the beginning of the cycle and an access is performed thereafter. However, since the time from the access request to the actual output of the data becomes longer, the application range is limited to low-speed applications.

[Reduction Effect of Current Consumption in Standby Mode] Next, the reduction effect of current consumption in the standby mode will be described. Note that, for simplicity of description, the memory cells MC1 and MC2 will be described.

Referring to FIG. 8, in the conventional SRAM, in the standby mode, P channel MOS transistors PT61 to PT63 in precharge circuit 6 are turned on to bring bit line pair BL0 and / BL0 to the level of power supply voltage VDD. Precharged. Further, the word lines WL0, W
An L level (0 V) voltage is supplied to L1. Therefore, the memory cell M is supplied from the power supply node receiving the power supply voltage VDD via the access transistors NT1b and NT2a.
Leakage current I1 flows to the ground node in C1 and MC2.

This leak current I1 flows from the power supply node to the L-level data holding nodes of all memory cells. Therefore, in the entire SRAM, a leak current I1 that is obtained by multiplying the number of memory cells by the leak current of each access transistor flows. FIG. 8 shows only two memory cells MC1 and MC2. For example, if the leak current of the access transistor is 0.1 μA, 10
In an SRAM having 100,000 memory cells, a current of 100 mA flows. When used in a small portable device that is driven by a battery, this value is not at all an acceptable value as the current consumption value in the standby mode.

As a method of reducing the leak current I1, there is a method of applying a negative voltage (for example, -0.3 V) to the gates of the access transistors NT1b and NT2a. According to this method, access transistor NT1
b, the source of NT2a (L-level data holding node N
1b, N2a) -the gate is reverse biased, so that the leakage current I1 can be reduced.

However, with the recent miniaturization of transistors, a new problem has arisen. GIDL current (Gate-Induced-Drain-Leeka)
Ge-current). As shown in FIG. 9, the GIDL current has a negative gate voltage Vgs,
In addition, when the drain voltage Vds is near the power supply voltage VDD, the drain voltage Vds becomes large and poses a problem. To avoid this problem,
It is effective to reduce the drain voltage Vds.

Access transistors NT1b, NT2a
When a negative voltage (e.g., -0.3 V) is applied to the gate, the negative potential difference between the gate and the drain increases. This is because the bit line pair BL0, / BL0 is precharged to the power supply voltage VDD level. Assuming that the power supply voltage VDD is 1.5 V, the gate-drain voltage Vgd is
Vgd = −0.3−1.5 = −1.8V Therefore, the GIDL current I2 flows, and the current consumption during standby cannot be reduced.

In the SRAM according to the first embodiment, in order to solve the problem of the GIDL current, in the standby mode, the P-channel MOS transistors PT61 to PT63 and PT71 to PT73 of the precharge circuits 6 and 7 are turned off. , Bit line pair BL0, / BL0, BL1, / BL
1 is electrically disconnected from the power supply node receiving the power supply voltage VDD.

The potential of bit line pair BL0, / BL0, BL1, / BL1 electrically disconnected from the power supply node is lower than the power supply voltage VDD level because there is no supply from the power supply node. Normally, it is considered that the voltage becomes stable at a level near the intermediate potential (1/2 VDD). Hereinafter, description will be made with reference to FIG. FIG. 10 shows the P-channel MOS transistor MP1a and the access transistor N shown in FIG.
T1a, NT2a, N-channel MOS transistor MN
2a is shown. When the precharge is stopped, the voltage VBN of the bit line BL0 stabilizes near the intermediate potential level (about 0.75 V when the power supply voltage VDD is 1.5 V).
As a result, the drain voltage Vds2 of the access transistor NT2a becomes about 0.75V. As a result, the current I2b flowing through the access transistor NT2a is
As shown in (2), it is reduced from I2 to I3. Further, the drain voltage Vds1 of the access transistor NT1a connected to the H-level data holding node N1a is also about 0.7.
5V, and the current I2b flowing through the access transistor NT1a also becomes about I3 as shown in FIG.

Thus, bit line pair BL0, / BL
By electrically disconnecting 0, BL1, and / BL1 from the power supply node, the source-drain voltage of both the access transistor connected to the L-level data holding node and the access transistor connected to the H-level data holding node Can be set to a level at which the problem of the GIDL current does not occur.

As described above, according to the first embodiment,
In the standby mode, the negative voltage V is applied to the word lines WL0 and WL1.
ng, and a pair of bit lines BL0, / BL0, B
Since L1 and / BL1 are electrically separated from the power supply node, current consumption in the standby mode can be reduced without causing a problem of GIDL current.

(Second Embodiment) An SRAM according to a second embodiment of the present invention has, in addition to the configuration shown in FIG. 1, a 1/2 VDD generating circuit 12 shown in FIG. 14.

The 1/2 VDD generating circuit 12 is a known circuit, receives the power supply voltage VDD, and receives one-half of the power supply voltage VDD.
A two-level voltage 1/2 VDD is generated.

The level holding circuit 13 is a P-channel MOS
Includes transistors PT131-PT133. P channel MOS transistor PT131 has a voltage of 1/2 VDD
And is turned on / off in response to mode signal MD. P channel M
OS transistor PT132 is connected between a node receiving voltage 1 / 2VDD and node N132, and turns on / off in response to mode signal MD. Node N131,
N132 is connected to bit lines BL0 and / BL0, respectively. P-channel MOS transistor PT133 is
It is connected between nodes N131 and N132, and turns on / off in response to mode signal MD.

The level holding circuit 14 is a P-channel MOS
Includes transistors PT141-PT143. P channel MOS transistor PT141 has a voltage of 1/2 VDD
And is turned on / off in response to mode signal MD. P channel M
OS transistor PT142 is connected between a node receiving voltage 1 / 2VDD and node N142, and turns on / off in response to mode signal MD. Node N141,
N142 is connected to bit lines BL1 and / BL1, respectively. P-channel MOS transistor PT143 has
It is connected between nodes N141 and N142, and turns on / off in response to mode signal MD.

In this SRAM, in standby mode, P
Channel MOS transistors PT131-PT133,
PT141-PT143 is turned on, and the bit line pair BL
0, / BL0, BL1, / BL1 are １ ／
It is kept at the VDD level. Thereby, in addition to the effect of reducing the current consumption similar to that of the first embodiment, the following effect is further obtained.

In the first embodiment, the bit line pair B
L0, / BL0, BL1, and / BL1 are floating, and their voltage levels are not constant. Therefore, the precharge period (dummy cycle period shown in FIG. 7) when returning from the standby mode to the normal mode cannot be set to a fixed period.

However, according to the second embodiment, the pair of bit lines BL0, / BL0, BL1, / 1 / in the standby mode is set.
Since the voltage level of BL1 is held at a constant level (1/2 VDD level), the precharge period (dummy cycle period shown in FIG. 7) when returning from the standby mode to the normal mode can be set to a fixed period. .

Here, the voltage level of the bit line is held at the Ｖ VDD level, but the held level may be any level as long as it is lower than the power supply potential VDD. Preferably, the level is equal to or lower than the intermediate potential 1/2 VDD level.

(Third Embodiment) FIG. 12 is a block diagram showing a configuration of a portable device according to a third embodiment of the present invention. The mobile device 200 illustrated in FIG. 12 includes a standby microcomputer 210 and a system LSI 220.
An example of such a mobile device 200 is, for example, a mobile phone.

The standby microcomputer 210 is a portable device 2
As a system 00, the power is always on. Further, a mode switching signal CTA for instructing switching between the normal mode and the standby mode is supplied to the system LSI 220.

The system LSI 220 includes a control circuit 221
, SRAMs 222 and 223, and a logic circuit 224
And a switch 225.

The control circuit 221 includes the standby microcomputer 2
The mode signal MD is supplied to the SRAM 222 and the switch signal CTB is supplied to the switch 225 in response to the mode switching signal CTA from the terminal 10. The SRAM 222 is similar to the SRAM shown in FIG. 1, and has an effect of reducing current consumption in the standby mode. In the SRAM 222,
The power supply voltage VDD is supplied also in the standby mode. S
The power is not supplied to the RAM 223 in the standby mode in order to cut off the leak current in the standby mode. Switch 225 is connected between a power supply node receiving power supply voltage VDD and power supply nodes of SRAM 223 and logic circuit 224, and is turned on / off in response to switching signal CTB. When the switch 225 is on, the SRAM
The power supply voltage VDD is supplied to the logic circuit 223 and the logic circuit 224. When the power supply voltage VDD is off, the power supply voltage VDD is not supplied.

That is, in the system LSI 220, power is always supplied only to the control circuit 221 and the SRAM 222 that exchange data with the standby microcomputer 210.

Next, the operation of the portable device configured as described above will be described with reference to FIG.

When the mode shifts from the normal mode to the standby mode (for example, when the mobile phone waits), the standby microcomputer 210 supplies a mode switching signal CTA for shifting to the standby mode to the system LSI 220. This corresponds to the mode switching signal CTA falling from H level to L level at time t11.

In response to mode switching signal CTA, control circuit 221 provides mode signal MD and switching signal CTB.
To the L level. The switch 225 is turned off in response to the L-level switching signal CTB. Thus, power supply to the SRAM 223 and the logic circuit 224 is cut off. On the other hand, in response to the L-level mode signal MD, the SRAM 222 stops the precharge operation.

When returning from the standby mode to the normal mode,
The mode switching signal CTA becomes H level (t12). In response, switching signal CTB attains H level, and switch 225 is turned on. On the other hand, the mode signal MD becomes H level, and the SRAM 222 starts precharging. During the standby mode, the bit line of the SRAM 222 is electrically disconnected from the power supply node, and thus has a lower potential. Therefore, when all the bit lines are precharged at the same time when starting the precharge, a large peak current is expected to flow. Therefore, it is desirable to perform the precharge stepwise with a time lag. For example, dividing several bit lines into several groups,
It is desirable to perform a precharge with a time difference for each group. It is expected that it takes several milliseconds from when the switch 225 is turned on until the voltage Vint stabilizes at the power supply voltage VDD level (t12-t13).
Thus, there is time until the system LSI 220 stably starts operating. Therefore, the SRAM 22
2 has a sufficient return time to the precharge state (dummy cycle shown in FIG. 7), and the above-described stepwise precharge is possible.

(Fourth Embodiment) FIG. 14 is a block diagram showing an entire configuration of an SRAM according to a fourth embodiment of the present invention. The SRAM shown in FIG. 14 includes a memory cell array 1, a row decoder 2, a column decoder 3, a column selection circuit 4, an input / output circuit 5, precharge circuits 6 and 7, word drivers 1401 and 1402, a NAND Circuit 11
And Word drivers 1401 and 1402 are H
The power supply voltage VDD is supplied to the word lines WL0 and WL1 in response to the word line selection signals SW0 and SW1 of the level, and the ground voltage Vss (= 0 V) is supplied to the word lines in response to the word line selection signals SW0 and SW1 of the L level. It is supplied to WL0 and WL1.

Next, the effect of reducing the current consumption in the standby mode of the SRAM shown in FIG. 14 will be described. Note that, for simplicity of description, the memory cells MC1, MC2
Will be described.

In the standby mode, word lines WL0, WL
1 is supplied with the ground voltage Vss (= 0 V), and the access transistors NT1a, NT1b, NT2a, NT2b are turned off. Also, transfer gate TG41-TG
44 and P-channel MOS transistor PT61-P
T63, PT71-PT73 are turned off and bit line B
L0, / BL0, BL1, / BL1 become floating. However, as shown in FIG.
1, data holding nodes N1a and N2b for holding H-level data from power supply nodes of MC2 and P2 MOS transistors MP1a and MP2b; access transistors NT1a and NT2b; bit lines BL0 and
/ BL0-access transistors NT2a, NT1
b-Data holding node N holding data at L level
2a, N1b-N-channel MOS transistor MN
2a, MN1b- Leakage current Ix flows in the path leading to the ground node. This is because the access transistor NT1
This is because the threshold values of a, NT1b, NT2a, and NT2b are low. The bit lines BL0, /
The potential of BL0 is maintained at a positive level higher than the ground voltage Vss (= 0 V) and lower than the power supply voltage VDD. As a result, a negative potential difference is applied between the gates and sources of access transistors NT1a and NT2b. Therefore, although the leak current Ix flows through the access transistors NT1a and NT2b, the amount of the current is reduced by the negative potential difference between the gate and the source.

As described above, the potential of bit lines BL0 and / BL0 is maintained at a positive level by leak current Ix. However, that level is not always constant. A level close to the ground voltage Vss (= 0 V) level (for example,
0.1V). At this time, the gate-source voltage Vgs of the access transistors NT1a and NT2b becomes negative (−0.1 V), and the drain-source voltage Vds becomes the power supply voltage VDD (here, VDD = 1.
5V). Therefore, FIG.
GIDL current (I11) flows as shown in FIG. To avoid the problem of the GIDL current, FIG.
2 and the level holding circuits 13, 14 and 1 /
The 2VDD generation circuit 12 may be provided. Then, as shown in FIG. 17, bit lines BL0, //
The potential (VNB) of BL0 becomes 1/2 VDD level,
Drains of access transistors NT1a, NT2b
The source-to-source voltage Vds is about 1/2 VDD level (0.75
V). As a result, as shown in FIG. 16, the level of the GIDL current is reduced to the level I12 at which there is no problem. The level holding circuits 13, 14 and 1/2 VD
The bit lines BL0 and / BL0 may be precharged to the 1/2 VDD level by the precharge circuits 6 and 7 without providing the D generation circuit 12. The level to hold is 1
/ 2VDD level. The GIDL current may be maintained at a level that does not cause a problem of the GIDL current in a range higher than the ground voltage Vss level (0 V) and lower than the power supply voltage VDD level.

[0109]

In the semiconductor memory device according to one aspect of the present invention, since the potential difference supply means is provided, the current consumption in the standby mode can be reduced.

Further, since the potential difference supply means includes the potential holding means, it is possible to reduce a leak current flowing from the data holding node holding logic high level data to the bit line via the access transistor.
The problem of the L current can be avoided.

Further, since the potential difference supplying means includes the word line driving means, it is possible to reduce a leak current flowing from the bit line to the data holding node holding data of a logic low level via the access transistor.

In the semiconductor memory device according to another aspect of the present invention, in the standby mode, the word line driving means supplies a negative voltage to the plurality of word lines, and the precharge means connects the plurality of bit lines to the power supply node. , The current consumption in the standby mode can be reduced without causing the problem of the GIDL current.

Further, since the level holding means is provided, the precharge period when returning from the standby mode to the normal mode can be set to a fixed period.

Since the word line driving means includes the ground voltage supplying means and the negative voltage supplying means, the power consumption of the negative voltage supplying means can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire configuration of an SRAM according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a memory cell shown in FIG.

FIG. 3 is a diagram illustrating a configuration of a negative voltage generation circuit illustrated in FIG. 1;

FIG. 4 is a diagram showing a configuration of a capacitor and a diode added to a node receiving a negative voltage.

FIG. 5 is a diagram showing a configuration of a word driver shown in FIG. 1;

FIG. 6 is a timing chart for explaining an operation of the word driver shown in FIG. 5;

FIG. 7 is a timing chart for explaining the operation of the SRAM shown in FIG. 1;

FIG. 8 is a diagram for explaining an effect of reducing current consumption in a standby mode.

FIG. 9 is a diagram for describing a GIDL current.

FIG. 10 is a diagram for explaining an effect of reducing current consumption in a standby mode.

FIG. 11 is a diagram showing a configuration of an SRAM according to a second embodiment of the present invention;

FIG. 12 is a block diagram showing a configuration of a portable device according to a third embodiment of the present invention.

FIG. 13 is a timing chart for explaining the operation of the mobile device shown in FIG.

FIG. 14 is a block diagram showing an entire configuration of an SRAM according to a fourth embodiment of the present invention.

FIG. 15 is a diagram showing a leak current flowing in a standby mode.

FIG. 16 is a diagram for explaining a GIDL current.

FIG. 17 is a diagram for describing an effect of reducing current consumption in a standby mode.

[Explanation of symbols]

MC1-MC4 Memory cell WL0, WL1 Word line BL0, / BL0, BL1, / BL1 Bit line NT1a-NT4a, NT1b-NT4b Access transistor N1a-N4a, N1b-N4b Data holding node 6,7 Precharge circuit 8,9, 1401, 1402 Word driver 10 Negative voltage generation circuit 13, 14 Level holding circuit 200 Portable device 210 Standby microcomputer 220 System LSI 222, 223 SRAM 224 Logic circuit 225 Switch

Claims (13)

[Claims] 1. A semiconductor memory device having a normal mode and a standby mode, comprising: a plurality of memory cells arranged in a matrix in rows and columns; and a plurality of memory cells arranged corresponding to each row of the plurality of memory cells. A plurality of bit lines arranged corresponding to each column of the plurality of memory cells; and a data holding node of a corresponding memory cell provided corresponding to each of the plurality of memory cells. A plurality of access transistors connected between a bit line corresponding to the memory cell and receiving a voltage of a word line corresponding to the memory cell at a gate; and a logic high level of the plurality of access transistors in a standby mode. An access transistor connected to a data holding node that holds data or a data holding node that holds logic low-level data The gate of the connection has been access transistor - a semiconductor memory device, characterized in that it comprises a potential supply means for providing a negative potential difference between the source. 2. The semiconductor memory device according to claim 1, wherein a current of 100 pA / μm or more flows between a drain and a source when a potential difference between a gate and a source is 0 V. A semiconductor memory device characterized by the above-mentioned. 3. The semiconductor memory device according to claim 1, wherein said potential difference supply means includes a potential holding means for holding potentials of said plurality of bit lines at a predetermined positive level in a standby mode. A semiconductor memory device characterized by the following. 4. The semiconductor memory device according to claim 1, wherein said potential difference supply means includes means for floating said plurality of bit lines in a standby mode. 5. The semiconductor memory device according to claim 1, wherein said potential difference supply means includes word line drive means for supplying a negative voltage to said plurality of word lines in a standby mode. Storage device. 6. A semiconductor memory device having a normal mode and a standby mode, comprising: a plurality of memory cells arranged in a matrix in rows and columns; and a plurality of memory cells arranged corresponding to each row of the plurality of memory cells. A plurality of bit lines arranged corresponding to each column of the plurality of memory cells; and a data holding node of a corresponding memory cell provided corresponding to each of the plurality of memory cells. A plurality of access transistors connected between a bit line corresponding to a memory cell and a gate receiving a voltage of a word line corresponding to the memory cell; a word corresponding to a memory cell to be accessed among the plurality of word lines; Word line driving means for activating a line; and precharging the potentials of the plurality of bit lines to a power supply voltage level for a predetermined period before accessing a memory cell. A word line driving means for supplying a negative voltage to the plurality of word lines; and a power supply receiving a power supply voltage for the plurality of bit lines in a standby mode. A semiconductor memory device which is electrically disconnected from a node. 7. The semiconductor memory device according to claim 6, further comprising: means for holding the potentials of said plurality of bit lines at a predetermined level in a standby mode. 8. The semiconductor memory device according to claim 7, wherein said predetermined level is a level equal to or lower than an intermediate potential. 9. The semiconductor memory device according to claim 6, wherein said word line driving means is configured to supply a ground voltage to said plurality of word lines in a standby mode, after said ground voltage is supplied. Means for supplying a negative voltage to the plurality of word lines. 10. A semiconductor integrated circuit device comprising the semiconductor memory device according to claim 6. 11. The semiconductor integrated circuit device according to claim 10, wherein a power supply voltage is supplied to a logic circuit unit and said logic circuit unit in a normal mode, and said power supply voltage is supplied to said logic circuit unit in a standby mode. And a supply switching unit that does not supply, wherein the precharge unit in the semiconductor memory device precharges the potentials of the plurality of bit lines to a power supply voltage level in response to switching from a standby mode to a normal mode. Semiconductor integrated circuit device. 12. A portable device comprising the semiconductor integrated circuit device according to claim 10. 13. The portable device according to claim 12, further comprising means for supplying a mode switching signal for instructing switching between a normal mode and a standby mode to said semiconductor integrated circuit.