JP2001344185A - Information processing device and i/o emulation control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To securely emulate the operation of an I/O device capable of dynamically mapping an I/O address with a software. SOLUTION: An I/O trap SMI is utilized as a program interface for starting an I/O emulation routine, and a software SMI to be periodically published is utilized as a program interface for starting an I/O address change detecting routine. The I/O address change detecting routine monitors a changeover of the I/O address of an I/O device 14 by an operating system, and when the I/O address is changed, the I/O address change detecting routine automatically renews a value of the I/O base address set in a trap address setting register 156 of an I/O trap SMI generating circuit 151 in response to the change of the I/O address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing apparatus capable of emulating the operation of an I / O device by software and an I / O emulation control method.

[0002]

2. Description of the Related Art In recent years, with the improvement of the communication interface of a computer system and the increase in the number of functions, in information processing apparatuses such as personal computers, new I / O devices have been added in addition to conventional legacy I / O devices. The implementation of is beginning to be required. As such a new I / O device, for example, a USB interface or IEEE
Examples include a controller such as an E1394 interface or a mobile phone interface.

By the way, in the field of information processing technology, an emulation technology for emulating specific hardware functions by software has been known. This emulation is effective for, for example, solving a bug occurring in a specific I / O port of an I / O device or providing a function of an I / O port that does not actually exist.

[0004]

SUMMARY OF THE INVENTION However, recent I / O
Many devices have PCI specifications, and depending on the emulation method to be applied, there is a danger that problems such as a failure to execute a correct emulation operation may occur. P
This is because an I / O device conforming to the CI specification is configured so that an I / O address can be dynamically mapped, and an I / O address map may be switched by an operating system.

The present invention has been made in view of the above circumstances, and has been made in consideration of an I / O address capable of dynamically mapping an I / O address.
An object of the present invention is to provide an information processing apparatus and an I / O emulation control method capable of reliably emulating the operation of an O device.

[0006]

In order to solve the above-mentioned problems, the present invention relates to an information processing apparatus capable of dynamically mapping an I / O address to an I / O device.
U and the I / O address of the I / O device are set as an I / O address for interrupt activation, and the I / O address from the CPU indicating the I / O address for interrupt activation.
Means for trapping an access and issuing a first interrupt signal to the CPU; and I / O activated by the first interrupt signal and emulating an operation of an I / O device specified by the I / O address. Emulation means, means for monitoring a change in the setting of an I / O address for the I / O device by the CPU, and I / O for starting the interrupt in response to the change in the setting of the I / O address for the I / O device. Means for updating the value of the O address.

In this information processing apparatus, an I / O address of an I / O device to be emulated is set as an I / O address for interrupt activation.
When an I / O access indicating the I / O address for interrupt activation is issued from the CPU, the trap is trapped and a first interrupt signal is issued to the CPU. The I / O emulation means is automatically started by the first interrupt signal, and the I / O emulation means specified by the I / O address from the CPU is started.
The operation of the / O device is emulated. In this method, since the I / O emulation means can be realized by an interrupt program, the operation of the I / O can be easily emulated without changing an application program, a driver, or the like. The address needs to match the emulation target I / O address.

Therefore, according to the present invention, even if the I / O address to be emulated is switched by the operating system, the setting change of the I / O address can be changed so that the I / O address for interrupt activation can be changed accordingly. Means for monitoring the I / O device
In response to the change in the setting of the / O address, I
Means for updating the value of the / O address.
By these means, the value of the I / O address for interrupt activation can be adjusted to the I / O address assigned to the I / O device, and the operation of the I / O device can be reliably emulated. .

As means for monitoring a change in the setting of the I / O address, means for periodically polling the value of the I / O base address set in the configuration space of the I / O device can be used. . In this case, at the time of polling, it is preferable to determine whether or not the I / O device is in the operation prohibited state, and to prohibit issuing the first interrupt signal when the I / O device is in the operation prohibited state. . As a result, it is possible to prevent a useless interrupt from occurring.

[0010] Further, the second interrupt signal is transmitted to an I / O
A mechanism is generated by trapping a configuration access from a CPU indicating a predetermined address belonging to a device configuration space,
Thereby, it is also possible to activate the monitoring means. This eliminates the need for a technique such as a timer interrupt as in the case of using polling, thereby improving system performance.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of an information processing apparatus according to an embodiment of the present invention. The information processing apparatus is a computer system such as a notebook personal computer, for example, and includes a CPU 11,
Host-PCI bridge 12, main memory 13, I / O device 14, system controller 15, PCI-IS
An A-bridge 16 and a BIOS-ROM 17 are incorporated.

The CPU 11 controls the operation of the entire system and executes data processing. As the CPU 11,
System management interrupt SMI (SMI; System Man)
Those that support agement interrupts are used. That is, in addition to the normal operation mode for executing the operating system, the application, and the like, the CPU 11 includes a system management mode (SMM; System Ma).
The system has an operation mode for realizing a system management function called a “management mode”.

System management interrupt (SMI; System)
When a Management Interrupt is issued to the CPU 11, the operation mode of the CPU 11 is the normal operation mode (real mode, protect mode, or virtual 86 mode).
Is switched to SMM. In the SMM, a system management program such as an I / O emulation routine for emulating the operation of an I / O device is executed.

The SMI is a type of non-maskable interrupt NMI, but is the highest priority interrupt having a higher priority than a normal NMI or maskable interrupt INTR. This SM
By issuing I, the system management program can be started without depending on the environment of the running application program or the operating system.

The host-PCI bridge 12 is a bridge LSI for connecting between the CPU bus 1 and the PCI bus 2, and has a built-in memory controller for controlling the main memory 13. I / O device 14 is PC
It is an I / O device (PCI device) of the I specification. In this system, it is a target device to be emulated by an I / O emulation program. This I / O device 14 is
The O address is configured to be dynamically mappable.
The I / O device 14 includes a configuration register group and an I / O register group. I /
The I / O address space to be assigned to the O register group is
It is determined according to the value of the I / O base address register (I / O base address) defined in the configuration register group in the I / O device 14. This I
The value of the / O base address is dynamically rewritten by the operating system as needed.

The system controller 15 includes a CPU 1
For example, hardware for controlling the generation of the SMI signal to S.1 is incorporated. The system controller 15 actually communicates with the host-PCI bridge 12 described above and a P
It can be built in the CI-ISA bridge 16.

The PCI-ISA bridge 16 is a bridge LSI connecting the PCI bus 2 and the ISA bus 3. I
A BIOS-ROM 17 is connected to the SA bus 3. The BIOS-ROM 17 stores the system BIOS (Bas
ic I / O System),
It is composed of a flash memory so that the program can be rewritten. The system BIOS systematizes a function execution routine for accessing various hardware in the system, and is configured to operate in a real mode. This system BIO
S includes an IRT routine executed when the system is powered on, and a group of BIOS drivers for various hardware controls. Each BIOS driver includes a plurality of function execution routine groups corresponding to the functions for providing a plurality of functions for hardware control to an operating system or an application program.

The BIOS-ROM 17 contains an SMI
A system management program (SMM-BIOS) executed in the SMM such as a service routine is also stored. The system management program includes the above-described I / O emulation routine, an I / O address change detection routine for monitoring switching of the I / O address of the I / O device 14 by the operating system, and the like.

Next, the hardware configuration for controlling SMI generation provided in the system controller 15 will be described.

As shown, the system controller 15 includes an I / O trap SMI generation circuit 151, a software SMI generation circuit 152, an SMI generation circuit 153 due to other factors, an OR circuit 154, and an SMI status register 155. . The I / O trap SMI generation circuit 151 is a circuit for generating an I / O trap SMI signal, and includes a P / S signal belonging to a predetermined address range.
The I / O address on the CI bus 2 is trapped to generate an I / O trap SMI signal. This I / O trap SM
As shown, the I generation circuit 151 includes a trap address setting register 156, an I / O trap circuit 157, and a mask register 158.

The trap address setting register 156 stores C
PU11 is a readable / writable register.
It is connected to the I bus 2. The trap address setting register 156 stores the I / O to be emulated.
The I / O base address of the device 14 is held as an I / O address (trap address) for interrupt activation. This I / O base address is set in the trap address setting register 156 by the IRT routine when the system is powered on, for example. When the I / O base address of the I / O device 14 is changed by the operating system after the system is started, the contents of the trap address setting register 156 are changed by the I / O address change detection routine that detects the change. It is rewritten according to the I / O base address of the device 14.

The I / O trap circuit 157 has an IO read /
I output on PCI bus 2 in a write cycle
The I / O address is compared with the I / O base address of the trap address setting register 156, and the I / O address is
Generates an I / O trap SMI signal when it belongs to the address range specified by the / O base address.

The mask register 158 is a register readable and writable by the CPU 11, and is connected to the PCI bus 2. This mask register 158 holds mask data for permitting or prohibiting the generation of the I / O trap SMI signal.

The software SMI generation circuit 152 has a timer and a control register, and the software SMI generation circuit 152 generates the software SMI at a predetermined time-out time interval specified by the control register.
MI is periodically generated. The OR circuit 154 includes an I / O trap SMI generation circuit 151, a software SMI generation circuit 152, and the SMI generation circuit 15 due to other factors.
3 generates an SMI signal, and supplies the SMI signal to the CPU 11. The SMI status register 155 holds status data indicating an SMI generation factor, and outputs the outputs of the I / O trap SMI generation circuit 151, the software SMI generation circuit 152, and the SMI generation circuit 153 due to other factors. Hold.

FIG. 2 shows the relationship between the I / O emulation routine and the I / O address change detection routine and the program interface for activating them. As shown in FIG. 2, the I / O trap SMI is used as a program interface for starting an I / O emulation routine,
The software SMI is used as a program interface for activating an I / O address change detection routine.

Next, the mechanism of I / O emulation used in this embodiment will be described with reference to FIG.

When an operating system or an application program executes an IN or OUT instruction for specifying an I / O address to be emulated,
An I / O trap SMI is issued from the I / O trap SMI generating circuit 151, whereby the I / O emulation routine of the SMM-BIOS is started. I / O
The emulation routine emulates the function of a specific I / O port (I / O register) of the I / O device 14, and first refers to the register value in the CPU 11 to determine the I / O port to be emulated. Confirm that it is the specified IN or OUT instruction.
If the instruction is an IN or OUT instruction designating an I / O port to be emulated, the I / O emulation routine executes the I / O port to be emulated.
A predetermined emulation process corresponding to the operation of the O port is executed, and a process of returning data to an operating system or an application program instead of actual hardware is performed. Note that the hardware, that is, the I / O device 14 does not function for an IN or OUT instruction that specifies an I / O port to be emulated.

When the emulation processing is completed, I /
Control is returned to the operating system or application program that interrupted the O emulation routine.

Next, referring to the flowchart of FIG.
The processing of the I / O address change detection routine will be described.

As described above, the I / O address change detection routine is periodically started by the software SMI. In the I / O address change detection routine, first, the configuration register of the I / O device 14 to be emulated is read-accessed, and the value of the I / O base address of the I / O device 14 set therein is emulated. It is acquired as a target I / O address (step S101). Even if the value of the I / O base address is rewritten, the current I / O base address can be normally acquired from the I / O device 14 because the configuration address of the configuration register does not change.

Next, the I / O address change detection routine determines whether the acquired I / O base address is a predetermined invalid address or not.
Is set to the operation prohibited state (disabled) or the operation state (enabled) (step S102). If the acquired I / O base address is an invalid address, that is, if the I / O device 14 is in the operation prohibited state (step S102)
NO), since there is no need for I / O emulation,
The I / O address change detection routine uses the I / O trap S
The mask data for prohibiting the occurrence of MI is written in the mask register 158 (step S114), and the process ends. As a result, it is possible to prevent the performance from deteriorating due to the occurrence of the unnecessary I / O trap SMI.

On the other hand, if the acquired I / O base address is a valid address, that is, if the I / O device 14 is operating (YES in step S102),
The I / O address change detection routine uses the mask register 1
58, referring to the mask data of I / O trap SMI
It is determined whether or not the occurrence of an error is permitted (step S
104). If the generation of the I / O trap SMI is prohibited, the I / O address change detection routine
The mask data for permitting the generation of the trap SMI is written into the mask register 158, and the I / O trap SM
I is made valid (step S105). Next, the I / O address change detection routine acquires an I / O address (I / O base address) for starting the I / O trap SMI from the trap address setting register 156 (step S).
106), it is compared with the I / O base address acquired in step S101 (step S107). If they do not match (NO in step S107), the I / O
The address change detection routine determines that the operating system has dynamically switched the I / O address of the I / O device 14, and obtains the I / O address acquired in step S101.
/ O base address to trap address setting register 1
Then, the I / O address for starting the I / O trap SMI is changed to the current I / O emulation address (step S108).

As described above, the I / O address change detection routine is periodically started by the software SMI,
By polling the I / O address of the I / O device 14, the I / O address for starting the I / O trap SMI can follow the switching of the I / O emulation address. As a result, even if the operating system dynamically switches the I / O address of the I / O device 14, the I / O emulation can be normally continued thereafter.

(Second Embodiment) Next, a second embodiment of the present invention will be described. The second embodiment differs from the first embodiment only in the method of activating the I / O address change detection routine and the processing procedure of the I / O address change detection routine, and the other points are the same as those of the first embodiment. is there.

That is, in the second embodiment, as shown in FIG. 5, two I / O trap SMI generating circuits 15 having different I / O trap SMI activation I / O address values.
1a and 151b are used. These I / O traps S
Both the MI generation circuits 151a and 151b are built in the system controller 15. Each of the I / O trap SMI generation circuits 151a and 151b has the same configuration as the I / O trap SMI generation 151 in FIG. I / O
In the trap address setting register of the trap SMI generating circuit 151a, the base address of the configuration space of the I / O device 14 is set as a configuration address for starting the I / O trap SMI. Thus, when the operating system accesses the configuration register of the I / O device 14, the first I / O trap SMI # 1 is generated from the I / O trap SMI generation circuit 151a. Also, I / O
The trap address setting register of the trap SMI generation circuit 151b stores the I / O trap SMI of the first embodiment.
Similarly to the generation 151, the I / O base address of the I / O device 14 is set. Thus, when the operating system accesses the I / O port to be emulated of the I / O device 14, the second I / O trap SMI # 2 is generated from the I / O trap SMI generation circuit 151b.

FIG. 6 shows the relationship between the I / O emulation routine and the I / O address change detection routine and the program interface for activating them. As shown in FIG. 6, the first I /
The O trap SMI # 1 is used as a program interface for activating an I / O address change detection routine, and the second I / O trap SMI # 2 is
It is used as a program interface for starting an O simulation routine.

Since the processing procedure of the I / O simulation routine is the same as that of the first embodiment, the processing procedure of the I / O address change detection routine of the second embodiment will be described below with reference to the flowchart of FIG. Will be described.

When the operating system executes an instruction for accessing the configuration register of the I / O device 14 (OUT instruction to the configuration space), the I / O trap SMI generation circuit 15
An I / O trap SMI # 1 is issued from 1a, whereby the I / O emulation routine of the SMM-BIOS is started.

The I / O address change detection routine first refers to the register in the CPU 11 to determine whether or not the write is to the I / O base address register (I / O base register) in the configuration register. (Step S111). If it is not a write to the I / O base address register (NO in step S111),
The O address change detection routine ends the process at that time.

If the write is to the I / O base address register (YES in step S111),
The O address change detection routine performs read access to the configuration register of the I / O device 14 and acquires the value of the I / O base address of the I / O device 14 set therein as the emulation target I / O address. (Step S112). Then I / O
The address change detection routine determines whether the I / O device 14 is set to the operation inhibition state (disabled) or the operation state (enabled) depending on whether the acquired I / O base address is a predetermined invalid address. ) Is determined (step S113). If the acquired I / O base address is an invalid address, that is, if the I / O device 14 is in the operation prohibited state (NO in step S113), there is no need for I / O emulation. The change detection routine includes a mask data for inhibiting the generation of the I / O trap SMI # 2 in the I / O trap SMI generation circuit 15.
1b (step S1).
14), end the process. As a result, it is possible to prevent the performance from deteriorating due to the occurrence of the unnecessary I / O trap SMI.

On the other hand, if the acquired I / O base address is a valid address, that is, if the I / O device 14 is operating (YES in step S113),
The I / O address change detection routine uses the I / O trap S
With reference to the mask register of MI generation circuit 151b, I
It is determined whether or not generation of the / O trap SMI # 2 is permitted (step S115). I / O trap SM
If the generation of I # 2 is prohibited, the I / O address change detection routine transmits the mask data for permitting the generation of I / O trap SMI # 2 to the I / O trap SMI.
Writing to the mask register of the generation circuit 151b, I / O
Enable trap SMI # 2 (step S11)
6).

Next, the I / O address change detection routine performs an I / O address (I / O base address) for starting I / O trap SMI # 2 from the trap address setting register of the I / O trap SMI generation circuit 151b. Is obtained (step S117), and is compared with the I / O base address obtained in step S112 (step S11).
8). If they do not match (step S11
8), the I / O address change detection routine determines that the operating system has dynamically switched the I / O address of the I / O device 14, and proceeds to step S
The I / O base address acquired in step 112 is written in the trap address setting register of the I / O trap SMI generation circuit 151b, and thereby the I / O trap SMI #
(2) Change the starting I / O address to the current I / O emulation address (step S119).

As described above, the I / O address change detection routine is started by the write to the I / O base address as a trigger, and the I / O for starting the I / O trap SMI # 2 is started.
By checking for a match with the base address, the I / O address for activating the I / O trap SMI # 2 can follow the switching of the I / O emulation address. As a result, even if the operating system dynamically switches the I / O address of the I / O device 14, the I / O emulation can be normally continued thereafter.

Although the first and second embodiments exemplify the case where the operation of a specific I / O register of the I / O device 14 is emulated, a mechanism for determining the register to be accessed is described. By providing
It is also possible to emulate the functions of all I / O registers of the I / O device 14. The target I / O device 14 includes a built-in PCI device as well as a PCI card type device that is installed in a PCI card slot as needed.

The present invention is not limited to the above embodiments, and can be variously modified at the stage of implementation without departing from the scope of the invention. Further, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effects described in the column of the effect of the invention can be solved. Is obtained, a configuration from which this configuration requirement is deleted can be extracted as an invention.

[0046]

As described above, according to the present invention,
It is possible to reliably emulate the operation of an I / O device capable of dynamically mapping I / O addresses.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing the configuration of a computer system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an I / O emulation routine and an I / O address change detection routine and a program interface for activating them in the first embodiment;

FIG. 3 is a flowchart for explaining I / O emulation processing in the first embodiment.

FIG. 4 is a flowchart for explaining an I / O address change detection process in the first embodiment.

FIG. 5 shows two types of I used in the second embodiment of the present invention.
FIG. 4 is a diagram for explaining an / O trap SMI generation circuit.

FIG. 6 is a diagram showing a relationship between an I / O emulation routine and an I / O address change detection routine and a program interface for activating them in the second embodiment;

FIG. 7 is a flowchart for explaining an I / O address change detection process in the second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... CPU 13 ... Main memory 14 ... I / O device 15 ... System controller 17 ... BIOS-ROM 151, 151a, 151b ... I / O trap SMI generation circuit 152 ... Software SMI generation circuit

Claims (9)

[Claims] 1. An information processing apparatus capable of dynamically mapping an I / O address to an I / O device, comprising: a CPU; and an I / O address of the I / O device, the I / O address for interrupt activation. Means for trapping I / O access from the CPU, which is set as an O address and indicating the I / O address for interrupt activation, and issues a first interrupt signal to the CPU; Activated and the I / O
I / O emulation means for emulating the operation of an I / O device specified by an address; means for monitoring a change in the setting of an I / O address for the I / O device by the CPU; Means for updating the value of the I / O address for interrupt activation in response to a change in the setting of the / O address. 2. The I / O address setting change monitoring means, comprising: periodically polling a value of an I / O base address set in a configuration space of the I / O device; I / O for I / O devices
2. The information processing apparatus according to claim 1, wherein the presence / absence of an address setting change is detected. 3. The means for monitoring a change in the setting of the I / O address, a means for determining whether or not the I / O device is in an operation prohibition state at the time of polling, and an operation of the I / O device. 3. The information processing apparatus according to claim 2, further comprising: a unit that prohibits the issuance of the first interrupt signal when in the prohibition state. 4. The apparatus according to claim 1, further comprising means for activating said means for monitoring a change in the setting of the I / O address by a second interrupt signal periodically generated by a timer. Information processing device. 5. A predetermined address belonging to a configuration space of the I / O device is set as a second address for activating an interrupt, and a configuration access from the CPU indicating the second address for activating the interrupt. Means for issuing a second interrupt signal to the CPU by trapping the I / O address, wherein the means for monitoring a change in the setting of the I / O address is activated by the second interrupt signal, and
The configuration access from the I / O
I / O defined in the device configuration space
2. The information according to claim 1, wherein it is determined whether or not the write is to the O base address register, and whether the setting of the I / O address for the I / O device is changed is detected based on the determination result. Processing equipment. 6. A means for monitoring a change in setting of an I / O address, comprising: means for determining whether or not the I / O device is in an operation-inhibited state at the time of activation by the second interrupt signal; 6. The information processing apparatus according to claim 5, further comprising: means for prohibiting issuance of the first interrupt signal when the I / O device is in an operation prohibition state. 7. An interrupt signal is issued to the CPU by trapping an I / O access from the CPU indicating the I / O address of the I / O device to be emulated, thereby specifying the I / O address specified by the I / O address. An I / O emulation control method for starting a program for emulating the operation of the I / O device, comprising: monitoring a change in an I / O address setting for the I / O device by the CPU; Updating the value of the I / O address of the trap target according to a change in the setting of the I / O address for the / O device. 8. The method according to claim 7, further comprising the step of activating the step of monitoring the change of the setting of the I / O address by a second interrupt signal periodically generated by a timer. / O emulation control method. 9. A method for activating a step of trapping a configuration access from the CPU indicating a predetermined address belonging to a configuration space of the I / O device and monitoring a change in the setting of the I / O address. The I / O emulation control method according to claim 7, further comprising a step of generating a second interrupt signal.