JP2001339072A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of photomechanical processes (number of masks) required for manufacturing a TFT array for improving the productivity of an active-matrix liquid crystal display device or reducing costs. SOLUTION: A thin-film transistor array substrate is provided with an insulating substrate, a first metal pattern that is formed on the insulating substrate, an insulating film on the first metal pattern, a semiconductor pattern on the insulating film, and a second metal pattern on the semiconductor pattern. And, the semiconductor pattern involves the second metal pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor array substrate and a method for manufacturing the same. More specifically, a thin-film transistor array substrate which has few point defects and line defects and can reduce the leak current of a thin film transistor (TFT) is manufactured by four photoengraving steps. It improves productivity.

[0002]

2. Description of the Related Art Electro-optical devices using liquid crystals are being widely applied to displays. Electro-optical elements using liquid crystals are generally
A configuration in which liquid crystal is sandwiched between two substrates having electrodes on the upper and lower sides, and a configuration in which polarizing plates are further disposed on the upper and lower sides are adopted. In the case of a transmission type, a backlight is disposed on the back. The surfaces of the upper and lower electrode substrates are subjected to so-called alignment treatment, and the director, which is the average direction of the liquid crystal molecules, is controlled to a desired initial state. The liquid crystal has birefringence, and light incident from a backlight through a polarizing plate changes to elliptically polarized light due to birefringence, and is incident on the opposite polarizing plate.
In this state, when a voltage is applied between the upper and lower electrodes, the arrangement state of the director changes, the birefringence of the liquid crystal layer changes, and the elliptically polarized state incident on the opposite polarizing plate changes. Therefore, the intensity and spectrum of light transmitted through the electro-optical element change. This electro-optic effect varies depending on the type of liquid crystal phase used, the initial alignment state, the direction of the polarizing axis of the polarizing plate, the thickness of the liquid crystal layer, or a color filter or various interference films installed on the way of transmitting light. In detail. Generally, a structure called TN or STN using a nematic liquid crystal phase is used.

[0005] Electro-optical elements for display using liquid crystal include a simple matrix type and a TFT-L using a thin film transistor (TFT) as a switching element.
There is a CD. TFT- with superior features in terms of portability and display quality compared to CRTs and simple matrix liquid crystal displays
LCDs are widely used in notebook computers and the like.
In a TFT-LCD, generally, a polarizing plate is disposed above and below a structure in which liquid crystal is sandwiched between a TFT array substrate in which TFTs are formed in an array and a counter substrate with a color filter in which a common electrode is formed. It has a configuration with a backlight. With such a configuration, a good color display can be obtained.

In a TFT-LCD, in order to apply a voltage to the liquid crystal, the TFT is turned on within a selection time of a gate line, electric charges flow from a source wiring to a pixel electrode, and a pixel potential is set to the same potential as the source wiring. Thereafter, when the gate is in the non-selected state, the TFT is turned off and the charge of the pixel is held, but in reality, the amount of charge of the pixel is reduced due to the leak current in the TFT and liquid crystal, and as a result, the potential of the pixel Decrease. In order to prevent these fluctuations in the pixel potential, an auxiliary capacitor is usually provided so that the amount of change in the pixel potential with respect to the change in the unit charge is reduced. Attempts have been made to reduce the number of manufacturing steps of the FTF array in order to improve the productivity of the TFT-LCD. Among them, attempts to reduce the photoengraving process are disclosed in JP-A-6-202153 and JP-A-8-32804.
No. 0 and JP-A-8-50308.

FIG. 57 is a sectional view of a pixel portion of a TFT array substrate manufactured by five photoengraving steps disclosed in a seventh embodiment of Japanese Patent Application Laid-Open No. Hei 8-50308. In this conventional example, first, Cr, with a thickness of about 100 nm on a transparent substrate,
A first conductive metal thin film of Ta, Mo, Al or the like is formed. Next, a gate electrode 51 is formed by patterning the first conductive metal thin film in a first photomechanical process. At this time, when the first conductive metal thin film is Cr, wet etching is performed using, for example, a solution of (NH ₄ ) ₂ [Ce (NO ₃ ) ₆ ] + HNO ₃ + H ₂ O. Next, a SiN _x film as the first insulating film 52 and an a-
N ⁺ a-S as the Si film and the ohmic contact film 54
The i films are laminated to a thickness of about 300 nm, 100 nm, and 20 nm, respectively. Next, in a second photolithography process, the semiconductor active film 53 and the ohmic contact film 54 are patterned in an island shape above the gate electrode with the semiconductor portion separated from other portions. At this time, the semiconductor active film and the ohmic contact film are dry-etched with, for example, SF ₆ + HCl + He.

Next, a second metal thin film such as Ti is formed to a thickness of about 300 nm. Next, in a third photolithography process, the second metal thin film and the ohmic contact film are patterned to form the source wiring 55, the source electrode 56, the drain electrode 57, and the semiconductor active layer 58 of the thin film transistor. Next, an interlayer insulating film (passivation film) 59 having a thickness of about 400 nm is formed by a method such as plasma CVD. Next, in a fourth photolithography process, the passivation film is patterned to form a contact hole 60 leading to the drain electrode 57, a contact hole leading to the gate wiring, and a contact hole leading to the source wiring.
At this time, the passivation film is etched by dry etching using, for example, SF ₆ + O ₂ . Next, a transparent conductive film made of ITO is formed with a thickness of about 150 nm. Next, in a fifth photolithography step, the transparent conductive film is patterned to form a transparent pixel electrode 61, a terminal portion for connecting a source line, and a terminal portion for connecting a gate line. At this time, the ITO film is wet-etched using, for example, an HCl + HNO ₃ + H ₂ O solution.

As described above, this conventional example discloses a method of manufacturing a TFT array in five photoengraving steps, and the effect is that the yield can be improved because the number of photoengraving steps can be reduced to five. The cost can be reduced, the voltage can be efficiently applied to the liquid crystal because there is no passivation film on the transparent pixel electrode, and the transparent pixel is formed because the transparent pixel electrode and the source wiring and gate wiring are separated by an insulating film. It is stated that there is no risk of short-circuiting between source wirings or gate wirings due to poor electrode formation. Further, as an effect of this conventional example, a laminated film of a first conductive metal thin film and a barrier film made of a material that is hardly oxidized or a material that forms a solid solution with a transparent conductive film as a conductive oxide is used. In the case where a barrier film is provided, furthermore, the barrier film exerts an antioxidant effect, and the problem of signal delay hardly occurs in order to secure the contact property between these films and the transparent conductive film. It is described that by using Al or Ta, the thickness of the metal thin film can be reduced, the step coverage of the entire TFT element can be improved, and the yield can be improved. The above TFT
In the array structure, since the gate wiring, the source wiring, and the pixel electrode are separated from each other by the insulating film, there is an advantage that a short circuit does not easily occur and the yield is easily increased.

FIGS. 59 (a), 59 (b), 59 (c),
60 (a), 60 (b), 60 (c), FIG.
(A), 61 (b), 61 (c), and 61 (d) show an example of a TFT array structure used in a conventional active matrix liquid crystal display device (AMLCD). Figure 59
(A), 59 (b), 59 (c), FIGS. 60 (a), 60
(B) and 60 (c) are examples of cross-sectional views, and FIGS.
1 (b), 61 (c) and 61 (d) are plan views of FIG.
(A), 59 (b), 59 (c), FIGS. 60 (a), 60
FIGS. 61 (b) and 60 (c) show FIGS. 61 (a), 61 (b) and 61, respectively.
(C), the cross-sectional structure of XX of 61 (d) and the gate / source terminal part is shown.

FIGS. 59 (a), 59 (b), 59 (c),
60 (a), 60 (b), 60 (c), FIG.
(A), 61 (b), 61 (c), 61 (d), 311 is an insulating substrate, 313 is a gate electrode and a gate wiring, 314 is a pixel electrode made of a transparent conductive layer, 316
Is a gate insulating film, 317 is a semiconductor layer (active layer), 318
Is a semiconductor layer containing impurities such as P or B (ohmic contact layer), 322 is an insulating film such as SiN4, 330 is a contact hole, 302 is a source wiring,
303 is a source electrode and 304 is a drain electrode.

A method for manufacturing a TFT array substrate used in a conventional active matrix liquid crystal display (AMLCD) will be described. Cr, Al, M on insulating substrate 311
A layer of a substance such as a metal such as o, an alloy containing them as a main component, or a metal obtained by laminating them is formed by a technique such as sputtering. Next, a gate electrode, a gate wiring pattern 313, and the like are formed by photolithography using a photoresist or the like, followed by an etching method (FIG. 5).
9 (a), FIG. 61 (a)).

Next, an insulating film 316 made of Si ₃ N ₄ , SiO _2, etc., which becomes a gate insulating film formed by various CVD methods such as plasma CVD, sputtering, vapor deposition, coating method, etc.
a-Si: a semiconductor layer 317 made of an H film (hydrogenated amorphous silicon film), phosphorus, antimony formed by a plasma CVD method or a sputtering method to make contact with a metal;
An ohmic contact layer 318, which is a semiconductor layer doped with an impurity such as boron and made of an n ⁺ a-Si: H film or a microcrystal n ⁺ Si layer, is formed continuously. Next, a semiconductor layer (active layer) 317 such as a TFT portion, a gate wiring / source wiring intersection, or a semiconductor layer containing an impurity such as P or B (an ohmic contact layer) is formed by photolithography using a photoresist or the like and a subsequent etching method. ) 318 (FIG. 59 (b), FIG. 6).
1 (b)).

Next, a transparent conductive layer made of a transparent conductive material such as ITO (Indium Tin Oxide) is sputtered, vapor-deposited,
It is formed by a method such as a sol-gel method. Next, a pixel electrode 314, a terminal electrode, and the like are formed by photolithography using a photoresist or the like and a subsequent etching method or the like (FIGS. 59C and 61C).

Next, a pattern was formed by photolithography using a photoresist or the like so as to form a contact hole in a gate terminal portion or the like, and the gate insulating film 316 was removed by a dry etching method or the like using a subsequent gas such as CF ₄ . After that, the photoresist is removed and the contact hole 330 is formed.
Is formed (FIG. 60A).

Next, a layer of a substance such as a metal such as Cr, Al, or Mo, an alloy mainly containing them, or a metal obtained by laminating them is formed by a technique such as sputtering. Next, the source wiring 302 and the source electrode 3 are formed by photolithography using a photoresist or the like and subsequent etching.
03, forming a drain electrode 304 (FIG. 60 (b),
FIG. 61 (d)).

[0015] Then various CVD or sputtering such as plasma CVD, vapor deposition, insulating film such as Si ₃ N ₄ consisting of Si ₃ N _4, SiO _2, etc., or laminates thereof which is to be a gate insulating film formed by a coating method or the like 322 is formed, followed by photolithography using photoresist or the like, followed by CF ₄
An insulating film such as a terminal portion is removed by a dry etching method using a gas of a system or the like so that a signal can be input to each wiring from an external TCP or the like. Thus, a TFT array is formed (FIG. 60C).

Next, an alignment film is formed on the TFT array,
An active matrix type liquid crystal display is formed by facing a counter substrate and sandwiching liquid crystal therebetween.

[0017] Japanese Patent Application Laid-Open No. H8-50308 No. 7
Although the embodiment discloses a technique in which the semiconductor layers 53 are separated from each other in an island shape, when the source wiring is formed of a single-layer metal and is patterned by wet etching, the semiconductor layer 53 is formed at the semiconductor layer step portion. In the case where the adhesion of the source metal is poor or the like, the etching solution enters the metal-semiconductor interface from the stepped portion during the etching and leads to the cause of disconnection. Therefore, as disclosed in JP-A-10-268353, It is better to extend the semiconductor pattern below. FIG. 58 is a plan view of a thin film transistor in which the semiconductor layers 53 are formed separately from each other. In general, a leakage current easily flows through a semiconductor end face, and thus, in such a structure, an end face leakage path 62 from the source electrode 56 to the drain electrode 57 exists, which increases the leak current of the thin film transistor. This greatly affects the display quality of the display, such as a decrease in contrast and an increase in bright spot defects when used at high temperatures (in the case of normally white).

On the other hand, a technique in which the photolithography process is performed five times in a state where the gate wiring, the source wiring and the pixel electrode are separated is disclosed, but a technology in which the photolithography process is further reduced is not disclosed. An object of the present invention is to reduce the number of photoengraving steps to four while maintaining the above structure, to eliminate a semiconductor layer step under a source electrode or a source wiring, and to efficiently prevent display defects due to semiconductor layer end face leaks. Thus, the display quality and the yield are maintained, and the productivity is further improved.

Further, when a TFT array is manufactured by using the conventional manufacturing method, at least five photolithography steps are required, so that the manufacturing steps become longer, and particularly, an exposure step in which the operating cost of production equipment is high is often used. There's a problem. For this reason,
Inevitably, the cost of the TFT array to be manufactured increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. Another object is to improve the performance and reduce the cost.

When a TFT array is manufactured by using the conventional manufacturing method, at least five photolithography steps are required, so that the manufacturing process becomes longer, and in particular, there is a problem in that a large number of exposure steps in which the operating cost of the production equipment is high are used. is there. For this reason, the cost of the TFT array necessarily produced has increased.

An object of the present invention is to reduce the number of photolithography (the number of masks) required for manufacturing a TFT array for the purpose of improving the productivity or reducing the cost of an active matrix type liquid crystal display device. And

[0023]

A thin film transistor array substrate according to one embodiment of the present invention includes an insulating substrate, a first metal pattern formed on the insulating substrate, and an insulating film on the first metal pattern. A semiconductor pattern on the insulating film,
The semiconductor device includes a second metal pattern on the semiconductor pattern, wherein the semiconductor pattern includes the second metal pattern.

According to another aspect of the present invention, there is provided a thin film transistor array substrate comprising: an insulating substrate; the substrate and a gate wiring formed on the substrate; a gate insulating film on the gate wiring;
A semiconductor layer on the gate insulating film, a source wiring on the semiconductor layer, a source electrode, a drain electrode, the source wiring, the source electrode, an interlayer insulating film formed on the drain electrode, and formed on the interlayer insulating film; A source electrode, the source electrode, and the drain electrode. The semiconductor pattern includes a first contact hole that penetrates the interlayer insulating film and reaches the drain electrode. A second contact hole reaching the wiring, and a third contact hole penetrating through the gate insulating film and the interlayer insulating film and reaching the gate wiring.
And the first to third contact holes are covered with a pattern of the pixel electrode material.

According to still another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, comprising the steps of:
After forming a metal thin film, a gate wiring is formed in a first photolithography and etching step, and then a gate insulating film,
A semiconductor film, an ohmic contact film, and a second metal film are formed, and then, in a second photolithography process, a resist pattern is formed on a source wiring, a source electrode, a drain electrode, and a portion corresponding to the semiconductor active layer of the thin film transistor. Only the portion corresponding to the active layer is formed so that the resist film thickness is smaller than that of the other portions, and then the second metal film is etched to form a source wiring, a source electrode, and a drain electrode. Etching the semiconductor film, then thinning the resist, removing the resist in the portion corresponding to the thin film transistor active layer, then etching the second metal film to remove the second metal film on the portion corresponding to the semiconductor active layer; Thereafter, the ohmic film on the portion corresponding to the semiconductor active layer is removed, and then an interlayer insulating film is formed.
Patterning the gate insulating film and the interlayer insulating film in the photolithography and etching steps of (a), a first contact hole reaching the drain electrode, a second contact hole reaching the source wiring, and a third contact hole reaching the gate wiring. A contact hole is formed, and then a conductive film is formed.
In the photolithography and etching steps, a pixel electrode is formed to connect to the drain electrode via the first contact hole, and a source terminal is formed to connect to the source wiring via the second contact hole. A gate terminal is formed so as to be connected to the gate wiring via the third contact hole.

According to still another aspect of the present invention, in order to reduce the number of photoengraving steps, the gate electrode, the gate wiring and the pixel electrode are constituted by at least two layers of a transparent conductor layer and a metal layer. A step of forming a film so that the gate wiring is on the transparent conductor layer and patterning it simultaneously to form respective predetermined patterns;
The region X where the thickness of the photoresist is left to leave the semiconductor layer, the region Z where at least the portion of the photoresist that exposes the pixel electrode is removed, and the thickness of the remaining portion of the photoresist are thinner than the thickness of the semiconductor layer Area Y
Forming a semiconductor layer and a gate insulating layer in the same pattern by using the photoresist to expose a pixel electrode; and forming a gate wiring material made of metal and a transparent conductive material in the exposed pixel electrode. Etching the layer from the metal on top in the two-layer structure, and leaving the photoresist in region A,
By including the step of removing the photoresist from the region Y and the step of removing the semiconductor layer other than the region X, the number of photolithography steps was reduced.

According to still another aspect of the present invention, in order to reduce the number of photolithography steps, after forming a gate insulating film and a semiconductor layer on a gate electrode and a gate wiring, the thickness of the photoresist is reduced to leave the semiconductor layer. A region A where a portion is thickened, a region C where at least a gate insulating film and a semiconductor layer are etched to remove a photoresist to expose a part of a gate electrode and a gate wiring, and a thickness of the photoresist in other portions are reduced. Forming a region B having a thickness smaller than the thickness of the photoresist in the portion of the semiconductor layer, etching the semiconductor layer and the gate insulating layer in the same pattern using the photoresist, and exposing at least a part of the gate wiring; A while leaving the photoresist on A
Including a step of removing the photoresist from above and a step of removing the semiconductor layer other than the region A, forming two layers of a transparent electrode and a metal film formed thereon, and simultaneously forming a source / drain electrode wiring and a pixel electrode After forming a source-drain wiring and a pixel electrode using a photoresist pattern to be formed, a protective film is formed thereon, and then at least a portion of the pixel electrode that transmits light and a connection portion of a terminal portion of the source-gate wiring. Then, the metal layer formed to form the source / drain electrode wiring at that portion is removed. As a result, the number of photolithography can be reduced to four.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIGS. 1 and 2 show a thin film transistor substrate according to a first embodiment of the present invention. FIG. 1 is a plan view, and FIG. FIG. 2B is a sectional view of FIG.
FIG. 2C is a cross-sectional view taken along a line CC in FIG. 1. 1 and 2, reference numeral 1 denotes a gate wiring;
a is a gate terminal metal pad, 2 is an auxiliary capacitance wiring, 3 is a gate insulating film, 4 is a semiconductor pattern, 4a is a semiconductor layer (semiconductor active film), 4b is an ohmic layer (ohmic contact film), 5 is a source wiring, 5a is a source terminal portion metal pad, 6 is a source electrode, 7 is a drain electrode, 8 is a semiconductor active layer of a thin film transistor, 9 is an interlayer insulating film, 10
Is a drain electrode contact hole, 11 is a gate terminal contact hole, 12 is a source terminal contact hole, 13 is a pixel electrode, 14 is a gate terminal connection pad,
5 is a source terminal connection pad.

Next, the manufacturing method will be described. 3 to 7 are plan views in each step, and FIGS. 8 to 14 show cross sections in FIG. 1A-A in each step. First, Cr, Ta, Mo, A are formed on a transparent substrate in a thickness of about 400 nm.
A first conductive metal thin film such as 1 is formed. Next, in a first photolithography step, the first conductive metal thin film is patterned to form a gate wiring 1, a gate terminal portion metal pad 1a, and an auxiliary capacitance wiring 2 as shown in FIGS. At this time, when the first conductive metal thin film is Cr, wet etching is performed using, for example, a solution of (NH ₄ ) ₂ [Ce (NO ₃ ) ₆ ] + HNO ₃ + H ₂ O. Next, as shown in FIG. 9, a SiN _x film as the gate insulating film 3, an a-Si film as the semiconductor active film 4a, an n ⁺ a-Si film as the ohmic contact film 4b, and Cr as the second metal film 16 are each 400 nm thick. , 150nm, 30nm, 400nm
It is laminated with a film thickness of about. SiN _x , a-Si, n ⁺ a-S
The i film is formed using a plasma CVD apparatus, and when forming an ohmic layer, PH ₃ is doped to form n ⁺ a-Si. The Cr film is formed using a DC magnetron type sputtering apparatus.

Next, in a second photolithography process, as shown in FIG. 4, a resist pattern 17a having a normal thickness for forming the source wiring 5, the source terminal metal pad 5a, the drain electrode 7, and the semiconductor active layer of the thin film transistor 8 is formed as a thin resist pattern 17b. Here, a novolak resin-based positive resist was used as the resist, and the resist was applied by a spin coater to 1.5 μm.
m. After the resist is applied, a pre-bake is performed at 120 ° C. for 90 seconds.
The exposure was performed for 00 msec, and then an additional exposure for 400 msec was performed using a mask pattern capable of exposing only the resist pattern 17b in the semiconductor active layer portion. By performing the two-stage exposure, the resist pattern 1 having a normal thickness is formed.
7a and the thin film resist pattern 17b have different thicknesses. The exposure device was a stepper or mirror projection type exposure device, and g-line and h-line of a high-pressure mercury lamp were used as a light source. Then, after developing using an organic alkali-based developer, post-baking is performed at 100 ° C. to 120 ° C. for 180 seconds to evaporate the solvent in the resist and at the same time increase the adhesion between the resist and Cr. Through these processes, the resist shape of the thin film transistor portion becomes a shape as shown in FIG. Here, the resist film thickness of the normal film thickness resist pattern 17a is about 1.4 μm, and the resist film thickness of the thin film resist pattern 17b is about 0.4 μm.
It is about 4 μm.

Thereafter, at 120 ° C. to 130 ° C.,
After baking, and the adhesion between resist and Cr
Enhance. If the baking temperature is too high at this time,
Care must be taken because the end face of the strike will fall. Then Cr
The film 16 is etched (NH _Four)_Two[Ce (NO_Three)₆] +
HNO_Three+ H_TwoPerform using O liquid. Then HCl + S
F₆Ohmic film 4b and semiconductor using + He gas
The film 4a is etched. After that, the oxygen plasma
Ash the dist and apply a thin film resist as shown in FIG.
Pattern 17b to remove the thin film transistor active layer 8
To expose the Cr film of the corresponding portion. Ashing is
The test was performed at a pressure of 40 Pa for 60 seconds. Ashing again
In this case, the RIE mode is compared with the PE mode, as shown in FIG.
The size of the resist opening shown in FIG. 18 is easy to control.

Then, after baking at 130 ° C. to 140 ° C., (NH ₄ ) ₂ [Ce (NO ₃ ) ₆ ] + H
The Cr film 16 in the opening 18 is etched using the NO ₃ + H ₂ O solution. At this time, since the entire Cr pattern is side-etched, the Cr pattern becomes narrower by about 1.5 to 2 μm than the a-Si pattern (becomes inside the a-Si pattern). This makes it possible to suppress a leak current from the source electrode to the drain electrode through the end surface of the a-Si pattern. This Cr etching requires some over-etching. The amount of over-etching is desirably about 50%. Then Figure 1
As shown in FIG. 2, a part of the ohmic layer 4b and a part of the semiconductor layer 4a in the portion 8 corresponding to the semiconductor active layer are etched using SF ₆ + HCl to a total of about 100 nm. After that, when the resist is removed, as shown in FIG.
A source wiring 5, a source electrode 6, a drain electrode 7, and a source terminal metal pad 5a are formed.

Next, as shown in FIG. 6 and FIG.
Using a CVD apparatus, SiN _x as the interlayer insulating film 9 is
2A, FIG. 2B, FIG. 2C, FIG. 6, FIG.
Contact hole 1 leading to drain electrode 7 shown in 3
0, a contact hole 11 leading to the gate terminal part metal pad 1a and a contact hole 12 leading to the source terminal part metal pad are formed by dry etching using CF ₄ + O ₂ . Next, as shown in FIG. 7 and FIG.
A transparent conductive film of ITO having a thickness of about m is formed using a DC magnetron type sputtering apparatus. Next, in a fourth photolithography process, the ITO is patterned to form the transparent pixel electrode 13, the gate terminal pad 14, and the source terminal pad 15. At this time, for example, HCl + HNO ₃
The ITO film is wet-etched using + H ₂ O solution.

The thin film transistor array substrate manufactured in this manner is formed in four photoengraving steps, and since there is no step in the semiconductor layer below the source wiring, source disconnection is less likely to occur, and the source and drain electrodes are not formed. Since the pattern is included inside the semiconductor pattern and does not intersect, the leakage current of the thin film transistor part was also suppressed low. Further, the second metal film 16 is made of a single-layer metal, so that the number of times of etching the second metal film 16 can be reduced to two. By using Cr as the metal, it is possible to prevent the etchant from corroding the source wiring and the like via the pinholes existing in the interlayer insulating film 9 when the pixel is formed of ITO.

FIG. 2A is a sectional view of a TFT portion, and FIG.
2B is a cross-sectional view of the gate terminal, and FIGS. 2C and 2D are cross-sectional views of the source terminal. The source terminal section is shown in FIG.
Although a configuration in which a source terminal pad 15 made of, for example, a transparent conductive layer is connected to the source wiring layer 5a as shown in FIG. 2C may be used, as shown in FIG. To the gate wiring material 1.
The position where the wiring material of the source terminal portion is converted can be changed below the repair line for the source wiring (in this case, the repair line is formed of the source wiring material), near the seal portion, or in the liquid crystal portion. By converting the wiring material from the source wiring material to the gate wiring material, disconnection due to corrosion of the source wiring material near the source terminal portion can be prevented.

The structure of the source terminal portion when the source wiring is converted to the gate wiring material 1 will be described with reference to FIG. In a step of forming a gate wiring pattern, a source wiring conversion unit 1 ′ is formed from the gate wiring material 1. Further, in the step of forming the first, second, and third contact holes 10, 11, and 12 through the interlayer insulating film 9 and the gate insulating film 3, the fourth and fifth contact holes 12 ', 12 "are formed.
And a transparent conductive film 1 connecting the contact hole 12 ″ on the source wiring to the contact hole 12 ′ at one end of the source wiring conversion part 1 ′ in the step of forming the pixel electrode 13.
5 ′ and a source terminal pad 15 formed in the contact hole 12 at the other end of the source wiring conversion unit 1 ′.

In the present embodiment, the interlayer insulating film 9 is used, but the interlayer insulating film 9 may not be used. In this case, a plan view corresponding to FIG. 1 is shown in FIG. 64, and sectional views corresponding to FIGS. 2A, 2B, 2C, and 2D showing manufacturing steps are shown in FIGS. 65A and 65B. , (C) and (d). In addition, in plan views of FIGS.
The step shown in FIG. 5 is the same as that described above, and the plan view showing the next step is shown in FIG.

In the process sectional views 8 to 14, FIG.
13 to 12 are the same as those described above.
4 is shown in FIGS. 67 and 68, and FIG.
FIG. 65 is a structural sectional view of the terminal portion in the process shown in FIG.

Embodiment 2 FIG. 15 shows a thin film transistor substrate according to a second embodiment of the present invention. The cross section taken along lines DD, EE, and FF in FIG. And respectively in FIG.
(A), FIG. 2 (b) and FIG. 2 (c). Here, 1 is a gate wiring, 1a is a metal pad of a gate terminal portion, 2 is an auxiliary capacitance wiring, 3 is a gate insulating film, 4 is a semiconductor pattern, 4a
Is a semiconductor layer, 4b is an ohmic layer, 5 is a source wiring, 5
a is a source terminal portion metal pad, 6 is a source electrode, 7 is a drain electrode, 8 is a semiconductor active layer of a thin film transistor, 9
Is an interlayer insulating film, 10 is a drain electrode contact hole,
Reference numeral 11 denotes a gate terminal portion contact hole, 12 denotes a source terminal portion contact hole, 13 denotes a pixel electrode, 14 denotes a gate terminal connection pad, and 15 denotes a source terminal connection pad.

Next, the manufacturing method will be described. FIG.
20 to FIG. 20 are plan views in each step, and similarly to the first embodiment, FIG. 8 to FIG. 14 show DD cross sections in FIG. 15 in each step.

First, a first conductive metal thin film of Cr, Ta, Mo, Al or the like is formed on a transparent substrate with a thickness of about 400 nm. Next, in a first photolithography process, the first conductive metal thin film is patterned to form a gate wiring 1, a gate terminal portion metal pad 1a, and an auxiliary capacitance wiring 2 as shown in FIGS. At this time, the first conductive metal thin film is made of Cr
In the case of, for example, (NH ₄ ) ₂ [Ce (NO ₃ ) ₆ ] + H
The wet etching process is performed using the NO ₃ + H ₂ O solution. Next, as shown in FIG.
The N _x film, the a-Si film as the semiconductor active film 4a, the n ⁺ a-Si film as the ohmic contact film 4b, and the Cr as the second metal film 16 are 400 nm and 105 nm, respectively.
The layers are laminated to a thickness of about 30 nm and 400 nm. Si
The N _x , a-Si, and n ⁺ a-Si films are formed using a plasma CVD device, and are doped with PH ₃ to form n ⁺ a-Si during ohmic film formation. The Cr film is formed using a DC magnetron type sputtering apparatus.

Next, in a second photolithography process, as shown in FIG. 17, a resist pattern 17a for forming a source wiring, a source terminal metal pad, a drain electrode, and a resist for forming a semiconductor active layer 8 of a thin film transistor. A pattern 17b, resist patterns 17c and 17d for preventing leakage of the semiconductor end face, and a resist pattern 17e for preventing a short circuit between the gate and the source wiring are formed. Here, a novolak resin-based positive resist is used as the resist, and the resist is applied to a thickness of 1.5 μm using a spin coater. After applying the resist, a pre-bake is performed at 120 ° C. for 90 seconds. Thereafter, the resist pattern 17 a is a normal Cr entire surface mask pattern and the resist pattern 17
b, 17c, 17d, and 17e are line / space = 1.
Exposure was performed for 1000 msec using a mask pattern having a Cr stripe shape of 5 μm / 1.5 μm. FIG. 21 shows the stripe mask pattern. The exposure device was a conventional stepper or mirror projection type exposure device, and g-line and h-line of a high-pressure mercury lamp were used as a light source. At this time, since the stripe pattern is a pattern finer than the resolution limit of the exposure apparatus, the resist is not exposed in a stripe shape, and the exposure amount is on average smaller than that of the other exposed portions.

Then, after development using an organic alkali-based developer, post-baking is performed at 100 ° C. to 120 ° C. for 180 seconds to evaporate the solvent in the resist and increase the adhesion between the resist and Cr. By these processes, the resist shape of the thin film transistor portion becomes a shape as shown in FIG.
Of the resist pattern 17b,
The film thicknesses of 7c, 17d and 17e are about 0.4 to 0.6 μm. Thereafter, oven baking is further performed at 120 ° C. to 130 ° C. to further increase the adhesion between the resist and Cr. At this time, if the baking temperature is too high, care must be taken because the resist end face will be sagged. After that, the etching of the Cr film 16 is performed by (NH ₄ ) ₂ [Ce (NO ₃ ) ₆ ] + H
This is performed using a NO ₃ + H ₂ O solution. Then HCl + SF
_The ohmic film 4b and the semiconductor film 4a are etched using _six gases. Thereafter, the resist is ashed by oxygen plasma, and the resist patterns 17b, 17c, 17
The d and 17e portions of the Cr film are exposed. Ashing was performed at a pressure of 40 Pa for 60 seconds. Also, when performing ashing, the RIE mode is compared with the PE mode in FIG.
The size of the resist opening indicated by 1 is easy to control.

After baking at 130 ° C. to 140 ° C., (NH ₄ ) ₂ [Ce (NO ₃ ) ₆ ] + H
17b, 17c, 17d, 17 using NO ₃ + H ₂ O solution
The Cr film 16 in e is etched. In this pattern, since the semiconductor patterns near the source electrode and the drain electrode are arranged farther apart, the effect of suppressing the occurrence of leakage at the semiconductor end face and the Cr overetch margin are wider than in the first embodiment. In the case of this pattern, Cr over-etching of about 20 to 50% becomes possible. However, in this case, it should be noted that when the a-Si pattern formed by the pattern 17c continuously protrudes from the outer edge of the gate wiring, the gate-off bias is applied to this portion in the holding state. Is not applied and light is not blocked by the gate pattern, so that the leakage current increases. Therefore, at least a part of the outer edge of the semiconductor pattern including the source wiring and the drain electrode is formed as shown in FIG.
17c, it is necessary to go inside the outer edge of the gate wiring. That is, in the semiconductor pattern, at least a part of the path on which the region including the thin film transistor extends toward the region including the source wiring extends so that the outer edges on both sides of the semiconductor pattern both intersect the outer edges on the gate wiring. Must be formed. 1
The intersection is automatically performed for 7d depending on the arrangement of the thin film transistors, but it is effective to intentionally intersect for 17c. SF ₆ and then, as shown in FIG. 12
+ HCl to form resist patterns 17b, 17c, 1
A part of the ohmic layer 4b and a part of the semiconductor layer 4a corresponding to the portions 7d and 17e are etched by a total of about 100 nm. Thereafter, when the resist is removed, as shown in FIG. 18, the semiconductor pattern 4, the source wiring 5, the source electrode 6, the drain electrode 7, and the source terminal portion metal pad 5a are formed.

Next, an interlayer insulating film 9 is formed using a PCVD apparatus.
The SiN _X to 300nm formed is, by patterning the third photolithography process, FIG. 2 (a), the FIG. 2 (b), the 2
(C) The contact hole 10 leading to the drain electrode 7, the contact hole 11 leading to the gate terminal part metal pad 1a, and the contact hole 12 leading to the source terminal part metal pad shown in FIGS. 13 and 19 are made of CF ₄ + O ₂ . It is formed by dry etching. Next, a transparent conductive film made of ITO having a thickness of about 100 nm is formed using a DC magnetron type sputtering apparatus. Next, in a fourth photomechanical process, the ITO is patterned to obtain a structure shown in FIGS.
(B), the transparent pixel electrode 13, the gate terminal pad 14, and the source terminal pad 15 shown in FIG. 2C, FIG. 14, and FIG. At this time, for example, HCl + HNO
₃ + H ₂ O solution ITO film using is wet etching.

The thin film transistor array manufactured in this manner is formed by four photoengraving processes, and since there is no step in the semiconductor layer under the source wiring, source disconnection hardly occurs and the pattern of the source electrode and the drain electrode is reduced. Does not intersect with the semiconductor pattern, and the distance between the end face of the thin film transistor semiconductor pattern and the source electrode and the drain electrode is widened, so that the leak current is further suppressed. In addition, a structure in which at least a part of the outer edge of the semiconductor pattern including the source wiring and the drain electrode enters inside the outer edge of the gate wiring prevents an increase in leak current due to light leak or the like.

In the above embodiment, the interlayer insulating film 9 is used, but the interlayer insulating film 9 may not be used.
In this case, a plan view corresponding to FIG. 15 is as shown in FIG. In addition, in the steps shown in FIGS. 16 to 20 showing the manufacturing steps, the steps shown in FIGS. 16 to 18 are carried out in the same manner as described above, and then the step shown in FIG.

In this embodiment, a transparent conductive film (pixel electrode 13) is formed on the first metal film 1a and the second metal film 5a as the gate terminal pad 14 and the source terminal pad 15, respectively. 12
, But the transparent conductive film 13 is not formed on the terminal pads 14 and 15, and the first metal film 1 a and the second metal film 5 a are left exposed at the respective contact holes. It may be directly mounted on it.

Third Embodiment FIG. 22 shows a thin film transistor substrate according to a third embodiment of the present invention, in which a section taken along line GG, a section taken along line HH, a section taken along line I-
2 (a), FIG. 2 (b), and FIG.
Same as (c). Here, 1 is a gate wiring, 1a is a gate terminal portion metal pad, 2 is an auxiliary capacitance wiring, 2a is IP
S counter electrode, 3 a gate insulating film, 4 a semiconductor pattern,
4a is a semiconductor layer, 4b is an ohmic layer, 5 is a source wiring, 5a is a source terminal portion metal pad, 6 is a source electrode,
7 is a drain electrode, 8 is a semiconductor active layer of a thin film transistor, 9 is an interlayer insulating film, 10 is a drain electrode contact hole, 11 is a gate terminal contact hole, 12 is a source terminal contact hole, 13a is an IPS electrode,
4 is a gate terminal connection pad, and 15 is a source terminal connection pad.

Next, the manufacturing method will be described. FIG.
To FIG. 27 are plan views in each step, and FIGS. 8 to 14 are FIG. 22 in each step as in the first embodiment.
GG section is shown.

First, a first conductive metal thin film of Cr, Ta, Mo, Al or the like is formed on a transparent substrate with a thickness of about 400 nm. Next, in a first photolithography process, the first conductive metal thin film is patterned to form a gate wiring 1, a gate terminal metal pad 1a, an auxiliary capacitance wiring 2, and an IPS counter electrode 2a as shown in FIGS. I do. At this time, when the first conductive metal thin film is Cr, for example, (NH ₄ )
Wet etching is performed using ₂ [Ce (NO ₃ ) ₆ ] + HNO ₃ + H ₂ O solution. Next, as shown in FIG. 9, a SiN _x film as the gate insulating film 3, an a-Si film as the semiconductor active film 4a, and n ⁺ as the ohmic contact film 4b.
The a-Si film and the second metal film 16 each include 4
The layers are laminated with a thickness of about 00 nm, 150 nm, 30 nm, and 400 nm. The SiN _x , a-Si, and n ⁺ a-Si films are formed by using a plasma CVD apparatus, and at the time of ohmic film formation, n ⁺ a-Si is formed by doping PH ₃ . The Cr film is formed using a DC magnetron type sputtering apparatus.

Next, as shown in FIG. 24, in a second photolithography process, a resist pattern 17a for forming a source wiring, a metal pad for a source terminal, a drain electrode and a resist for forming a semiconductor active layer 8 of a thin film transistor. The pattern 17b is formed. Here, a novolak resin-based positive resist is used as the resist, and the resist is applied to a thickness of 1.5 μm using a spin coater. After resist application, pre-bake is performed at 120 ° C. for 90 seconds, and then, exposure is performed for 1000 msec with a mask pattern including the resist pattern 17a and the resist pattern 17b.
Thereafter, additional exposure was performed for 400 msec using a mask pattern capable of exposing only the resist pattern 17b in the semiconductor active layer portion. The exposure device was a stepper or mirror projection type exposure device, and g-line and h-line of a high-pressure mercury lamp were used as a light source. Then, after developing using an organic alkali-based developer, post-baking is performed at 100 ° C. to 120 ° C. for 180 seconds to evaporate the solvent in the resist and at the same time increase the adhesion between the resist and Cr. Through these processes, the resist shape of the thin film transistor portion becomes a shape as shown in FIG. Here, the resist film thickness of 17a is about 1.4 μm, and the resist film thickness of 17b is about 0.4 μm.

Thereafter, at 120 ° C. to 130 ° C.,
After baking, and the adhesion between resist and Cr
Enhance. If the baking temperature is too high at this time,
Care must be taken because the end face of the strike will fall. Then Cr
The film 16 is etched (NH _Four)_Two[Ce (NO_Three)₆] +
HNO_Three+ H_TwoPerform using O liquid. Then HCl + S
F₆+ He gas and ohmic layer 4b and semiconductor
Etch layer 4a. After that, the oxygen plasma
Ash the dying and activate the semiconductor as shown in FIG.
The Cr film in the corresponding portion of the layer 8 is exposed. Assin
The pressing was performed at a pressure of 40 Pa for 60 seconds. Ashing again
When the RIE mode is used, compared to the PE mode, FIG.
The size of the resist opening shown in 18 of 1 is easy to control
No.

After baking at 130 ° C. to 140 ° C., (NH ₄ ) ₂ [Ce (NO ₃ ) ₆ ] + H
The Cr film 16 in the opening 18 is etched using the NO ₃ + H ₂ O solution. (NH ₄ ) ₂ [Ce (NO ₃ ) ₆ ] + HN
The Cr film 16 in the opening 18 is etched using an O ₃ + H ₂ O solution. At this time, since the entire Cr pattern is side-etched, the Cr pattern becomes narrower by about 1.5 to 2 μm than the a-Si pattern. This makes it possible to suppress a leak current from the source electrode to the drain electrode through the end surface of the a-Si pattern. This C
r etching requires some over-etching. The amount of over-etching is desirably about 50%.

Next, as shown in FIG. 12, SF ₆ + HCl
The ohmic film 4 in the corresponding portion of the semiconductor active layer 8 by using
b and a part of the semiconductor layer 4a are etched to a total of about 100 nm. Thereafter, when the resist is removed, as shown in FIG. 25, the semiconductor pattern 4, the source wiring 5, the source electrode 6, the drain electrode 7, and the source terminal portion metal pad 5a are formed. Next, as shown in FIG. 6 and FIG.
Using a VD apparatus, the SiN _X as the interlayer insulating film 9 is
nm and patterned in a third photolithography process,
26, FIG. 2 (a), FIG. 2 (b), and FIG. 2 (c), the contact hole 10 leading to the drain electrode 7, the contact hole 11 leading to the gate terminal part metal pad 1a, and the source terminal part metal pad. The contact hole 12 is formed by dry etching using CF ₄ + O ₂ .

Next, as shown in FIG. 27 and FIG.
A conductive film made of Cr having a thickness of about 00 nm is formed using a DC magnetron type sputtering apparatus. Next, Cr is patterned in a fourth photolithography process to form an IPS electrode 13.
a, a gate terminal portion pad 14 and a source terminal portion pad 15 are formed. At this time, for example, (NH ₄ ) ₂ [Ce
The Cr film is wet-etched using (NO ₃ ) ₆ ] + HNO ₃ + H ₂ O solution.

The thin film transistor array manufactured in this manner is formed by four photoengraving steps, and since there is no step in the semiconductor layer under the source wiring, source disconnection is unlikely to occur, and the pattern of the source and drain electrodes is reduced. Is included in the semiconductor pattern and does not intersect with each other, so that the leakage current is suppressed to a low level.

The IPS electrode arranged on the uppermost layer is made of Cr
Thus, even in brush cleaning in a post-process such as a panel assembling process, it is possible to prevent the occurrence of pattern disorder such as scratches.

In the above embodiment, the interlayer insulating film 9 is used, but the interlayer insulating film 9 may not be used.
In this case, a plan view corresponding to FIG. 22 is as shown in FIG. 23 to 27 are plan views showing manufacturing steps. In the steps shown in FIGS. 23 to 27, the steps shown in FIGS.

Fourth Embodiment FIG. 28 shows an example of a circuit diagram of a TFT array substrate of an active matrix type liquid crystal display (AMLCD) to which the present invention is applied. The circuit configuration shown in FIG.
Is formed by the pixel electrode and the gate wiring
This is called e-type. Here, 101 is a gate line for supplying a scanning voltage, 102 is a source line for supplying a signal voltage, 103 is a thin film transistor (TFT) used as a switching element when applying a voltage to liquid crystal, and 104 is a light source. A liquid crystal that performs transmission / non-transmission switching is represented by a capacitance in an equivalent circuit, 105
Is a storage capacitor Cs arranged in parallel with the liquid crystal 104 to reduce the effect of the parasitic capacitance of the TFT; 106 is a common electrode connecting one electrode of the liquid crystal 104 to a common voltage;
Is a gate terminal for connecting the gate-side external circuit to the gate wiring 101 using TCP or the like, 108 is a source terminal for connecting the source-side external circuit to the source wiring 102 using TCP or the like, and 109 and 110 are respectively TFT
A high-resistance element formed of a linear or non-linear element having a high or low level, electrically separating the gate terminal 107 and the source terminal 108 when a signal is applied, and electrically coupling when high-voltage static electricity enters. 111 denotes wirings A and 11 connected to the gate wiring 101 via the high resistance element 109.
2 is a wiring B connected to the source wiring 102 via the high-resistance element 110, and 113 is a wiring A for preventing static electricity.
This is a connection portion for connecting (111) to the wiring B (112). Reference numeral 114 denotes a repair wiring used when the source wiring has an open failure. After combining a counter substrate on which a color filter is formed facing the TFT array substrate and injecting liquid crystal, generally, the outside of a region 115 shown by a dotted line in the drawing is cut off to obtain an LCD (liquid crystal display) panel.

In some cases, it is not necessary to form at least a part of the portion outside the area indicated by the dotted line 115 when forming the TFT array.

FIGS. 29, 30, and 31 are cross-sectional views showing the steps of manufacturing a TFT array substrate according to the present invention in which the number of photolithography steps (the number of masks) is reduced. The circuit of the TFT array substrate shown in FIG. 28 is realized. 1 shows a manufacturing process. FIG. 32 is FIG.
FIG. 29 is a plan view corresponding to FIGS.
1 shows a cross-sectional structure of the Y-Y cross section and the gate / source terminal portion of FIG.

29, 30, and 31, reference numeral 211 denotes an insulating substrate; 212, a gate electrode and a gate wiring made of a transparent conductive layer; 213, a gate electrode and a gate wiring made of a metal layer; 10
Form one. 214 is a pixel electrode made of a transparent conductor layer, 215 is a pixel electrode made of a metal layer, 216 is a gate insulating film, 217 is a semiconductor layer (active layer), and 218 is a semiconductor containing a high concentration of impurities such as P or B. The layers (contact layers) and 219 (219a, b) are photosensitive organic resins that can be used as photoresist, and 220 (22
0a, b, and c) are conductor layers serving as source and drain electrodes, 102 is a source wiring, 103 is a thin film transistor (TFT) portion, 221 is a storage capacitor electrode, and 222 is S
An insulating film such as i ₃ N ₄ and 230 are semiconductor regions on the plan view (FIG. 32).

The numbers used in FIG.
The same numbers as to 31 indicate the same contents.

Next, the manufacturing method of the present invention will be described.

[0086] ITO (Indiumu Tin Oxide), SnO ₂ ,
A transparent conductor layer such as InZnO or a laminate thereof,
Alternatively, a transparent conductor layer composed of a mixed layer is
1 is formed by a technique such as sputtering, vapor deposition, coating, CVD, printing, and sol-gel method. Then, on the transparent conductor layer, Cr, Al, Mo, W, Ti, Cu, Ag, Au,
A layer made of a metal such as Ta, an alloy mainly containing them, a metal obtained by laminating them, or the like, and having a lower resistance than the transparent conductor layer is formed by a technique such as sputtering, vapor deposition, CVD, or printing. As a result, a wiring structure in which at least one low-resistance layer made of metal is laminated on the transparent conductor layer is obtained. Next, a gate electrode and gate wiring patterns 212 and 213 made of a transparent conductor layer and a low-resistance layer such as a metal are formed by photolithography and subsequent etching using a photoresist or the like. At this time, the pixel electrode patterns 214 and 215 are simultaneously formed in a layer structure including a transparent conductor layer having the same material and configuration as the gate wiring and a low-resistance layer such as a metal (FIG. 29A).
And FIG. 32 (a)).

For a transparent conductor layer such as ITO, polycrystal is generally used. In this case, as an etchant such as ITO, for example, ferric chloride or one containing HCl and nitric acid as main components is used.

However, for example, the ITO layer 214 is formed in an amorphous state, and the metal layer 215 formed thereon is
When the film is formed at a temperature lower than the temperature at which TO crystallizes, ITO is in an amorphous state at the time of forming a gate electrode and the like, and therefore, can be etched with a relatively weak acid such as oxalic acid. A when etching ITO
metal is rarely etched, and in forming the structure, the IT is used until the metal etching is completed.
O may be in an amorphous state. For this reason, it is desirable to form a film of a metal such as Al at a temperature of 160 ° C. or less at which ITO is not crystallized.

The etching of ITO may be performed using HC
Etching may be performed using a gas such as l, HBr, or HI.

Next, various types of CVD such as plasma CVD
Law and, sputtering, vapor deposition, a gate insulating film formed by a coating method or the like _{Si 3 N 4, SiO x N} y, SiO 2, Ta 2 O
₅ , an insulating film 216 made of Al ₂ O ₅ or the like or a material slightly deviated from the stoichiometric composition or a laminate thereof, such as an impurity intentionally formed as a dopant by a plasma CVD method or a sputtering method. The impurity concentration is suppressed to about 50 ppm or less even if it is not doped or intentionally doped, or the leak current in the dark under actual operating voltage conditions of the TFT does not exceed 50 pA. A-Si: H film (hydrogenated amorphous silicon film) 217 used as a channel semiconductor layer (active layer); phosphorus, antimony, boron, etc. formed by plasma CVD or sputtering to make contact with metal A semiconductor layer doped with impurities at a high concentration in which impurities are present in the film at an atomic ratio of, for example, 0.05% or more Contact layer), for example, n ⁺ a
-Si: H film and microcrystal n ⁺ Si film 218 are continuously formed.

Next, a photoresist is first applied to the entire surface. Next, a photoresist pattern is formed by exposure using a photomask. The shape of this photoresist pattern is as follows. First, as shown in FIG. 29B or FIG. 32B, at least a part of a portion to be a pixel electrode and a contact hole portion do not form a photoresist (region C). A photoresist having a thickness of A is formed in a portion where the semiconductor layer made of the a-Si: H film is left (region A).
219a). For example, only the a-Si: H film 217 and the n ⁺ a-Si: H film 218 are etched, and a photoresist having a thickness B is formed in a region where the gate insulating film 216 is to be left (region B 219b). Region A (219
The thickness of the photoresist in a) is as follows.
The thickness is set to be larger than the thickness of 19b). For example, a region B (2
19b), it is desirable to remove the a-Si: H film 217 and the film 218 such as n ⁺ a-Si: H in that portion and to keep the electrically adjacent source wirings in an insulated state. Further, at least a part of the source wiring is in the region A
Alternatively, the semiconductor layers 217 and 218 may be left below to help prevent disconnection of the source wiring.

The difference in the thickness of the photoresist depending on the location is formed as follows. The positive photoresist will be described. Even in the case of a negative type, a pattern is formed by basically the same method.

The portion on which the photoresist is not formed is made substantially transparent on the mask, and light is sufficiently transmitted so that a sufficient amount of light is applied so that the photoresist does not remain during development. As a result, a region C where the photoresist is not formed is formed. On the other hand, the portion of the photoresist having a thickness A, for example, the portion of the mask corresponding to that position is shielded from light by a light-impermeable material such as Cr, which has a sufficient thickness so that light is not substantially transmitted. As a result, since sufficient light does not reach the photoresist in this portion at the time of exposure, an area A where the photoresist remains with a sufficient thickness during development can be realized. In the region B having the photoresist thickness B, the photoresist is irradiated with a light exposure amount intermediate between the region A and the region C. By adjusting the exposure amount, the thickness of the region B is set to be smaller than that of the region A during development. As a result, the shapes of the photoresist shown in FIGS. 29B and 32B are realized. The amount of exposure or the amount of light is represented by irradiation light intensity × time.

When the thickness of the photoresist is in the region A> region B>
In order to set the region C (substantially 0), the amount of exposure applied to the photoresist in the region B is set so that the exposure amount between the region A and the region C is applied. <Region B <region C), and there are several methods.
For example, the transmittance of the pattern on the mask that forms the region B is higher than the transmittance of the region A on the mask used when forming the region A, and is higher than the transmittance of the portion that forms the region C. Also lower. For this purpose, for example, Cr used as a light-shielding film of a photoresist in a portion where the region B is formed is used.
The light amount may be controlled by making the thickness of a light-shielding material such as a thinner than that of a portion forming the region A. Alternatively, an insulating film is formed in a single layer or a multi-layer on the portion of the region B, and the transmittance and the
The transmittance of the region B may be substantially lower than the transmittance of the region C by changing the reflectance or the phase.

There is also the following method for setting the exposure amount so that the area A (substantially 0) <the area B <the area C. A pattern is formed on the mask in a light-shielding portion having a low transmittance of the same degree for both the region A and the region B, and a pattern having a sufficient transmittance for the region C, for example, a pattern in which no light-shielding pattern is formed is used. Form on top. Next, using only a mask having a light-shielding pattern of the area A + the area B, only the exposure is performed at the exposure amount 1, and the area C is irradiated with light. Next, exposure is performed at an exposure amount of 2 using a mask having a pattern in which only a portion corresponding to the region A is shielded from light, and light is irradiated at an exposure amount of 2 other than the portion where the region A is formed. At this time, the exposure amount 1 is set so that the photoresist in the area C can be sufficiently removed at the time of development, and the exposure amount 2 is set so that the photoresist having a necessary thickness remains in the area B at the time of development. Generally, when a positive photoresist is used, the exposure amount 1 is set to be larger than the exposure amount 2 in that the calculation result of “light intensity at light irradiation × light irradiation time” becomes larger.

When the thickness of the photoresist is in the region A> region B>
As a third method for setting the area C (substantially 0), a pattern is formed on a mask with a light-shielding layer having a low transmittance to form the area A, and the pattern is sufficiently formed for the area C. For example, a pattern which does not form any light-shielding pattern having a high transmittance is formed on a mask.

For region B, a so-called halftone mask as shown in FIG. 33 may be used, for example. In the halftone mask, the spatial frequency of the light-shielding pattern on the mask like the pattern 233 is made higher than the pattern resolving ability (for example, 1/6 μm) of the exposure machine, and the pattern of the mask cannot be resolved on the photoresist. Exposure intensity is set lower than that. The fineness of the halftone mask is formed such that the width of the light-shielding portion and the light-transmitting portion is repeated at a cycle of 6 μm or less in total.

As a result, the thickness of the photoresist can be set in the range of area A> area B> area C (substantially 0). As a result, the photoresist shapes shown in FIGS. 29 (b) and 32 (b) are realized.

Then, an n ⁺ a-Si: H film, a-Si:
A semiconductor film such as an H film and a gate insulating film such as Si ₃ N ₄ are etched. The etch, for example a mixed gas of the gas and CF ₄ and O ₂ as a main component gas and CF ₄ mainly containing HCl, such as a gas mainly composed of SF ₆ is performed. As a result, these films on a portion where light is to be transmitted at least in a portion to be a pixel electrode are removed. In addition, a terminal portion 224 connected to a gate wiring and a TCP or the like for inputting a signal from the outside, for example, a portion short-circuited to a source wiring portion directly via a source wiring or a TFT or a resistor for preventing static electricity (FIGS. 28 and 113, etc.) )
In this step, the n ⁺ a-Si: H film and the a-S
A part of the gate insulating film such as the i: H film and Si ₃ N ₄ may be removed (FIG. 30A).

The n ⁺ a-Si: H film, a-Si: H
Etching of film, gate insulating film such as Si ₃ N ₄ is CF ₄
Or may be etched all films with a single gas such as CH ₄ + O _2, but for example, at the time of the S-a-Si TFT film etching
At least the a-Si: H film and the Si ₃ N ₄ film may be dry-etched with different etching gases, such as by using a gas that can suppress the etching of the iN film. In this case, the etching of a-Si: H is performed by SF ₆ , HCl, F1.
23, or a mixed gas of these, or a mixed gas of these and an inert gas or O _2, and CF ₄ , SF _6, a mixed gas of these or a mixed gas of these and O ₂ or an inert gas is used for etching the Si ₃ N ₄ film. May be used.

Next, ashing is performed using plasma such as oxygen plasma that can reduce the thickness of the resist, and the resist is shaved, and the resist is removed from the region B (219b). At this time, although the film thickness of the resist in the region A (219a) is smaller than the initial film thickness, the resist is controlled so as to maintain a sufficient thickness to protect a portion which is not etched in the following etching. Then, at least n ⁺ a-Si: H
The film and the a-Si: H film are etched by a dry etching method or the like and removed from the region B (FIG. 30B).

This step of reducing the thickness of the resist is not performed independently, and the n + a-Si: H film,
Etching of gate insulating film such as Si ₃ N ₄
Using the phenomenon that the photoresist itself can be slightly removed, the photoresist in the region B may be removed at the same time.

Thereafter, as shown in FIG. 30B, n ⁺
A portion of the metal layer 215 on the pixel electrode 214 which is removed by etching the a-Si: H film, the a-Si: H film, and the gate insulating film such as Si ₃ N ₄ is removed by wet etching or dry etching (FIG. 31). (A)). Next, the photoresist is removed.

Then, for example, Cr, Al, Ti, T
a, W, Mo, Mo-W, Cu or these as main components
Alloys or multilayer stacks of them
Conductor to be source electrode, source wiring, drain electrode
The layer 220 (220a, b, c) is formed. Then pictures
The source electrode, source wiring, and drain electrode
After forming a wiring pattern on the shape,
And then the source electrode 220c and the drain electrode
N formed by an a-Si: H film between the poles 220b ⁺Semiconduct
The body layer 218 is removed by dry etching or the like, and finally
Form a predetermined pattern by stripping the resist
(FIG. 31 (b), FIG. 32 (c)). At this time, the storage capacity
Holding to form Cs simultaneously with source wiring
The capacitor electrode 221 is connected at least with the gate insulating film 216 interposed.
For example, the next stage or the preceding stage consisting of 212 and 213
It faces the gate wiring. At this time, the storage capacitor electrode 22
1 and the gate insulating film 216
Not just n⁺a-Si: H film, leaving a-Si: H film
Is also good. The storage capacitor electrode is smaller than the pixel electrode as shown in the figure.
It is necessary to connect at least a part.

Next, a protective film 222 made of an insulating film made of a material such as Si ₃ N ₄ , SiO ₂ , or a mixture thereof, and a laminate is formed. In photolithography, a pattern is formed so that contact holes can be formed in the gate terminal portion 223 and the source terminal portion 225 which are connected to an external TCP or the like in order to at least input a signal, and then dry etching using a gas such as CF ₄ is used. And a contact hole by wet etching. After the etching is completed, the photoresist is removed. Thereby, a TFT array is formed (FIGS. 31C and 32D).

Next, an alignment film is formed on the TFT array, and a liquid crystal is injected between the counter substrate having at least a surface on which an alignment film and a common electrode are formed, thereby forming an active matrix type liquid crystal display.

By the above process, a TFT array having the configuration shown in FIG. 28 and a liquid crystal display using the same are formed.

In FIG. 28, for example, a repair wiring 114 for a source wiring formed by using a gate wiring material is shown, but this may not be formed depending on circumstances.

Further, as shown in FIG.
At the intersection with 14, the source wiring 102 may be temporarily converted to a wiring 117 of the same layer as the gate wiring formed of the gate wiring material using the contact holes 116a and 116b. At this time, the repair wiring 114 is formed using a source wiring material.

In FIG. 31, except for the metal layer 215 on the pixel electrode 214 formed of the gate electrode material in FIG.
In FIG. 31B, the source / drain electrodes 220b and 220c and the source wiring 102 are patterned by etching.
When both are the same material, the etching of the gate electrode material 215 shown in FIG. 31A is omitted, and the pixel electrode 215 formed of the gate electrode material is simultaneously formed when the source wiring 220 is etched in FIG. It may be removed by etching.

The shape of the semiconductor region 230 protrudes on both sides of the gate wiring 213 in FIG.
One side or both sides may be inside the gate wiring as shown in FIG. In FIG. 32D, the outer edge on the upper side of the semiconductor region 230 protrudes outside the gate electrode 213, and a gate-off bias is not applied. Therefore, leakage current may be generated by light irradiation. In order to avoid this, a notch is provided at the upper edge of the semiconductor region 230 as shown in FIG.
It is particularly effective to intersect with the outer edge of thirteen.

Further, as shown in FIG. 73, at least the source electrode side of the semiconductor region 230, preferably both sides of the source and drain electrodes are placed inside the gate wiring, and the semiconductor layer of the source electrode portion is formed only on the gate wiring (gate electrode). In this case, the gate electrode can block light emitted from below the gate electrode and prevent the light from irradiating the semiconductor layer of the source electrode portion, so that leakage current due to light can be prevented.

The semiconductor region 230 may be extended as shown in FIG. 74, and may be formed continuously from the thin film transistor portion to the lower portion of the source wiring 102. In this manner, disconnection that is likely to occur in the source wiring 102 at the step portion at the end of the semiconductor layer 23 can be prevented. Such a semiconductor region 23
Changing the shape of 0 is also effective in the following embodiments. The first embodiment shown in FIG. 1 has a similar arrangement.

Fifth Embodiment In the above-described embodiment, the storage capacitor 105 is a so-called Cs on which is formed between the next or previous gate wiring.
Although the gate structure has been described, a common wiring structure in which a storage capacitor wiring advantageous for one gate delay is formed separately from the gate wiring as shown in the circuit diagram of FIG. 35 may be used. Here, the storage capacitor 105 is connected to the common wiring 120. Further, the common wiring 120 is connected to the common wiring lead line 121 via the contact hole 122.
The common voltage is applied from outside via a common wiring terminal 123 connected to the common wiring lead line 121. The functions and reference numerals of the other parts are the same as those in FIG.

In the common wiring method, for example, FIG.
37 and the plane arrangement shown in FIG.
Also, as shown in FIG. 38, a common wiring 120 is formed in the pixel, the pixel electrode is divided into two parts, and a storage capacitor electrode 221 formed at the same time as the source wiring is bridged between the two, and a storage capacitor 105 is formed there. You may.

In the case of adopting a common wiring structure as shown in FIG. 37, a common wiring 120 which is drawn out in parallel with the gate wiring and a common wiring drawing line 121 which runs the common wiring 120 and runs perpendicularly to the gate wiring are required. The common wiring is most preferably formed simultaneously with the same material as the gate wiring 101, and the common wiring lead line is formed at least at the intersection 124 with the gate wiring.
Uses a material of the source wiring 102 in a different layer from the gate wiring. In some cases, the common wiring lead line may be formed of the gate wiring material except for the intersection with the gate wiring.

Also, as shown in FIG.
At the intersection with 14, the source wiring 102 may be temporarily converted to a wiring 117 of the same layer as the gate wiring formed of the gate wiring material using the contact holes 116a and 116b.

Embodiment 6 In the above embodiment, the insulating film 222 is formed so as to cover the entire surface of the TFT array. However, this insulating film need not be formed. If the formation of the insulating film is omitted, the number of masks becomes three. In this case, corrosion of the source wiring outside the liquid crystal seal becomes a problem, but before it goes outside the seal, it is converted into a gate wiring material using a contact hole inside the seal. Thereby, corrosion of the source wiring can be prevented.

Embodiment 7 In the step of FIG. 29B, the resist pattern 219b in the region B may be arranged so as to overlap the pixel electrode patterns (214, 215). In this way, as shown in FIG. 40, the pixel electrode (transparent conductor layer) 21
4 has a metal layer 215 left on the outer periphery thereof.
Is formed.

Eighth Embodiment In the above-described embodiment, a case has been described in which the common electrode for applying a voltage to the liquid crystal itself is provided on the opposing substrate.
The present invention can be applied to a case where all the electrodes for applying a liquid crystal voltage are provided on a TFT substrate for applying a horizontal electric field, such as in a (ing) mode. In this case, for example, the pixel electrode 214 need not be a transparent conductor layer, but may be a metal such as Cr. I
Examples of the plan view in the PS mode are shown in FIGS. Here, the same components as those in FIGS. 32 and 37 are denoted by the same reference numerals.

In FIG. 41A, the pixel electrode 231 is formed when the pixel electrodes 214/215 shown in FIG. 29A are formed.

In FIG. 41B, the pixel electrode 232 is formed when the drain electrode shown in FIG. 31B is formed. In this case, the pixel electrode is not formed in FIG.

In FIGS. 41A and 41B, the gate electrode and the wiring may be formed of only the metal layer 213. Also, the pixel electrodes 214/215 may be formed of only the metal layer 215.

Embodiment 9 In the above-described embodiment, as shown in FIGS. 29 (a), (b) and 30 (a), an a-Si: H film is formed into an island shape. Although the thickness of the resist was partially changed on a plane using the technique, this process was stopped and a-S
The photolithography of islanding of the i: H film may be performed separately. In this case, for example, the thickness of the resist is not changed spatially. In the state of FIG. 29B, the thickness of the resist is not changed planarly, and the SiN 216 / a-SiH 217 / n + on the pixel electrodes 214 and 215 and the contact portion 223 are formed.
After the step of removing the a-Si: H 218 is performed, the resist is removed, a pattern for forming a transistor island is created again, and the a-Si: H film 217 other than the TFT portion and the n + a-S
The i: H film 218 is removed by etching, and FIG.
Create the structure of In this case, the number of times of photolithography is increased as compared with the embodiment shown in FIGS. 29 to 31, but can be reduced as compared with the prior art.

Embodiment 10 In Embodiment 4, after the gate insulating film 216 made of SiN or the like, the a-Si: H layer 218 and the metal layer 215 on the pixel electrode 214 made of the gate wiring material are etched, the source The drain electrode and the wiring 220 were formed. On the other hand, without using a step of spatially changing the thickness of the photoresist, FIGS.
(B), 42 (c), FIGS. 43 (a), 43 (b), at least a portion of the pixel portion where the light is transmitted through the gate insulating film 216, a-SiH: layer 217, n + a-S
i: After removing the H layer 218 by etching, the source
A drain electrode 220 may be formed. In this case, island formation of the Si film 217 used as a channel cannot be generally performed.

[0106] ITO (Indium Tin Oxide), SnO2,
A transparent conductor layer such as InZnO or a laminate thereof,
Alternatively, the transparent conductor layers 212 and 214 formed of a mixed layer are formed on the insulating substrate 211 by sputtering, vapor deposition, coating, CVD,
It is formed by a printing method, a sol-gel method, or the like. Then, Cr, Al, Mo, W, Ti, C are formed on the transparent conductor layer.
The layers 213 and 215 made of a metal such as u, Ag, Au, Ta, an alloy containing them as a main component, or a laminated metal thereof, and having a lower resistance than the transparent conductor layer are formed by sputtering, vapor deposition, CVD, or printing. It is formed by such a method.
As a result, a wiring structure in which at least one low-resistance layer made of metal is laminated on the transparent conductor layer is obtained. Next, a gate electrode and gate wiring patterns 212 and 213 made of a transparent conductor layer and a low-resistance layer such as a metal are formed by photolithography and subsequent etching using a photoresist or the like. At this time, at the same time, the pixel electrode patterns 214, 2
15 are formed (FIG. 42A).

Next, various types of CVD such as plasma CVD
Law and, sputtering, vapor deposition, Si ₃ N ₄ having a gate insulating film formed by a coating method or the _{like, SiO x N y, SiO 2} , Ta 2 O
Insulating film 216 made of ₅ Al ₂ O ₅ or the like or a material slightly deviated from the stoichiometric composition or a laminate thereof, and doped with impurities intentionally formed as a dopant by plasma CVD or sputtering. For the channel whose impurity concentration is not less than 50 ppm even if it is not doped or intentionally doped, or the leakage current in the dark under the actual operating voltage condition of TFT does not exceed 50 pA. A-Si: H film (hydrogenated amorphous silicon film) 21 used as a semiconductor layer
7. A semiconductor doped with a high concentration of impurities such as phosphorus, antimony, and boron, which are formed by plasma CVD or sputtering to make contact with a metal, for example, having an atomic ratio of 0.05% or more in the film. For example, an n ⁺ a-Si: H film or a microcrystal n ⁺ Si layer 218 as a layer is continuously formed.

Next, a gate insulating film 216 made of SiN or the like from at least a pixel portion that transmits light, a-Si:
After forming a photoresist so as to remove the H layer 217 and the n ⁺ a-Si: H layer 218, etching is performed (FIG. 42).
(B), 42 (c)). Here, the photoresist 219 is removed.

Then, for example, Cr, Al, Ti, T
a, W, Mo, Mo-W, Cu, or an alloy containing these as a main component, or a multilayered product thereof; a source electrode, a source wiring, and a conductor layer 220 (220a, b, c) serving as a drain electrode. Form a film. Then the source electrode and the source wiring by photolithography, after forming the wiring pattern in the shape of the drain electrode wet, etched in such as dry, then between the source electrode 220c and the drain electrode 220b n ⁺ a-Si: H film or the like N + formed
The semiconductor layer 218 is removed by dry etching or the like, and the resist is finally stripped to form a predetermined pattern (FIG. 43A).

Next, a protective film formed of an insulating film made of Si ₃ N ₄ , SiO ₂ , or a mixture thereof, or a laminate is formed. At least a gate terminal portion 22 connected to an external TCP or the like for inputting a signal in photolithography.
3. A pattern is formed so that a contact hole can be formed in the source terminal portion 225, and then etching is performed by dry etching or wet etching using a gas such as CF ₄ . After the etching is completed, the photoresist is removed. Thus, a TFT array is formed. (FIG. 43
(B)) According to this method, the a-Si: H film 217 and the like remain in portions other than the TFT portion, but the number of photolithography (the number of masks)
Can be completed four times (four).

Embodiment 11 According to the above embodiment, the semiconductor layer is formed of an a-Si: H film, but may be formed of poly-Si (polycrystalline silicon).

Embodiment 12 FIG. 28 shows another example of a circuit diagram of a TFT array substrate of an active matrix liquid crystal display (AMLCD) used in the present invention. The circuit configuration shown in FIG. 28 has a so-called CS on structure in which a storage capacitor is formed by a pixel electrode and a gate wiring.
ate type. Here, 101 is a gate wiring for supplying a scanning voltage, 102 is a source wiring, 103 is a thin film transistor (TFT) used as a switching element when applying a voltage to the liquid crystal, and 104 performs light transmission / non-transmission switching. The liquid crystal is represented by a capacitance in an equivalent circuit, 105 is a storage capacitor arranged in parallel with the liquid crystal 104 to reduce the influence of the parasitic capacitance of the TFT, and 106 is a connection for connecting one electrode of the liquid crystal 105 to a common voltage. 107, a gate terminal for connecting the gate-side external circuit to the gate wiring 101 using TCP or the like; 108, a T-connection between the source-side external circuit and the source wiring 102;
A source terminal for connection using a CP or the like, 109,
Reference numeral 110 denotes a TFT or a high-resistance linear or non-linear element.
Is a high-resistance element that electrically separates when a signal is applied and electrically couples when a high voltage such as static electricity is applied. 111 is a wiring A connected to the gate wiring 101 via the high resistance element 109, and 112 is a source wiring 102
B, 1 connected to the
13 is a wiring A (111) and a wiring B for preventing static electricity.
This is a connection part for connecting (112). This portion may be connected via a non-linear element such as a resistance element or a TFT. Reference numeral 114 denotes a repair wiring used when the source wiring is open. After injecting liquid crystal into the TFT array in combination with a counter substrate on which a color filter is formed, generally, the outside of a region 115 shown by a dotted line in the drawing is cut off to form an LCD (liquid crystal display).

In some cases, at the time of forming the TFT array, at least a part of the portion outside the area indicated by the dotted line 115 may not be formed.

FIGS. 44 (a), 44 (b), 44 (c),
FIGS. 45 (a), 45 (b), and 45 (c) are cross-sectional views showing the steps of manufacturing a TFT array substrate according to the present invention in which the number of photolithography steps is reduced, and the circuit of the TFT array substrate shown in FIG. An example of a structure that realizes the above will be described. FIG. 44 (a), 44
(B), 44 (c), FIGS. 45 (a), 45 (b), 45
(C) shows FIGS. 46 (a), 46 (b), 46 (c), FIG.
7 (a) and 7 (b) show a cross-sectional structure of a section taken along the line Y1-Y1 and gate / source terminal portions.

FIGS. 44 (a), 44 (b), 44 (c),
In FIGS. 45 (a), 45 (b) and 45 (c), 410
Is an insulating substrate, 411 is a gate electrode or gate wiring made of a metal layer, and 412 is an adjacent gate wiring / electrode in the previous or next stage. 413 is a gate insulating film, 41
4 is a semiconductor layer (active layer), 415 is an ohmic contact layer made of a semiconductor layer containing a high concentration of impurities such as P or B, 416 is a transparent conductor layer used as source / drain electrodes and pixel electrodes, and 417 is metal The source wiring 102 is also formed by the source / drain electrodes made of layers. 418 is a photosensitive organic resin that can be used as a photoresist, 419 is a storage capacitor electrode, and 420 is Si ₃
N ₄ is a protective insulating film used as a protective film such.

FIGS. 46 (a), 46 (b), 46 (c),
Among the reference numerals used in FIGS. 47 (a) and 47 (b), FIGS. 28, 44 (a), 44 (b), 44 (c),
45 (a), 45 (b) and 45 (c) indicate the same parts. 442a is a drain electrode, 4
42b is a source electrode; 430 is a semiconductor region; 445 is a pixel electrode;

Next, the production method of the present invention will be described.

On the insulating substrate 410, Cr, Al, Mo,
A material made of a metal such as W, Ti, Cu, Ag, Ta, an alloy containing these as a main component, or a metal obtained by laminating them is formed by a technique such as sputtering, vapor deposition, CVD, or printing. Next, a gate electrode and a gate wiring pattern 411 made of a low-resistance layer such as a metal are formed by photolithography using a photoresist or the like and subsequent etching.
Then, an adjacent gate wiring 412 at the next or previous stage is formed (FIGS. 44A and 46A).

Next, various types of CVD such as plasma CVD
Law and, sputtering, vapor deposition, a gate insulating film formed by a coating method or the like _{Si 3 N 4, SiO x N} y, SiO 2, Ta 2 O
₅ , a gate insulating film 413 made of Al ₂ O ₅ or the like or a material slightly shifted from the stoichiometric composition or a laminate thereof, an impurity intentionally formed as a dopant by a plasma CVD method or a sputtering method The impurity concentration is suppressed to about 50 ppm or less even if it is not doped or intentionally doped, or the leak current in the dark under actual operating voltage conditions of the TFT does not exceed 50 pA. A semiconductor layer 414 made of an a-Si: H film (hydrogenated amorphous silicon film) used as a channel semiconductor layer, such as phosphorus, antimony, or boron formed by plasma CVD or sputtering to make contact with metal. Highly doped semiconductor in which impurities are present in the film in an atomic ratio of, for example, 0.05% or more. In a example n ⁺ a-Si: H
An ohmic contact layer 415 made of a film or a macrocrystal n ⁺ Si layer is continuously formed.

Next, a photoresist is first applied to the entire surface. Next, a photoresist pattern is formed by exposure using a photomask. The shape of this photoresist pattern is as follows. First, as shown in FIG. 44B or FIG. 46B, at least the gate electrode / wiring 4
In order to form a contact hole in the gate terminal portion 423 in the gate insulating film 413, the semiconductor layer 414, and the ohmic contact layer 415 in order to make contact 11,
At least a part of the portion does not form a photoresist (region C). A photoresist having a thickness of A is formed in a portion where the semiconductor layer made of the a-Si: H film is to be left (region A (418)
a, 430)). Further, the a-Si: H film 414 and n
⁺ A-Si: forming a thin photoresist thicknesses is only H film 415 in a region to be left by etching the gate insulating film 413 (a region B (418b)). Region A (418a,
The thickness of the photoresist in 430) is set to be larger than the thickness of the photoresist in the region B (418b). Region B (418) is located between adjacent source lines on the gate line.
It is desirable to form b) and remove the a-Si: H film 414 and the film 415 of n ⁺ a-Si: H or the like in that portion, and keep the adjacent source wirings electrically insulated.

The difference in the thickness of the photoresist is formed as follows. The case where a positive photoresist is used will be described. Even in the case of a negative type, a pattern can be formed by basically the same method.

The portion where the photoresist is not formed is made substantially transparent on the mask, so that light is sufficiently transmitted so that a sufficient amount of light is applied so that the photoresist does not remain during development. As a result, a region C where the photoresist is not formed is formed. On the other hand, the portion having the photoresist thickness A is shielded from light by a light-impermeable material such as Cr having a sufficient thickness so that light is not substantially transmitted through a portion of the mask corresponding to the position. As a result, since sufficient light does not reach the photoresist in this portion at the time of exposure, an area A where the photoresist remains with a sufficient thickness during development can be realized. In the region B having an intermediate photoresist thickness, the photoresist is irradiated with the exposure amount between the region A and the region C. By adjusting the exposure amount, the thickness of the region B is set to be smaller than that of the region A during development. As a result, the shapes shown in FIGS. 44 (b) and 46 (b) are realized. The amount of exposure or the amount of light is represented by light intensity applied to the photoresist × time. In order to set the thickness of the photoresist such that the area A> the area B> the area C (substantially 0), the exposure amount applied to the photoresist in the area B is an intermediate exposure amount between the area A and the area C. (Exposure amount is area A <area B <area C), and there are several methods. For example,
The transmittance of the pattern on the mask forming the region B is higher than the transmittance of the region A on the mask used for forming the region B, and the transmittance of the portion on which the region C is formed. Lower than For this purpose, for example, the light amount may be controlled by making the thickness of a light-shielding material such as Cr used as a photoresist light-shielding film in the portion where the region B is formed thinner than that in the portion where the region A is formed. Or area B
A single or multi-layer insulating film is formed on
The transmittance of the region B may be effectively made lower than the transmittance of the region C by changing the reflectance or the phase.

In order to set the exposure amount in the region A (substantially 0) <region B <region C, the following method is also available.
A pattern is formed on the mask with a light-shielding portion having a low transmittance of the same degree for both the region A and the region B, and a pattern having a sufficient transmittance for the region C, for example, a pattern without any light-shielding pattern is formed. Form on top. Next, exposure is performed at an exposure amount of 1 using a mask having a light-shielding pattern of the area A + the area B, and light is irradiated to a portion of the photoresist corresponding to the area C. Then, using the light-shielding pattern mask for the region A, the exposure amount 2
Irradiate with light. At this time, the exposure amount 1 is set to an intensity at which the photoresist in the region C can be sufficiently removed at the time of development.
The exposure amount 2 is set so that a photoresist having a necessary thickness remains in the region B during development. Generally, when a positive photoresist is used, the exposure amount 1 is set to be larger than the exposure amount 2 in the calculation result of “light intensity at light irradiation × light irradiation time”.

When the thickness of the photoresist is in the region A> region B>
As a third method for setting the area C (substantially 0), in order to form the area A, a pattern is formed on a mask with a light-shielding layer having a low transmittance such as metal, and For example, a pattern having sufficient transmittance, for example, without forming any light-shielding pattern is formed on a mask.

For the region B, for example, a so-called halftone mask may be used. FIG. 33 shows an example of an actual pattern. The halftone mask 233 makes the spatial frequency of the light-shielding pattern on the mask sufficiently higher than the pattern resolving ability of the exposing machine so that the pattern of the mask cannot be fully decomposed and imaged on the photoresist. Try to be less. In the pattern of the halftone mask, it is desirable that a region that does not transmit light at all and a region having a transmittance equivalent to that of the glass of the photomask are periodically formed with a total width of 6 μm or less.

As a result, the thickness of the photoresist is reduced in the region A>
It is possible to set region B> region C (substantially 0), and as a result,
The photoresist shapes shown in FIGS. 44 (b) and 46 (b) are realized.

Next, for example, n on the gate wiring⁺a-
Semiconductors such as Si: H film 415 and a-Si: H film 414
Body membrane and Si_ThreeN_FourEtch the gate insulating film 413
To In this etching, for example, HCl is used as a main component.
Gas or CF_FourGas or CF mainly containing_FourAnd O_TwoBlend of
Joint gas, SF₆Is performed using a gas mainly containing. this
As a result, at least, for example, signals from gate wiring and external
Gate terminal part 42 connected to TCP or the like for input
3. Direct source wiring or TFT
Or a portion that is short-circuited to the source wiring via a resistor (FIG. 2).
8, 113, etc.)⁺a-Si: H film 41
5, the n-Si: H film 414 and the gate insulating film 413
Be chilled. Upon completion of this etching, the photo of region B
The film thickness is set so that the resist remains. this
N⁺a-Si: H film 415, a-Si: H film 41
4, Si_ThreeN_FourEtching of the gate insulating film 413 such as
CF _FourAnd CF_Four+ O_TwoEtch all films with a single gas such as
However, for example, at the time of etching the a-Si: H film,
Use a gas that can suppress the etching of the SiN film
Such as at least a-Si: H film and Si_ThreeN_FourSeparate membranes
Dry etching with etching gas or different conditions
May be etched. In this case, the edge of a-Si: H
SF as ching₆, HCl, F123 or these
Mixed gas or these and inert gas or O_TwoWhen
Mixed gas of Si_TwoN_FourCF for film etching_Four, S
F₆Or a mixed gas of these or O and_TwoYa no
An active gas and a mixed gas may be used.

Next, ashing is performed using a plasma such as oxygen plasma that can reduce the thickness of the resist, and the resist is shaved, and the resist is removed from the region B (418b) (FIG. 44 (c)). At this time, the area A (4
Although the film thickness of the resist of 18a) is smaller than the initial film thickness, the resist is controlled so as to maintain a thickness that can sufficiently protect portions that are not etched during the following etching. Then
At least the n ⁺ a-Si: H film 415 and the a-Si: H film 414 are etched by a dry etching method or the like to form a region B
These films are further removed (FIG. 45A).

At this time, the step of reducing the thickness of the resist in the region B is not performed independently, and the n ⁺ a-Si: H film 41 is not used.
5. When etching the gate insulating film 413 such as the a-Si: H film 414 or Si ₃ N ₄ , the photoresist in the region B may be simultaneously removed by using a development capable of slightly removing the photoresist itself. Next, the photoresist 418a is removed.

Next, a transparent conductive layer 416 made of, for example, a transparent conductive film such as ITO (indium tin oxide), SnO ₂ , InZnO, or a laminated or mixed layer thereof, and Cr, Al, Ti, Ta, Au, Ag ,
The source electrode 442b, the source wiring 102, and the drain electrode 4 made of W, Mo, Mo—W, Cu, an alloy containing these as main components, or a multilayer laminate thereof.
A metal layer 417 to be 42a is formed. Next, after forming a wiring pattern in the shape of a source electrode, a source wiring, a drain electrode, and a pixel electrode by a photoengraving method, the transparent conductive layer 416 and the metal layer 417 are etched by wet or dry using the same photoresist pattern. An electrode, a source wiring, a drain electrode, and a pixel electrode are formed. Next, the source electrode 442b and the drain electrode 442
The ohmic contact layer 415 formed of an n ⁺ a-Si: H film or the like between a is removed by dry etching or the like,
Finally, a predetermined pattern is formed by removing the resist (FIGS. 44B and 45C).

At this time, in order to form a storage capacitor, the storage capacitor electrode 419 formed simultaneously with the source wiring is opposed to the next or previous gate wiring 412 via at least the gate insulating film 413. At this time, the storage capacitor electrode 4
Between the gate insulating film 413 and the gate insulating film 413;
Not only the n ⁺ a-Si: H film 415 and the a-Si: H film 414 may be left. As shown in FIG. 46C, the storage capacitor electrode needs to have a structure in which at least a part of the pixel electrode 445 protrudes over the previous or next gate wiring 412 in order to increase the capacitance value. .

Then, a protective film 420 made of an insulating film made of a material such as Si ₃ N ₄ , SiO ₂ , or a mixture and a laminate thereof is formed. In photolithography, a photoresist pattern for removing the protective film 420 is formed so that a contact hole can be formed in a gate terminal portion 423 and a source terminal portion 424 which are connected to an external TCP or the like in order to at least input a signal. After forming a photoresist pattern capable of removing the protective film 420 on the region 443 through which light is transmitted, CF ₄
The protective film 420 is removed by dry etching or wet etching using a system gas. Further, the upper metal layer of the two source wiring material layers is removed. As an etchant, use a solution or gas that etches the upper metal film but does not etch the lower ITO film.
Perform wet or dry etching. This allows
The contact hole and the ITO film of the pixel electrode are exposed. After the etching is completed, the photoresist is removed. This allows
A TFT array is formed (FIG. 45C, FIG. 47).
(A)). The completed plan pattern diagram is shown in FIG.

Next, an alignment film is formed on the TFT array,
At least face the opposing substrate on which the alignment film and common electrode are formed, hold both glass substrates, and form a seal around the liquid crystal, inject liquid crystal between them, seal the injection hole, and activate A matrix type liquid crystal display is formed.

By the above process, a TFT array having the configuration shown in FIG. 28 and a liquid crystal display using the same are formed.

In FIG. 28, for example, a repair wiring 114 of a source wiring formed by using a gate wiring material is shown, but this may not be formed depending on circumstances.

Further, as shown in FIG.
At the intersection with 14, the source wiring 102 may be temporarily converted to a wiring 117 of the same layer as the gate wiring formed of the gate wiring material using the contact holes 116a and 116b. At this time, the repair wiring 114 is formed using a source wiring material.

As shown in FIGS. 48 and 49, the source wiring 302 may be converted into a gate wiring material via a contact hole and connected to the source terminal 308 as shown in FIGS. For example, when the protective film 420 is thin, moisture may enter through a pinhole, and the source wiring may be corroded in the vicinity of the source terminal portion 308 outside the seal portion.
The conversion to the gate wiring material in this way can avoid the problem of corrosion of the source wiring.

Embodiment 13 In the above-described embodiment, a so-called CS on gate in which a storage capacitor is formed between the next or previous gate wiring.
Although the structure e has been described, as shown in the circuit diagram of FIG. 50, a common wiring structure in which a storage capacitor wiring advantageous for gate delay is formed separately from the gate wiring may be used. Here, the storage capacitor 305 is connected to the common wiring 320. The common wiring 320 is connected to a common wiring lead 321 via a contact hole 322. The common voltage is applied from the outside via a common wiring terminal 323 connected to the common wiring lead 321. The functions and figure numbers of the other parts are the same as those in FIG.

In the common wiring system, for example, FIG.
52 (a), 52 (b), 5
2 (c) and the plane arrangement shown in FIGS. 53 (a) and 53 (b). 52 (a), 52 (b), 52 (c), FIG.
(A) and 53 (b) show plan views for each flow. Here, FIG. 51 shows FIGS. 52 (a), 52 (b), 52 (c),
53 (a) and 53 (b) are cross-sectional views taken along line Z1-Z1.
The flow of the cross section is shown in FIGS. 44 (a), 44 (b) and 44 (c).
And basically the same.

As shown in FIG. 50, when a common wiring structure is used, a common wiring 32 extending in parallel with the gate wiring is formed.
0 and a common wiring lead line 321 which runs together and runs perpendicular to the gate wiring 301 are required. In the case of FIG. 50, the common wiring 320 formed at the same time as the gate wiring 301 is connected to the common wiring lead line 321 formed at the same time as the source wiring 302 via the contact hole 322 at the left end.

As shown in FIG. 54, the common wiring 320 is best formed simultaneously with the same material as the gate wiring 301.
At least the intersection 324 of the common wiring lead line 321 with the gate wiring uses a source wiring material in a different layer from the gate wiring. In some cases, the common wiring lead line may be formed of the gate wiring material except for the intersection with the gate wiring.

In addition, as shown in FIG.
At the intersection with 14, the source wiring 302 may be once converted to a wiring 316 of the same layer as the gate wiring formed of the gate wiring material by using the contact holes 315a and 315b.

As shown in FIG. 56, the source wiring 302 may be converted to the same material as the gate wiring via a contact hole and connected to the source terminal 308 via a contact hole. For example, when the protective film 420 is thin, moisture enters through the pinhole, and the terminal portion 308 existing outside the seal portion is formed.
Although the source wiring may be corroded in the vicinity, the problem of corrosion of the source wiring can be avoided by converting to the gate wiring material in this manner. FIG. 4 is a sectional view of a terminal portion having this structure.
Same as 9.

Embodiment 14 FIGS. 47 (a) and 47 (b), FIGS. 53 (a) and 53 (b)
Although the region 443 from which the protective film 420 is removed to remove the metal for transmitting light to the pixel electrode is written inside the 442a as shown in FIG.

Embodiment 15 In Embodiments 12 to 14, the case where the common electrode for applying a voltage to the liquid crystal itself is provided on the opposite substrate has been described. However, an IPS (In-plane switch-in) capable of realizing a wide viewing angle is provided.
g) The present invention can be applied to a TFT substrate for applying a lateral electric field in a mode or the like. In this case, the source wiring is a transparent conductive film 4
16 and the metal layer 417 need not be formed in two layers.
Only 7 may be used. At least two electrodes for a horizontal electric field formed at the same time as the gate electrode (FIG. 62B), at least two electrodes for the horizontal direction formed at the same time as the source electrode, or at least one electrode formed at the same time as the source electrode. At least two lateral electric field electrodes (FIG. 62) in which at least one lateral electric field electrode formed simultaneously with one lateral electric field electrode and at least one horizontal electric field electrode are formed simultaneously.
By using (a), an electrode configuration for applying a horizontal electric field to the liquid crystal can be formed. In this case, the protective insulating film 420
Need not be removed on the pixel electrode as shown in FIG. Further, the protective insulating film need not be formed.

Also, the flow of FIGS. 45 (b) and 45 (c) may be changed to a flow as shown in FIGS. 63 (a) and 63 (b). At this time, the source electrode / wiring is made of a single metal layer. Here, after forming a drain electrode 442a and a source electrode 442b as shown in FIG. 63A, a protective insulating film 420 (SiN) is formed as shown in FIG. 63B. Then, the drain electrode 4
After a contact hole is formed on the common wiring 412 and on the common wiring 412, a third electrode serving as the IPS electrode 447 on the drain electrode side and the IPS electrode 448 on the common wiring side is formed. A plan view is shown in FIG.

Embodiment 16 In the above embodiment, the a-Si: H film is formed into an island shape.
Using a technique such as halftone as shown in FIG.
Although the thickness of the resist is partially changed in a planar shape, this step may be stopped and photolithography of island formation of the a-Si: H film may be performed separately. In this case, for example, the thickness of the resist is not changed spatially. In the state of FIG. 44 (b), the contact portion 42 is not planarly changed in thickness of the resist.
3 on SiN 413 / a-Si: H414 / n ⁺ a-
After performing the step of removing Si: H415, the resist is removed, a pattern for forming a transistor island is again formed, and the a-Si: H film 414 other than the TFT portion and the n ⁺ a-S
The i: H film 415 is removed by etching, and FIG.
The structure of is manufactured. In this case, the number of photolithography steps increases as compared with FIG. 28, but can be reduced as compared with the conventional example.

Embodiment 17 According to the above embodiment, the semiconductor layer is formed of the a-Si: H film, but may be formed of poly-Si.

Embodiment 18 An n ⁺ a-Si: H film 415 is formed of an n + microcrystal S
In this case, the ITO layer 416 and the n ⁺ a
-Si: The contact resistance between the H films 415 decreases,
The ON current of T can be improved.

Embodiment 19 The ITO layer 416 used also as the source wiring may be amorphous ITO. At the same time, when an Al-based material such as Al or Cr / Al is used as the source metal, the ITO
Can be used as an etchant having low corrosiveness to Al such as oxalic acid, which can reduce the corrosion of Al during etching.

Embodiment 20 In the above embodiment, when an Al-based material is used for the gate, the contact with the ITO layer can be improved if the surface of Al and its alloy is made of Al nitride or oxide.

Embodiment 21 In the above embodiment, the surface of the n ⁺ a-Si: H film 415 may be slightly exposed to oxidizing plasma or the like to be oxidized, whereby the ITO 416 and the n ⁺ a-Si: Variation in contact resistance between the H films 415 can be reduced.

[0153]

According to the thin film transistor array substrate and the method of manufacturing the same of the present invention, an insulating substrate, a first metal pattern formed on the insulating substrate, an insulating film on the first metal pattern, A semiconductor pattern on the film, a second metal pattern on the semiconductor pattern, and the semiconductor pattern includes the second metal pattern. Since there is no semiconductor layer step, source disconnection hardly occurs, and since the patterns of the source electrode and the drain electrode are included in the semiconductor pattern and do not intersect, the leakage current can be suppressed to a low level.

Further, since at least a part of the outer edge of the semiconductor pattern including the source wiring and the drain electrode enters inside the outer edge of the gate wiring, it is possible to suppress the occurrence of a leak current due to light leak or the like.

As described above, according to the present invention, a TFT array can be formed in four photolithography steps of a mask, so that a low-cost TFT array can be realized.
Cost reduction and increased production can be realized.

[Brief description of the drawings]

FIG. 1 is a plan view of a thin film transistor array according to a first embodiment of the present invention.

2A is a sectional view taken along line AA of FIG. 1, FIG. 2B is a sectional view taken along line BB of FIG. 1, and FIG. 2C is a sectional view taken along line CC of FIG.

FIG. 3 is a plan view of a thin film transistor array in each step of the first embodiment of the present invention.

FIG. 4 is a plan view of a thin film transistor array in each step of the first embodiment of the present invention.

FIG. 5 is a plan view of a thin film transistor array in each step of the first embodiment of the present invention.

FIG. 6 is a plan view of a thin film transistor array in each step of the first embodiment of the present invention.

FIG. 7 is a plan view of a thin film transistor array in each step of the first embodiment of the present invention.

FIG. 8 is a cross-sectional view of each step of the first embodiment of the present invention.
It is sectional drawing in A.

FIG. 9 is a sectional view taken along line A- in FIG. 1 in each step of the first embodiment of the present invention.
It is sectional drawing in A.

FIGS. 10A and 10B show each step of the first embodiment of the present invention.
It is sectional drawing in -A.

FIG. 11A is a view illustrating each step of the first embodiment of the present invention.
It is sectional drawing in -A.

FIGS. 12A to 12C show the respective steps of the first embodiment of the present invention.
It is sectional drawing in -A.

FIG. 13A is a view illustrating each step of the first embodiment of the present invention.
It is sectional drawing in -A.

FIG. 14A is a view showing each step of the first embodiment of the present invention.
It is sectional drawing in -A.

FIG. 15 is a plan view of a thin film transistor array according to a second embodiment of the present invention.

FIG. 16 is a plan view of a thin film transistor array in each step of the second embodiment of the present invention.

FIG. 17 is a plan view of a thin film transistor array in each step of the second embodiment of the present invention.

FIG. 18 is a plan view of a thin film transistor array in each step of the second embodiment of the present invention.

FIG. 19 is a plan view of a thin film transistor array in each step of the second embodiment of the present invention.

FIG. 20 is a plan view of a thin film transistor array in each step of the second embodiment of the present invention.

FIG. 21 is a diagram illustrating a TFT portion pattern of a mask used in the second photolithography according to the second embodiment of the present invention.

FIG. 22 is a plan view of a thin film transistor array according to a third embodiment of the present invention.

FIG. 23 is a plan view of a thin film transistor array in each step of the third embodiment of the present invention.

FIG. 24 is a plan view of a thin film transistor array in each step of the third embodiment of the present invention.

FIG. 25 is a plan view of a thin film transistor array in each step of the third embodiment of the present invention.

FIG. 26 is a plan view of a thin film transistor array in each step of the third embodiment of the present invention.

FIG. 27 is a plan view of a thin film transistor array in each step of the third embodiment of the present invention.

FIG. 28 is a circuit diagram of a TFT array substrate of an active matrix liquid crystal display device to which the present invention is applied.

FIG. 29 is a cross-sectional view showing a manufacturing step of the TFT array substrate of the present invention.

FIG. 30 is a cross-sectional view showing a step of manufacturing the TFT array substrate of the present invention.

FIG. 31 is a cross-sectional view showing a manufacturing step of the TFT array substrate of the present invention.

FIG. 32 is a plan view corresponding to FIGS. 29, 30, and 31.

FIG. 33 is a diagram showing an example of a pattern of a halftone mask.

FIG. 34 is a circuit diagram showing an example of an intersection of a source wiring and a repair wiring.

FIG. 35 is a circuit diagram showing a common wiring system in which a storage capacitor wiring is provided separately from a gate wiring.

FIG. 36 is a cross-sectional view showing a configuration of a common wiring system.

FIG. 37 is a plan view corresponding to FIG. 9;

FIG. 38 is a plan view showing another example of the common wiring system.

FIG. 39 is a circuit diagram showing an intersection of a source wiring and a repair wiring in a common wiring scheme.

FIG. 40 is a plan view showing an example of a plane arrangement in which a light-shielding pattern is formed around a pixel electrode.

FIG. 41 is a plan view showing an example of a plane arrangement in the IPS mode.

FIG. 42 is a cross-sectional view showing another method for manufacturing the TFT array substrate of the present invention.

FIG. 43 is a cross-sectional view showing another method for manufacturing the TFT array substrate of the present invention.

FIG. 44 is a cross-sectional view showing a step of manufacturing the TFT array substrate of the present invention.

FIG. 45 is a cross-sectional view showing a step of manufacturing the TFT array substrate of the present invention.

FIG. 46 is a plan view corresponding to FIGS. 44 and 45.

FIG. 47 is a plan view corresponding to FIGS. 44 and 45.

FIG. 48 is a circuit diagram of a TFT array substrate of an active matrix liquid crystal display device to which the present invention is applied.

FIG. 49 is a cross-sectional view of an example of a source portion.

FIG. 50 is a circuit diagram showing a common wiring method of a storage capacitor.

FIG. 51 is a cross-sectional view showing a cross-sectional structure of the TFT array substrate of the present invention.

FIG. 52 is a plan view corresponding to FIG. 51.

FIG. 53 is a plan view corresponding to FIG. 51.

FIG. 54 is a circuit diagram showing a common wiring system for holding capacitors.

FIG. 55 is a circuit diagram showing a common wiring system of storage capacitors.

FIG. 56 is a circuit diagram showing a common wiring system of storage capacitors.

FIG. 57 is a sectional view of a thin film transistor portion in a conventional structure.

FIG. 58 is a plan view of a thin film transistor portion in a conventional structure.

FIG. 59 is a cross-sectional view showing a step of manufacturing a TFT array substrate of a conventional active matrix liquid crystal display device.

FIG. 60 is a cross-sectional view showing a step of manufacturing a TFT array substrate of a conventional active matrix liquid crystal display device.

FIG. 61 is a plan view of a TFT array substrate of a conventional active matrix type liquid crystal display device.

FIG. 62 is a plan view of a lateral electric field TFT array substrate.

FIG. 63 is a cross-sectional view showing a manufacturing step corresponding to FIG. 62 (c).

FIG. 64 is a plan view showing another mode corresponding to FIG. 1;

FIGS. 65 (a) to 65 (d) are cross-sectional views showing another embodiment corresponding to FIGS. 2 (a) to 2 (d).

FIG. 66 is an explanatory view showing a further step which is added to the manufacturing steps shown in FIGS. 3 to 5;

FIG. 67 is an explanatory view showing a manufacturing step of another mode corresponding to FIG. 13;

FIG. 68 is an explanatory view showing a manufacturing step of another mode corresponding to FIG. 14;

FIG. 69 is a plan view showing another mode corresponding to FIG. 15;

70 is added to the manufacturing process shown in FIGS.
It is explanatory drawing which shows a further process.

FIG. 71 is a plan view showing another mode corresponding to FIG. 22;

FIG. 72 is a view showing an example of a manufacturing process shown in FIGS.
It is explanatory drawing which shows the process performed instead of the process shown to 6-27.

FIG. 73D showing another mode of the semiconductor region;
FIG.

FIG. 74 is an explanatory view corresponding to (d) of FIG. 32 and illustrating still another mode of the semiconductor region.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Gate wiring 1a Gate terminal metal pad 2 Auxiliary capacitance wiring 2a IPS counter electrode 3 Gate insulating film 4 Semiconductor pattern 4a Semiconductor layer 4b Ohmic layer 5 Source wiring 5a Source terminal metal pad 6 Source electrode 7 Drain electrode 8 Thin film transistor semiconductor active layer Reference Signs List 9 interlayer insulating film 10 drain electrode contact hole 11 gate terminal portion contact hole 12 source terminal portion contact hole 13 pixel electrode 13a IPS electrode 14 gate terminal connection pad 15 source terminal connection pad 16 second metal film 17a second photolithography normal thickness Resist pattern 17b, 17c, 17d, 17e Second photolithography thin film pattern 18 Second photolithography resist pattern Opening after ashing 19 TFT section pattern 51 Gate wiring 52 Gate insulating film 53 Semiconductor 54 Ohmic layer 55 Source wiring 56 Source electrode 57 Drain electrode 58 Thin film transistor semiconductor active layer 59 Interlayer insulating film 60 Contact hole 61 Pixel electrode 62 Edge leakage path 101 Gate wiring 102 Source wiring 103 Thin film transistor (TFT) 104 Liquid crystal (capacitance) 105 Storage capacitance 106 Common electrode 107 Gate terminal 108 Source terminal 109, 110 High resistance element 111 Wiring A 112 Wiring B 113 Wiring A, B connection 114 Repair wiring 115 Separation line 120 Common wiring 121 Common wiring lead 211 Insulating substrate 212 Gate electrode and Gate line (transparent conductor layer) 213 Gate electrode and gate line (metal layer) 214 Pixel electrode (transparent conductor layer) 215 Pixel electrode (metal layer) 216 Gate insulating film 21 Semiconductor layer (active layer) 218 Semiconductor layer (contact layer) 219, 219a, 219b Photoresist 220a Source wiring 220b Drain electrode 220c Source electrode 221 Storage capacitor electrode 222 Insulating film 224 Gate terminal 225 Source terminal 230 Semiconductor region 231 232 Pixel Electrode 233 Halftone mask 302 Source wiring 305 Storage capacitance 308 Source terminal 314 Repair wiring 320 Common wiring 321 Common wiring lead 410 Insulating substrate 411 Gate electrode / wiring 412 Gate electrode / wiring (adjacent) 413 Gate insulating film 414 Semiconductor layer 415 Ohmic contact layer 416 Transparent conductor layer 417 Metal layer 418 Photoresist 419 Storage capacitor electrode 420 Protective insulating film 423 Gate terminal 430 Semiconductor region 443 Light transmission Frequency 445 pixel electrodes 447 and 448 IPS electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) H01L 29/78 617M (72) Inventor Kazushiki 997 Miyoshi, Nishi-Koshi-cho, Kikuchi-gun, Kumamoto Pref. Inside the display (72) Inventor Takuji Yoshida 997 Miyoshi, Nishi-Koshi-cho, Kikuchi-gun, Kumamoto Prefecture Inside Advanced Display Co., Ltd. Inventor Yuichi Masutani 997, Miyoshi, Nishi-Koshi-cho, Kikuchi-gun, Kumamoto Prefecture, Japan Inside the Advanced Display Co., Ltd. (72) Inventor Hironori Aoki 997, Miyoshi, Nishi-Koshi-cho, Kikuchi-gun, Kumamoto Prefecture, Japan

Claims (28)

[Claims] An insulating substrate; a first metal pattern formed on the insulating substrate; an insulating film on the first metal pattern; a semiconductor pattern on the insulating film; A thin film transistor array substrate, comprising: a metal pattern, wherein the semiconductor pattern includes the second metal pattern. 2. The thin film transistor array substrate according to claim 1, wherein, in the source electrode portion of the pixel portion, a portion of the semiconductor pattern including the source electrode portion is formed only on the first metal pattern. 3. An insulating substrate, the substrate and a gate wiring formed on the substrate, a gate insulating film on the gate wiring, a semiconductor layer on the gate insulating film, a source wiring on the semiconductor layer,
A source electrode, a drain electrode, and a pixel electrode formed on the drain electrode, wherein the semiconductor pattern includes the source wiring, the source electrode, and the drain electrode, and the pixel electrode on the drain electrode is A thin film transistor array substrate, which is in direct contact with at least a part of a drain electrode. 4. An insulating substrate, the substrate and a gate wiring formed on the substrate, a gate insulating film on the gate wiring, a semiconductor layer on the gate insulating film, a source wiring on the semiconductor layer,
A source electrode, a drain electrode, the source wiring, the source electrode, an interlayer insulating film formed on the drain electrode, a pixel electrode formed on the interlayer insulating film, and the semiconductor pattern includes the source wiring, A first contact hole penetrating the interlayer insulating film, penetrating the interlayer insulating film and reaching the drain electrode, and a second contact hole reaching the source wiring; the gate insulating film and the interlayer insulating film; A thin film transistor array substrate having a third contact hole penetrating an insulating film and reaching the gate wiring, wherein the first to third contact holes are covered with a pattern of the pixel electrode material. 5. The thin film transistor array substrate according to claim 4, wherein, in the source electrode portion of the pixel portion, the semiconductor pattern of the portion including the source electrode portion is formed only on the gate wiring. 6. A method of forming a first metal thin film on an insulating substrate, forming a gate wiring in a first photolithography and etching step, and then forming a gate insulating film, a semiconductor film and an ohmic contact film, After that, in a second photoengraving process, a resist pattern is formed on the source wiring, the source electrode, the drain electrode, and the portion corresponding to the semiconductor active layer of the thin film transistor, at least in the portion corresponding to the semiconductor active layer,
The resist film is formed so as to have a smaller thickness than other portions, and then the second metal film is etched to form a source wiring,
Forming a source electrode and a drain electrode, then etching the ohmic contact film and the semiconductor film, thinning the resist, removing the resist in a portion corresponding to the thin film transistor active layer, and then etching the second metal film The second metal film on the portion corresponding to the semiconductor active layer is removed, then the ohmic film on the portion corresponding to the semiconductor active layer is removed, and then the gate insulating film is patterned by a third photolithography and etching process. To form a contact hole reaching the gate wiring, and then a conductive film is formed.
Forming a pixel electrode so as to connect to the drain electrode in the photolithography and etching steps. 7. After forming a first metal thin film on an insulating substrate, a gate wiring is formed in a first photolithography and etching step, and thereafter, a gate insulating film, a semiconductor film and an ohmic contact film, After that, in a second photoengraving process, a resist pattern is formed on the source wiring, the source electrode, the drain electrode, and the portion corresponding to the semiconductor active layer of the thin film transistor, at least in the portion corresponding to the semiconductor active layer,
The resist film is formed so as to have a smaller thickness than other portions, and then the second metal film is etched to form a source wiring,
Forming a source electrode and a drain electrode, then etching the ohmic contact film and the semiconductor film, thinning the resist, removing the resist in a portion corresponding to the thin film transistor active layer, and then etching the second metal film The second metal film on the portion corresponding to the semiconductor active layer is removed, then the ohmic film on the portion corresponding to the semiconductor active layer is removed, and then the gate insulating film is patterned by a third photolithography and etching process. To form a contact hole reaching the gate wiring, and then a conductive film is formed.
In the photolithography and etching steps, a pixel electrode is formed to connect to the drain electrode, a source terminal is formed to connect to the source wiring, and a gate terminal is formed to connect to the gate wiring via a contact hole. A method for manufacturing a thin film transistor array substrate, comprising: 8. A method of forming a first metal thin film on an insulating substrate, forming a gate wiring in a first photolithography and etching step, and then forming a gate insulating film, a semiconductor film and an ohmic contact film, After that, in a second photoengraving process, a resist pattern is formed on the source wiring, the source electrode, the drain electrode, and the portion corresponding to the semiconductor active layer of the thin film transistor, at least in the portion corresponding to the semiconductor active layer,
The resist film is formed so as to have a smaller thickness than other portions, and then the second metal film is etched to form a source wiring,
Forming a source electrode and a drain electrode, then etching the ohmic contact film and the semiconductor film, thinning the resist, removing the resist in a portion corresponding to the thin film transistor active layer, and then etching the second metal film The second metal film on the portion corresponding to the semiconductor active layer is removed, then the ohmic film on the portion corresponding to the semiconductor active layer is removed, an interlayer insulating film is formed, and then the third photolithography and etching are performed. Patterning the gate insulating film and the interlayer insulating film in a step to form a first contact hole reaching the drain electrode, a second contact hole reaching the source wiring, and a third contact hole reaching the gate wiring; Then, a conductive film is formed, and the pixel electrode is formed through the first contact hole in the fourth photolithography and etching process. Formed to connect to in the electrode,
A thin film transistor array, wherein a source terminal is formed so as to be connected to the source wiring through the second contact hole, and a gate terminal is formed so as to be connected to the gate wiring through the third contact hole. Substrate manufacturing method. 9. A method of forming a first metal thin film on an insulating substrate, forming a gate wiring and a source wiring conversion part in a first photolithography and etching step, and thereafter forming a gate insulating film, a semiconductor film and an ohmic contact. A contact film and a second metal film are formed, and then, in a second photolithography process, a resist pattern is formed at least on the source wiring, the source electrode, the drain electrode, and the portion corresponding to the semiconductor active layer of the thin film transistor. In the portion, the resist film is formed to be thinner than the other portions, and then the second metal film is etched to form a source wiring, a source electrode, and a drain electrode, and then the ohmic contact film and the semiconductor film are formed. Then, the resist is thinned, the resist in the portion corresponding to the thin film transistor active layer is removed, and then the second metal film is etched. To remove the second metal film on the portion corresponding to the semiconductor active layer, thereafter remove the ohmic film on the portion corresponding to the semiconductor active layer, and thereafter, perform third photolithography,
Patterning the gate insulating film in an etching step,
A first contact hole reaching the drain electrode and a second contact hole reaching the source wiring; a third contact hole reaching the gate wiring and a fourth contact hole reaching the gate wiring in the source wiring conversion section; A fifth contact hole reaching the first contact hole is formed, and then a conductive film is formed. In a fourth photolithography and etching step, a pixel electrode is formed so as to be connected to the drain electrode via the first contact hole. Forming a source terminal to be connected to the source line via the second, fourth and fifth contact holes, and forming a gate terminal to be connected to the gate line via the third contact hole; A method for manufacturing a thin film transistor array substrate, comprising: 10. A method of forming a first metal thin film on an insulating substrate, forming a gate wiring and a source wiring conversion part in a first photolithography and etching step, and thereafter forming a gate insulating film, a semiconductor film and an ohmic contact. A contact film and a second metal film are formed, and then, in a second photolithography process, a resist pattern is formed at least on the source wiring, the source electrode, the drain electrode, and the portion corresponding to the semiconductor active layer of the thin film transistor. In the portion, the resist film is formed to be thinner than the other portions, and then the second metal film is etched to form a source wiring, a source electrode, and a drain electrode, and then the ohmic contact film and the semiconductor film are formed. Then, the resist is thinned, the resist in the portion corresponding to the thin film transistor active layer is removed, and then the second metal film is etched. To remove the second metal film on the portion corresponding to the semiconductor active layer, thereafter remove the ohmic film on the portion corresponding to the semiconductor active layer, and then form an interlayer insulating film, and then a third photograph The gate insulating film and the interlayer insulating film are patterned in a plate making and etching process to form a first contact hole reaching the drain electrode, a second contact hole reaching the source wiring, and a third contact hole reaching the gate wiring. And forming a fourth contact hole reaching the first metal film and a fifth contact hole reaching the second metal film in the source wiring conversion portion,
Thereafter, a conductive film is formed, a pixel electrode is formed in the fourth photolithography and etching steps so as to be connected to the drain electrode through the first contact hole, and a source terminal is formed in the second, fourth and fourth steps. 5. A method of manufacturing a thin film transistor array substrate, comprising: forming a gate terminal so as to be connected to the source wiring through the contact hole of No. 5, and connecting the gate terminal to the gate wiring through the third contact hole. 11. The gate wiring and gate electrode are composed of two layers, an upper metal layer and a lower transparent conductor layer.
The transparent conductive layer of the same layer as the transparent conductive layer of the gate wiring / gate electrode is formed.The storage capacitor electrode is formed of the same electrode material as the source wiring and is connected to the pixel electrode. A thin film transistor array substrate for a liquid crystal display device, wherein a metal layer above a gate wiring and a gate electrode is removed. 12. The gate wiring / gate electrode and the common wiring are composed of two layers, an upper metal layer and a lower transparent conductor layer, and the pixel electrode is formed in the same layer as the transparent conductor layer of the gate wiring / gate electrode. The storage capacitor electrode is formed of a transparent conductor layer, the storage capacitor electrode is formed of the same layer of electrode material as the source wiring, and is connected to the pixel electrode.The metal layer on the gate wiring and the gate electrode is removed at the pixel electrode portion. A thin film transistor array substrate for a liquid crystal display device. 13. The gate wiring / gate electrode is composed of two layers, an upper metal layer and a lower transparent conductor layer.
The transparent conductive layer of the same layer as the transparent conductive layer of the gate wiring / gate electrode is formed.The storage capacitor electrode is formed of the same electrode material as the source wiring and is connected to the pixel electrode. If the source wiring material or the source wiring is a multilayer film, at least the material of the lowermost layer of the source wiring is the same material as the metal film on the pixel electrode A thin film transistor array substrate for a liquid crystal display device, comprising: 14. The gate wiring / gate electrode and the common wiring are composed of two layers of an upper metal layer and a lower transparent conductor layer, and the pixel electrode is formed in the same layer as the transparent conductor layer of the gate wiring / gate electrode. The storage capacitor electrode is formed of a transparent conductor layer, the storage capacitor electrode is formed of the same layer of electrode material as the source wiring, and is connected to the pixel electrode.The metal layer on the gate wiring and the gate electrode is removed at the pixel electrode portion. And a thin film transistor array substrate for a liquid crystal display device, wherein when the source wiring material or the source wiring is a multilayer film, at least the material of the lowermost layer of the source wiring is the same material as the metal film on the pixel electrode. 15. A gate wiring / gate electrode comprising at least two layers of a metal layer and a transparent conductor layer, wherein the metal layer is formed on the transparent conductor layer, and a pixel electrode is provided on the gate wiring / gate. A transparent conductive layer of the same layer as the transparent conductive layer of the electrode is formed, a gate insulating film, a semiconductor layer is formed at least on the gate electrode, and a source / drain electrode is formed so as to be in contact with the semiconductor layer. At least the n ⁺ -Si layer of the semiconductor layer between the drain electrodes is removed, and the storage capacitor electrode is formed of the same electrode material as the source wiring and is connected to the pixel electrode. At the same time, the storage capacitor electrode formed of at least two layers of a metal layer and a transparent conductor layer formed at the same time, and the storage capacitor electrode is paired with the gate line with at least a gate insulating film interposed therebetween. A storage capacitor is formed by facing the pixel electrode, and at least a gate insulating film, a semiconductor layer, and a gate electrode / gate formed of at least two layers are formed on the pixel electrode formed at the same time when the electrode is formed. Of these, at least the metal layer is removed, at least a part of the semiconductor layer is removed so that the adjacent source wiring is not short-circuited by the semiconductor layer, and the gate insulating film immediately below the semiconductor layer has a thickness of other gate insulating layers. A thin film transistor array substrate for a liquid crystal display device, wherein the thickness is larger than the film thickness. 16. The gate wiring / gate electrode and the common wiring are composed of at least two layers of a metal layer and a transparent conductor layer.
The metal layer is formed on the transparent conductor layer, and the pixel electrode is formed from the same transparent conductor layer as the transparent conductor layer of the gate wiring / gate electrode, and the gate insulating film and the semiconductor layer are formed. A source / drain electrode is formed at least on the gate electrode, in contact with the semiconductor layer, and n ⁺ -S
The i-layer is at least removed, the storage capacitor electrode is formed of an electrode of the same layer as the source wiring, is connected to the pixel electrode, and has at least one of the gate wiring or a metal layer formed simultaneously with the gate wiring and the transparent conductor layer. A storage capacitor is formed by sandwiching a storage capacitor line formed of two layers and at least the gate insulating film with the storage capacitor electrode facing the common line, and at least a gate insulating film is formed on a portion of the pixel electrode that transmits light. A semiconductor layer, at least a metal layer of a pixel electrode formed at the same time as forming a gate wiring and a gate electrode comprising at least two layers is removed, and at least a semiconductor layer is formed so that an adjacent source wiring is not short-circuited by the semiconductor layer. Partially removed, it is noted that the thickness of the gate insulating layer immediately below the semiconductor layer is larger than the thickness of the other gate insulating layers. Thin film transistor array substrate of a liquid crystal display device according to. 17. A structure in which a gate electrode, a gate wiring, and a pixel electrode are composed of at least two layers of a transparent conductor layer and a metal layer, and the metal layer is formed on the transparent conductor layer to form a film. A step of forming each predetermined pattern by performing etching using a photoresist of each pattern shape; a step of forming a gate insulating film and a semiconductor layer; and performing an etching process using the photoresist of each pattern shape. Exposing the pixel electrode; removing the metal layer on the exposed pixel electrode by etching on the pixel electrode having the at least two-layer structure;
A method for manufacturing a thin film transistor array substrate of a liquid crystal display device, comprising a step of forming a source wiring. 18. A structure in which a gate electrode, a gate wiring, and a pixel electrode are composed of at least two layers of a transparent conductor layer and a metal layer, and a film is formed such that the metal layer is an upper layer of the transparent conductor layer. A step of forming each predetermined pattern by performing etching using a photoresist of each pattern shape; a step of forming a gate insulating film and a semiconductor layer; and performing an etching process using the photoresist of each pattern shape. Exposing the pixel electrode, forming a drain electrode / source electrode / source wiring metal layer, and performing etching using the photoresist of the respective pattern shapes to form a drain electrode / source electrode / source wiring. Removing the upper metal layer in the at least two-layer structure of the exposed pixel electrode. A method for manufacturing a thin film transistor array substrate of a liquid crystal display device. 19. A structure in which a gate electrode / gate wiring and a pixel electrode are composed of at least two layers of a transparent conductor layer and a metal layer, and a film is formed so that a metal is formed on an upper layer of the transparent conductor layer. A step of forming respective predetermined patterns by performing etching using a photoresist having a pattern shape of, a step of forming a gate insulating film and a semiconductor layer, and a region A in which the thickness of the photoresist is increased at least a portion where the semiconductor layer is left. Forming a region C in which the host resist has been removed to expose at least a portion of the pixel electrode that transmits light, and a region B in which the thickness of the photoresist in other portions is smaller than the thickness of the semiconductor layer portion; The layer and the gate insulating layer are etched in the respective patterns using the photoresist having the above-mentioned thickness to expose the pixel electrodes. A step of removing the metal layer above the at least two-layer structure in the exposed pixel electrode by etching; a step of removing the photoresist from the area B while leaving the photoresist in the area A; A method of manufacturing a thin film transistor array substrate of a liquid crystal display device, comprising the steps of: removing a semiconductor layer and forming source / drain electrodes. 20. A structure in which a gate electrode / gate wiring, a pixel electrode, and a common wiring are composed of at least two layers of a transparent conductor layer and a metal layer, and the metal layer is formed on the transparent conductor layer, The step of forming each predetermined pattern by etching it using the photoresist of the respective pattern shapes, the step of forming a gate insulating film and a semiconductor layer, and the thickness of the photoresist, at least the portion where the semiconductor layer is left. A region A where the thickness is increased, a region C where the photoresist is removed to expose at least a portion of the pixel electrode that transmits light, and a region B where the thickness of the photoresist in other portions is smaller than the thickness of the semiconductor layer are formed. And etching the semiconductor layer and the gate insulating layer in the respective patterns using the photoresist having the thickness. Exposing the elementary electrodes, removing the metal layer above the at least two-layer structure in the exposed pixel electrodes by etching, removing the photoresist from the area B while leaving the photoresist in the area A; A method for manufacturing a thin film transistor array substrate for a liquid crystal display device, comprising: a step of removing a semiconductor layer in a portion other than A; and a step of forming source / drain electrodes. 21. A structure in which a gate electrode / gate wiring and a pixel electrode are composed of at least two layers of a transparent conductor layer and a metal layer, and a film is formed such that the metal layer is an upper layer of the transparent conductor layer. A step of forming each predetermined pattern by performing etching using a photoresist of each pattern shape, a step of forming a gate insulating film and a semiconductor layer, and a region where the thickness of the photoresist is increased at least a portion where the semiconductor layer is left. A, a region C where the photoresist has been removed to expose at least a portion of the pixel electrode that transmits light, and a process in which the thickness of the photoresist in other portions is smaller than the thickness of the semiconductor layer portion and a process of forming the region B. And etching of the semiconductor layer and the gate insulating layer in the respective patterns using the photoresist having the above-mentioned thickness. Exposing the poles, removing the photoresist from the region B while leaving the photoresist in the region A, removing the semiconductor layer in a portion other than the region A, and removing the photoresist from the same metal material applied to the upper layer of the gate wiring. Forming a source / drain electrode, and simultaneously removing the metal layer above the at least two-layer structure in the exposed pixel electrode by removing the source / drain electrode by etching. A method for manufacturing a thin film transistor array substrate of a display device. 22. A source wiring and a gate wiring are formed on a matrix, at least a thin film transistor and a pixel electrode for applying a voltage to a liquid crystal are present at an intersection thereof, and a gate electrode and a gate insulating film formed thereon are provided. And at least two layers of a semiconductor layer formed so as to be in contact with the gate insulating film on at least the gate electrode, a transparent conductive film formed so as to be at least partially in contact with the semiconductor layer, and a metal film formed thereon. The drain electrode and the pixel electrode are connected by the transparent conductive film itself, and the light-transmitting portion of the pixel electrode has a protective film and a metal film immediately above the pixel electrode removed. A thin film transistor array substrate for a liquid crystal display device. 23. A step of forming at least a gate insulating film and a semiconductor layer on a gate electrode, a region (A) in which the thickness of the photoresist is increased to leave a portion of the semiconductor layer, and removing the photoresist to expose at least the gate wiring Forming a region (C) which has been formed and a region (B) where the thickness of the photoresist is thinner than the thickness of the semiconductor layer in the other portions. To remove at least the gate insulating film and the semiconductor layer on the gate wiring and to expose a part of the gate electrode; and to reduce the thickness of the photoresist and leave the photoresist in the region (A) in the region ( B) a step of removing the photoresist, and a step of removing the semiconductor layer other than the region (A) using the photoresist. A method for manufacturing a thin film transistor array substrate of a liquid crystal display device, comprising: 24. A step of forming a conductive material for a gate electrode and a gate wiring and etching the same using a photoresist having a pattern shape of the gate electrode and the gate wiring to form respective predetermined patterns; Gate insulating film,
A step of forming a semiconductor layer, a region (A) in which the thickness of the photoresist is increased in a portion where the semiconductor layer is left, a region (C) in which the photoresist is removed to expose at least a part of the gate wiring, and other portions Where the thickness of the photoresist is smaller than the thickness of the semiconductor layer (B)
Forming a semiconductor layer and a gate insulating layer by using a photoresist having the above-mentioned shape to expose at least a part of the gate wiring; and removing the photoresist in the region (B) while leaving the photoresist in the region A. Removing the semiconductor layer in a portion other than the region (A) using the photoresist; and forming a transparent conductive layer formed so that at least a portion thereof is in contact with the semiconductor layer and a metal layer formed thereon. Forming a source / drain electrode using a photoresist having a pattern shape of the source / drain electrode, forming a protective film, and removing at least a portion of the protective film that transmits light on the pixel electrode; Removing the metal layer on the transparent conductive layer from the area where the protective film formed on the electrode has been removed to form a pixel electrode. TFT array substrate manufacturing method of a liquid crystal display device according to claim. 25. A region including the thin film transistor,
A semiconductor layer having a pattern including at least a part of the source wiring and a region including the source electrode, wherein a portion including the source electrode of the pattern of the semiconductor layer in the pixel portion is formed only on the gate wiring; Claim 11, 12, 13, 14, 15, 16 or 22
The thin film transistor array substrate according to any one of the preceding claims. 26. The method of forming a semiconductor layer, wherein the pattern of the semiconductor layer includes a region including a thin film transistor, and a region including at least a part of a source wiring and a source electrode. 17. The semiconductor device according to claim 17, wherein a portion including the source electrode of the pattern of the semiconductor layer is formed only on the gate wiring.
The method for producing a thin film transistor array substrate according to 8, 19, 20, 21, 23 or 24. 27. The method of claim 6, 7, 8, 9, 10, 17,
A liquid crystal display device comprising a thin film transistor array substrate manufactured by using the manufacturing method described in 18, 19, 20, 21, 23 or 24. 28. The method of claim 1, 2, 3, 4, 5, 11, 1.
A liquid crystal display device manufactured using the thin film transistor array substrate described in 2, 13, 14, 15, 16 or 22.