JP2001337643A - Digital image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital image display device which is capable of realizing good gradation even with a simple and inexpensive circuitry by enhancing efficiency in a light source utilization. SOLUTION: This device is the digital image display device 1 to represent the gradation of the picture 25a by weighting a light emitting time of the pixel 25a on a bit plane by bit plane basis mainly through a pulse width modulation method in plural bit planes each of which has plural pixels 25a arranged in a matrix form, and is equipped with the optical space modulators 7, 7a to binary modulate to light or not to light the light source 5 emitting on each one of pixel 25a and the control means 11 to control the optical space modulator so that plural pixels 25a can be sequentially driven on line by line in a unit where plural pixels 25a are grouped on plural lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image display device for displaying an image by modulating light from a light source by an optical spatial modulator that performs binary modulation for each pixel.

[0002]

2. Description of the Related Art In recent years, it has been required to reduce the size of an image display device, and an image display device using a small optical spatial modulator has been frequently used. The optical spatial modulator has a function of displaying a desired image by modulating light from a light source for each pixel. Examples of the optical spatial modulator include, for example, a liquid crystal panel and a ferroelectric liquid crystal (FLC: FLC).
erroelectric Liquid Christ
al) panels. The liquid crystal panel has a problem that response speed is slow and high-speed operation is difficult. On the other hand, it is difficult for the ferroelectric liquid crystal to continuously change the liquid crystal state, and usually, it can take only two states. Therefore, this ferroelectric liquid crystal panel can perform only binary modulation of ON or OFF to modulate light.

When an image display device using such an optical spatial modulator gives a gradation to luminance, pulse width modulation is performed by a combination of ON and OFF of light by the optical spatial modulator. The human eye has afterglow properties,
The amount obtained by integrating the amount of incident light is recognized as luminance. For this reason, if the ON / OFF time of each pixel of the optical spatial modulator is controlled, a change in luminance (referred to as a gray scale) to human eyes.
Will be recognized as there is.

FIG. 15 is a block diagram showing an example of an electrical configuration of a general light valve 107. As shown in FIG. The light valve 107 as the optical spatial modulator is, for example, 1920
A pixel group 12 which is an aggregate of × 1080 pixels 125a
5, a ferroelectric liquid crystal 129, a line address decoder driver 141, a line data latch 139, and a shift register 137. The line address decoder driver 141 controls the line addresses 0 to 1 in the pixel group 125.
079 is specified. The shift register 137 has a configuration in which 120 16-bit shift registers are arranged. The image is configured by the human eye by instantaneously displaying a plurality of frames, and is displayed based on pixel data in pixel units. The shift register 137 divides the input pixel data obtained by dividing one line (1920 bits) of a certain bit plane into 120 pieces by 16 (19
(20/120) bits. The line data latch 139 is connected to the shift register 13
7 stores pixel data for each line. Accordingly, the light valve 107 processes the frame data for each pixel data of one line of each bit plane under the control of a read / write controller (not shown).

[0005] Here, for comparative study, 200 is an example.
Consider a case in which all data for one bit plane is written to each pixel 125a of the light valve 107 within a time of μs. The data transfer by the 120 data lines in the light valve 107 is 16 × 10 in 200 μs.
This means that 80-bit pixel data is taken in.
Therefore, the data transfer time of 1-bit pixel data is 0.0115 μs, and the data transfer rate is 86.4.
Mhz. This value is a data transfer time or the like which can be sufficiently realized even in the current digital image display device 101. Here, 200 μs is exemplified for the following reason. That is, the minimum display period width when gradation is expressed by 8 bits is 65.4 μs,
To achieve this, it is necessary to greatly increase the number of 120 data lines or to further increase the data transfer rate of 86.4 MHz. Therefore, in order to reduce the number of data lines to 120 or less and the data transfer rate to 90 Mhz or less, the data transfer rate must be 200
This is because it is desired to be about μs. On the other hand, in order to complete the data transfer within the minimum inversion time of 65.4 μs when performing the gradation expression with 8 bits, it is necessary to further increase the number of data lines 120 or further increase the data transfer rate 86.4 MHz. There is. However, in this method, the manufacturing cost increases due to the increase in the number of data lines. The buffer memory system has improved this disadvantage. In this buffer memory system, the same effect as the short emission time can be realized even if the data transfer rate is not high.

FIG. 16 is a diagram showing a configuration example of the pixel group 125 of FIG. 15, and FIG. 17 is a diagram showing bit planes B0 to B7.
FIG. 3 is a diagram showing an example of the configuration of FIG. The image display device is, for example, an HD
The light valve 107 adopts a (High Definition) method. The light valve 107 has, for example, 1920 horizontal pixels × 1080 vertical pixels 1
It has a pixel group 125 composed of 25a. In this image display device, one pixel expresses 256 gradations by, for example, 8 bits. The image data (frame data) constituting the screen is represented by a bit plane B0 (LS
B) to B7 (MSB) can be used for gradation expression.

Each of the bit planes B0 to B7 is composed of, for example, 1920 × 1080 pixel data. Each of the bit planes B0 to B7 has a plurality of binary pixel data (“0” or “1”) weighted the same. Each of the bit planes B0 to B7 has a display period (pixel emission time) as the above-mentioned weighting.
Are allocated.

For example, when displaying an image in which 256 gradations are displayed, the bit plane B0 is set to the subfield SF.
It is displayed for a period of 0. Subsequently, the bit plane B1 is displayed during the subfield SF1. Similarly, bit planes B2 to B7 are displayed during the subfields SF2 to SF7, respectively. Then, after the display up to the bit plane B7, the bit planes of the next image are sequentially displayed again.

[0009] Here, the time ratio of each subfield is S
F0: SF1: SF2: SF3: SF4: SF5: SF
6: SF7 = 1: 2: 4: 8: 16: 32: 64: 12
8 is assumed. As a result, the bit plane B0 becomes an image display in which the luminance level recognized by the human eye is 1. The bit plane B1 displays an image with a luminance level of 2 recognized by the human eye. In the same manner, the bit planes B2 to B7 display images with luminance levels of 4 to 128 recognized by the human eye, respectively. Then, the digital image display device 1 controls each of these bit planes B0 to B7.
Can be displayed in 256 gradations. That is, the image display device 1 continuously displays these eight bit planes B0 to B7, so that the human eye can recognize an image displayed in 256 gradations due to the afterimage effect.

The first conventional image display device disclosed in US Pat. No. 5,339,116 employs a buffer memory system. FIG. 18 is a block diagram showing an example of an electrical configuration of one pixel of the light valve 107 in the first conventional image display device. The light valve 107 is
The pixel driving circuit 127 includes a first memory M1 and a second memory M2. This conventional first image display device includes, in addition to a first memory M1 for holding image data indicating a display state (on / off) of each pixel in an image for a certain display period, and simultaneously and in parallel with the next display period. Has a second memory M2 for capturing and storing image data of an image to be displayed.

In this conventional first image display device, after the image data for one screen is arranged in the first memory M1, the image data for all pixels are simultaneously transferred from the first memory M1 to the second memory M1. It is set to M2, and is driven for each pixel by the pixel drive circuit 127 based on the contents of the second memory M2. Accordingly, in the first conventional image display device, a new display period for displaying a new image is started. Then, the first image display device in the related art ends all the pixels of the image data stored in the second memory M2 at once, thereby ending the predetermined display period. Such an image display device is characterized in that a display period can be set independently of the length of a period for rewriting image data in the first memory M1.

FIGS. 19 and 20 are timing charts showing an example of the relationship between the data transfer timing to the first memory M1 and the display period in FIG. 18, respectively. FIG.
Indicates that the data rewriting time Tw (writing period) for the first memory M is the display period (the display time of the contents of the second memory M2).
FIG. 20 shows a case where the data rewriting time Tw to the first memory M is longer than the display period. In the drawing, “response of pixel (display state)” indicates a state where the pixel actually emits light or does not emit light. The “x” part in FIGS. 19 and 20 indicates a transition period of the on / off state.

In FIG. 19, the switching of the bit plane display is performed by simultaneous writing (timing A at the left end) from the first memory M1 to the second memory M2, and at the same time, the first bit of the image data of the next bit plane BP1 is changed. To the memory M1 is started. In FIG. 20, the start of the display is started by simultaneous writing from the first memory M1 to the second memory M2 (timing A at the left end), and the end of the display is performed by the second memory M2.
At the same time (time B at the right end). Note that timings B to
The timing A is an off period and a period during which black display is performed.

By the simultaneous reset, the display becomes a luminance level 0 (off state) for displaying black, and until the second memory M2 is rewritten next, that is, the current subfield period (display is performed based on the bit plane). Period). The display period is determined by two points of simultaneous writing (timing A) and simultaneous reset (timing B), and a time width smaller than the data transfer speed can be set.

The second conventional image display device disclosed in US Pat. No. 5,757,348 employs a sequential writing method. FIG. 21 is a block diagram showing an electrical configuration example of one pixel of the light valve 107 in the second conventional image display device. The configuration of the light valve 107 is almost the same as the configuration shown in FIG. This light valve 107 has one memory M for storing image data. In this sequential writing method, for example, the memory M and the pixel driving circuit 127 can be configured with a very simple configuration having one capacitor and one transistor. The memory M stores pixel data during the subfield period, and displays an image based on the stored image data.

FIG. 22 is a diagram showing the relationship between the display period of each bit plane B0 to B5 and the data rewriting time Tw.
In FIG. 22, for example, it is assumed that one pixel is expressed by 6-bit gradation. Bit plane B5 (MS
The subfield SF5 of B) is 32 times as long as the subfield SF0 (minimum display period) of the bit plane B0, and the subfield SF4 is 16 times as long.
Subfield SF3 is eight times longer, subfield SF2 is four times longer and subfield SF1
Is twice as long. Therefore, subfield SF0
Is 1/63 of 16.667 ms of one frame time, and 2
65 μs. The image display device displays the data rewriting time Tw.
Is shorter than 265 μs (SF0), the image (frame) can be displayed without having a separate buffer memory for holding the image data of the next frame to be displayed while the image (frame) is being displayed.

FIG. 23 is a diagram showing the relationship between the data rewriting time Tw and the subfield SF1 and the like. Time T1 to T2
Corresponds to the display period of the subfield SF1. Data is sequentially written from line address 0 at the timing of time T1, and all data of bit plane B1 is written to all lines after data rewriting time Tw. The next bit plane B0 is written from the line address 0 at the signal T2 indicating the end of the display period of the subfield SF1 and the start of the subfield SF0. In this way, the data rewriting time Tw is changed to the subfield S
If it is shorter than F1, a sufficient light emission time (display period) is given to all the lines.

FIG. 24 is a diagram showing how pixel data is rewritten for each line. Each of the 120 shift registers SR0 to SR119 shown in FIG. 15 captures one line of 1920-bit pixel data L0 in, for example, 16 clocks. During this time, for example, 1920-bit pixel data L1079 is simultaneously held in the line data latch 139 in FIG. This one line of pixel data L1079 is simultaneously sent to each pixel of the line 1079 specified by the line address decoder driver 141, and the memory M in FIG. 21 is rewritten. Therefore, it takes, for example, 16 × 1080 clocks to rewrite the pixel data of the memory M of all lines. Therefore, in order to complete the rewriting of all pixel data in, for example, 200 μs, it is necessary to use 86 MHz (16 × 1).
080/200). As the pixel data increases to 7 bits and 8 bits, the required data rewriting time Tw becomes 133 μs and 66 μms, and the clock rates are 130 MHz and 260 M, respectively.
Hz, which is practically difficult to implement.

As a modification of the conventional second image display device, a method has been proposed in which, when applied to a projection device, the illumination (or luminance) of a lamp as a light source is changed. In the second conventional image display device, the time width of the subfield SF0 (minimum display period) of the bit plane B0 is made longer by reducing the irradiation amount of the lamp, and the image resolution is secured.

Further, as a third conventional image display apparatus, there is an apparatus adopting a sub-pixel system. The sub-pixel method is also called a pixel division method, and is a method of realizing 8-bit gray scale without increasing a clock rate by a sequential writing method. FIG. 25 is a plan view showing a configuration example of one pixel of the light valve 107 in the third conventional image display device. The conventional third image display device includes one pixel, for example, a main pixel 125aa having an area of ／ of one pixel and １ ／ of one pixel.
Is divided into two sub-pixels 125ab having an area of The main pixel 125aa and the sub-pixel 125ab in one pixel can be driven independently, and have the same display period.
To express the luminance at the minimum in a certain pixel,
If the sub-pixel 125ab is displayed, it is possible to express a small luminance even if the time for displaying the pixel is long,
The resolution of the luminance of the pixel can be obtained.

FIG. 26 is a diagram showing an example of a sub-field display period for expressing an 8-bit gray scale by the sub-pixel method of FIG. The display period of the hatched subfields SF0 (LSB) and SF1 is shown in FIG.
The gradation is expressed by the driving period of only the five sub-pixels 125ab. Subfield SF0 is subfield S
The time width is the same as F2 (minimum display period), and the subfield SF1 is twice as long as the subfield SF2. Since the area of one pixel of the sub-pixel 125ab is １ ／, the luminance level is ４ ， and の of the sub-field SF2, and an 8-bit gray scale can be realized in the same minimum display period.

[0022]

SUMMARY OF THE INVENTION However, the conventional first
In the image display device described above, two memories are required for each pixel, and the amount of circuits and wiring for driving one pixel is large. For this reason, the conventional first image display device has a large pixel size in the same semiconductor process, which is disadvantageous for high definition of an image. Further, the conventional first image display device requires an advanced semiconductor process in order to realize the same pixel size, and has a disadvantage of increasing the cost. Therefore, the conventional first image display device has the disadvantages that the manufacturing cost is increased due to the integration, and the disadvantage that it is disadvantageous when trying to reduce the size of one pixel because two memories are provided for each pixel. there were.

In the conventional second image display device, 1
Since the circuit configuration per pixel can be simplified and downsized, it is suitable for high integration of pixels. However, subfield SF0 of bit plane B0 (minimum display period)
Is limited by the data rewriting time of the memory M. That is, there is a problem that the display of the bit plane B0 cannot be switched until the data of the memory M is completely rewritten. Therefore, in the second conventional image display device, if the data to be written in the memory M is large, it is not possible to display an image with high gradation expression at high speed. Further, in a modification of the second conventional image display device, it is difficult to finely and accurately modulate the brightness of a lamp in a commonly used projection device.

Further, in the third conventional image display device, since the pixel is divided into the main pixel 125aa and the sub-pixel 125ab, the number of pixels is doubled, the pixel size is reduced, and the pixel configuration is complicated. there were.

Accordingly, an object of the present invention is to provide a digital image display device which can solve the above-mentioned problems, improve the light use efficiency of a light source and realize a high gradation while being inexpensive with a simple circuit configuration. I have.

[0026]

According to the first aspect of the present invention, the light emission time of the pixels in a plurality of bit planes each having a plurality of pixels arranged in a matrix is mainly determined for each bit plane. What is claimed is: 1. A digital image display device for expressing an image by gradation by weighting with a pulse width modulation method, comprising: an optical spatial modulator for performing binary modulation so as to emit light from a light source for each pixel or not to emit light. Control means for controlling the optical spatial modulator so that the plurality of pixels are sequentially driven line by line in a unit obtained by grouping the pixels into a plurality of lines. This is achieved by an image display device.

According to the first aspect of the present invention, the digital image display apparatus is configured to set the light emission time of the pixels in a plurality of bit planes each having a plurality of pixels arranged in a matrix in a pulse width modulation system for each bit plane. The image is expressed in gradation by weighting. A plurality of pixels arranged in a matrix on the bit plane are grouped for each of a plurality of lines. The control unit controls the optical spatial modulator such that the plurality of pixels are sequentially driven line by line in a unit in which the plurality of pixels are grouped into a plurality of lines. The control unit does not need to handle all the pixels in the bit plane at once, and only has to drive the pixels in groups, so that the amount of data transferred per operation can be reduced and the data transfer time can be shortened. Therefore, in the digital image display device, the amount of data transferred per time is reduced, so that the time required for data transfer is short. For this reason, the digital image display device can set the shortest display period of the bit plane affected by the data transfer time to be shorter in accordance with the shortened bit plane data transfer time. Therefore, the digital image display device can express an image to be displayed with high luminance in gradation. In addition, the digital image display device does not need to separately hold image data for displaying a plurality of pixels and image data to be transferred, which has been conventionally performed. Image can be displayed quickly. For this reason, the digital image display device only needs to provide one storage means for storing image data, and the structure can be simplified, and the size can be reduced at low cost. Here, “mainly by the pulse width modulation method” means that the gradation expression of the luminance of the pixel recognized by the human eye by the afterimage effect is realized by the pulse width modulation method of modulating the light emission time width of the pixel. This means that the present invention may be realized by another light modulation method such as a luminance modulation method for modulating the luminance of the pixel instead or in combination.

According to a second aspect of the present invention, in the configuration of the first aspect, the control means divides the plurality of pixels into groups of powers of 2 for each of a plurality of lines. Is controlled. Claim 2
, A display time width of 1/2, 1/4, 1/8,... Of the time required for data transfer for one bit plane is obtained, and the shortest display period of the bit plane is shortened. Therefore, high gradation display is possible.

According to a third aspect of the present invention, in the configuration of the second aspect, the plurality of pixels in the group are selected and driven in a subfield period which is a light emission time of the pixel for each bit plane. And other non-light-emitting groups in which the pixels are not selected within the sub-field period and the pixel is in a non-light emitting state.

According to a fourth aspect of the present invention, in the configuration of the third aspect, instead of sequentially driving the plurality of pixels in a certain bit plane for each group, the driving groups in each bit plane are selected at random and driven. It is characterized by the following. According to the configuration of the fourth aspect, by appropriately setting the access order of the drive group in each bit plane, the number of non-light-emitting groups can be reduced and the light use efficiency of the light source can be improved. Further, in the digital image display device, since the ratio of the non-light emitting group is reduced, the interval between the driving groups is narrowed, and the image can be displayed at high speed.

According to a fifth aspect of the present invention, in the configuration of the first aspect, the plurality of pixels arranged in a matrix are divided, and each of the divided pixels is independently driven in parallel. . According to the configuration of the fifth aspect, even in a digital image display device in which the transfer speed of image data is constant, the time required to display the entire image by parallel processing can be reduced. Therefore, the digital image display device can reduce the non-light emitting time and improve the light use efficiency of the light source.

According to a sixth aspect of the present invention, in the configuration of the fifth aspect, the control means divides the plurality of pixels into groups of powers of 2 for each of a plurality of lines. Is controlled. Claim 6
According to the configuration, in addition to the effect of claim 5, a plurality of pixels can be further finely divided and handled, so that the amount of data handled at one time can be reduced and an image can be displayed at high speed. .

According to a seventh aspect of the present invention, in the configuration of the sixth aspect, only a plurality of the pixels in a drive group selected in a subfield period as a light emission time of the pixel for each bit plane are driven, A plurality of the pixels which are not selected in the subfield period and belong to other non-light emitting groups are controlled to be in a non-light emitting state.

According to an eighth aspect of the present invention, in the configuration of the seventh aspect, instead of sequentially driving the plurality of pixels in a certain bit plane for each group, the driving groups in each bit plane are selected at random and driven. It is characterized by the following. According to the configuration of claim 8, by appropriately setting the access order of the drive groups, it is possible to reduce the number of the non-light-emitting groups and improve the light use efficiency of the light source.
Further, in the digital image display device, since the ratio of the non-light emitting group is reduced, the interval between the driving groups is narrowed, and the image can be displayed at high speed.

[0035]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The embodiment described below is a preferred specific example of the present invention,
Although various technically preferable limits are given, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description. In the following description, “pixel data” refers to n-bit binary information (2 ⁰ , 2 ¹ ,...)
·, 2 ^n-1 ). However, 2 ⁰ , 2
¹ ,..., 2 ^n-1 indicate the weight of each digit. Further, the “frame data” refers to pixel information that constitutes one image composed of 1 × m pixels in the vertical l, horizontal m, and n-bit gradation representations. Further, the “bit plane” is defined as n consisting of only bit information having the same weight of pixel data.
Xm binary information consisting of 0 or 1 patterns. That is, the above-mentioned “frame data” includes bits 0 (2 ⁰ ) to
It is composed of n bit planes of bit n (2 ^n-1 ). The “subfield” is defined for each bit plane, and has a display period corresponding to the bit weight. Further, the “frame (period)” is a minimum display unit for one image which is composed of subfields corresponding to n bit planes and has a gradation corresponding to n bits. 8, 9, 10, 11, 13, and 14 in the following description indicate that the time elapses as the time progresses rightward on the horizontal axis.

First Embodiment FIG. 1 is a block diagram showing an outline of a configuration example of a digital image display device 1 as a first embodiment of the present invention. The digital image display device 1 is an image display device such as a television receiver, a display device of a computer, a display unit of an information terminal, or a projection display device. Digital image display device 1
Has a frame memory 9, a read / write controller 11 (control means), a light valve 7 (optical spatial modulator), an optical system 3 and a light source 5, and a tuner 15 having an antenna 17 controls the A / D converter 13. Connected through.

The antenna 17 is an antenna for receiving a predetermined broadcast wave. The tuner 15 is connected to the A / D converter 13 and converts a broadcast wave received by the antenna 17 into an electric signal (analog data AD). The A / D converter 13 converts the analog data AD into binary frame data FD. The image data is, for example, frame data FD of a broadcast wave image in a unit of a frame at predetermined time intervals. The digital image display device 1
May be binary data output from the digital device 19 as shown in FIG. The frame memory 9 of FIG. 1 has a first frame memory 9a and a second frame memory 9b. The frame data FD is stored in the read / write controller 1
1 controls the first frame memory 9a and the second frame memory 9a.
Are alternately stored in the frame memory 9b.

Read / write controller 11
Are connected to the first frame memory 9a and the second frame memory 9b of the frame memory 9, respectively.
The read / write controller 11 is also connected to the light valve 7. The read / write controller 11 controls the first frame memory 9a and the second frame memory 9b, and reads the stored frame data FD to the light valve 7 in a procedure described later.

The light valve 7 modulates the light of the light source 5 for each pixel by the operation of the ferroelectric liquid crystal. Light valve 7
Is, for example, a ferroelectric liquid crystal (FLC: Ferroelec).
3 is a (tric Liquid Crystal) panel. It is difficult for a ferroelectric liquid crystal to continuously change a liquid crystal state, and usually, it can take only two states. Therefore, this ferroelectric liquid crystal panel can perform binary modulation of only ON or OFF to perform light modulation, and can perform binary control.

The optical system 3 is, for example, a lens and a polarization detection element, and detects and expands the light from the light source 5. Accordingly, light from the light source 5 is modulated by the light valve 7, and the modulated light enters the human eye E via the optical system 3. The light source 5 is lit at a constant luminance, for example.
As an example of the light source 5, various kinds of lamps such as a halogen lamp, a metal halide lamp, and a xenon lamp, a light emitting diode, and the like can be used. When displaying a color image, a light source capable of emitting red pulse light, green pulse light, and blue pulse light corresponding to the three primary colors of light is used as the light source 5, and the red pulse light and the green pulse light are used. And the image display timing by the blue pulse light is switched by time division driving.

FIG. 3 is a sectional view showing a configuration example of the light valve 7 of FIG. In the light valve 7, a mirror 31, a ferroelectric liquid crystal 29, and a glass 35 for each pixel are formed on a substrate 33 as a circuit substrate (back plane) made of, for example, silicon. In the light valve 7, a mirror 31 in which one pixel is made of aluminum or the like having a size of, for example, 10 to 15 μm is arranged in a plane. In the semiconductor (substrate 33) below the mirror 31 constituting the pixel, a pixel drive circuit 27 and the like are incorporated for each pixel. The mirror 31 itself operates to modulate the light by the DMD (D
digital Micromirror Device
e: trade name), but here, an example of driving the ferroelectric liquid crystal 29 will be described.

In the light valve 7, for example, pixels 25a to 25e (pixel group 25) are formed along the arrangement of the mirrors 31. The ferroelectric liquid crystal 29 can perform high-speed binary modulation by a voltage applied to the mirror 31 by the pixel driving circuit 27. In the light valve 7, light incident from the glass 35 passes through the ferroelectric liquid crystal 29 and is reflected by the mirror 31. The polarization state of the light reflected by the mirror 31 is controlled in accordance with the liquid crystal state of the ferroelectric liquid crystal 29 driven in pixel units. Therefore, the light valve 7 can emit or not emit light by the polarization detector according to the polarization state of the ferroelectric liquid crystal 29. It goes without saying that the light valve 7 is not limited to such a reflection type, but may be a transmission type. In the transmission type light valve 8, the polarization of incident light is controlled by the modulation state of the ferroelectric liquid crystal 29 so as to emit or not emit light (black display).

FIG. 4 is a block diagram showing an example of an electrical configuration of the light valve 7 of FIG. The light valve 7 includes, for example, a pixel group 25, which is an aggregate of 1920 × 1080 pixels 25a, a ferroelectric liquid crystal 29, a line address decoder driver 41, a line data latch 39, and a shift register 37. The line address decoder driver 41 specifies line addresses 0 to 1079 in the pixel group 25 in which the plurality of pixels 25a are arranged in a matrix. The shift register 37 has a configuration in which 120 16-bit shift registers are arranged. The image is configured by the human eye by, for example, instantaneously displaying a plurality of frames, and is displayed based on pixel data in pixel units.

The shift register 37 converts one line (1920 bits) of the input bit plane data into 12 bits.
The pixel data divided into 0 pieces is divided into 16 (1920/12
0) Bits can be fetched bit by bit. The line data latch 39 stores the one stored in the shift register 37.
It stores pixel data for each line. Accordingly, the light valve 7 processes the bit plane data for each of a plurality of pixel data of one line under the control of the read / write controller 11 of FIG.

FIG. 5 is a block diagram showing an example of the electrical configuration of one pixel in the light valve 7 adopting the sequential writing method. One pixel 25a in the digital image display device 1 is provided with one memory M for storing image data and a pixel drive circuit 27. In the sequential writing method, for example, the memory M and the pixel driving circuit 27 can be configured with a very simple configuration having one capacitor and one transistor. The pixel drive circuit 27 modulates the ferroelectric liquid crystal 29 based on the pixel data stored in the memory M. The light of the light source 5 is modulated by the modulation of the ferroelectric liquid crystal 29, and the pixels in the image are displayed.

FIG. 6 is a diagram showing a configuration example of the pixel group 25 in FIG. 4, and FIG. 7 is a diagram showing a configuration example of the bit planes B0 to B7. The image display device 1 is, for example, an HD (Hi
gh Definition) light valve 7. The light valve 7 has a pixel group 25 composed of, for example, 1920 horizontal pixels × 1080 vertical pixels 25a. In the image display device 1, one pixel expresses 256 gradations by, for example, 8 bits.
The frame data (image data) constituting the screen is shown in FIG.
Bit planes B0 (LSB) to B7 (MSB)
Can be expressed in gradation. Each bit plane B0
B7 is composed of 1920 × 1080 pixel data. Each of the bit planes B0 to B7 has a plurality of binary pixel data (“0” or “1”) weighted the same. Bit plane B0
B7 is assigned with subfields SF0 to SF7 each indicating a display period (pixel emission time) as the above weighting.

When displaying an image with 256 gradations, the bit plane B0 is displayed during the subfield SF0. Subsequently, the bit plane B1 is displayed during the subfield SF1. Similarly, the bit planes B2 to B7 are in the subfield S
Displayed during the period from F2 to SF7. Then, after the display up to the bit plane B7, the bit planes of the next image are sequentially displayed again. Therefore, an image is composed of a plurality of bits of pixel data per pixel. That is, the image is expressed in gradation by a plurality of pixel data located at the same position in each of the different bit planes B0 to B7 per pixel.

Here, the time ratio of each subfield is S
F0: SF1: SF2: SF3: SF4: SF5: SF
6: SF7 = 1: 2: 4: 8: 16: 32: 64: 12
8 is assumed. As a result, the bit plane B0 becomes an image display in which the luminance level recognized by the human eye is 1. The bit plane B1 displays an image with a luminance level of 2 recognized by the human eye. In the same manner, the bit planes B2 to B7 display images with luminance levels of 4 to 128 recognized by the human eye, respectively. Then, the digital image display device 1 controls each of these bit planes B0 to B7.
Can be displayed in 256 gradations. That is, the image display device 1 continuously displays these eight bit planes B0 to B7, so that the human eye can recognize an image displayed in 256 gradations due to the afterimage effect.

The digital image display device 1 has a total of 255
Is the highest luminance (luminance level 255) for one frame full time, and the lowest luminance (luminance level 0) is non-light emission (off) for one frame all time for a total of 0. In a general television system, one field time is 16.667.
ms (60 Hz), and the subfield SF0 for expressing the luminance level 1 in gradation has a time width of 65.4 μs (16.6 ms / 255) by the pulse width modulation method.

FIG. 8 is a diagram showing the relationship between the weighting by the combination of the bit planes B0 to B7 and the light emission time. The non-light emission for the entire frame is at the luminance level 0 (black display) because all the bit planes B0 to B7 are turned off. Brightness level 0 means black display. Also, the level 176 is
This is a case where the bit planes B4, B5, and B7 are on and the other bit planes B1 and the like are off.
The one-frame full-time light emission is at the luminance level 255 (highest luminance) because all of the bit planes B0 to B7 are turned on. Therefore, the digital image display device 101 can perform gradation expression by a combination of these bit planes B0 to B7.

The driving principle (digital image display method) of the digital image display device 1 will be described with reference to FIGS. 1 to 8. FIG. 9 is a diagram illustrating an example of a procedure of writing to the memory M. In FIG. 9, the vertical axis indicates the arrangement of lines, and the horizontal axis indicates time. One frame includes, for example, subfields SF7 (MSB) to SF0
(LSB). Subfield SF7
Indicates a bit plane B7, a subfield SF6 indicates a bit plane B6,..., A subfield SF0 indicates a time width for displaying the bit plane B0.

The subfield SF2 is の of the subfield SF3, the subfield SF3 is の of the subfield SF4, the subfield SF4 is の of the subfield SF5, and the subfield SF5 is 1 of the subfield SF6. / 2, the subfield SF6 has a half time width of the subfield SF7,
The subfields SF1 and SF0 have a time width of 、 and １ ／ of the subfield SF2, respectively. Further, there is a relationship of data rewriting time Tw ≦ subfield SF2.

FIG. 10 is a diagram showing an example of a procedure for writing to the memory M. In FIG. 10, the horizontal axis indicates time, and the vertical axis indicates the line address of the pixel group 125. In FIG. 10, for simplification of description, it is assumed that the data rewriting time Tw in FIG. 9 is set to be the same as the subfield SF2 of the bit plane B2. When the data rewriting time Tw is shorter than the subfield SF0, it can be easily controlled by adjusting the writing timing. When the digital image display device 1 completes the data rewriting step DW in the subfield SF2 over all the line addresses 0 to 1079 (lines),
The line address 0 is the timing when the display period of the subfield SF2 ends.

Accordingly, the digital image display device 1 immediately starts the reset writing step RST immediately after the line address 0, performs the reset processing up to the line L1079, and completes the subfield SF2. The reset writing step RST means a writing process for displaying black. The reset writing step RST is performed in order to obtain an accurate gradation of a displayed image. The digital image display device 1 returns to the line address 0 again and writes the image data of the bit plane B1 to, for example, the line address 0539 (write step DW).

The reason why the line address is halfway up to the line address 0539 is that the number of lines 1080 is divided into two. The digital image display device 1 returns to the line address 0, sequentially resets to the line address 0538 (reset writing step RST), and subsequently writes the remaining half of the bit plane B1 from the line address 0540 to the line 1079 (writing step DW). ).

The digital image display device 1 returns to the line address 0540 upon completion, and sequentially resets to the line 1079 (reset writing step RS
T). The data rewriting time for the line addresses 0 to 0539 and the line addresses 0540 to 1079 is exactly の of the writing period of the subfield SF2.
Therefore, the subfield SF1 is
Subfield S having a display period equivalent to 1/2 of 2
F1a and subfield SF1b. Second half of subfield SF1a and subfield SF1b
The first half is a period for displaying black (corresponding to the non-light-emitting area 46 in FIG. 9). That is, the digital image display device 1 sets the display period corresponding to the subfield SF1 to two.
It is divided into the first half subfield SF1a and the second half subfield SF1b, and these are displayed in half.

On the other hand, in the subfield SF0, the data write step DW and the reset write step RST are alternately repeated almost every 270 (1080/4) lines, for example, almost as in the subfield SF1. As a result, the digital image display device 1 divides the display period corresponding to the subfield SF0 into four to be the subfield SF0a, the subfield SF0b, the subfield SF0c, and the subfield SF0d. . In the figure, the access order of the lines is indicated by arrows. In this example, the digital image display device 1 sequentially accesses the bit planes B1 and B0 subsequent to the bit plane B2, and the pixel data in each of the bit planes B2 to B0 does not move back and forth until the line addresses 0 to 1079. Are accessed sequentially.

As described above, the plurality of pixels in the bit plane are divided and driven in power-of-two groups for each of the plurality of lines. Also, a feature of the present embodiment is that a plurality of pixels in each group include a driving region 45 (a driving group) that is selected and driven in a subfield period, and a plurality of pixels that are not selected in the subfield period. That is, it is divided into other non-light-emitting regions 46 (non-light-emitting groups) in a non-light-emitting state. In other words, the image displayed by the digital image display device 1 has a drive area 45 in consideration of a moment.
Means that a part of the image is displayed by the pixel corresponding to.

FIG. 11 is a diagram showing another example of the procedure of writing to the memory M. In FIG. 11, the horizontal axis represents time, and the vertical axis represents the line address of the pixel group 125. The digital image display device 1 includes subfields SF1 and SF
The order of writing the bit planes B1 and B0 to the memory M at 0 is changed. In practice, the digital image display device 1 changes the read / write control sequence of the read / write controller 11 of FIG. 1 and writes data from the frame memory 9 to the memory M of each pixel of the light valve 7.

The digital image display device 1 does not perform the reset writing after the writing of the bit plane B2 of the subfield SF2 until the end (line address 1079), but executes, for example, the line address 539 at the intermediate point (reset writing RST). ). Subsequently, the digital image display device 1 writes the bit plane B1 of the subfield SF1b into the memory M (write step DW). The digital image display device 1 performs the reset writing after the writing of the bit plane B1 of the subfield SF1b from the line address 540 to the line address 809 (reset writing RST).

Then, the digital image display device 1 sets the subfield SF0 for the line address 810 and thereafter.
Write the bit plane B0 of d to the memory M (write step DW). Subsequently, the digital image display device 1
Indicates that the reset write after the bit plane B0 of the sub-field SF0d is written to the line address 8
The processing is performed from 10 to the end (reset write RST). That is, the digital image display device 1 is driven (writes) by randomly selecting the drive area 45 in each bit plane B0 or the like and changing the access order. The order of writing bit planes of each subfield to the memory M is not limited to this, and can be set arbitrarily.

According to such a configuration, the digital image display device 1 changes the order of writing to the memory M as shown in FIG. Corresponding to) the subfield SF0
× 17 was reduced to subfield SF0 × 12. For this reason, the digital image display device 1
Since the non-display period of the frame can be shortened, the light use efficiency of the light source can be increased.

According to the first embodiment of the present invention, the following effects can be obtained. 1. The digital image display device 1 does not need to provide a buffer memory for temporarily storing image data of an image to be displayed next while displaying an image, and only the memory M required for display is provided. Good. For this reason, the digital image display device 1 can simplify the circuit configuration per pixel and achieve downsizing, and can display a high-definition image with a large number of pixels by integrating a large number of pixels. become. In addition, the digital image display device 1 can reduce the manufacturing cost by simplifying the circuit configuration per pixel, so that the cost can be reduced. 2. The digital image display device 1 has the same overall circuit configuration as that of the simplest line sequential system, and desires the shortest display period (minimum display period) of a bit plane only by controlling the driving order of pixels for each line. For a short period of time. That is, the digital image display device 1
A desired minimum display period can be obtained. Here, the minimum display period means the above-described subfield SF0. 3. The digital image display device 1 can realize a desired minimum display period without increasing the data transfer speed. For this reason, the digital image display device 1 can achieve low power consumption. 4. The digital image display device 1 has a subfield SF
Since it is sufficient to divide the bit plane B0 into one power of 2 and write it in the memory M for display, the amount of data handled at one time can be reduced. For this reason, the digital image display device 1 can realize the minimum display period at a moderate data transfer speed. That is, specifically, since the time for writing one bit plane data (the entire data writing time) is equal to the minimum display period, it is necessary to increase the bit rate at a high speed in order to increase the gradation level (increase the number of bits). Transfer plain data,
The entire data writing time was shortened. On the other hand, according to the present embodiment, one bit plane data can be transferred while being divided into 、, ４, ８,. It is not necessary to transfer data collectively. For this reason, the data transfer time of the divided bit plane data becomes shorter, such as 1/2, 1/4, 1/8, ... of the total write time. Therefore, the minimum display period can be set as short as desired in accordance with the shortened data transfer time.
Therefore, the digital image display device 1 can obtain a desired minimum display time even at a low data transfer rate,
An image can be expressed with high brightness in gradation. 5. In the digital image display device 1, the blackout time (black display period) is shortened, and the light use efficiency can be improved. Therefore, the digital image display device 1
Can display high-luminance gradation to display an image.

Second Embodiment FIG. 12 is a plan view showing a configuration example of a light valve 7a in a digital image display device 1a as a second embodiment. The digital image display device 1a according to the second embodiment has substantially the same configuration and operation as the digital image display device 1 according to the first embodiment in FIGS. 1 to 11, and thus only different points will be described. In the digital image display device 1a, a light valve 7a is used instead of the light valve 7 used in the first embodiment. The light valve 7a has two sets of shift registers 37, line data latches 39a and 39b, and line address decoder drivers 41a and 41b.
That is, the light valve 7a includes a shift register 37 and a line data latch 3 having substantially the same configuration as the light valve 7.
9a, line address decoder driver 41a
It has a configuration having a set.

The light valves 7a are, for example, 54
The upper pixel group 25a and the lower pixel group 25b for the 0 line are assigned to the upper and lower shift registers 37 and the like, and writing is performed simultaneously in the upper and lower directions. The data transfer rate of the shift register 37 is the same, but the number of assigned lines is 1
/ 2, the data rewriting time Tw becomes 1/2.

FIG. 13 is a diagram showing an example of a procedure for writing to the memory M. The digital image display device shown in FIG.
0, immediately after the subfield SF2, without requiring the reset write RST, following the subfield SF2.
You can start writing. Therefore, in the digital image display device, the total reset period (the period during which black display is performed without emitting light) can be significantly reduced to the subfield SF0 × 5. For this reason, the digital image display device can greatly improve the light use efficiency of the light source 5.

FIG. 14 is a diagram showing another example of the procedure of writing to the memory M. Digital image display devices
By changing the data write order as shown in FIG. 11 by substantially the same data write order, the write order of the subfield SF1 can be immediately started without requiring the reset write RST following the subfield SF2. In the digital image display device, the total reset period can be further reduced to the subfield SF0 × 3.

According to the second embodiment of the present invention, substantially the same effects as in the first embodiment can be exerted, and in addition to this, the light use efficiency of the light source 5 can be improved and the image can be displayed. It can be displayed even faster.

The present invention is not limited to the above embodiment. In the above embodiment, the brightness of the pixel recognized by the human eye due to the afterimage effect is exemplified by adopting the pulse width modulation method of modulating the light emission time width of the pixel. However, the present invention is not limited to this. Alternatively, another light modulation method such as a luminance modulation method for modulating the luminance of the pixel may be adopted. Further, in the above embodiment, the number of lines of the HD system 1080 is described as an example. However, the present invention is not limited to this, and the number of lines can be arbitrarily set. The digital image display apparatus sets the number of lines of the pixel group 25 to, for example, 1024, and divides the number of lines into a power of 2, for example, 1/4, so that the lines constituting one group are exactly 256 (1).
024/4), and the address bits of the pixel are 10 bits. For example, the digital image display device 1
Two bits, the eighth bit and the ninth bit, out of the 0 bits are control signals indicating each group. By setting the number of lines to 1024 in this way, the digital image display device
The circuit configuration of the line address decoder driver 41 can be significantly simplified. The above embodiment can be applied to any digital image display device of a binary control type, and can be applied whether or not the optical spatial modulator itself corresponding to the light valve 7 emits light. Further, in the above-described embodiment, the case where the number of display lines is 1080 has been described as an example. However, this method can be applied regardless of the number of lines. Further, in the above embodiment, since FIG. 1 is a schematic configuration example, the eye E is disposed on the opposite side of the optical system 3 with respect to the light source 5, but the configuration is not limited to this. That is, the digital image display device 1 may have a configuration in which a screen is arranged at the position of the human eye E in FIG. 1 and an image is projected on the screen. Each configuration of the above embodiment may be partially omitted or arbitrarily combined so as to be different from the above.

[0070]

As described above, according to the present invention,
It is possible to provide a digital image display device capable of improving light use efficiency of a light source and realizing a high gradation while being inexpensive with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a configuration example of a digital image display device as a first embodiment of the present invention.

FIG. 2 is a block diagram showing a modification of the digital image display device of FIG.

FIG. 3 is a sectional view showing a configuration example of the light valve of FIG. 1;

FIG. 4 is a block diagram showing an example of an electrical configuration of the light valve of FIG. 1;

FIG. 5 is a block diagram showing an example of an electrical configuration of one pixel in a light valve employing a sequential writing method.

FIG. 6 is a diagram illustrating a configuration example of a pixel group in FIG. 4;

FIG. 7 is a diagram showing a configuration example of a bit plane.

FIG. 8 is a diagram showing a relationship between weighting based on a combination of bit planes and a light emission time.

FIG. 9 is a diagram showing an example of a procedure of writing to a memory.

FIG. 10 is a diagram showing an example of a procedure for writing to a memory.

FIG. 11 is a diagram showing another example of the procedure of writing to the memory.

FIG. 12 is a plan view showing a configuration example of a light valve in a digital image display device as a second embodiment.

FIG. 13 is a diagram showing an example of a procedure of writing to a memory.

FIG. 14 is a diagram showing another example of the procedure of writing to the memory.

FIG. 15 is a block diagram showing an electrical configuration example of a general light valve.

FIG. 16 is a diagram showing a configuration example of a pixel group in FIG. 15;

FIG. 17 is a diagram showing a configuration example of a bit plane.

FIG. 18 is a block diagram showing an example of the electrical configuration of one pixel of a light valve in a conventional first image display device.

FIG. 19 is a timing chart showing an example of the relationship between the data transfer timing to the first memory and the display period.

FIG. 20 is a timing chart showing an example of the relationship between the data transfer timing to the first memory and the display period.

FIG. 21 is a block diagram showing an example of the electrical configuration of one pixel of a light valve in a second conventional image display device.

FIG. 22 is a diagram showing a relationship between a display period of each bit plane and a data rewriting time.

FIG. 23 is a diagram showing a relationship between a data rewriting time and subfields and the like.

FIG. 24 is a diagram showing how pixel data is rewritten for each line.

FIG. 25 is a plan view showing a configuration example of one pixel of a light valve in a third conventional image display device.

FIG. 26 is a diagram showing an example of a display period of a subfield for expressing an 8-bit gray scale by the subpixel method of FIG. 25;

[Explanation of symbols]

1, 1a: Digital image display device, 5: Light source, 7, 7a: Light valve (optical spatial modulator),
11: read / write controller (control means), 25a: pixel, FD: frame data (image data)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/36 G09G 3/36 H04N 5/66 102 H04N 5/66 102B

Claims (8)

[Claims] 1. A digital image display in which a light emission time of a pixel in a plurality of bit planes each having a plurality of pixels arranged in a matrix is weighted mainly by a pulse width modulation method for each bit plane, and an image is expressed in gradation. An apparatus, comprising: an optical spatial modulator that performs binary modulation so as to emit light from a light source for each pixel or not to emit light for each pixel; and a plurality of units in which the plurality of pixels are grouped into a plurality of lines. As the pixels are sequentially driven line by line,
Control means for controlling the optical spatial modulator. 2. The optical spatial modulator according to claim 1, wherein the control unit controls the optical spatial modulator so as to divide the plurality of pixels into groups of powers of 2 for each of a plurality of lines. The digital image display device as described in the above. 3. A driving group selected and driven in a subfield period which is a light emission time of the pixel for each bit plane, and a plurality of pixels in the group are not selected in the subfield period. 3. The digital image display device according to claim 2, wherein the pixel has another non-light emitting group in a non-light emitting state. 4. The digital device according to claim 3, wherein, instead of sequentially driving the plurality of pixels in a certain bit plane for each group, the driving group in each bit plane is selected at random and driven. Image display device. 5. The digital image display device according to claim 1, wherein the plurality of pixels arranged in a matrix are divided, and each of the divided pixels is independently driven in parallel. 6. The optical spatial modulator according to claim 5, wherein the control unit controls the optical spatial modulator so as to divide the plurality of pixels into groups of powers of 2 for each of a plurality of lines. The digital image display device as described in the above. 7. A plurality of pixels in a drive group selected during a subfield period as a light emission time of the pixel for each bit plane are driven, and other pixels that are not selected during the subfield period and are not selected are driven. The digital image display device according to claim 6, wherein the plurality of pixels belonging to a light emitting group are controlled to be in a non-light emitting state. 8. The digital device according to claim 7, wherein, instead of sequentially driving the plurality of pixels in a certain bit plane for each group, the driving group in each bit plane is selected at random and driven. Image display device.