JP2001331124A - Matrix array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a matrix array substrate which is used for a plane display device, etc., includes contact holes integrally penetrating gate insulating films and interlayer insulating films and patterns for forming auxiliary capacitors(Cs) to be superposed on scanning lines 11 and is capable of preventing the shorting between pixel electrodes 52 and the scanning line 11 and between the pixel electrodes 52 and preventing the fluctuation in the auxiliary capacitors. SOLUTION: The contours of the float patterns 35 which are superposed on the scanning lines 11 and are connected to the pixel electrodes 52 across the contact holes 43 exist on the outer side of the contour lines of the scanning lines 11 exclusive of the points crossing the scanning lines 11 and extend in proximity along the contour lines of the scanning lines 11. The pixel electrodes 52 are arranged apart the sufficient margins placed from the contour lines of the scanning lines 11 by taking the deviation in the patterns into consideration exclusive of the points near the contact holes 43. The sufficient margins are also disposed between the float patterns 35 and the neighboring pixel electrodes 52 connected thereto.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix array substrate used for a flat panel display represented by a liquid crystal display.

[0002]

2. Description of the Related Art In recent years, flat display devices such as liquid crystal display devices have been used as display devices such as personal computers, word processors or TVs, and as projection display devices, taking advantage of the features of thinness, light weight, and low power consumption. It is used in various fields.

Among them, an active matrix type display device in which a switch element is electrically connected to each pixel electrode is capable of realizing a good display image without crosstalk between adjacent pixels. Have been done.

[0004] The structure of the active matrix type liquid crystal display device of the light transmission type will be briefly described below.

Generally, in an active matrix type liquid crystal display device, a matrix array substrate (hereinafter, referred to as an array substrate) and an opposing substrate are arranged close to each other at a predetermined interval, and are provided on the surface layer of both substrates during this interval. The liquid crystal layer is held via the aligned alignment film.

In an array substrate, for example, a plurality of signal lines as an upper metal wiring pattern and a plurality of scanning lines as a lower metal wiring pattern are formed on a transparent insulating substrate such as glass via an insulating film. ITO (Indium-Tin-Oxid) is arranged in a grid, and in an area corresponding to each square of the grid.
A pixel electrode made of a transparent conductive material such as e) is provided. At each intersection of the grid, a switching element for controlling each pixel electrode is arranged. When the switching element is a thin film transistor (hereinafter abbreviated as TFT), the gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to the pixel electrode. It is connected to the.

[0007] The opposing substrate is formed by disposing an opposing electrode made of ITO or the like on a transparent insulating substrate such as glass, and a color filter layer for realizing color display.

In order to ensure a high display quality of an active matrix type liquid crystal display device, an array substrate is required
A storage capacitor (storage capacitor C) is connected between the pixel electrode and the storage capacitor line or the like.
It is necessary to provide a means for forming s).

Conventionally, an auxiliary capacitance line extending substantially in parallel with a scanning line is provided between each scanning line in the same step as the scanning line. However, when the auxiliary capacitance line is provided, there is a problem that the pixel aperture ratio is reduced accordingly.

Therefore, Japanese Patent Application Laid-Open No. H11-258634 describes
It is possible to partially overlap the pixel electrode made of the third conductive layer (uppermost layer) with the scanning line made of the first conductive layer (lowermost layer) and its extension to form an auxiliary capacitance therebetween. Proposed.

In Japanese Patent Application Laid-Open No. H11-258634, the following manufacturing method is employed in order to reduce the manufacturing cost of the array substrate. First, the semiconductor film and the like, together with the signal line, the source and the drain electrodes made of the second conductive layer, are collectively patterned based on the same mask pattern. Next, a contact hole for connecting the source electrode and the pixel electrode, a contact hole for exposing a connection end of the signal line formed of the second conductive layer, and a connection end of the scanning line formed of the first conductive layer are exposed. And a contact hole for the same. By such a method, productivity can be improved with a small number of masks.

[0012]

However, according to such a manufacturing method, the first insulating film (gate insulating film) covering the scanning line and the second insulating film disposed between the scanning line and the signal line. It is indispensable to form a contact hole that penetrates the insulating film (interlayer insulating film) all at once. Therefore, in the patterning step for forming the contact hole, a pinhole that exposes the scanning line of the first conductive layer or the extension thereof may be formed due to dust or the like in the resist.
When the pixel electrode is superimposed on the pinhole, an interlayer short circuit occurs between the scanning line of the first conductive layer and the pixel electrode of the third conductive layer, which may cause display failure.

Further, when the position of the mask pattern when forming the scanning line is shifted from the position of the mask pattern when forming the pixel electrode, there is a problem that the auxiliary capacitance fluctuates.

On the other hand, it is conceivable to provide a float pattern (island-shaped independent pattern) created simultaneously with the signal line and form an auxiliary capacitance between the float pattern and the pixel electrode. It is also conceivable to form a storage capacitor between the float pattern and the scan line by providing a float pattern at a position overlapping the scan line and electrically connecting the pixel electrode and the float pattern by a contact hole. However, even when such a float pattern is used, there is a problem that a short circuit occurs between two adjacent pixel electrodes via the float pattern. Also,
There is also the same problem of variation of the auxiliary capacity as described above.

The present invention has been made in view of the above problems, and is directed to a matrix array substrate used for a flat panel display device and the like, wherein a first insulating film covering a first conductive layer and a second insulating film are provided.
A contact hole penetrating the second insulating film covering the conductive layer at a time, and a conductive layer pattern overlapping the scan line to form an auxiliary capacitor; Provide a device capable of preventing a short circuit. Another object is to provide a device capable of preventing a change in auxiliary capacity.

[0016]

According to the first aspect of the present invention, there is provided an array substrate comprising: a plurality of scanning lines arranged substantially in parallel; a plurality of signal lines arranged substantially orthogonal to the scanning lines; A pixel electrode arranged in a matrix-shaped region defined by a scanning line and a signal line, a thin film transistor arranged for each pixel electrode and switching a signal input from the signal line to the pixel electrode, and the scanning line; A first conductive layer including a gate electrode of the thin film transistor, the first conductive layer covering the first conductive layer, forming a gate insulating film of the thin film transistor, and a semiconductor active film of the thin film transistor Including the signal line, the source and drain electrodes of the thin film transistor, and patterned under the same mask pattern as the semiconductor layer. A second conductive layer, a second insulating film covering the second conductive layer, a third conductive layer including the pixel electrode disposed thereon, and a contact hole penetrating the first and second insulating films. A matrix array substrate comprising:
An island-shaped independent pattern made of the second conductive layer and an independent pattern penetrating the second insulating film and forming one pixel electrode and one independent pattern for forming an auxiliary capacitance between the scan line and the second conductive layer. Pixel electrode for independent connection and a contact hole between independent patterns, and where the scanning line and the pixel electrode overlap, the independent pattern is always interposed between them, and the one independent pattern and The adjacent another pixel electrode is separated from a contour of the one independent pattern on a plane along the array substrate, except for a portion where the pixel electrode and the independent pattern overlap,
The pixel electrode is separated from the scanning line on the plane.

According to the above configuration, a short circuit between the pixel electrode and the scanning line is prevented, and two pixel electrodes adjacent to each other with the scanning line interposed therebetween are not short-circuited to each other via the independent pattern of the conductive layer. Further, the plurality of pixel electrodes are not short-circuited via the scanning line.

According to a second aspect of the present invention, in the array substrate, the contour of the independent pattern is located outside the contour of the scanning line except for a position crossing the scanning line.

As a result, a change in the auxiliary capacitance due to the displacement of the mask pattern is prevented.

According to a third aspect of the present invention, in the array substrate, the contour of the independent pattern extends in parallel with and near the contour of the scanning line, except at a position crossing the scanning line.

Thus, the pixel aperture ratio can be kept high.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A flat display device and a matrix array substrate 10 according to an embodiment will be described with reference to FIGS.

FIGS. 1 and 2 are plan views showing the structure of the pixel portion of the array substrate 10. FIG. 3 shows a laminated structure of the flat panel display device in the vicinity of the TFT (cross section AA in FIG. 2), and FIG. 4 shows the vicinity of a thin portion of the signal line along the pixel electrode (in FIG. 2). 2 shows a stacked structure of the flat panel display device in (BB section).

The flat display device of the embodiment is an XGA-TFT type normally white mode light transmission type liquid crystal display device having a diagonal dimension of an image display area of 13.3 inches.

In the array substrate 10 of the flat panel display, 1024 × 3 signal lines 1 and 768 scanning lines 11 are arranged so as to be orthogonal to each other. The lower metal wiring pattern including the scanning line 11 and the gate electrode 11a is
The gate insulating film 17 is formed entirely of a single-layer molybdenum-tungsten (Mo-W) alloy.

For each pixel opening defined by the signal line 8 and the scanning line 11, a TFT 9 as a switching element is arranged near the intersection of the signal line 8 and the scanning line 11. As shown in FIG. 4, the TFT 9 is of an inverted stagger type using the extending portion 11a of the scanning line 11 as a gate electrode, and a portion covering the gate electrode 11a is provided with an amorphous silicon An a-Si: H) layer 36 is provided. On the amorphous silicon layer 36, a channel protective film 2 is disposed at a substantially central channel portion, and phosphorus-doped amorphous silicon (n + a-Si: H)
The layers 37 are stacked. Further thereon, a source electrode 33 and a drain electrode 32 made of aluminum (Al) are formed.
Is arranged. The upper metal wiring pattern including the source electrode 33 and the drain electrode 32 is entirely covered with the interlayer insulating film 4 made of a silicon nitride film.

On the interlayer insulating film 4, an IT
A pixel electrode 52 made of an O layer is provided, and is electrically connected to the source electrode 33 via a source-pixel electrode contact hole 42 penetrating the interlayer insulating film 4.

The signal line 8 has a redundant wiring structure of a lower wiring (Al) 31 formed simultaneously with the drain electrode 32 and an upper wiring (auxiliary conductive layer) (ITO layer) 51 formed simultaneously with the pixel electrode 3. The upper and lower wirings 31 and 51 are provided with contact holes 4 penetrating through the interlayer insulating film 4.
1 are electrically connected to each other. The upper and lower interlayer contact holes 41 are formed between the signal line 8 and the drain electrode 32.
, More specifically, at a location where the drain electrode 32 branches from the signal line lower wiring 31 and becomes wider.

As shown in FIGS. 1 and 2, the scanning line 11 is formed wide enough to prevent deterioration of the switching signal. Each scanning line 11 extending between pixels is sandwiched between two adjacent pixel electrodes 52-1 and 52-2 in each region sandwiched between two adjacent signal lines 8 and extends along a gate electrode of the TFT 9. The input of an image signal to one of the pixel electrodes 52-1 is controlled via the existing portion 11a.

The contour of the scanning line 11 on the side of the extending portion 11a, that is, the contour of one of the pixel electrodes 52-1 has a T
A deep notch 11b and a shallow notch 11c continuous with the deep notch 11b are provided in a portion of the FT 9 adjacent to the source electrode 33. Each of the cutout shapes of the cutouts 11b and 11c is a rectangle whose long side faces the direction of the scanning line 11. In the illustrated example, the deep notch 11b
The notch depth (dimension in the scanning line width direction) is about 1/3 of the width of the scanning line 11, and the notch depth of the shallow notch 11c is about 5% of the width of the scanning line 11. Deep notch 11b
The dimension along the scanning line 11 is substantially the same as that of the shallow notch 11c. The deep notch 11b is the scanning line extension 11
Starting from the position of the base of “a”, a shallow notch 11 c following this extends to a position slightly beyond an intermediate point between adjacent signal lines 8.

On the contour of the scanning line 11 on the side opposite to the extending part 11a, that is, on the contour of the other side of the pixel electrode 52-2, a protruding part 11d has substantially cutouts 11b and 11b.
c is provided. The protruding portion 11 d is formed in a rectangular shape whose long side extends in the direction of the scanning line 11. In the illustrated specific example, the protrusion size of the protrusion 11d is substantially the same as or slightly larger than the notch depth of the deep notch 11b. Therefore, the width dimension of the scanning line 11 is determined by the notches 11b and 11c and the protrusion 11d.
And the other locations are substantially the same.

These notches 11 in the scanning line 11
A float pattern 35 for forming a storage capacitor (Cs) with the scanning line 11 is arranged so as to substantially cover the arrangement positions of b and 11c and the protruding portion 11d.
The outline of the float pattern 35 is located so as to protrude slightly outside the outline of the scanning line 11 except for a portion crossing the scanning line 11, and extends substantially in parallel with the outline of the scanning line 11. The dimension protruding in this manner is set to a dimension that can sufficiently absorb the alignment margin in patterning the pattern of the scanning lines 11 and the conductive layer pattern including the float pattern 35.

As described above, since the float pattern 35 is arranged so as to “straddle” the scanning line 11, the float pattern 35 is displaced at the time of patterning.
Even when the position of the scanning line 11 with respect to the contour line deviates from the predetermined position, the storage capacitance (Cs) does not change.

The outline of the float pattern 35 extends in parallel with and near the outline of the scanning line 11 except for the portion crossing the scanning line 11. That is, the dimension of the float pattern 35 protruding from the contour of the scanning line 11 toward the pixel electrode 52 is small. Therefore, the pixel aperture ratio is not impaired by the float pattern 35.

The float pattern 35 and the pixel electrode 52 are electrically connected by a float-pixel electrode contact hole 43 arranged substantially at the center of the float pattern 35. The pixel electrode 52 is provided with a connection extending portion 52a extending to the periphery of the float-pixel electrode contact hole 43.

The pixel electrode 52 is arranged so as not to overlap the scanning line 11 except for the vicinity of the contact hole 43 between the float and the pixel electrode. That is, except for the vicinity of the float-pixel electrode contact hole 43, the pixel electrode 52 is
They are arranged with a margin sufficient to absorb the displacement during pattern formation. In other words, the pixel electrode 52 has a scanning line 11 on a plane along the array substrate.
Is well separated from

As shown in FIG. 1, one pixel electrode 5
2-2 and the float pattern 35 connected by the contact hole 43 are connected to another pixel electrode 5 adjacent thereto.
2-1 is arranged so as not to overlap. That is, the other pixel electrode 52-1 is disposed with a margin between the float electrode 35 and the float pattern 35 to sufficiently absorb a positional shift during pattern formation.

On the other hand, at the place where the signal line 8 intersects the scanning line 11, the signal line lower layer wiring 31 is connected to the signal line upper layer wiring 5
1, a margin is provided between both edges of the signal line lower layer wiring 31 and both edges of the signal line upper layer wiring 51 so as to sufficiently absorb a positional shift during pattern formation. I have. Therefore, even if a pinhole occurs in the insulating film, a short circuit does not occur between the signal line upper wiring 51 and the scanning line 11.

Next, an outline of a manufacturing process of the array substrate 10 will be described.

(1) First Patterning After, for example, a molybdenum-tungsten alloy film (MoW film) is deposited on the glass substrate 18 (FIG. 3) by a sputtering method, the scanning lines 11 and the extending portions thereof are formed. The gate electrode 11a made of is formed. At the same time, the signal line thin line portion 8a
A band-shaped float pattern 13 is formed so as to sandwich a predetermined portion (a portion of the signal line 8 along the pixel electrode other than the drain electrode forming portion) from left and right. As shown in FIG. 4, the band-shaped float pattern 13 overlaps with the edge of the pixel electrode 52, shields light, and partially forms an auxiliary capacitance.

(2) Second patterning The first patterning of a silicon oxide film is performed by plasma CVD.
A gate insulating film 15 and a second gate insulating film 16 made of a silicon nitride film are deposited, and amorphous silicon (a-Si: H) for forming a semiconductor active layer of the TFT 9 is formed.
The layer 36 and the silicon nitride film are sequentially deposited.

Thereafter, the silicon nitride film is patterned to form a channel protective film 2 at a position corresponding to the channel portion of the TFT 9.

(3) Third Patterning A phosphorus-doped amorphous silicon (n + a-Si: H) layer 37 is deposited by a plasma CVD method, and a metal layer made of, for example, aluminum (Al) is deposited by sputtering. . By patterning the metal layer and the semiconductor layers 36 and 37 collectively, the signal line lower layer wiring 31, the drain electrode 32 including the extending portion, and the source electrode 33 are formed.
To form

At the same time, a float pattern 35 for forming an auxiliary capacitance (Cs) with the scanning line 11 is formed.
It is formed so as to have a required distance from the signal line lower wiring 51 and the source electrode 33. In the illustrated example, the outline of the float pattern 35 is such that a rectangular notch 11a is provided at a corner of one rectangle close to a square.

The signal line lower layer wiring 31 forms a thin line portion 31a having a width of 5 μm at most portions, and a thick line portion 31b having a width of 8 μm in a region intersecting with the scanning line 11.

(4) Fourth Patterning After the interlayer insulating film 4 made of silicon nitride is deposited, the upper and lower interlayer contact holes 41 of the signal lines, the source-pixel electrode contact holes 42, and the float-pixel electrode contact holes are formed. 43 at the same time.

Although not shown, the array substrate 10
At the same time, the pad portion of the signal line lower wiring 31 and the pad portion of the scanning line 11 are exposed. In addition, a contact hole for forming a redundant wiring structure for a lead line (oblique wiring) for drawing the signal line 8 and the scanning line 11 from the image display area to the vicinity of the pad portion is simultaneously formed. That is, a part of the wiring layer created at the same time as the scanning line 11,
A part of a wiring layer formed at the same time as the signal line lower wiring 31 is exposed, and these wiring layers are electrically connected by a conductive layer formed at the same time as the pixel electrode 52 (see JP-A-11-258634). ). Therefore, in the fourth patterning, the gate insulating films 15 and 16 and the interlayer insulating film 4 are collectively patterned, so that various contact holes are formed and the pad portions are exposed.

(5) Fifth Patterning After depositing, for example, ITO as a transparent conductive layer, the signal line upper layer wiring 51 and the pixel electrode 5 are patterned by patterning.
Create 2. The signal line upper layer wiring 51 is entirely formed of a thin line portion having a width of 4 μm, except for a place where the contact hole 41 is arranged. In the place where the contact hole 41 is arranged,
It is formed wide so as to substantially cover the signal line lower wiring 31 and the drain electrode 32.

The extending portion 52a of the pixel electrode 52 is always arranged so as to come within the region of the float pattern 35 for forming the auxiliary capacitance. In addition to the extension 52a, the pixel electrode 52 and the scanning line 11 are not overlapped with each other, and the interval between the contour of the pixel electrode 52 and the contour of the scanning line 11 may be a mask deviation error at the time of patterning. Has a width that can be sufficiently absorbed. Therefore, even when a pinhole penetrating through the interlayer insulating film 4 and the gate insulating films 15 and 16 occurs in the contact hole forming step (fourth patterning), an interlayer short circuit occurs between the pixel electrode 52 and the scanning line 11. Will not occur.

In the example shown in the figure, small cutouts 52b are provided corresponding to the fact that the upper and lower wirings 31, 51 above and below the signal line slightly project toward the pixel electrode.

The array substrate 10 thus prepared is
The liquid crystal 7 is injected in combination with the counter substrate 6 (FIG. 3).
4). The opposing substrate 6 has a grid-like light-shielding film (black matrix) 61 made of chromium or the like and a red (R), green (G), and blue (B) coloring pattern 62 disposed therebetween on a glass substrate. Prepare. This black matrix 61
Is combined with the array substrate 10 when the TFT 9
And the pixel electrode 52, the signal line 8, and the scanning line 11
To shield the gap. That is, the black matrix 6
1 is provided corresponding to the effective aperture area of the array substrate 10, the aperture ratio of the liquid crystal display device is limited to the following when the alignment accuracy between the array substrate 10 and the counter substrate 6 is the same.
It is determined by the effective area of the pixel aperture of the array substrate 10, that is, the aperture ratio of the array substrate 10.

According to the above embodiment, the pixel electrode and the scanning line are arranged at a sufficient interval except for the contact hole between the pixel electrode and the float pattern for forming the auxiliary capacitance. A short circuit with the scan line is prevented. Further, since the float pattern for forming the auxiliary capacitance and the adjacent pixel electrode are arranged at a sufficient distance, a short circuit between the pixel electrodes via the float pattern for forming the auxiliary capacitance is prevented.

Further, according to the above embodiment, a change in the auxiliary capacitance due to a mask shift during patterning can be prevented.

Further, since the floating pattern for forming the auxiliary capacitance and the pixel electrode are connected via the contact hole located on the scanning line, the floating pattern for forming the auxiliary capacitance is extended to the pixel electrode side. As compared with the case, the pixel aperture ratio is prevented from lowering due to the arrangement of the auxiliary capacitance forming float pattern.

[0055]

According to the present invention, there is provided a matrix array substrate used for a flat panel display device or the like, wherein a contact hole penetrating through a gate insulating film and an interlayer insulating film at a time and a conductive pattern formed on a scanning line to form an auxiliary capacitance are provided. Including
Short circuit between the pixel electrode and the scanning line or between the pixel electrodes can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a schematic configuration of a pixel portion on an array substrate according to an embodiment.

FIG. 2 is a plan view similar to FIG. 1, showing an overall outline of one pixel portion.

FIG. 3 is a partial cross-sectional view showing a stacked structure of a flat panel display device in the vicinity of a TFT (cross section taken along line AA in FIG. 2).

FIG. 4 is a partial cross-sectional view illustrating a stacked structure of the flat panel display device in the vicinity of a thin line portion of a signal line along a pixel electrode (cross section taken along line BB in FIG. 2).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Array substrate 11 Scan line 11a Gate electrode 11b, 11c Cutout of scan line 11d Projection part of scan line 31 Signal line lower layer wiring 32 Drain electrode 33 Source electrode 35 Float pattern for forming auxiliary capacitance 38 Semiconductor layer 41 Upper and lower of signal line Interlayer contact hole 42 Source electrode-pixel electrode contact hole 43 Float-pixel electrode contact hole 51 Signal line upper layer wiring (ITO) 52 Pixel electrode 52a Pixel electrode extension 8 Signal line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 JA26 JA29 JA36 JA38 JA42 JA44 JA46 JB13 JB23 JB32 JB33 JB38 JB52 JB57 JB63 JB69 KA05 KA07 KA12 KA16 KA18 KB14 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA25 NA29 PA06 QA07 5C094 AA21 AA31 BA03 BA43 CA19 DA13 DA15 EA04 EA05 EA07 FB12 FB14 FB15 FB19 5F110 AA26 BB01 CC07 DD02 EE06 EE44 FF02 FF03 FF30 GG02 GG15 GG45 HK03 HK09 HK19 HK19 HK16 HK19

Claims (5)

[Claims] A plurality of scanning lines arranged substantially in parallel, a plurality of signal lines arranged substantially orthogonal to the scanning lines, and a plurality of matrix-shaped regions defined by the scanning lines and the signal lines; A pixel electrode to be arranged, a thin film transistor arranged for each pixel electrode to switch a signal input from the signal line to the pixel electrode, a gate electrode of the thin film transistor including the scanning line, and a part or extension of the scanning line A first insulating layer covering the first conductive layer, forming a gate insulating film of the thin film transistor, a semiconductor layer including a semiconductor active film of the thin film transistor, the signal line, and a source of the thin film transistor. And a second pattern including a drain electrode and patterned under the same mask pattern as the semiconductor layer.
A conductive layer, a second insulating film covering the second conductive layer, a third conductive layer disposed on the second insulating layer and including the pixel electrode,
And a contact hole penetrating through a second insulating film, wherein the island-shaped independent pattern of the second conductive layer is formed for forming an auxiliary capacitance with the scanning line; A pixel electrode for penetrating the second insulating film and electrically connecting the one pixel electrode and the one independent pattern; and a contact hole between the independent patterns, where the scanning line and the pixel electrode overlap. Is always interposed between the independent patterns, adjacent to the one independent pattern, another pixel electrode is separated from the contour of the one independent pattern in a plane along the array substrate, The matrix array, wherein the pixel electrode is separated from the scanning line on the plane, except where the pixel electrode and the independent pattern overlap each other. Plate. 2. The matrix array substrate according to claim 1, wherein the outline of the independent pattern is located outside the outline of the scanning line except for a position crossing the scanning line. 3. The matrix array substrate according to claim 1, wherein the contour of the independent pattern extends in parallel with and near the contour of the scanning line, except at a position crossing the scanning line. 4. The scanning line has a protruding portion on the side of the one pixel electrode and a cutout on the side of the other pixel electrode at a position where the scanning line overlaps the independent pattern. The matrix array substrate according to claim 3. 5. The matrix array substrate according to claim 4, wherein said notch is provided so as to separate said independent pattern from said source electrode.