JP2001324303A - Surface shape recognition device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability of a surface shape recognition device for recognizing a minute surface shape such as unevenness of a fingerprint by using a capacitance-type sensor. SOLUTION: This device has a plurality of sensor electrodes 105 disposed on an interlayer insulation film on a substrate and insulated/separated from each other, passivation films 107 made of a dielectric and disposed to cover upper surfaces and side surfaces of the respective sensor electrodes on the insulation film, and capacitance detection circuits 200 for detecting capacitance formed between the sensor electrodes and a surface of an object of recognition standing opposite to the sensor electrodes when the object of recognition touches a surface of the passivation film. This device is further provided with earth electrodes 106 as a means for causing static electricity on the passivation films to pass therethrough, or provided, in addition to the earth electrodes, with electrostatic protection elements Q4, Q5 between the sensor electrodes and the detection circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface shape recognizing device, and more particularly to a surface shape recognizing device for recognizing minute irregularities such as human fingerprints and animal nose prints.

[0002]

2. Description of the Related Art In the progress of the information society and the environment of the modern society, interest in security technology is increasing. For example, in the information-oriented society, personal authentication technology for system construction such as electronic cash is becoming an important key. Also,
In fact, research and development are also being actively conducted on authentication technologies for protection against theft and unauthorized use of cards (for example, Yoshimasa Shimizu et al., A study on IC cards with functions with personal authentication, IEICE Technical report of IEICE,
OFS92-32, p25-30 (1992)).

[0003] There are various authentication methods using fingerprints and voice prints as such authentication methods for preventing unauthorized use. Among them, many fingerprint authentication technologies have been developed. . Fingerprint authentication methods are roughly classified into an optical reading method and a method of detecting unevenness of a fingerprint by using electric characteristics of a human to replace the unevenness of the fingerprint with an electric signal. The optical reading method is a method in which a fingerprint is captured as optical image data by using light reflection and a CCD image sensor and collation is performed (Japanese Patent Laid-Open No. 61-221883).

As another method, a method using a piezoelectric thin film to read the pressure difference of a fingerprint of a finger has been developed (JP-A-5-61965). Similarly,
As a method of detecting the shape of a fingerprint by replacing the change in electrical characteristics caused by contact with the skin with the distribution of an electrical signal, an authentication method based on a resistance change amount or a capacitance change amount using a pressure-sensitive sheet has been proposed. Kaihei 7-168930). However, in the above-mentioned technologies, first, it is difficult to reduce the size of the system using light, it is difficult to use the system for general purposes, and there is a problem that the application is limited. Next, the method of detecting the unevenness of the finger using a pressure-sensitive sheet, etc., is difficult due to the special material and the difficulty of workability.
It is considered that practical application is difficult and reliability is poor.

On the other hand, a capacitive fingerprint sensor manufactured by using LSI manufacturing technology has been developed (Marco Tartag).
ni and Roberto Guerrieri, A 390dpi Live Fingerprint
Imager Based on Feedback Capacitive Sensing Schem
e, 1997 IEEE International Solid-State Circuits Conf
erence, p200-201 (1997)). This is a method in which a small sensor arranged two-dimensionally on an LSI chip detects a concave / convex pattern on the skin using a feedback capacitance method. This capacitive sensor basically has a plate formed on the uppermost layer of LSI wiring and a passivation film formed on the plate.

When a fingertip touches the sensor, the surface of the skin functions as a second plate, is isolated by an insulating layer made of air, and detects a fingerprint by sensing the difference in distance between the skin surface and the plate. Is what you do. In this technique, a reference plate is arranged near a plate arranged on the uppermost layer, and a difference from the reference plate is used for actual sensing. This structure is characterized in that a special interface is not required and the size can be reduced as compared with the conventional optical type.

[0007] In principle, the fingerprint sensor has a sensor electrode formed on a semiconductor substrate and a passivation film formed on the sensor electrode, and detects the capacitance between the skin and the sensor via the passivation film. This is a method for detecting unevenness of a fine structure. Here, a conventional capacitive fingerprint sensor will be briefly described with reference to the drawings. This capacitive sensor is configured as shown in the sectional view of FIG. First, a wiring 403 is formed on a semiconductor substrate 401 on which an LSI or the like is formed via a lower insulating film 402, and an interlayer insulating film 404 is formed thereon.

On the interlayer insulating film 404, for example, a sensor electrode 406 having a rectangular planar shape is formed. The sensor electrode 406 is connected to the wiring 403 via a plug 405 in a through hole formed in the interlayer insulating film 404. On the interlayer insulating film 404, the sensor electrode 40
6, a passivation film 407 is formed,
A sensor element is configured. As shown in the plan view of FIG. 11, a plurality of sensor elements are two-dimensionally arranged such that the sensor electrodes 406 of adjacent sensor elements do not contact.

Next, the operation of the capacitive sensor will be described. At the time of fingerprint detection, first, a finger whose fingerprint is to be detected contacts the passivation film 407. in this way,
When the finger comes into contact, on the sensor electrode 406, the skin that has touched the passivation film 407 functions as an electrode, and a capacitance is formed with the sensor electrode 406. This capacitance is detected via the wiring 403. Here, the fingerprint of the fingertip is
When the finger is brought into contact with the passivation film 407, the skin as an electrode is
The distance from the sensor electrode 406 differs between the convex portion and the concave portion forming the fingerprint. This difference in distance is detected as a difference in capacity. Therefore, if the distribution of different capacitances in each sensor electrode is detected, the fingerprint becomes uneven. Thus, the capacitive sensor can detect the fine unevenness of the skin.

Such a capacitive fingerprint sensor does not require a special interface as compared with a conventional optical sensor, and can be reduced in size. This capacitive sensor can be integrated and mounted on an integrated circuit (LSI) chip in which the following components are integrated. That is, a capacitance detection circuit that detects the capacitance of the sensor electrode 406, a processing circuit that receives and processes the output of the capacitance detection circuit, a storage circuit that stores fingerprint data for collation, and fingerprint data of the storage circuit. The above-described capacitive sensor can be mounted on an integrated circuit chip on which a comparison and collation circuit for comparing and collating with a fingerprint detected by the capacitance detection circuit and processed by the processing circuit is integrated. In this way, by forming the information on one integrated circuit chip, it becomes difficult to falsify information in data transfer between units, and it is possible to improve confidentiality retention performance. Note that a capacitance detection type sensor using such an LSI manufacturing technique is, for example, an 'ISSCC DI
GEST OF TECHNICAL PAPERS '
FEBRUARY 1998 pp. 284-285
It is described in.

FIG. 12 is a circuit diagram of a conventional capacitance detecting circuit for detecting an electrostatic capacitance formed between the skin of a finger and an electrode to detect an uneven pattern of a fingerprint. In FIG.
Reference numeral 50 denotes a detection element which outputs a capacitance value Cf formed between the contact surface 400 of the finger and the sensor electrode 406 as a voltage signal. Capacitance detection circuit 500
Is composed of a signal generation circuit 510, an output circuit 520, and the like. The sensor electrode 406 of the detection element 50 has NchM
It is connected to the input side of the current source 511 of the current I via the OS transistor Q2. The input side of the output circuit 520 is connected to a node N1 between the sensor electrode 406 and the transistor Q2. The power supply voltage VDD is applied to the node N1 via the PchMOS transistor Q1.
This node N1 has a parasitic capacitance Cp0. further,
Signals PRE (bar) and RE are applied to the gate terminals of the transistors Q1 and Q2, respectively. Here, the current source 5
11 and a transistor Q2 form a signal generation circuit 510, and an NchMOS transistor Q3 and a bias resistor Ra form an output circuit 520.

The operation of the capacitance detection circuit 500 shown in FIG. 12 will be described. First, H is connected to the gate terminal of the transistor Q1.
The signal PRE (bar) at the high level (VDD) is supplied, and the signal RE at the low level (GND) is supplied to the gate terminal of the transistor Q2. Therefore,
At this time, both transistors Q1 and Q2 are not conducting. When the signal PRE (bar) changes from the high level to the low level in this state, the transistor Q1 is turned on. At this time, since the transistor Q2 is kept off, the potential of the node N1 is precharged to VDD.

After the precharge is completed, the signal PRE
(Bar) changes to High level and the signal RE
Changes to a High level. As a result, the transistor Q1 is turned off and the transistor Q2 is turned on, and the charge at the node N1 is extracted by the current source 511. As a result, the potential of the node N1 decreases. Signal RE
Is a High level, and Δt is the potential drop ΔV of the node N1 after the lapse of Δt. ΔV = IΔt / (Cf + Cp0) (1) Here, Cf is the value of the capacitance.

Since the current I of the current source 511, the period Δt, and the parasitic capacitance Cp0 are constant, the potential drop ΔV is determined by the capacitance value Cf. Since this capacitance value Cf is determined by the distance between the electrode 406 and the finger surface 400, the value Cf of the capacitance 400 differs depending on the unevenness of the fingerprint.
From this, the magnitude of the reduced potential ΔV changes reflecting the unevenness of the fingerprint. This potential drop ΔV is supplied to the output circuit 520 as an input signal.
Is input, and a signal reflecting the unevenness of the fingerprint is output.

[0015]

However, since the above-mentioned capacitive sensor uses the skin of the finger or the like as an electrode, when the electrostatically-charged finger comes into contact with the capacitive sensor, the capacitive sensor is not used. There has been a problem that the integrated LSI is easily damaged by static electricity and the reliability is reduced. That is, usually, the MOS transistor constituting the LSI has a characteristic of outputting a signal with high sensitivity to a signal input to the gate terminal. For this reason, in the conventional capacitance detection circuit 500, the gate terminal of the MOS transistor Q3 of the output circuit 520 is directly connected to the node N1 connected to the sensor electrode 406, and the minute signal change ΔV occurring at the node can be detected with high sensitivity. Detect and output.

However, since the gate oxide film of the MOS transistor is as thin as 10 nm, its withstand voltage is about 100 V. When a high voltage exceeding this withstand voltage is input to the gate terminal, the gate oxide film is destroyed and the MOS transistor becomes inoperable. For this reason, the conventional capacitance detection circuit shown in FIG. 12 is configured such that when a recognition target object such as a finger is charged with static electricity when recognizing a surface shape such as unevenness of a fingerprint, this 1
Static electricity of 000 V or more reaches the gate terminal of the MOS transistor Q3 in the output circuit 3 via the sensor electrode 406, and as a result, the transistor Q3 is destroyed and reliability is reduced. Therefore, the present invention
An object of the present invention is to improve the reliability of a surface shape recognition device that recognizes a fine surface shape such as unevenness of a fingerprint using a capacitive sensor.

[0017]

A surface shape recognition apparatus according to the present invention comprises a plurality of sensor electrodes (105) arranged on an interlayer insulating film on a substrate and each of which is insulated and separated from each other. A passivation film (107), which is disposed over the top and side surfaces of each of the sensor electrodes and is made of a dielectric, and a sensor electrode and the recognition object facing the sensor electrode when the recognition object comes into contact with the surface of the passivation film And a capacitance detecting circuit (200) for detecting a capacitance formed between the surface of the passivation film and static electricity avoiding means (106, Q4, Q5) for passing static electricity on the surface of the passivation film. Further, the static electricity avoiding means is provided as an earth electrode (106) which is formed on the interlayer insulating film insulated from the sensor electrode and partially forms one surface together with the passivation film. Further, the static electricity avoiding means is provided as an electrostatic protection element on the input side of all the circuits connected to the sensor electrodes in the capacitance detecting circuit.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a sectional view showing a main part of a first embodiment of a surface shape recognition apparatus according to the present invention. In FIG. 1, a sensor chip constituting the present surface shape recognition device is provided on an interlayer insulating film 104 formed on a lower insulating film 102 on a semiconductor substrate 101 made of, for example, silicon.
For example, a plurality of 80 μm square sensor electrodes 105 and a grid-like ground electrode 106 are provided. Further, the plurality of sensor electrodes 105 and the ground electrode 106 are
They are arranged on the same plane defined by the surface of the interlayer insulating film 104. Note that the ground electrode 106 does not need to be arranged on the same plane as the sensor electrode 105.

As shown in the plan view of FIG. 2, the ground electrode 106 is arranged such that the sensor electrode 105 is disposed at the center of the grid formed by the ground electrode 106, and is insulated and separated from the sensor electrode 105. It is in the state that has been done. The ground electrode 106 is made of, for example, Au, and the interlayer insulating film 1
The height from the bottom in contact with 04 to the head exposed on the surface of the passivation film 107, that is, the film thickness was about 3 μm. Therefore, the thickness of the passivation film 107 is also 3
It is about μm. The upper surface of the ground electrode 106 forms one surface together with the surface of the passivation film 107, and in the present embodiment, this surface is one plane.

The ground electrode 106 is formed on the interlayer insulating film 1.
In this case, the wiring 106a formed on the pad 104 is electrically connected to the pad (reference electrode) 106b to which the ground line is connected, and the sensor electrode 10
5 is formed in the detection region 105a where the interlayer insulating film 1 is formed.
04 only. In the present embodiment, the ground electrode 106 is formed in contact with the interlayer insulating film 104, but is not limited to this. Earth electrode 106
May be disposed so as to be buried from the surface of the passivation film 107, and the bottom of the ground electrode 106 may be separated from the upper surface of the interlayer insulating film 104. The pad 106b may be provided with a predetermined fixed potential instead of being connected to the ground line.

The sensor electrode 105 is formed on the interlayer insulating film 10
4 is covered with a passivation film 107 formed on
A plurality was provided at intervals of 0 μm. The sensor electrode 105 is made of, for example, Au and has a thickness of about 1 μm. Since the film thickness of the passivation film 107 is about 3 μm, the passivation film 107 has a thickness of about 2 (= 3-1) μm on the sensor electrode 105. The passivation film 107 may be made of an insulator such as polyimide having a relative dielectric constant of about 4.0.

On the lower insulating film 102, a wiring 103 connected to the sensor electrode 105 via a through hole is formed. Further, on the semiconductor substrate 101, a capacitance detection circuit 200 for detecting a capacitance formed between the finger and the sensor electrode 105 when a finger or the like touches the sensor is formed. This capacitance detection circuit 200 is connected to the wiring 10 described above.
3, etc., are connected to the sensor electrode 105. The capacitance detection circuit 200 is prepared, for example, for each sensor electrode 105, and detects a capacitance formed between the sensor electrode 105 and a part of the recognition target.

The output OUT of each capacitance detection circuit 200 is processed by the processing circuit 300, and by the processing of this processing circuit 300, the capacitance between each sensor electrode 105 and the surface of the finger to be recognized (that is, the capacitance) Image data is generated by converting a later-described fingerprint that indicates the surface shape of the finger (concavities and convexities of the fingerprint) into light and shade. The capacitance detection circuit 200 and the processing circuit 300 are formed as an integrated circuit on the semiconductor substrate 101 below the sensor electrode 105. The capacitance detection circuit 200 and the processing circuit 30
0 need not necessarily be monolithically integrated on the semiconductor substrate 101. However, it is desirable that the sensor electrode 105 and the capacitance detection circuit 200 or the processing circuit 300 be arranged as close as possible.

As described above, in the first embodiment, the ground electrode 106, which is partially exposed, is provided on the surface of the passivation film 107 with which a finger or the like to be recognized contacts for recognition. As a result, static electricity generated when a finger contacts the surface of the passivation film 107 flows to the ground electrode 106, so that the application of static electricity to the capacitance detection circuit 200 disposed below the interlayer insulating film 104 can be suppressed. Become. Thus, the capacitance detection circuit 200
Is hardly affected by static electricity by the ground electrode 106, so that the reliability of the capacitance detection circuit is improved.

(Second Embodiment) FIG. 3 is a diagram showing a second embodiment, and is a circuit diagram of a capacitance detection circuit constituting a surface shape recognition device. This capacitance detection circuit 200A
Is for detecting a capacitance between the recognition target object 100 such as a contacted human finger and the sensor electrode 105, and generates a signal corresponding to an electric quantity corresponding to the detected capacitance value Cf. The circuit 210 includes an output circuit 220 that detects and outputs a signal at a connection point between the sensor electrode 105 and the signal generation circuit 210, and the like.

In FIG. 3, a sensor electrode 105 constituting the detecting element 1 is connected to a drain terminal of an NchMOS transistor Q2 in a signal generating circuit 210, and a source terminal of the transistor Q2 is connected to an input side of a current source 211 having a current value I. Connected to. The source terminal of the PchMOS transistor Q4 is connected to a node N1 between the sensor electrode 105 and the transistor Q2. The drain terminal of the transistor Q4 is connected to the Pch with the power supply voltage VDD applied to the source terminal.
Drain terminal of MOS transistor Q1 and output circuit 2
20 inputs are connected. The output circuit 200 is constituted by the NchMOS transistor Q3 and the bias resistor Ra. Here, Cp0 and Cp1 are parasitic capacitances. Note that elements such as the transistor are formed on the semiconductor substrate 101 below the lower insulating film 102 shown in FIG. Elements such as the above transistors are connected by a wiring layer on the lower insulating film 102 to form a capacitance detection circuit.

Now, the operation of the capacitance detection circuit 200A configured as described above will be described. In the standby state, a high-level (VDD) signal PRE (bar) is applied to the gate terminal of the transistor Q1 in FIG. 3, and a low-level (GND) signal RE is applied to the gate terminal of the transistor Q2. Therefore, at this time, both transistors Q1 and Q2 are non-conductive. The potential VGP is applied to the gate terminal of the transistor Q4 so that the transistor Q4 conducts.

Here, when the signal PRE (bar) changes from High level to Low level, the transistor Q1
Becomes conductive. At this time, the transistor Q2 remains non-conductive, and thus the signal generation circuit 210 is stopped, so that the potential of the node N2 is precharged to VDD. The node N1 is also precharged to VDD via the transistor Q4. After the precharge is performed in this manner, the signal PRE (bar) is changed from the low level to the high level.
gh level to make the transistor Q1 non-conductive. At the same time, the signal RE is changed from the low level to the high level.
Level to make the transistor Q2 conductive. As a result, the signal generation circuit 210 enters an operation state, and the electric charges of the nodes N1 and N2 are drawn out by the current source 211 of the signal generation circuit 210, and the potentials of the nodes N1 and N2 decrease.

Here, assuming that the period during which the signal RE is maintained at the high level is Δt, the voltage drop ΔV at the nodes N1 and N2 after Δt is as follows: ΔV = I · Δt / (Cf + Cp0 + Cp1) (2) Here, Cf is a capacitance value, Cp0 and Cp1 are parasitic capacitance values, and I is a current value of the current source 211. Since the capacitance Cf is determined by the distance between the finger skin 100 and the sensor electrode 105, the capacitance value Cf differs according to the unevenness of the fingerprint. In addition, since the current value I and the values of Cp0 and Cp1 are constant, the voltage drop ΔV changes according to the unevenness of the fingerprint in Expression (2). Since this voltage drop ΔV is supplied to the output circuit 220 as an input signal, the output circuit 22
At 0, ΔV is input, and a signal reflecting the unevenness of the fingerprint can be output.

In the capacitance detection circuit shown in FIG.
4 and the sensor terminal 1 of the detection element 1
05. Here, FIG. 4 is a diagram schematically showing a cross-sectional structure of the transistor Q4 in the capacitance detection circuit of FIG. In FIG. 4, a power supply having a voltage VGP is connected to the gate of the transistor Q4, the node N1 is connected to the source terminal, and the node N2 is connected to the drain terminal.
The source terminal and the drain terminal of the transistor Q4 have p + electrical polarity as a semiconductor, and the substrate (or well) has n polarity. Therefore, a parasitic pn diode is connected to the node N1.
Since the n-polarity substrate (or well) is connected to the power supply potential VDD, the parasitic pn diode is connected to the node N1 as the diode D1 as shown in FIG.

For this reason, even if a high voltage is applied to the node N1, the diode D1 becomes conductive and functions as a protection circuit. In addition, the pn junction has a sufficiently high breakdown voltage with respect to the gate oxide film. Therefore, even if a high negative voltage is applied to the node N1, the transistor Q4 is not destroyed. Thus, the MO is applied to the sensor electrode 105 of the detecting element 1.
By connecting the PchMOS transistor Q4 to the sensor electrode 105 without connecting the gate terminal of the S transistor, a parasitic pn diode is formed between the source terminal and the substrate, thereby increasing the dielectric breakdown voltage of the node N1. Functions as a protection circuit against application of high voltage. Therefore, when a finger or the like charged with static electricity touches the sensor, the high-voltage static electricity is applied to the output circuit 22 through the sensor electrode 105 as in the conventional capacitance detection circuit shown in FIG.
Reaching the gate terminal of the MOS transistor Q3 within 0,
The transistor Q3 is prevented from being destroyed,
The reliability of the processing circuit 300 including the capacitance detection circuit 200A is improved.

In the second embodiment, the detecting element 1
Although the example in which the source terminal of the PchMOS transistor Q4 is connected to the sensor electrode 105 described above has been described, since the source of the MOS transistor generally has the same characteristics as the drain, the PchMOS transistor Q4 is connected to the sensor electrode 105.
Even if the drain terminal is connected, a parasitic pn diode is formed between the drain terminal and the substrate, thereby similarly increasing the dielectric breakdown voltage of the node N1 and functioning as a protection circuit against application of a high voltage. Further, the signal generation circuit 210 and the output circuit 2 in the capacitance detection circuit 200A of FIGS.
Configurations such as 20 show one of the implementation examples, and these configurations are not limited to the configurations shown in FIGS.

(Third Embodiment) FIG. 6 is a circuit diagram of a capacitance detecting circuit according to a third embodiment of the present invention. In the second embodiment shown in FIG. 3, the PchMOS transistor Q4 is provided between the sensor electrode 105 and the output circuit 220, whereas in the third embodiment, the PchMOS transistor Q4 is provided between the detection element 1 and the output circuit 220. The NchMOS transistor Q5 is provided.

Next, the operation of the capacitance detection circuit 200B of FIG. 6 will be described. When the signal PRE (bar) changes from a high level to a low level, the transistor Q1 is turned on. At this time, since the transistor Q2 is kept off, the potential of the node N2 is precharged to VDD. As a result, the potential of the node N1 becomes the transistor Q5
, And the transistor Q5 is turned off. VGN is the potential of the gate terminal of the transistor Q5, and Vth is the threshold voltage of the transistor Q5.

After the precharging is performed, the signal PRE (bar) is changed from a low level to a high level, and the transistor Q1 is turned off. At the same time, the signal RE is changed from the low level to the high level to turn on the transistor Q2. Thereby, the signal generation circuit 2
10 is activated, and the current source 2 of the signal generation circuit 210 is turned on.
11, the charge of the node N1 is extracted, and the node N1
Slightly lowers. Then, the transistor Q5 is turned on, the charge at the node N2 is also extracted by the current source 211, and the potential at the node N2 is also reduced.

Here, the parasitic capacitance value Cp1 mainly includes the parasitic capacitance of each drain terminal of the transistors Q1 and Q5 and the gate terminal of the transistor Q3, and can be made sufficiently smaller than the parasitic capacitance value Cp0 depending on the actual layout. Therefore, the potential change at the node N2 is larger than the potential change at the node N1. Thus, transistor Q5 functions as an amplifier circuit for amplifying the voltage signal generated from signal generation circuit 210.

Here, assuming that the period during which the signal RE is maintained at the high level is Δt, the voltage drop ΔV at the node N1 after Δt is ΔV = VDD− (VGN−Vth) + I · Δt / (Cf + Cp0 + CP1) (3) Becomes Here, I is the current value of the current source 211. Since the capacitance value Cf is determined by the distance between the finger skin 100 and the sensor electrode 105, the capacitance value Cf depends on the irregularities of the fingerprint.
Is different. In addition, since all the values other than the capacitance value Cf in the equation (3) are constant, the voltage drop ΔV changes according to the unevenness of the fingerprint in the equation (3). Since this voltage drop ΔV is supplied to the output circuit 220 as an input signal, the output circuit 220 receives ΔV and can output a signal reflecting the unevenness of the fingerprint.

In the capacitance detection circuit 200B of FIG. 6, the source terminal of the transistor Q5 is connected to the sensor electrode 105 as an input of the amplification circuit. Here, FIG. 7 schematically shows a cross-sectional structure of the transistor Q5 in the capacitance detection circuit 200B of FIG. In FIG. 7, a power supply of a voltage VGN is connected to the gate terminal of the transistor Q5,
The node N1 is connected to the source terminal, and the node N2 is connected to the drain terminal. The source and drain terminals of the transistor Q5 have n + electrical polarity as a semiconductor,
The substrate (or well) has p polarity. Therefore, a parasitic pn diode is connected to the node N1. Further, since the p-polarity substrate (or well) is connected to the ground potential, the parasitic pn diode is connected to the node N1 as the diode D2 as shown in FIG.

As described above, the pn junction has a sufficiently high breakdown voltage with respect to the gate oxide film. Therefore, the third
In the capacitance detection circuit shown in the embodiment, even when a high voltage is applied to the node N1, the transistor Q5 is not destroyed. When a high negative voltage is applied to the node N1, the diode D2 conducts and functions as a protection circuit.

As described above, the sensor electrode 10 of the detecting element 1
By connecting the source terminal of the Nch MOS transistor Q5 to the sensor electrode 105 without connecting the gate terminal of the MOS transistor to the gate electrode 5, a parasitic pn diode is formed between the source terminal and the substrate, thereby causing the dielectric breakdown of the node N1. The voltage is increased, and functions as a protection circuit against a negative voltage. Accordingly, when a finger or the like charged with static electricity touches the sensor, the high-voltage static electricity is applied to the gate terminal of the MOS transistor Q3 in the output circuit 220 via the sensor electrode 105 as in the conventional capacitance detection circuit shown in FIG. To prevent the transistor Q3 from being broken, and the processing circuit 3 including the capacitance detection circuit 200B.
00 is improved.

In the third embodiment, the detecting element 1
Although the example in which the source terminal of the NchMOS transistor Q5 is connected to the sensor electrode 105 described above has been described, since the source of the MOS transistor generally has the same characteristics as the drain, the NchMOS transistor Q5 is connected to the sensor electrode 105.
Even if the drain terminal is connected, a parasitic pn diode is formed between the drain terminal and the substrate, thereby similarly increasing the breakdown voltage of the node N1 and functioning as a protection circuit against a negative voltage. Further, since the transistor Q5 has an amplifying function, an amplifier circuit having a protection function can be realized without increasing the number of elements as compared with the capacitance detection circuit of the second embodiment. Therefore, when increasing the detection sensitivity of the capacitance detection circuit, the circuit can be configured economically and small. Note that the configurations of the signal generation circuit 210 and the output circuit 220 in the capacitance detection circuit 200B in FIGS. 6 to 8 show one example of an implementation, and these components are shown in FIGS.
Is not limited to the configuration shown in FIG.

(Fourth Embodiment) Although the capacitance detection circuit of the fourth embodiment is not shown, the polarity of each transistor and signal of the capacitance detection circuit 200A of the second embodiment shown in FIG. Inverted and ground (GND) shown in FIG.
The potential and the power supply potential VDD are interchanged. With this configuration, the capacitance detection circuit 2 according to the second embodiment can be used.
The same effect as 00A can be obtained.

(Fifth Embodiment) Although the capacitance detection circuit of the fifth embodiment is not shown, the polarity of each transistor and signal of the capacitance detection circuit 200B of the third embodiment shown in FIG. Inverted and ground (GND) shown in FIG.
The potential and the power supply potential VDD are interchanged. With such a configuration, the capacitance detection circuit 2 of the third embodiment
The same effect as 00B is obtained.

(Sixth Embodiment) A capacitance detection circuit according to a sixth embodiment is an example in which another source input type amplifier circuit is used as an amplifier circuit, and has a function of amplifying.
The transistor Q5 is composed of two transistors Q5A and Q5B as shown in FIG.
A and Q5B are configured to function as a differential amplifier circuit by cross-connecting the drain terminal and the gate terminal. By connecting the source terminal of the MOS transistor Q5A or Q5B shown in FIG. 9 to the sensor electrode 105 as an input of the differential amplifier circuit, the same effect as in the third and fifth embodiments can be obtained.

As described above, the parasitic pn diode is formed by connecting the source terminal of the MOS transistor to the sensor electrode 105 of the detecting element 1 and inputting the signal from the detecting element 1 to the input circuit. Is done. For this reason,
Since the dielectric breakdown voltage is increased and functions as a protection circuit, the reliability of the capacitance detection circuit 200 is improved. Therefore, if this surface shape recognition device is applied as a fingerprint detection device using LSI manufacturing technology, the device can be prevented from being destroyed even when a finger is charged with static electricity, and the reliability of the surface shape recognition device is improved. I do.

[0046]

As described above, according to the present invention, the earth electrode is provided on the surface of the apparatus, and the earth electrode and the wiring connected thereto are not arranged inside the apparatus. The current generated on the surface of the device when the object to be recognized contacts the surface of the device does not flow inside the device, but flows to the ground via the ground electrode. As a result, the influence of static electricity on the capacitance detection circuit and the like inside the device can be suppressed, and therefore, the reliability of the device is improved, and the surface shape of the recognition target object in contact with the device surface can be detected stably and with high sensitivity. Further, since the electrostatic protection elements are provided on the input sides of all the circuits in the capacitance detection circuit connected to the sensor electrodes for detecting the recognition target, it is possible to prevent the capacitance detection circuit from being damaged by static electricity.

[Brief description of the drawings]

FIG. 1 is a sectional view of a sensor chip showing a first embodiment of a surface shape recognition device according to the present invention.

FIG. 2 is a plan view of the sensor chip.

FIG. 3 is a circuit diagram of a capacitance detection circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a main configuration of the capacitance detection circuit of FIG. 3;

FIG. 5 is a diagram showing an equivalent circuit of the capacitance detection circuit of FIG.

FIG. 6 is a circuit diagram of a capacitance detection circuit according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a main configuration of the capacitance detection circuit of FIG. 6;

FIG. 8 is a diagram showing an equivalent circuit of the capacitance detection circuit of FIG. 7;

FIG. 9 is a circuit diagram of a capacitance detection circuit according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view of a conventional sensor chip.

FIG. 11 is a plan view of a conventional sensor chip.

FIG. 12 is a circuit diagram of a conventional capacitance detection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Detection element, 100 ... Recognition object, 101 ... Semiconductor substrate, 102 ... Lower insulating film, 103 ... Wiring, 104 ... Interlayer insulating film, 105 ... Sensor electrode, 105a ... Detection area, 1
06: earth electrode, 106a: wiring, 106b: pad, 107: passivation film, 200, 200A, 2
00B: capacitance detection circuit, 210: signal generation circuit, 211
... current source, 220 ... output circuit, 300 ... processing circuit, Q
1, Q4: Pch MOS transistor, Q2, Q3, Q
5, Q5A, Q5B ... NchMOS transistor, D
1, D2: parasitic diode, Cf: capacitance value, Cp0, C
p1 parasitic capacitance, N1, N2 nodes.

Continuing from the front page (72) Katsuyuki Machida, Inventor 2-3-1 Otemachi, Chiyoda-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation (72) Inventor Buri Kuraki 2-3-1, Otemachi, Chiyoda-ku, Tokyo F-term (reference) in Nippon Telegraph and Telephone Corporation 2F063 AA41 BA29 CA28 DA02 DA05 DD07 HA04 4C038 FF01 FF05 FG00 5B047 AA25 BA02 BB10 BC01 CB11

Claims (23)

[Claims] A plurality of sensor electrodes disposed on an interlayer insulating film on a substrate and each of which is insulated and separated; and a plurality of sensor electrodes disposed on the interlayer insulating film so as to cover upper surfaces and side surfaces of the respective sensor electrodes. And a capacitance formed between the sensor electrode and the surface of the object facing the sensor electrode when the object to be recognized contacts the surface of the passivation film. A surface shape recognition device, comprising: a capacitance detection circuit that performs static electricity; and static electricity avoiding means that passes static electricity on the surface of the passivation film. 2. The static electricity avoiding means according to claim 1, wherein the static electricity avoiding means is an earth electrode which is formed on the interlayer insulating film so as to be insulated and separated from the sensor electrode and partially forms one surface together with the passivation film. An apparatus for recognizing a surface shape. 3. The grounding electrode according to claim 1, wherein the static electricity avoiding means is formed on the interlayer insulating film so as to be insulated from the sensor electrode and partially forms one surface together with the passivation film. A surface shape recognition device, comprising: the capacitance detection circuit; and an electrostatic protection element provided between sensor electrodes. 4. The surface shape recognition device according to claim 1, wherein the capacitance detection circuit is formed as an integrated circuit on a substrate on which the sensor electrode and the passivation film are formed. 5. The processing circuit according to claim 4, further comprising a processing circuit formed as an integrated circuit on the substrate together with the capacitance detection circuit, for processing a detection output of the capacitance detection circuit and outputting it as a surface shape of the recognition target. A surface shape recognition device characterized by the following. 6. The capacitance detection circuit according to claim 2, wherein each of the sensor electrodes is formed in such a size that a plurality of sensor electrodes are covered by a contact surface of the object to be recognized in contact with the surface of the passivation film, and the capacitance detection circuit is provided. Is formed under the interlayer insulating film on the substrate, and the ground electrode is connected to a reference electrode to which a predetermined potential is applied outside a region where the sensor electrode is arranged. Shape recognition device. 7. The processing circuit according to claim 6, further comprising a processing circuit configured to process a detection output of the capacitance detection unit and output the detected output as a surface shape of the recognition target object, wherein the processing target is configured such that the recognition target object is a surface of the passivation film. A surface shape recognition device that processes a difference between respective electrostatic capacities corresponding to each of the sensor electrodes detected by the capacitance detection circuit when contacted with the object, and outputs the processed difference as a surface shape of the recognition target. 8. The surface shape according to claim 2, wherein the ground electrode is formed in a lattice shape, and the sensor electrode is arranged at the center of the grid of the ground electrode formed in the lattice shape. Recognition device. 9. The surface shape recognition device according to claim 2, wherein a part of the ground electrode forms one plane together with the passivation film. 10. The surface shape recognition apparatus according to claim 6, wherein a ground potential is applied to the reference electrode. 11. The signal detection circuit according to claim 1, wherein the capacitance detection circuit is connected to the sensor electrode and generates a signal corresponding to the capacitance, and is generated at a connection between the sensor electrode and the signal generation circuit. And an output circuit that converts the input signal into a desired signal and outputs the desired signal. The static electricity avoiding means is provided as an electrostatic protection element on the input side of all circuits connected to the sensor electrodes. Surface shape recognition device. 12. The MOS transistor according to claim 11, wherein one of a source terminal and a drain terminal is connected to the sensor electrode.
A transistor, and the one terminal of the MOS transistor and the MO
A surface shape recognition apparatus, wherein a parasitic pn diode is formed between a substrate or a well on which an S transistor is formed. 13. The signal detection circuit according to claim 1, wherein the capacitance detection circuit is connected to the sensor electrode and generates a signal corresponding to the capacitance, and is generated at a connection between the sensor electrode and the signal generation circuit. A signal amplifying circuit for amplifying the converted signal, and an output circuit for converting a signal from the signal amplifying circuit into a desired signal and outputting the signal, wherein the static electricity avoiding means is connected to the sensor electrode. A surface shape recognition apparatus characterized by being included in an input of a surface. 14. The signal amplification circuit according to claim 13, wherein the signal amplifying circuit includes a MOS transistor having one of a source terminal and a drain terminal connected to the sensor electrode as the input. One terminal and this MO
A surface shape recognition apparatus, wherein a parasitic pn diode is formed between a substrate or a well on which an S transistor is formed. 15. The signal detection circuit according to claim 1, wherein the capacitance detection circuit is connected to the sensor electrode and generates a signal corresponding to the capacitance, and is generated at a connection between the sensor electrode and the signal generation circuit. An output circuit for converting the input signal into a desired signal and outputting the signal, and wherein the static electricity avoiding means is provided as an electrostatic protection element between the sensor electrode and the output circuit. 16. The static electricity protection device according to claim 15, wherein one of the source terminal and the drain terminal is connected to the sensor electrode, and the other one of the source terminal and the drain terminal is connected to the sensor electrode. A MOS transistor connected to an input side of the output circuit, the one terminal of the MOS transistor,
A surface shape recognition apparatus, wherein a parasitic pn diode is formed between a substrate or a well on which an S transistor is formed. 17. A plurality of sensor electrodes arranged on an interlayer insulating film on a substrate and each of which is insulated and separated, and arranged on the interlayer insulating film so as to cover an upper surface and a side surface of each of the sensor electrodes. And a passivation film made of a dielectric, and the sensor electrode are formed on the interlayer insulating film by being insulated and separated, and a part of the passivation film is formed together with the passivation film.
A ground electrode forming one surface, and an integrated circuit for detecting a capacitance formed between the sensor electrode and the opposing recognition target surface when a part of the recognition target comes into contact with the passivation film surface. The sensor electrode is formed in a size to cover a plurality of the sensor electrodes when the recognition target comes into contact with the passivation film, and the capacitance detecting means is provided on the substrate. The ground electrode is formed under an interlayer insulating film, and the ground electrode is connected to a reference electrode to which a predetermined fixed potential is applied outside a region where the sensor electrode is arranged. When the recognition target contacts the surface of the passivation film, Surface shape recognition characterized by recognizing a surface shape of the recognition target based on a change in capacitance corresponding to each of the sensor electrodes detected by a capacitance detection unit. Location. 18. The surface shape according to claim 17, wherein the ground electrode is formed in a lattice shape, and the sensor electrode is arranged at the center of the grid of the ground electrode formed in the lattice shape. Recognition device. 19. The surface shape recognition apparatus according to claim 17, wherein a part of the ground electrode forms one plane together with the passivation film. 20. The surface shape recognition device according to claim 17, wherein a ground potential is applied to the reference electrode. 21. A detection element whose electric quantity changes in accordance with the shape of the surface of the detection target, a signal generation circuit connected to the detection element for generating a signal corresponding to the electric quantity, and the detection element and a signal. An output circuit that converts a signal generated at a connection portion of the generation circuit into a desired signal and outputs the converted signal, and outputs a signal to the detection element as an input of all circuits connected to the detection element. A MOS transistor to which one of the terminal and the drain terminal is connected, and a protective pn diode formed between one of the source terminal and the drain terminal and a substrate or a well forming the MOS transistor. A surface shape recognition device characterized by being used as a device. 22. A detection element whose electric quantity changes according to the shape of the surface of the detection target, a signal generation circuit connected to the detection element for generating a signal corresponding to the electric quantity, and the detection element and a signal. A surface shape recognition device comprising: a signal amplification circuit that amplifies a signal generated at a connection portion of a generation circuit; and an output circuit that converts a signal input from the signal amplification circuit into a desired signal and outputs the signal. A MOS transistor having one of a source terminal and a drain terminal connected to the detection element is provided as an input of the signal amplification circuit connected to the element, and one of the source terminal and the drain terminal is connected to the M transistor.
A surface shape recognition device using a parasitic pn diode formed between a substrate or a well forming an OS transistor as a protection element. 23. A detection element whose electric quantity changes according to the shape of the surface of the detection target, a signal generation circuit connected to the detection element for generating a signal corresponding to the electric quantity, and the detection element and a signal. An output circuit for converting a signal generated at a connection portion of the generation circuit into a desired signal and outputting the converted signal, wherein one of a source terminal and a drain terminal is connected to the detection element. With a transistor,
One of the source terminal and the drain terminal of the MOS transistor is connected to the input side of the output circuit, and one of the source terminal and the drain terminal is connected to the MOS transistor.
A surface shape recognition device using a parasitic pn diode formed between a substrate or a well forming a transistor as a protection element.