JP2001319935A - SiGe FILM FORMING METHOD, METHOD OF MANUFACTURING HETEROJUNCTION TRANSISTOR AND HETEROJUNCTION BIPOLAR TRANSISTOR - Google Patents
SiGe FILM FORMING METHOD, METHOD OF MANUFACTURING HETEROJUNCTION TRANSISTOR AND HETEROJUNCTION BIPOLAR TRANSISTORInfo
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- JP2001319935A JP2001319935A JP2000138994A JP2000138994A JP2001319935A JP 2001319935 A JP2001319935 A JP 2001319935A JP 2000138994 A JP2000138994 A JP 2000138994A JP 2000138994 A JP2000138994 A JP 2000138994A JP 2001319935 A JP2001319935 A JP 2001319935A
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えば、ヘテロ接
合トランジスタにおけるベース引き出し線として好適な
ＳｉＧｅ膜の形成方法とヘテロ接合トランジスタの製造
方法、及びヘテロ接合バイポーラトランジスタに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a SiGe film suitable as a base lead line in a heterojunction transistor, a method for manufacturing a heterojunction transistor, and a heterojunction bipolar transistor.
【０００２】[0002]
【従来の技術】ベース領域よりもエミッタ領域のバンド
ギャップを大きくしてエミッタの注入効率を大幅に向上
させることにより、電流利得の増大を図るＨＢＴ（ヘテ
ロ接合トランジスタ）は、低雑音かつＳｉでは達成し得
ない高速動作が可能であり、論理回路、通信システム、
マイクロ波デバイス（Ａ／Ｄ変換に用いるアンプ等）等
に用いられる高機能デバイスである。2. Description of the Related Art An HBT (heterojunction transistor) for increasing the current gain by increasing the bandgap of the emitter region more than the base region and greatly improving the injection efficiency of the emitter is achieved with low noise and Si. High-speed operation that cannot be performed is possible, logic circuits, communication systems,
This is a high-performance device used for microwave devices (such as an amplifier used for A / D conversion).
【０００３】従来、ＨＢＴは、ＧａＡｓとＡｌＧａＡｓ
との組み合わせ等により製作されていたが、近年、Ｓｉ
（シリコン）よりもＳｉＧｅ（シリコン−ゲルマニウ
ム）のバンドギャップが小さいことから、ＳｉＧｅを用
いたＨＢＴ（以下、ＳｉＧｅ−ＨＢＴと称す）が開発・
研究されている。このＳｉＧｅ−ＨＢＴは、技術蓄積の
豊富なＳｉプロセスと整合し易い、Ｓｉ−ＬＳＩとの混
載（１チップ化）が可能、ＧａＡｓデバイスに比べて製
造コストが下がる、Ｓｉに比べて環境的に扱いが難しい
Ａｓ等を多量に用いないで済む等の利点がある。Conventionally, HBTs are composed of GaAs and AlGaAs.
Has been manufactured in combination with
Since the band gap of SiGe (silicon-germanium) is smaller than that of (silicon), an HBT using SiGe (hereinafter referred to as SiGe-HBT) has been developed.
Has been studied. This SiGe-HBT is easily compatible with the Si process, which has a wealth of accumulated technology, can be mixed with a Si-LSI (one chip), has lower manufacturing costs than GaAs devices, and is more environmentally friendly than Si. There is an advantage that it is not necessary to use a large amount of As or the like which is difficult.
【０００４】ベース領域にＳｉＧｅを用いるＳｉＧｅ−
ＨＢＴの製造プロセスとしては、例えば、コレクタ領域
が形成されたシリコンウェーハ上にＳｉＯ2を形成し、
このＳｉＯ2に対してベース開口部（ベース窓部）を設
け、このベース開口部にＳｉＧｅをエピタキシャル成長
してベース領域を形成した後、ベース領域上にＳｉのエ
ミッタ領域を形成している。[0004] SiGe- using SiGe for the base region
As an HBT manufacturing process, for example, SiO 2 is formed on a silicon wafer on which a collector region is formed,
A base opening (base window) is provided for this SiO 2 , SiGe is epitaxially grown in the base opening to form a base region, and then a Si emitter region is formed on the base region.
【０００５】なお、従来、例えば、特開平９−１８１０
９１号公報や特開２０００−３１１５５号公報では、Ｓ
ｉＧｅの非選択エピタキシャル成長を行う前にバッファ
としてＳｉを１０〜５０ｎｍ成膜する技術が開示されて
いる。また、例えば、D.L.Harame等(IEEE Transactions
on Electron Devices, Vol.42,No.,March 1995,p469.)
やJ.L.Regolini等(Materials Science in Semiconducto
r Processing)では、ベース開口部を加工する際、ウェ
ーハ全面に多結晶Ｓｉ薄膜を堆積し、これをマスクとし
てベース部の絶縁膜をエッチングした後、多結晶Ｓｉ薄
膜を剥離することなく、ＳｉＧｅの非選択エピタキシャ
ル成長を行う技術が提案されている。[0005] Conventionally, for example, Japanese Patent Application Laid-Open No. 9-1810
No. 91 and JP-A-2000-31155, S
A technique for forming a 10 to 50 nm Si film as a buffer before performing non-selective epitaxial growth of iGe is disclosed. Also, for example, DL Harame and the like (IEEE Transactions
on Electron Devices, Vol.42, No., March 1995, p469.)
And JLRegolini (Materials Science in Semiconducto
In (r Processing), when processing the base opening, a polycrystalline Si thin film is deposited on the entire surface of the wafer, the insulating film in the base is etched using the thin film as a mask, and the SiGe thin film is removed without peeling the polycrystalline Si thin film. A technique for performing non-selective epitaxial growth has been proposed.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来の技術では、以下のような課題が残されている。非選
択エピタキシャル成長によってＳｉＧｅを成膜させるＳ
ｉＧｅ−ＨＢＴでは、ベース開口部に成長するエピタキ
シャル層がベース層（ベース領域）として用いられると
共に、ベース層に連続してＳｉＯ2上に成長する多結晶
層がベース引き出し線として用いられる。この場合、Ｓ
ｉＯ2上に直接ＳｉＧｅを成膜するとＳｉＯ2上に成長す
る多結晶層が膜荒れを起こし、結果としてベース引き出
し線の抵抗が高くなり、トランジスタ特性を劣化させて
しまう場合がある。特に、ＨＢＴのベース領域に要求さ
れる高いＧｅ組成比ほど膜荒れが生じ易く、また膜厚が
薄いほど、その効果が顕著になり易いという傾向があ
る。However, the above-mentioned conventional technique has the following problems. S for depositing SiGe by non-selective epitaxial growth
In iGe-HBT, an epitaxial layer grown in a base opening is used as a base layer (base region), and a polycrystalline layer grown on SiO 2 continuously from the base layer is used as a base lead line. In this case, S
If SiGe is formed directly on iO 2 , the polycrystalline layer grown on SiO 2 may be roughened, and as a result, the resistance of the base lead line may be increased and the transistor characteristics may be degraded. In particular, there is a tendency that the higher the Ge composition ratio required for the base region of the HBT, the more easily the film becomes rough, and the thinner the film thickness, the more the effect becomes more remarkable.
【０００７】上記従来技術では、ＳｉＯ2上に予めＳｉ
のバッファ層を１０〜５０ｎｍ成膜しているため、その
上に成長するＳｉＧｅの膜荒れが生じ難いと思われる
が、このバッファ層をベース層とする場合、バッファ層
厚１０〜５０ｎｍ分だけ実質的にベース層厚が厚くなっ
てしまう。すなわち、一般的にトランジスタのベース層
幅は薄いほど高速なトランジスタとなるが、従来技術で
はバッファ層厚の分だけ電子のベース走行時間が長くな
り、高速動作のためにＳｉＧｅベース層を採用したメリ
ットが低減し、トランジスタの動作速度がＳｉＧｅのみ
でベース領域を形成する場合よりも遅くなってしまう不
都合があった。[0007] the above-described conventional art, pre-Si on SiO 2
Since the buffer layer having a thickness of 10 to 50 nm is formed, it is considered that SiGe grown on the buffer layer is unlikely to be roughened. However, when this buffer layer is used as a base layer, the buffer layer is substantially 10 to 50 nm thick. As a result, the base layer becomes thicker. In other words, in general, the thinner the base layer width of the transistor is, the faster the transistor is. However, in the prior art, the base transit time of electrons is increased by the thickness of the buffer layer, and the merit of using the SiGe base layer for high-speed operation is obtained. And the operating speed of the transistor becomes slower than when the base region is formed only by SiGe.
【０００８】また、多結晶Ｓｉ薄膜をマスクとしてベー
ス部の絶縁膜をエッチングした後にＳｉＧｅ成長を行う
上記従来技術では、多結晶Ｓｉの成膜とＳｉＧｅの成膜
とで異なる製造工程を必要とするが、近年のＬＳＩ製造
では微細配線の結果、製造工程中の熱履歴を極力抑える
必要があり、デバイスに対する熱影響の観点からも、こ
の従来技術のように熱工程が多いことは好ましいことで
はない。In addition, in the above-described conventional technology in which SiGe growth is performed after etching the insulating film of the base portion using the polycrystalline Si thin film as a mask, different manufacturing steps are required for forming polycrystalline Si and forming SiGe. However, in recent LSI manufacturing, as a result of fine wiring, it is necessary to minimize the thermal history during the manufacturing process, and from the viewpoint of the thermal effect on the device, it is not preferable that there are many thermal processes as in this conventional technique. .
【０００９】本発明は、前述の課題に鑑みてなされたも
ので、絶縁膜上のＳｉＧｅ膜が荒れることを防いで膜質
及び膜抵抗を改善することができるＳｉＧｅ膜の形成方
法とヘテロ接合トランジスタの製造方法、及びヘテロ接
合バイポーラトランジスタを提供することを目的とす
る。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a method of forming a SiGe film capable of improving the film quality and film resistance by preventing the SiGe film on the insulating film from being roughened, and a heterojunction transistor. It is an object of the present invention to provide a manufacturing method and a heterojunction bipolar transistor.
【００１０】[0010]
【課題を解決するための手段】本発明者らは、ＳｉＧｅ
の成膜技術について研究を行ってきた結果、一定範囲の
Ｇｅ組成比であれば非常に薄いＳｉＧｅバッファ層厚で
も、膜荒れ及び抵抗を大幅に改善することができること
を見出した。すなわち、本発明者らは、ＳｉＯ 2上にＧ
ｅ組成比を変えたＳｉＧｅ膜を成長し、その成膜状態等
を調べると共に、バッファ層の厚さを変えたＳｉＧｅ膜
を成長し、その抵抗を測定した。なお、図５、図６及び
図７は、それぞれＧｅ組成比を０．０４、０．１３及び
０．３０としたＳｉＧｅ膜のＳＥＭ写真である。また、
図８は、抵抗測定の一例であり、ＳｉＯ2上にバッファ
層としてＳｉ膜を成長し、該バッファ層の層厚を０〜５
ｎｍまで変えた場合のＳｉＧｅ膜（Ｇｅ組成比０．３
０、バッファ層上の層厚は同一）のシート抵抗を示すグ
ラフである。Means for Solving the Problems The present inventors have proposed SiGe.
As a result of conducting research on film deposition technology,
With a Ge composition ratio, a very thin SiGe buffer layer
Can significantly improve film roughness and resistance
Was found. That is, the present inventors have proposed that SiO 2 TwoG on
eGrow SiGe films with different composition ratios and their film formation conditions
And the thickness of the buffer layer was changed.
Was grown and its resistance was measured. 5 and 6 and
FIG. 7 shows Ge composition ratios of 0.04, 0.13 and
It is a SEM photograph of the SiGe film set to 0.30. Also,
FIG. 8 shows an example of the resistance measurement, in which SiO 2 is used.TwoBuffer on top
A Si film is grown as a layer, and the thickness of the buffer layer is set to 0 to 5
SiGe film (Ge composition ratio 0.3
0, the layer thickness on the buffer layer is the same).
It is rough.
【００１１】図６〜図７からわかるように、Ｇｅ組成比
が０．１３の場合では、ＳｉＧｅ膜は部分的に不連続化
しており、さらにＧｅ組成比０．３０の場合では完全に
不連続化してしまいほとんど成膜されていないのに対
し、０．０４の場合では、全体的に不連続化しておら
ず、良質な成膜状態が得られていることがわかった。ま
た、図８からわかるように、バッファ層の層厚が０．５
ｎｍでは抵抗値が約半分に低減され、さらに層厚が１ｎ
ｍで抵抗値が一桁下がることがわかった。As can be seen from FIGS. 6 and 7, when the Ge composition ratio is 0.13, the SiGe film is partially discontinuous, and when the Ge composition ratio is 0.30, it is completely discontinuous. In contrast, in the case of 0.04, the film was not discontinuous as a whole, and a good film formation state was obtained. Further, as can be seen from FIG. 8, the thickness of the buffer layer is 0.5
nm, the resistance is reduced to about half and the layer thickness is 1n
It was found that the resistance value decreased by one digit at m.
【００１２】したがって、本発明は、この知見に基づい
た技術であり、前記課題を解決するために以下の構成を
採用した。すなわち、本発明のＳｉＧｅ膜の形成方法
は、絶縁膜上にＳｉＧｅ膜を形成する方法であって、前
記絶縁膜上に第１のＳｉ(1-x)Ｇｅx膜（０≦ｘ＜０．０
５）を形成するバッファ形成工程と、前記第１のＳｉ
(1-x)Ｇｅx膜上に第２のＳｉ(1 -y)Ｇｅy膜（０．０５≦
ｙ＜１）を形成する主膜形成工程とを備え、前記バッフ
ァ形成工程は、前記第１のＳｉ(1-x)Ｇｅx膜を０．５ｎ
ｍ以上５ｎｍ以下の厚さ範囲で成膜することを特徴とす
る。Therefore, the present invention is a technique based on this finding, and employs the following configuration in order to solve the above-mentioned problems. That is, the method of forming a SiGe film of the present invention is a method of forming a SiGe film on an insulating film, and a first Si (1-x) Ge x film (0 ≦ x <0. 0
5) forming a buffer; and forming the first Si
On the (1-x) Ge x film, a second Si (1- y) Ge y film (0.05 ≦
and a main membrane formation step of forming a y <1), the buffer forming step, 0.5n the first Si (1-x) Ge x film
The film is formed in a thickness range of m to 5 nm.
【００１３】このＳｉＧｅ膜の形成方法では、バッファ
形成工程において、第１のＳｉ(1-x )Ｇｅx膜を０．５ｎ
ｍ以上５ｎｍ以下の厚さ範囲で成膜するので、従来のよ
うに１０〜５０ｎｍという厚いバッファ層を不要とし、
非常に薄いバッファ層で第２のＳｉＧｅ膜の不連続化
（膜荒れ）を改善し、抵抗も大幅に抵抗させることがで
きる。なお、上述したように、第１のＳｉ(1-x)Ｇｅx膜
を少なくとも０．５ｎｍとすると、全く第１のＳｉ
(1-x)Ｇｅx膜を設けない場合（第２のＳｉ(1-y)Ｇｅy膜
のみ）よりも抵抗値を大幅に低減する効果が得られる。
例えば、第２のＳｉ(1 -y)Ｇｅy膜がＧｅ組成比ｙ＝０．
３であっても、第１のＳｉ(1-x)Ｇｅx膜を０．５ｎｍと
すると抵抗値を約半分に低減でき、より好ましくは１ｎ
ｍとすると抵抗値を一桁下げることができる。なお、第
１のＳｉ(1-x)Ｇｅx膜を５ｎｍ以下としたのは、これ以
上厚くしても低抵抗化の効果が小さく、抵抗値があまり
変わらないためである。[0013] In the method of forming the SiGe film, 0.5n in the buffer forming step, a first Si (1-x) Ge x film
Since the film is formed in a thickness range of not less than m and not more than 5 nm, a thick buffer layer having a thickness of 10 to 50 nm is unnecessary as in the related art.
The discontinuity (roughness) of the second SiGe film can be improved with a very thin buffer layer, and the resistance can be greatly reduced. As described above, when at least 0.5nm first Si (1-x) Ge x layer, exactly the first Si
The effect of greatly reducing the resistance value can be obtained as compared with the case where the (1-x) Ge x film is not provided (only the second Si (1-y) Ge y film).
For example, the second Si (1- y) Ge y film has a Ge composition ratio y = 0.
Even 3 can reduce the first Si (1-x) Ge x layer to about half the resistance value between the 0.5 nm, more preferably 1n
If m, the resistance value can be reduced by one digit. Incidentally, the first Si (1-x) Ge x film was 5nm or less, more even when the thickness reduced the effect of low resistance, the resistance value is because not much.
【００１４】また、本発明のＳｉＧｅ膜の形成方法は、
少なくとも前記第２のＳｉ(1-y)Ｇｅy膜を、０．１３３
Ｐａ以上１．３３×１０4Ｐａ以下の圧力範囲の減圧Ｃ
ＶＤ法により成膜する場合に好適である。すなわち、減
圧ＣＶＤ法は、高真空で成膜を行うＵＨＶ−ＣＶＤ法よ
りもＳｉＧｅ膜の膜荒れが顕著になるおそれがあるが、
本発明の第２のＳｉ(1-y)Ｇｅy膜の成膜方法に減圧ＣＶ
Ｄ法を適用することにより、ＵＨＶ−ＣＶＤ法等の成長
方法に比べて顕著に膜荒れ抑制の効果を得ることができ
る。また、減圧ＣＶＤ法でも容易に良質なＳｉＧｅ膜を
得ることができるため、ＵＨＶ−ＣＶＤ法等の高真空技
術を用いる必要が無くなり、生産性等を向上させること
ができる。Further, the method of forming a SiGe film according to the present invention comprises:
At least the second Si (1-y) Ge y film is 0.133
Decompression C in a pressure range of not less than Pa and not more than 1.33 × 10 4 Pa
It is suitable for forming a film by the VD method. That is, the low-pressure CVD method has a possibility that the roughness of the SiGe film becomes more remarkable than the UHV-CVD method in which the film is formed in a high vacuum.
The second method for forming a Si (1-y) Ge y film according to the present invention employs a reduced pressure CV method.
By applying the method D, it is possible to obtain a remarkable effect of suppressing film roughness as compared with a growth method such as a UHV-CVD method. In addition, since a high-quality SiGe film can be easily obtained even by a low-pressure CVD method, it is not necessary to use a high vacuum technique such as a UHV-CVD method, so that productivity and the like can be improved.
【００１５】本発明のヘテロ接合トランジスタの製造方
法は、ＳｉＧｅのベース領域を有するヘテロ接合トラン
ジスタを製造する方法であって、コレクタ領域が形成さ
れたＳｉ基板上に絶縁膜を形成する工程と、前記絶縁膜
の一部に前記コレクタ領域に通じる窓部を形成する工程
と、前記窓部上及び前記絶縁膜上にＳｉＧｅ膜を非選択
的に形成し窓部上に前記ベース領域を形成すると共に前
記絶縁膜上にベース電極までの引き出し線に供される領
域を形成するＳｉＧｅ膜形成工程と、前記ベース領域上
にＳｉのエミッタ領域を形成する工程とを備え、前記Ｓ
ｉＧｅ膜形成工程は、前記ＳｉＧｅ膜を上記本発明のＳ
ｉＧｅ膜の形成方法により形成することを特徴とする。A method for manufacturing a heterojunction transistor according to the present invention is a method for manufacturing a heterojunction transistor having a SiGe base region, comprising the steps of: forming an insulating film on a Si substrate on which a collector region is formed; Forming a window portion communicating with the collector region in a part of the insulating film, and forming a SiGe film on the window portion and the insulating film non-selectively and forming the base region on the window portion; A step of forming an SiGe film on the insulating film to form a region serving as a lead line to the base electrode; and forming a Si emitter region on the base region.
In the iGe film forming step, the SiGe film is formed on the SiGe film of the present invention.
It is characterized by being formed by an iGe film forming method.
【００１６】また、本発明のヘテロ接合トランジスタ
は、ＳｉＧｅのベース領域を有するヘテロ接合トランジ
スタであって、Ｓｉ基板に形成されたコレクタ領域と、
前記Ｓｉ基板上に形成され前記コレクタ領域に通じる窓
部を有した絶縁膜と、前記窓部上に形成されＳｉＧｅ膜
からなるベース領域と、前記絶縁膜上に形成され前記ベ
ース領域に接続されたＳｉＧｅ膜からなる引き出し線
と、前記ベース領域上に形成されたＳｉのエミッタ領域
とを備え、少なくとも前記引き出し線は、前記絶縁膜上
に形成された第１のＳｉ(1-x)Ｇｅx膜（０≦ｘ＜０．０
５）と、前記第１のＳｉ(1-x)Ｇｅx膜上に形成された第
２のＳｉ(1-y)Ｇｅy膜（０．０５≦ｙ＜１）とを備え、
前記第１のＳｉ(1-x)Ｇｅx膜は、０．５ｎｍ以上５ｎｍ
以下の厚さであることを特徴とする。Further, the heterojunction transistor of the present invention is a heterojunction transistor having a base region of SiGe, and comprises a collector region formed on a Si substrate,
An insulating film formed on the Si substrate and having a window communicating with the collector region, a base region formed on the window and made of a SiGe film, and formed on the insulating film and connected to the base region; A lead line made of a SiGe film and an emitter region of Si formed on the base region, wherein at least the lead line is a first Si (1-x) Ge x film formed on the insulating film (0 ≦ x <0.0
5) and a second Si (1-y) Ge y film (0.05 ≦ y <1) formed on the first Si (1-x) Ge x film,
Said first Si (1-x) Ge x film, 5 nm or more 0.5nm
The thickness is as follows.
【００１７】これらのヘテロ接合トランジスタの製造方
法及びヘテロ接合トランジスタでは、第１のＳｉ(1-x)
Ｇｅx膜（０≦ｘ＜０．０５）上に第２のＳｉ(1-y)Ｇｅ
y膜（０．０５≦ｙ＜１）が形成され、第１のＳｉ(1-x)
Ｇｅx膜が０．５ｎｍ以上５ｎｍ以下の厚さであるの
で、絶縁膜上に膜荒れが抑制されたＳｉＧｅ膜が得ら
れ、ベース引き出し線を低抵抗化できると共に、ベース
領域のＳｉＧｅ膜として、薄い第１のＳｉ(1-x)Ｇｅx膜
をバッファとしているので、全体としてベース層幅を薄
くすることができる。In the method of manufacturing a heterojunction transistor and the heterojunction transistor, the first Si (1-x)
Second Si (1-y) Ge on Ge x film (0 ≦ x <0.05)
A y film (0.05 ≦ y <1) is formed, and the first Si (1-x)
Since the Ge x film has a thickness of 0.5 nm or more and 5 nm or less, a SiGe film in which film roughness is suppressed is obtained on the insulating film, and the resistance of the base lead line can be reduced. since the thin first Si (1-x) Ge x layer and the buffer, it is possible to reduce the width of the base layer as a whole.
【００１８】また、本発明のヘテロ接合トランジスタの
製造方法は、前記ＳｉＧｅ膜形成工程が、前記第２のＳ
ｉ(1-y)Ｇｅy膜のＧｅ組成比ｙが０．０８≦ｙ≦０．３
の範囲内であることが好ましい。また、本発明のヘテロ
接合トランジスタは、前記第２のＳｉ(1-y)Ｇｅy膜のＧ
ｅ組成比ｙが０．０８≦ｙ≦０．３の範囲内であること
が好ましい。In the method of manufacturing a hetero junction transistor according to the present invention, the step of forming the SiGe film may include the step of forming the second S
The Ge composition ratio y of the i (1-y) Ge y film is 0.08 ≦ y ≦ 0.3
Is preferably within the range. Further, the heterojunction transistor of the present invention is characterized in that the second Si (1-y) Ge y film has a G
e The composition ratio y is preferably in the range of 0.08 ≦ y ≦ 0.3.
【００１９】これらのヘテロ接合トランジスタの製造方
法及びヘテロ接合トランジスタでは、第２のＳｉ(1-y)
Ｇｅy膜のＧｅ組成比ｙが０．０８≦ｙ≦０．３の範囲
内であるので、ＨＢＴのベース領域として好適なバンド
ギャップが得られる。In these heterojunction transistor manufacturing methods and heterojunction transistors, the second Si (1-y)
Since the Ge composition ratio y of the Ge y film is in the range of 0.08 ≦ y ≦ 0.3, a band gap suitable as a base region of the HBT can be obtained.
【００２０】[0020]
【発明の実施の形態】以下、本発明に係るＳｉＧｅ膜の
形成方法とヘテロ接合トランジスタの製造方法、及びヘ
テロ接合バイポーラトランジスタの一実施形態を、図１
から図３を参照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for forming a SiGe film, a method for manufacturing a heterojunction transistor, and a heterojunction bipolar transistor according to the present invention will be described below with reference to FIG.
This will be described with reference to FIG.
【００２１】図１は、本発明のヘテロ接合バイポーラト
ランジスタシリコン（ＨＢＴ）の概略的な断面構造を示
すものである。該ＨＢＴの構造をその製造プロセスと合
わせて説明すると、図２の（ａ）に示すように、ｐ型シ
リコンウェーハ（Ｓｉ基板）１表面には、ヒ素打ち込み
によりｎ++にドーピングされた埋込みサブコレクタ領域
２が形成され、さらにシリコンウェーハ１表面にｎ型単
結晶シリコンのｎ−Ｓｉエピタキシャル層３をエピタキ
シャル成長により形成する。FIG. 1 shows a schematic sectional structure of a heterojunction bipolar transistor silicon (HBT) of the present invention. The structure of the HBT will be described together with its manufacturing process. As shown in FIG. 2A, the surface of a p-type silicon wafer (Si substrate) 1 has a buried sub-type doped with n ++ by arsenic implantation. A collector region 2 is formed, and an n-Si epitaxial layer 3 of n-type single crystal silicon is formed on the surface of the silicon wafer 1 by epitaxial growth.
【００２２】次に、図２の（ｂ）に示すように、ｎ−Ｓ
ｉエピタキシャル層３に埋込みサブコレクタ領域２に達
するようにリン打ち込みにより、ｎ+にドーピングされ
た第１のコレクタウェル４及び第２のコレクタウェル５
（コレクタ領域）が生成される。そして、図２の（ｃ）
に示すように、ｎ−Ｓｉエピタキシャル層３の表面に絶
縁膜として第１のＳｉＯ2層（二酸化シリコン層）６を
熱酸化工程により形成する。この後、第１のＳｉＯ2層
６にマスク処理を施して選択的にエッチングを行い、第
１のコレクタウェル４に通じるベース窓部７を形成す
る。Next, as shown in FIG.
A first collector well 4 and a second collector well 5 doped with n + by phosphorus implantation to reach the buried sub-collector region 2 in the i-epitaxial layer 3.
(Collector region) is generated. Then, (c) of FIG.
As shown in FIG. 1, a first SiO 2 layer (silicon dioxide layer) 6 is formed as an insulating film on the surface of the n-Si epitaxial layer 3 by a thermal oxidation process. Thereafter, the first SiO 2 layer 6 is subjected to a masking treatment and is selectively etched to form a base window 7 communicating with the first collector well 4.
【００２３】次に、図２の（ｄ）に示すように、ベース
窓部７上及び第１のＳｉＯ2層６上にＳｉＧｅ膜８を非
選択的に形成する。このＳｉＧｅ膜８は、バッファ層と
して形成される第１のＳｉ(1-x)Ｇｅx膜（０≦ｘ＜０．
０５）９と、該第１のＳｉ(1 -x)Ｇｅx膜９上に形成され
る第２のＳｉ(1-y)Ｇｅy膜（０．０５≦ｙ＜１）１０と
の２層構造を有する。Next, as shown in FIG. 2D, a SiGe film 8 is non-selectively formed on the base window 7 and the first SiO 2 layer 6. This SiGe film 8 is formed of a first Si (1-x) Ge x film (0 ≦ x <0.
05) 9 and a second Si (1-y) Ge y film (0.05 ≦ y <1) 10 formed on the first Si (1- x) Ge x film 9 Having a structure.
【００２４】すなわち、ＳｉＧｅ膜８を形成するには、
まず、ベース窓部７上及び第１のＳｉＯ2層６上に第１
のＳｉ(1-x)Ｇｅx膜９を０．５ｎｍ以上５ｎｍ以下の厚
さ範囲で非選択エピタキシャル成長により成膜する（バ
ッファ形成工程）。さらに、第１のＳｉ(1-x)Ｇｅx膜９
上に第２のＳｉ(1-y)Ｇｅy膜１０を非選択エピタキシャ
ル成長により成膜する。That is, to form the SiGe film 8,
First, the first window is formed on the base window 7 and the first SiO 2 layer 6.
Of Si (1-x) Ge x film 9 is formed by non-selective epitaxial growth at 5nm less thickness range of 0.5 nm (buffer forming step). Further, a first Si (1-x) Ge x film 9
A second Si (1-y) Ge y film 10 is formed thereon by non-selective epitaxial growth.
【００２５】なお、第１のＳｉ(1-x)Ｇｅx膜９及び第２
のＳｉ(1-y)Ｇｅy膜１０は、０．１３３Ｐａ以上１．３
３×１０4Ｐａ以下の圧力範囲の減圧ＣＶＤ法により成
膜する。また、第２のＳｉ(1-y)Ｇｅy膜１０のＧｅ組成
比ｙは、より好ましくは０．０８≦ｙ≦０．３の範囲内
に設定される。また、この減圧ＣＶＤ法における成膜温
度は、６００〜８００℃であると共に、キャリアガスと
してＨ2を、ソースガスとしてＳｉＨ4及びＧｅＨ4を用
いている。[0025] The first Si (1-x) Ge x film 9 and the second
Of the Si (1-y) Ge y film 10 is 0.133 Pa or more and 1.3.
A film is formed by a low pressure CVD method in a pressure range of 3 × 10 4 Pa or less. Further, the Ge composition ratio y of the second Si (1-y) Ge y film 10 is more preferably set within a range of 0.08 ≦ y ≦ 0.3. The film forming temperature in this low-pressure CVD method is 600 to 800 ° C., H 2 is used as a carrier gas, and SiH 4 and GeH 4 are used as source gases.
【００２６】この成膜工程では、ベース窓部７に形成さ
れる第１のＳｉ(1-x)Ｇｅx膜９及び第２のＳｉ(1-y)Ｇ
ｅy膜１０が、単結晶のエピタキシャル層として形成さ
れ、第１のＳｉＯ2層６上に形成される第１のＳｉ(1-x)
Ｇｅx膜９及び第２のＳｉ(1-y)Ｇｅy膜１０が、多結晶
の非エピタキシャル層として形成される。なお、第１の
Ｓｉ(1-x)Ｇｅx膜９及び第２のＳｉ(1-y)Ｇｅy膜１０
は、ホウ素によりｐにドーピングされる。このようにし
て、ベース窓部７にＳｉＧｅ膜８によるヘテロ接合のベ
ース領域１１が形成される。[0026] In the film forming step, the first Si (1-x) which is formed in the base window 7 Ge x film 9 and the second Si (1-y) G
An e y film 10 is formed as a single crystal epitaxial layer, and a first Si (1-x) is formed on the first SiO 2 layer 6.
A Ge x film 9 and a second Si (1-y) Ge y film 10 are formed as polycrystalline non-epitaxial layers. The first Si (1-x) Ge x film 9 and the second Si (1-y) Ge y film 10
Is doped to p by boron. In this manner, a heterojunction base region 11 of the SiGe film 8 is formed in the base window 7.
【００２７】次に、第２のＳｉ(1-y)Ｇｅy膜１０上にマ
スク処理を施して選択的にエッチングを行い、図３の
（ａ）に示すように、ベース引き出し線１２及びベース
領域１１に供される部分を残して第１のＳｉ(1-x)Ｇｅx
膜９及び第２のＳｉ(1-y)Ｇｅy膜１０を除去する。さら
に、図３の（ｂ）に示すように、残った第２のＳｉ(1-y
)Ｇｅy膜１０上及び露出した第１のＳｉＯ2層６上に第
２のＳｉＯ2層１３を成膜する。Next, the second Si (1-y) Ge y film 10 is selectively etched by performing a mask process on the second Si (1-y) Ge y film 10 as shown in FIG. The first Si (1-x) Ge x except for the portion provided for the region 11
Removing the film 9 and the second Si (1-y) Ge y layer 10. Further, as shown in FIG. 3B, the remaining second Si (1-y
) A second SiO 2 layer 13 is formed on the Ge y film 10 and the exposed first SiO 2 layer 6.
【００２８】次に、第２のＳｉＯ2層１３上にマスク処
理を施して選択的にウェットエッチングを行い、ベース
領域１１に通じるエミッタ窓部１４を形成する。この
後、エミッタ窓部１４及び第２のＳｉＯ2層１３上にＣ
ＶＤ法によりＳｉをエピタキシャル成長させ、エミッタ
窓部１４にＳｉ単結晶層１５を成膜してエミッタ領域１
６を形成する。そして、エミッタ窓部１４にマスク処理
を施し、エミッタ領域１６に供される部分を残して第２
のＳｉＯ2層１３上のＳｉをエッチング処理により除去
する。Next, a mask process is performed on the second SiO 2 layer 13 to selectively perform wet etching to form an emitter window portion 14 communicating with the base region 11. Thereafter, C is deposited on the emitter window 14 and the second SiO 2 layer 13.
Si is epitaxially grown by the VD method, and an Si single crystal layer 15 is formed in the emitter window 14 to form the emitter region 1.
6 is formed. Then, a mask process is performed on the emitter window portion 14 to leave a portion provided for the emitter region 16 in the second region.
Of the SiO 2 layer 13 is removed by etching.
【００２９】次に、第２のＳｉＯ2層１３上にマスク処
理を施して選択的にウェットエッチングを行い、図３の
（ｃ）に示すように、ベース引き出し線１２に通じるベ
ース電極窓部１７と、エミッタ領域１６に通じるエミッ
タ電極窓部１８と、第２のコレクタウェル５に通じるコ
レクタ電極窓部１９とを形成する。この後、ベース電極
窓部１７、エミッタ電極窓部１８及びコレクタ電極窓部
１９に、金属材料を選択的に埋め込んでそれぞれベース
電極２０、エミッタ電極２１及びコレクタ電極２２を形
成することにより、本実施形態のＨＢＴが製造される。Next, a mask process is performed on the second SiO 2 layer 13 to selectively perform wet etching, and as shown in FIG. 3C, a base electrode window portion 17 leading to the base lead line 12 is formed. Then, an emitter electrode window 18 communicating with the emitter region 16 and a collector electrode window 19 communicating with the second collector well 5 are formed. Thereafter, the base electrode 20, the emitter electrode 21, and the collector electrode 22 are formed by selectively embedding a metal material in the base electrode window 17, the emitter electrode window 18, and the collector electrode window 19, respectively. A form of HBT is manufactured.
【００３０】本実施形態のＳｉＧｅ膜の形成方法、ＨＢ
Ｔの製造方法及びＨＢＴでは、第１のＳｉ(1-x)Ｇｅx膜
９（０≦ｘ＜０．０５）上に第２のＳｉ(1-y)Ｇｅy膜１
０（０．０５≦ｙ＜１）が形成され、第１のＳｉ(1-x)
Ｇｅx膜９が０．５ｎｍ以上５ｎｍ以下の厚さであるの
で、第１のＳｉＯ2層６上に膜荒れが抑制されたＳｉＧ
ｅ膜８が得られ、ベース引き出し線１２を低抵抗化でき
ると共に、ベース領域１１のＳｉＧｅ膜８としては、薄
い第１のＳｉ(1-x)Ｇｅx膜９をバッファとしているの
で、全体としてベース層幅が薄くなり、高速動作を得る
ことができる。The method for forming a SiGe film of the present embodiment, HB
In the method of manufacturing T and the HBT, the second Si (1-y) Ge y film 1 is formed on the first Si (1-x) Ge x film 9 (0 ≦ x <0.05).
0 (0.05 ≦ y <1) is formed and the first Si (1-x)
Since the Ge x film 9 has a thickness of not less than 0.5 nm and not more than 5 nm, SiG in which film roughness is suppressed is formed on the first SiO 2 layer 6.
The e film 8 is obtained, the resistance of the base lead line 12 can be reduced, and the thin first Si (1-x) Ge x film 9 is used as the buffer as the SiGe film 8 in the base region 11, so that the whole is The base layer width is reduced, and high-speed operation can be obtained.
【００３１】また、第２のＳｉ(1-y)Ｇｅy膜１０を０．
１３３Ｐａ以上１．３３×１０4Ｐａ以下の圧力範囲の
減圧ＣＶＤ法で成膜するので、ＵＨＶ−ＣＶＤ法等の成
長方法に比べて顕著に膜荒れ抑制の効果を得ることがで
きると共に、減圧ＣＶＤ法でも容易に良質なＳｉＧｅ膜
を得ることができるため、ＵＨＶ−ＣＶＤ法等の高真空
技術を用いる必要が無くなり、生産性等を向上させるこ
とができる。なお、第２のＳｉ(1-y)Ｇｅy膜１０のＧｅ
組成比ｙが０．０８≦ｙ≦０．３の範囲内であるので、
ＨＢＴのベース領域１１として好適なバンドギャップが
得られる。Further, the second Si (1-y) Ge y film 10 is set to 0.
Since the film is formed by a low pressure CVD method in a pressure range of 133 Pa or more and 1.33 × 10 4 Pa or less, an effect of suppressing film roughness can be obtained remarkably as compared with a growth method such as a UHV-CVD method. Since a high-quality SiGe film can be easily obtained by the method, it is not necessary to use a high vacuum technique such as the UHV-CVD method, and the productivity can be improved. Note that the Ge of the second Si (1-y) Ge y film 10
Since the composition ratio y is in the range of 0.08 ≦ y ≦ 0.3,
A band gap suitable for the base region 11 of the HBT is obtained.
【００３２】[0032]
【実施例】次に、本発明に係るＳｉＧｅ膜の形成方法と
ヘテロ接合トランジスタの製造方法、及びヘテロ接合バ
イポーラトランジスタを、実施例により具体的に説明す
る。Next, a method for forming a SiGe film, a method for manufacturing a hetero-junction transistor, and a hetero-junction bipolar transistor according to the present invention will be specifically described with reference to examples.
【００３３】上記実施形態と同様に第１のＳｉＯ2層上
に第１のＳｉ(1-x)Ｇｅx膜及び第２のＳｉ(1-y)Ｇｅy膜
を実際に成膜し、その成膜状態及び抵抗（シート抵抗）
を調べた。なお、本発明に係る実施例の第２のＳｉ
(1-y)Ｇｅy膜は、Ｇｅ組成比ｙが０．３０である。ま
た、第１のＳｉ(1-x)Ｇｅx膜は、層厚が５ｎｍであって
Ｇｅ組成比が０、すなわちＳｉ膜を用いている。As in the above embodiment, a first Si (1-x) Ge x film and a second Si (1-y) Ge y film are actually formed on the first SiO 2 layer. Film formation state and resistance (sheet resistance)
Was examined. The second Si of the embodiment according to the present invention
The (1-y) Ge y film has a Ge composition ratio y of 0.30. The first Si (1-x) Ge x film, Ge composition ratio thickness is a 5nm is 0, that is, using a Si film.
【００３４】図４は、本発明の実施例によるＳｉＧｅ膜
のＳＥＭ写真を示したものである。この図４と、比較例
としての図７とを比較すると、バッファ層を有しない比
較例の場合は、ＳｉＧｅが不連続化してほとんど成膜さ
れていないのに対し、本実施例の場合では、連続かつ良
質な成膜状態が得られていることがわかる。FIG. 4 is a SEM photograph of the SiGe film according to the embodiment of the present invention. Comparing FIG. 4 with FIG. 7 as a comparative example, in the case of the comparative example having no buffer layer, SiGe is discontinued and almost no film is formed, whereas in the case of the present embodiment, It can be seen that a continuous and good quality film formation state is obtained.
【００３５】また、ＳｉＧｅ層（Ｇｅ組成比０．３０）
を成膜した際のシート抵抗を調べたところ、図８に示す
ように、バッファ層のないＳｉＧｅ層の場合は１×１０
5Ωであったのに対し、本発明の実施例では、１×１０4
Ωであり、一桁も低抵抗化していた。このように、本発
明を適用した場合では、従来と比べて良質な膜が得られ
ると共に大幅な低抵抗化が得られた。Further, a SiGe layer (Ge composition ratio 0.30)
When the sheet resistance at the time of film formation was examined, as shown in FIG. 8, in the case of a SiGe layer without a buffer layer, 1 × 10
In contrast to 5 Ω, in the embodiment of the present invention, 1 × 10 4
Ω, and the resistance was reduced by an order of magnitude. As described above, when the present invention is applied, a film having a higher quality than that of the related art can be obtained, and the resistance can be significantly reduced.
【００３６】なお、本発明は、次のような実施形態をも
含むものである。上記実施形態では、本発明のＳｉＧｅ
膜の形成方法をＨＢＴにおけるベース引き出し線形成に
適用したが、絶縁膜上にＳｉＧｅ膜を成膜した構造を有
する他のデバイス等の製造に適用しても構わない。例え
ば、ＭＯＳトランジスタ等のＭＯＳ構造において、ゲー
ト酸化膜上にゲート電極としてＳｉＧｅ膜を形成する場
合等に本発明を適用してもよい。The present invention also includes the following embodiments. In the above embodiment, the SiGe of the present invention is used.
Although the method of forming the film is applied to the formation of the base lead line in the HBT, it may be applied to the manufacture of another device having a structure in which a SiGe film is formed on an insulating film. For example, the present invention may be applied to a case where a SiGe film is formed as a gate electrode on a gate oxide film in a MOS structure such as a MOS transistor.
【００３７】また、上記実施形態では、第１のＳｉＧｅ
膜としてＧｅ組成比が一定の層を形成したが、Ｇｅ組成
比ｘが０≦ｘ＜０．０５の範囲内で変化している第１の
ＳｉＧｅ膜でも構わない。例えば、絶縁膜（ＳｉＯ2）
上にＧｅ組成比ｘを０から０．１５まで徐々に増加させ
ながら組成が傾斜したＳｉＧｅ層を形成し、この傾斜組
成のＳｉＧｅ層上にさらにＧｅ組成比ｘが０．１５のＳ
ｉＧｅ層を形成する場合も本発明に含まれる。In the above embodiment, the first SiGe
Although a layer having a constant Ge composition ratio is formed as the film, a first SiGe film in which the Ge composition ratio x varies within a range of 0 ≦ x <0.05 may be used. For example, an insulating film (SiO 2 )
A Ge composition ratio is gradually increased from 0 to 0.15 to form a SiGe layer having a gradient composition on the SiGe layer having the gradient composition.
The case where an iGe layer is formed is also included in the present invention.
【００３８】すなわち、絶縁膜上に形成される傾斜組成
ＳｉＧｅ層のうち初期の０≦ｘ＜０．０５のＧｅ組成比
ｘを有する層の領域が、０．５ｎｍ≦５ｎｍ以下の厚さ
であれば、この層の領域が本発明における第１のＳｉＧ
ｅ膜とみなすことができる。そして、この領域以降のＧ
ｅ組成比ｘが０．０５から０．１５までのＳｉＧｅ領域
は、本発明における第２のＳｉＧｅ膜とみなすことがで
きる。このように、本発明における第１のＳｉＧｅ膜上
に成膜する第２のＳｉＧｅ膜は、第１のＳｉＧｅ膜の成
膜後に成膜工程を中断することなく連続的に成膜される
ＳｉＧｅ層も含むものである。That is, in the gradient composition SiGe layer formed on the insulating film, the region of the layer having the initial Ge composition ratio x of 0 ≦ x <0.05 has a thickness of 0.5 nm ≦ 5 nm or less. If this layer region is the first SiG in the present invention,
It can be regarded as an e-film. And G after this area
The SiGe region where the e composition ratio x is 0.05 to 0.15 can be regarded as the second SiGe film in the present invention. As described above, the second SiGe film formed on the first SiGe film in the present invention is a SiGe layer that is continuously formed without interrupting the film forming process after the formation of the first SiGe film. Is also included.
【００３９】[0039]
【発明の効果】本発明によれば、以下の効果を奏する。
本発明のＳｉＧｅ膜の形成方法によれば、バッファ形成
工程において、第１のＳｉ(1-x)Ｇｅx膜を０．５ｎｍ以
上５ｎｍ以下の厚さ範囲で成膜するので、従来のように
１０〜５０ｎｍという厚いバッファ層を不要とし、非常
に薄い厚さのバッファ層で第２のＳｉＧｅ膜の不連続化
（膜荒れ）を改善し、抵抗も大幅に低抵抗化させること
ができ、絶縁膜上のＳｉＧｅ膜を種々のデバイスにおけ
る低抵抗な配線や電極として用いることが可能になる。According to the present invention, the following effects can be obtained.
According to the method for forming the SiGe film of the present invention, in the buffer forming step, since the first Si (1-x) Ge x film is formed at 5nm less thickness range of 0.5 nm, as in the prior art Eliminating the need for a thick buffer layer of 10 to 50 nm, improving the discontinuity (film roughness) of the second SiGe film with a very thin buffer layer, and greatly reducing the resistance can be achieved. The SiGe film on the film can be used as low-resistance wirings and electrodes in various devices.
【００４０】また、本発明のヘテロ接合トランジスタの
製造方法及びヘテロ接合トランジスタによれば、第１の
Ｓｉ(1-x)Ｇｅx膜（０≦ｘ＜０．０５）上に第２のＳｉ
(1-y )Ｇｅy膜（０．０５≦ｙ＜１）が形成され、第１の
Ｓｉ(1-x)Ｇｅx膜が０．５ｎｍ以上５ｎｍ以下の厚さで
あるので、絶縁膜上に膜荒れが抑制されたＳｉＧｅ膜が
得られ、薄いバッファ層厚にもかかわらず、低抵抗ベー
ス引き出し線として使用し得る膜を得ることができる。
この結果、ＳｉＧｅベース領域を厚いバッファ層無しで
作製することができるようになり、非選択エピタキシャ
ル成長によって、より高速な動作が可能なＳｉＧｅ−Ｈ
ＢＴを実現することができる。Further, according to the manufacturing method and heterozygous transistor heterojunction transistor of the present invention, the first Si (1-x) Ge x layer (0 ≦ x <0.05) second Si on
(1-y) Ge y layer (0.05 ≦ y <1) is formed, the first Si (1-x) Ge x layer is less than the thickness of 5nm or 0.5 nm, the insulating film Thus, a SiGe film with reduced film roughness can be obtained, and a film that can be used as a low-resistance base lead line despite a small buffer layer thickness can be obtained.
As a result, a SiGe base region can be manufactured without a thick buffer layer, and non-selective epitaxial growth enables higher-speed operation of SiGe-H.
BT can be realized.
【図１】 本発明に係るＳｉＧｅ膜の形成方法とヘテロ
接合トランジスタの製造方法、及びヘテロ接合バイポー
ラトランジスタの一実施形態におけるＨＢＴを示す概略
的な断面図である。FIG. 1 is a schematic cross-sectional view showing an HBT in one embodiment of a method for forming a SiGe film, a method for manufacturing a heterojunction transistor, and a heterojunction bipolar transistor according to the present invention.
【図２】 本発明に係るＳｉＧｅ膜の形成方法とヘテロ
接合トランジスタの製造方法、及びヘテロ接合バイポー
ラトランジスタの一実施形態において、ＨＢＴの第２の
ＳｉＧｅ膜形成までの製造プロセスを工程順に示す断面
図である。FIG. 2 is a cross-sectional view showing a manufacturing process up to the formation of a second SiGe film of an HBT in an embodiment of a method for forming a SiGe film, a method for manufacturing a heterojunction transistor, and a heterojunction bipolar transistor according to an embodiment of the present invention. It is.
【図３】 本発明に係るＳｉＧｅ膜の形成方法とヘテロ
接合トランジスタの製造方法、及びヘテロ接合バイポー
ラトランジスタの一実施形態において、ＨＢＴの第２の
ＳｉＧｅ膜形成後から各電極形成までの製造プロセスを
工程順に示す断面図である。FIG. 3 is a diagram illustrating a method of forming a SiGe film, a method of manufacturing a heterojunction transistor, and a heterojunction bipolar transistor according to an embodiment of the present invention. It is sectional drawing shown in order of a process.
【図４】 本発明に係るＳｉＧｅ膜の形成方法とヘテロ
接合トランジスタの製造方法、及びヘテロ接合バイポー
ラトランジスタの一実施形態において、ＨＢＴの第２の
ＳｉＧｅ膜の成膜状態を示すＳＥＭ写真である。FIG. 4 is an SEM photograph showing a state of forming a second SiGe film of an HBT in one embodiment of the method for forming a SiGe film, the method for manufacturing a heterojunction transistor, and the embodiment of the heterojunction bipolar transistor according to the present invention.
【図５】 ＳｉＯ2上に形成したＧｅ組成比０．０４の
ＳｉＧｅ膜の成膜状態を示すＳＥＭ写真である。FIG. 5 is an SEM photograph showing a film formation state of a SiGe film having a Ge composition ratio of 0.04 formed on SiO 2 .
【図６】 ＳｉＯ2上に形成したＧｅ組成比０．１３の
ＳｉＧｅ膜の成膜状態を示すＳＥＭ写真である。FIG. 6 is an SEM photograph showing a film formation state of a SiGe film having a Ge composition ratio of 0.13 formed on SiO 2 .
【図７】 ＳｉＯ2上に形成したＧｅ組成比０．３０の
ＳｉＧｅ膜の成膜状態を示すＳＥＭ写真である。FIG. 7 is an SEM photograph showing a film formation state of a SiGe film having a Ge composition ratio of 0.30 formed on SiO 2 .
【図８】 バッファ層の層厚を０〜５ｎｍまで変えた場
合のＳｉＧｅ膜のシート抵抗を示すグラフである。FIG. 8 is a graph showing the sheet resistance of the SiGe film when the thickness of the buffer layer is changed from 0 to 5 nm.
１ ｐ型シリコンウェーハ（Ｓｉ基板） ４ 第１のコレクタウェル（コレクタ領域） ５ 第２のコレクタウェル（コレクタ領域） ６ 第１のＳｉＯ2層（絶縁膜） ７ ベース窓部（窓部） ８ ＳｉＧｅ膜 ９ 第１のＳｉ(1-x)Ｇｅx膜 １０ 第２のＳｉ(1-y)Ｇｅy膜 １１ ベース領域 １２ ベース引き出し線（引き出し線） １６ エミッタ領域 ２０ ベース電極Reference Signs List 1 p-type silicon wafer (Si substrate) 4 first collector well (collector region) 5 second collector well (collector region) 6 first SiO 2 layer (insulating film) 7 base window (window) 8 SiGe Film 9 First Si (1-x) Ge x film 10 Second Si (1-y) Ge y film 11 Base region 12 Base lead line (lead line) 16 Emitter region 20 Base electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/165 (72)発明者 水嶋 一樹 埼玉県大宮市北袋町１丁目297番地 三菱 マテリアル株式会社総合研究所内 Ｆターム(参考） 4M104 AA01 AA07 BB36 BB38 CC05 DD43 FF13 HH16 5F003 BB00 BB02 BB04 BB05 BB07 BB08 BB90 BC08 BE08 BF06 BH18 BH99 BM01 BP31 BP33 BP94 BP97 5F033 HH03 LL09 MM05 PP03 PP09 VV06 WW02 WW04 WW05 XX10 5F045 AA06 AB01 AC01 AE15 AE17 AE19 AE21 AE23 AE25 AE27 AE29 AE30 AF08 CA02 DA53 DA57 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 29/165 (72) Inventor Kazuki 1-297 Kitabukuro-cho, Omiya-shi, Saitama Mitsubishi Materials Corporation In-house F-term (reference) 4M104 AA01 AA07 BB36 BB38 CC05 DD43 FF13 HH16 5F003 BB00 BB02 BB04 BB05 BB07 BB08 BB90 BC08 BE08 BF06 BH18 BH99 BM01 BP31 BP33 BP94 BP97 5F03 BB09 BB09 BB09 BB09 BB09 BB09 BB09 BB09 AE19 AE21 AE23 AE25 AE27 AE29 AE30 AF08 CA02 DA53 DA57
Claims (6)
あって、 前記絶縁膜上に第１のＳｉ(1-x)Ｇｅx膜（０≦ｘ＜０．
０５）を形成するバッファ形成工程と、 前記第１のＳｉ(1-x)Ｇｅx膜上に第２のＳｉ(1-y)Ｇｅy
膜（０．０５≦ｙ＜１）を形成する主膜形成工程とを備
え、 前記バッファ形成工程は、前記第１のＳｉ(1-x)Ｇｅx膜
を０．５ｎｍ以上５ｎｍ以下の厚さ範囲で成膜すること
を特徴とするＳｉＧｅ膜の形成方法。1. A method of forming a SiGe layer on the insulating film, the first Si (1-x) on the insulating film Ge x layer (0 ≦ x <0.
05) forming a buffer, and forming a second Si (1-y) Ge y on the first Si (1-x) Ge x film.
A main film forming step of forming a film (0.05 ≦ y <1), wherein the buffer forming step includes forming the first Si (1-x) Ge x film to have a thickness of 0.5 nm or more and 5 nm or less. A method for forming a SiGe film, wherein the film is formed within a range.
であって、 少なくとも前記第２のＳｉ(1-y)Ｇｅy膜を、０．１３３
Ｐａ以上１．３３×１０4Ｐａ以下の圧力範囲の減圧Ｃ
ＶＤ法により成膜することを特徴とするＳｉＧｅ膜の形
成方法。2. The method for forming a SiGe film according to claim 1, wherein at least the second Si (1-y) Ge y film is 0.133.
Decompression C in a pressure range of not less than Pa and not more than 1.33 × 10 4 Pa
A method for forming a SiGe film, comprising forming a film by a VD method.
合トランジスタを製造する方法であって、 コレクタ領域が形成されたＳｉ基板上に絶縁膜を形成す
る工程と、 前記絶縁膜の一部に前記コレクタ領域に通じる窓部を形
成する工程と、 前記窓部上及び前記絶縁膜上にＳｉＧｅ膜を非選択的に
形成し窓部上に前記ベース領域を形成すると共に前記絶
縁膜上にベース電極までの引き出し線に供される領域を
形成するＳｉＧｅ膜形成工程と、 前記ベース領域上にＳｉのエミッタ領域を形成する工程
とを備え、 前記ＳｉＧｅ膜形成工程は、前記ＳｉＧｅ膜を請求項１
又は２に記載のＳｉＧｅ膜の形成方法により形成するこ
とを特徴とするヘテロ接合トランジスタの製造方法。3. A method of manufacturing a hetero-junction transistor having a SiGe base region, comprising: forming an insulating film on a Si substrate on which a collector region is formed; and forming the collector region on a part of the insulating film. Forming a window portion that leads to the above, forming a SiGe film on the window portion and the insulating film in a non-selective manner, forming the base region on the window portion, and leading to a base electrode on the insulating film. 2. An SiGe film forming step of forming a region to be used for a line, and a step of forming a Si emitter region on the base region, wherein the SiGe film forming step includes forming the SiGe film on the base region.
Or a method for manufacturing a heterojunction transistor, wherein the method is formed by the method for forming a SiGe film according to 2.
タを製造する方法において、 前記ＳｉＧｅ膜形成工程は、前記第２のＳｉ(1-y)Ｇｅy
膜のＧｅ組成比ｙが０．０８≦ｙ≦０．３の範囲内であ
ることを特徴とするヘテロ接合トランジスタの製造方
法。4. The method for manufacturing a heterojunction transistor according to claim 3, wherein the step of forming the SiGe film includes the step of forming the second Si (1-y) Ge y.
A method for manufacturing a heterojunction transistor, wherein the Ge composition ratio y of the film is in the range of 0.08 ≦ y ≦ 0.3.
合トランジスタであって、 Ｓｉ基板に形成されたコレクタ領域と、 前記Ｓｉ基板上に形成され前記コレクタ領域に通じる窓
部を有した絶縁膜と、 前記窓部上に形成されＳｉＧｅ膜からなるベース領域
と、 前記絶縁膜上に形成され前記ベース領域に接続されたＳ
ｉＧｅ膜からなる引き出し線と、 前記ベース領域上に形成されたＳｉのエミッタ領域とを
備え、 少なくとも前記引き出し線は、前記絶縁膜上に形成され
た第１のＳｉ(1-x)Ｇｅx膜（０≦ｘ＜０．０５）と、 前記第１のＳｉ(1-x)Ｇｅx膜上に形成された第２のＳｉ
(1-y)Ｇｅy膜（０．０５≦ｙ＜１）とを備え、 前記第１のＳｉ(1-x)Ｇｅx膜は、０．５ｎｍ以上５ｎｍ
以下の厚さであることを特徴とするヘテロ接合トランジ
スタ。5. A heterojunction transistor having a SiGe base region, comprising: a collector region formed on a Si substrate; an insulating film formed on the Si substrate and having a window communicating with the collector region; A base region formed on the window portion and formed of a SiGe film; and a S region formed on the insulating film and connected to the base region.
a lead line made of an iGe film; and an emitter region of Si formed on the base region. At least the lead line is a first Si (1-x) Ge x film formed on the insulating film. (0 ≦ x <0.05); and a second Si formed on the first Si (1-x) Ge x film.
(1-y) Ge y film (0.05 ≦ y <1), wherein the first Si (1-x) Ge x film is 0.5 nm or more and 5 nm or more.
A heterojunction transistor having the following thickness.
タにおいて、 前記第２のＳｉ(1-y)Ｇｅy膜は、Ｇｅ組成比ｙが０．０
８≦ｙ≦０．３の範囲内であることを特徴とするヘテロ
接合トランジスタ。6. The heterojunction transistor according to claim 5, wherein said second Si (1-y) Ge y film has a Ge composition ratio y of 0.0.
A heterojunction transistor characterized by the range of 8 ≦ y ≦ 0.3.
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| US6737670B2 (en) | 2000-08-16 | 2004-05-18 | Massachusetts Institute Of Technology | Semiconductor substrate structure |
| US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
| KR100849835B1 (en) * | 2000-12-20 | 2008-08-01 | 소니 가부시끼 가이샤 | Vapor growth method, semiconductor producing method, and production method for semiconductor device |
| WO2002050880A1 (en) * | 2000-12-20 | 2002-06-27 | Sony Corporation | Vapor growth method, semiconductor producing method, and production method for semiconductor device |
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| US6730551B2 (en) | 2001-08-06 | 2004-05-04 | Massachusetts Institute Of Technology | Formation of planar strained layers |
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| US7138649B2 (en) | 2001-08-09 | 2006-11-21 | Amberwave Systems Corporation | Dual-channel CMOS transistors with differentially strained channels |
| US7776697B2 (en) | 2001-09-21 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
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| US7138310B2 (en) | 2002-06-07 | 2006-11-21 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
| US7838392B2 (en) | 2002-06-07 | 2010-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming III-V semiconductor device structures |
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| US7829442B2 (en) | 2002-08-23 | 2010-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor heterostructures having reduced dislocation pile-ups and related methods |
| JP4711827B2 (en) * | 2003-07-11 | 2011-06-29 | パナソニック株式会社 | Hetero bipolar transistor and manufacturing method thereof |
| WO2005006444A1 (en) * | 2003-07-11 | 2005-01-20 | Matsushita Electric Industrial Co., Ltd. | Heterojunction bipolar transistor and method for manufacturing same |
| JPWO2005006444A1 (en) * | 2003-07-11 | 2006-08-24 | 松下電器産業株式会社 | Hetero bipolar transistor and manufacturing method thereof |
| US7719031B2 (en) | 2003-07-11 | 2010-05-18 | Panasonic Corporation | Heterojunction biploar transistor and method for manufacturing same |
| US8183627B2 (en) | 2004-12-01 | 2012-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid fin field-effect transistor structures and related methods |
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