JP2001319470A - Fifo circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a FIFO circuit for which miniaturization can be performed by sharing the FIFO of a plurality of data paths and the data transfer efficiency at the time of sharing can be enhanced. SOLUTION: The FIFO of M pieces of data paths are shared by a single FIFO section 2, and the FIFO section 2 is divided into N pieces of FIFO 2-1 to 2-N having comparatively small capacity. FIFO capacity for every data path is changed to an arbitrary capacity by input selectors 1-1 to 1-N for each FIFO 2-1 to 2-N, output selectors 3-1 to 3-M for each data path, pointers for FIFO 6-1 to 6-M for every data path, and a FIFO capacity setting register 40. Miniaturization of the FIFO circuit and improvement of data transfer efficiency can be achieved by setting FIFO capacity in accordance with the data transfer status of each data path to each data path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO circuit, and particularly to a FIFO (First In First Ou) used in a computer device or other electronic devices.
t) circuit.

[0002]

2. Description of the Related Art When performing read or write data transfer from a certain device to a certain device (or a certain module to a certain module), the transfer capability of a bus (or port) connecting the devices (or between the modules) is effective. For this purpose, a method is widely used in which each data path has an individual FIFO and collectively transfers data during a usable period of a bus (or port).

There is also known a technique such as a serial data transmission / reception circuit which uses a transmission FIFO and a reception FIFO in a time-division manner to achieve sharing, thereby reducing the circuit scale. Regarding this serial data transmission / reception circuit,
No. 066243.

[0004]

In the conventional data transfer method described above, when trying to maximize the transfer capability, it is necessary to have a separate FIFO for each transfer type, so that the transfer capability of the data transfer is maximized. However, there is a problem that the circuit scale becomes large when trying to extract the maximum.

[0005] When the transmission FIFO and the reception FIFO are used in a time-division manner for sharing, the FIFO is used.
Since O is used in a time-sharing manner, even if a request for data transfer in a direction different from the current data transfer occurs, for example, even if only a part of the FIFO is used for the current data transfer, the current data transfer is not performed. Since the shared FIFO cannot be used until it is completely finished,
When the FIFO is shared by time sharing, there is a problem that its performance cannot be obtained.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems, and to reduce the size by sharing the FIFO of a plurality of data paths and improve the data transfer efficiency when sharing the FIFO. It is to provide a circuit.

[0007]

SUMMARY OF THE INVENTION A FIFO circuit according to the present invention comprises a FIFO (FiFi) shared by a plurality of data paths.
A plurality of FIFOs obtained by dividing an rst in first out (e.g., first in first out) section into equal capacities, and means for varying the FIFO capacity of each data path in units of the capacities of the plurality of FIFOs are provided.

Another FIFO circuit according to the present invention comprises a plurality of relatively small FIFOs (First I / O) having the same capacity.
n First Out), an input selector for selecting one from a plurality of data paths for each FIFO, an output selector for selecting one from the data outputs of the plurality of FIFOs for each data path, Corresponding FIF
A pointer for designating a write position and a read position for each O, and an FI for setting a FIFO capacity of each data path.
A FO capacity setting register, wherein a combination of the plurality of FIFOs, a selection signal of the input selector, a selection signal of the output selector, and a depth of the pointer are moved according to a setting value of the FIFO capacity setting register. Each data path is configured to realize an arbitrary capacity by changing the data path.

That is, the FIFO circuit of the present invention shares the FIFOs of a plurality of data paths,
O is divided into relatively small-sized FIFOs having the same capacity, and the F of each data path is determined in units of the capacity of the divided FIFO.
The IFO capacity is made variable.

More specifically, the FIFO circuit of the present invention comprises:
FIFO unit with N (N is a positive integer) small-capacity FIFO units
And the FIFO control unit sends a FI
A FIFO write signal and a pointer for determining a write position are output to perform a write operation to each FIFO, and a FIFO read signal and a pointer for determining an output position are output from the FIFO control unit to each FIFO, and each FIFO is output. Is performing a data read operation.

Each FIFO has M (M is a positive integer, M <
An input selector for selecting one path from the N) data paths is connected for every N FIFOs. Each FIF
As for the output of O, an output selector for selecting one of the outputs of N FIFOs is connected to each data path. Also, M
The FIFO control unit sets the depth (that is, the capacity) of the FIFO for each data path in the pointer of each data path according to the setting value of the FIFO capacity setting register that determines the FIFO capacity for each data path. By incorporating such means in the FIFO circuit, the FIFO of each data path
Can be obtained in units of FIFO capacity obtained by dividing the capacity of N into N pieces.

As described above, since one FIFO is shared by a plurality of data paths, it is possible to reduce the circuit scale as compared with having individual FIFOs. In addition, since the capacity of the FIFO allocated to each data path can be changed, by changing the capacity of the FIFO according to the data transfer amount of each data path, the utilization efficiency of the entire FIFO can be improved. Transfer efficiency is improved.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a FIFO circuit according to an embodiment of the present invention. In FIG. 1, a FIFO circuit according to an embodiment of the present invention includes an input selector unit 1, a FIFO unit 2, and an output selector unit 3.
, FIFO capacity setting register 4, FIFO control unit 5
And a pointer unit 6.

N input selectors 1 (N is a positive integer)
Of input selectors 1-1 to 1-N.
Select one of input,.
Output to IFO unit 2.

The FIFO unit 2 includes N small-capacity FIFO2s.
-1 to 2-N. The output selector unit 3 includes M output selectors 3-1 to M (M is a positive integer, M <N).
3-M, and the output selectors 3-1 to 3-M select one of the outputs of the FIFOs 2-1 to 2-N to output data 1, data 2,. Output the output.

The FIFO capacity setting register 4 inputs the setting data and the write timing signal, and outputs the written set value to the FIFO control unit 5. The FIFO control unit 5
.., FIFOON write signal, FIFO1 write signal, FIFO2 write signal,..., FIFOON write signal, FIFO1 write signal, FIFO2 write signal
Read signal and FIFO1 status signal, F
.., And a FIFOON status signal, and outputs setting data to the pointer unit 6.

The pointer section 6 is a FIFO pointer 6-1.
6-M, and FIFO pointers 6-1 to 6
-M is composed of write pointers 61-1 to 61-M and read pointers 62-1 to 62-M, respectively.

The FIFO unit 1 includes N small-capacity FIFOs 1
-1 to 1-N. Each FIFO1-1-1
-N performs a write operation when a FIFO write signal and the outputs of the write pointers 61-1 to 61-M for determining a write position are input from the FIFO control unit 5.

Each of the FIFOs 1-1 to 1-N is a FIFO.
When the FIFO control signal and the outputs of the read pointers 62-1 to 62-M for determining the output position are input from the O control unit 5, the data read operation is performed.

The input of each of the FIFOs 1-1 to 1-N is connected to the input selectors 1-1 to 1-N of the input selector 1 for selecting one of the M data paths. The outputs of the FIFOs 1-1 to 1-N are output selectors 3-1 to 3- for selecting one of the outputs.
M connects to each data path.

In accordance with the value set in the FIFO capacity setting register 4 for determining the FIFO capacity for each of the M data paths, the FIFO control unit 5 sets the FIFO capacity for each data path.
The depths (that is, capacities) of 1-1 to 1-N are set in FIFO pointers 6-1 to 6-M of each data path.

By incorporating the above means into the FIFO circuit, it is possible to obtain an arbitrary capacity in units of the capacity of FIFOs 1-1 to 1-N obtained by dividing the capacity of the FIFO unit 1 of each data path into N pieces. it can.

In the present invention, one FIFO unit 1 is shared by a plurality of data paths.
The circuit scale can be made smaller than that having. Further, since the capacity of the FIFO allocated to each data path can be changed, the use efficiency of the entire FIFO can be improved by changing the capacity of the FIFO according to the data transfer amount of each data path. Can be improved.

FIG. 2 is a block diagram showing a configuration of a FIFO circuit according to one embodiment of the present invention. In FIG. 2, FI
The FO circuit 7 includes an input selector section 10 and a FIFO section 20.
, An output selector section 30, a FIFO capacity setting register 40, a FIFO control section 50, and a pointer section 60.

The input selector section 10 includes input selectors 11 to
The input selectors 11 to 14 respectively select one of a CPU write input, a CPU read input, and a display read input and output the selected one to the FIFO unit 20.

The FIFO unit 20 comprises four small-capacity FIFOs.
21 to 24. The output selector unit 30 includes output selectors 31 to 33, and the output selector 3
1 to 33 select one of the outputs of the FIFOs 21 to 24 and output a CPU write output, a CPU read output, and a display read output.

The FIFO capacity setting register 40 inputs the setting data and the write timing signal, and outputs the written set value to the FIFO control unit 50. FIFO control unit 5
0 is a set value from the FIFO capacity setting register 40, an output of the pointer unit 60, a CPU write FIFO write signal, a CPU read FIFO write signal, and a display read FI.
FO write signal, CPU write FIFO read signal,
CPU read FIFO read signal, display read FIFO
A read signal is input, a CPU write FIFO status signal, a CPU read FIFO status signal, and a display read FIFO status signal are output, and setting data for the pointer unit 60 is output.

The pointer section 60 includes a FIFO pointer 61.
To 63, and the FIFO pointers 61 to 63 are composed of write pointers 611, 621, 631 and read pointers 612, 622, 632, respectively.

FIG. 3 is a diagram showing a computer system using the FIFO circuit 7 of FIG. Referring to FIG. 3, a computer system according to an embodiment of the present invention includes a CPU (central processing unit) 100, a frame buffer 300 for storing display data, a display device 400 for displaying data stored in the frame buffer 300, and a display. Circuit 200
It is composed of

The display circuit 200 includes a CPU I / F 201 serving as an entrance of a data read or data write command from the CPU 100 to the frame buffer 300, a display control circuit 203 for transferring data of the frame buffer 300 to the display device 400, and a CPU I / F 201. And a memory control circuit 202 for actually accessing the frame buffer 300 in response to an instruction to read data from or write data to the frame buffer 300 and a display data read instruction from the display control circuit 203, and the FIFO circuit 7 described above. Have been.

The configuration of the FIFO circuit 7 is as described above. In this embodiment, the FIFOs are divided into four relatively small-capacity FIFO units 21 to 24 each having the same capacity, and each of the FIFOs 21 to 24 is provided with a FIFO unit. Enter 3
An input selector unit 10 including input selectors 11 to 14 for selecting one data path from one data path;
An output selector unit 30 including output selectors 31 to 34 for selecting one data output from the outputs of the four FIFOs 21 to 24 for the output data from the FOs 21 to 24 for every three data paths, and a FIFO capacity of the three data paths. , A pointer unit 60 including three data path FIFO pointers 61 to 63, and write pointers 611, 621, 631 indicating write positions of the FIFO pointers 61 to 63.
Read pointers 612, 622, and 632 indicating the read positions of the FIFO pointers 61 to 63;
The input selector sections 10 and F
It has an FIFO section 20, an output selector section 30, and a FIFO control section 50 for controlling the pointer section 60.

In this embodiment, the data width is all 32 bits, the depth of the FIFO circuit 7 is 32, and the divided F
If the number of IFOs 21 to 24 is 4, the divided FIFOs
The depth of O21 to O24 is 8.

Accesses to the frame buffer 300 are of the following three types. One is a CP that performs a data write operation on the frame buffer 300 of the CPU 100.
U-light. The second is a CPU read for reading data from the frame buffer 300 of the CPU 100. The third is a display read for performing an operation of reading display data from the frame buffer 300 for displaying the display data. Therefore, FIFO7 contains CP
There are three data paths: U write, CPU read, and display read.

In the CPU write operation, when the CPU 100 writes data to the frame buffer 300, the data is stored in the FIFO 7 through the CPU I / F 201 in the display circuit 200, and the address of the frame buffer 300 and the timing signal are stored in the memory control. Generated in circuit 202 and written to frame buffer 300.

In the CPU read operation, when the CPU 100 reads data from the frame buffer 300, an address and a timing signal of the frame buffer 300 are generated in the memory control circuit 202 through the CPU I / F 201 in the display circuit 200. Frame buffer 30
0 is accessed and the read data is temporarily stored in the FIFO 7 and returned to the CPU 100 through the CPII / F 201.

In the display read operation, when the display circuit 200 is in the display period, the data range to be read is instructed to the memory control circuit 202, and data is read from the frame buffer 300 according to the instruction. The read data is temporarily stored in the FIFO 7, and the display circuit 200 sequentially reads the display data.

The display system of the present embodiment is roughly divided into the following two types of states. This indicates the state of the minimum necessary FIFO capacity of the FIFO 7. One is the display device 4
00, a display period during which display data stored in the frame buffer 300 is sequentially displayed;
It is divided into a non-display period in which display data is not displayed.

During the display period, it is necessary to always read out the display data stored in the frame buffer 300 at regular intervals. Therefore, the data transfer efficiency of the write operation and the read operation from CPU 100 decreases. Since there is no need to transfer the display data stored in the frame buffer 300 during the non-display period, the display circuit 200 does not need to perform a data read operation on the frame buffer 300. Therefore, the data transfer efficiency of the write operation and the read operation from the CPU 100 is maximized.

For example, in the display period and the non-display period, the following FIFO capacity is set. During the display period, CPU access is restricted due to display read.
Therefore, even if the FIFO capacity is increased, the performance cannot be improved.

However, if the CPU access is not accepted at all, the performance is degraded. Therefore, it is sufficient if there is a FIFO capacity between the display lead and the display lead enough to allow the CPU access. Therefore, the depth of the FIFO of the data path of the CPU write is set to 8, the depth of the FIFO of the data path of the CPU read is set to 8, and the depth of the FIFO of the data path of the display read is set to 16.

Since the display read is not performed during the non-display period, the FIFO is not required in the data path of the display read. Therefore, the depth of the FIFO in the data path of the CPU write is set to 1
6, the depth of the FIFO in the data path of the CPU lead is 16, and the depth of the FIFO in the data path of the display lead is 0.

During the non-display period, the FIFO control unit 50 sets the FI
The input selector unit 10, the FIFO unit 20, the output selector 30, and the pointer unit 60 are controlled based on the set value of the FO capacity setting register 40 to configure the FIFO of each data path.

The CPU write data path includes input selectors 11 and 12, FIFOs 21 and 22, and output selector 31.
It is constituted by and. Input selectors 11 and 12 are FI
FIFO capacity setting register 40 by FO control unit 50
The CPU light input is selected from the set values of. FIFO
Reference numerals 21 and 22 denote the FIFO capacity depth 16 from the setting value of the FIFO capacity setting register 40 by the FIFO control unit 50.
Is selected to achieve

When data is written, the data is written at the location indicated by the write pointer 611, and at the time of reading, the data at the location indicated by the read pointer 612 is output by the FIFOs 21 and 22. The output selector 31 selects the FIFOs 21 and 22 indicated by the read pointer 612.

The data path of the CPU read includes input selectors 13 and 14, FIFOs 23 and 24, and output selector 32.
It is constituted by and. Input selectors 13 and 14 are FI
FIFO capacity setting register 40 by FO control unit 50
The CPU read input is selected from the set values of. FIFO
Reference numerals 23 and 24 denote the FIFO capacity depth 16 from the set value of the FIFO capacity setting register 40 by the FIFO control unit 50.
Is selected to achieve

When writing data, the data is written at the location indicated by the write pointer 621, and at the time of reading, the FIFO 23 and 24 output the data at the location indicated by the read pointer 622. The output selector 32 selects the FIFOs 23 and 24 indicated by the read pointer 622.

No FIFO is assigned to the display lead. During the display period, the FIFO controller 50 controls the input selector 1 based on the setting value of the FIFO capacity setting register 40.
0, FIFO unit 20, output selector 30, pointer unit 6
0 to configure a FIFO for each data path.

The data path of the CPU write includes an input selector 11, a FIFO 21, and an output selector 31. The input selector 11 allows the FIFO control unit 50 to select a CPU write input from the set value of the FIFO capacity setting register 40. FIFO21 is also FIFO
The control unit 50 selects from the set value of the FIFO capacity setting register 40 to realize the FIFO capacity depth 8.

When data is written, the data is written at the location indicated by the write pointer 611, and at the time of reading, the data at the location indicated by the read pointer 612 is output by the FIFO 21. The output selector 31 selects the FIFO 21 indicated by the read pointer 612.

The data path of the CPU read is constituted by the input selector 12, the FIFO 22, and the output selector 32. The input selector 12 causes the FIFO control unit 50 to select a CPU read input from the set value of the FIFO capacity setting register 40. FIFO22 is also FIFO
The control unit 50 selects from the set value of the FIFO capacity setting register 40 to realize the FIFO capacity depth 8.

When writing data, the data is written at the location indicated by the write pointer 621, and at the time of reading, the FIFO 22 outputs the data at the location indicated by the read pointer 622. The output selector 32 selects the FIFO 22 indicated by the read pointer 622.

The data path of the display lead is input selector 1
3 and 14, FIFOs 23 and 24, and an output selector 33. Input selectors 13 and 14 are FIFO
The control unit 50 allows the CPU read input to be selected from the set value of the FIFO capacity setting register 40. FIFO2
3 and 24 are also selected by the FIFO control unit 50 from the set value of the FIFO capacity setting register 40 to realize the FIFO capacity depth 16.

When data is written, the data is written at the location indicated by the write pointer 631, and at the time of reading, the data at the location indicated by the read pointer 632 is output by the FIFO 22. The output selector 33 selects the FIFO 23 or the FIFO 24 indicated by the read pointer 632.

As described above, by changing the capacity of the FIFO according to the data transfer amount of each data path, the utilization efficiency of the entire FIFO can be improved, so that the data transfer efficiency can be improved and the common use of the FIFO can be improved. The size can be reduced.

As described above, the FIFO of a plurality of data paths
Is shared by one FIFO, the circuit size can be reduced. Also, by changing the FIFO capacity according to the data transfer status of each data path, a larger FIFO capacity is set for a frequently used data path, and a smaller FIFO capacity is set for a less frequently used data path. Thus, the efficiency of data transfer can be improved.

[0056]

As described above, according to the present invention, the FIFO shared by a plurality of data paths is divided into a plurality of FIFOs having the same capacity, and each data path is divided into a plurality of FIFO units. By making the FIFO capacity variable, there is an effect that it is possible to reduce the size by sharing the FIFO of a plurality of data paths and to improve the data transfer efficiency when sharing the FIFO.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a FIFO circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a FIFO circuit according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating a computer system using the FIFO circuit of FIG. 2;

[Explanation of symbols]

1, 10 input selector section 1-1 to 1-N, 11 to 14 input selector 2, 20 FIFO section 2-1 to 2-N, 21 to 24 FIFO 3, 30 output selector section 3-1 to 3-M, 31 to 33 Output selector 4, 40 FIFO capacity setting register 5, 50 FIFO control unit 6, 60 Pointer unit 6-1 to 6-M, 61 to 63 FIFO pointer 7 FIFO circuit 61-1 to 61-M, 611, 621, 631 write pointer 62-1 to 62-M, 612, 622, 632 read pointer 100 CPU 200 display circuit 201 CPU I / F 202 memory control circuit 203 display control circuit 300 frame buffer 400 display device

Claims (6)

[Claims] 1. An FIF shared by a plurality of data paths
A plurality of FIFOs obtained by dividing an O (First In First Out) portion into equal capacities;
Means for varying the FIFO capacity of each data path in units of IFO capacity. 2. The means for varying the FIFO capacity of each data path is provided corresponding to each of the plurality of FIFOs, and selects an input to a corresponding FIFO from among signals from each of the data paths. 2. The FIFO circuit according to claim 1, further comprising: an input selector; and an output selector for selecting outputs of the plurality of FIFOs and outputting the selected outputs to the respective data paths. 3. An FIF assigned to each data path
3. An F according to claim 1, further comprising a pointer for generating a write position and a read position for each O.
IFO circuit. 4. A combination of the FIFO, a selection signal to the input selector, a selection signal to the output selector, and a depth of the pointer are changed according to an external set value for setting the FIFO capacity. 4. The FI according to claim 3, further comprising control means for controlling the change.
FO circuit. 5. The control means outputs a FIFO write signal and a pointer for determining a write position to the plurality of FIFOs, performs a write operation to the plurality of FIFOs, and performs a write operation on the plurality of FIFOs. 5. The FIFO circuit according to claim 4, wherein a FIFO read signal and a pointer for determining an output position are output to perform a data read operation to said plurality of FIFOs. 6. A plurality of relatively small FIs having the same capacity.
FO (FirstIn First Out) and each F
An input selector for selecting one from a plurality of data paths for each FIFO, an output selector for selecting one from the data outputs of the plurality of FIFOs for each data path, and a write position for each FIFO corresponding to each data path A pointer for designating a read position, and a FIFO capacity setting register for setting a FIFO capacity of each data path. A combination of the plurality of FIFOs according to a set value of the FIFO capacity setting register; A FIFO circuit, wherein an arbitrary capacity is realized in each data path by dynamically changing a selection signal of a selector, a selection signal of the output selector, and a depth of the pointer.