JP2001312454A - Data processing system and control method of data processing system, and external storage device and control method of external storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform input and output processes of the same logical volume of an external storage device in parallel. SOLUTION: In a frame 500 used by a serial channel interface between an input/output channel part (CH) and a disk controller (DKC), the CH sets unique parallel access discrimination information 522b-1 managing the parallel operations of I/O's to VOLs having the same VOL address in a standby area 522b other than the VOL address 522a of the device address 522 of the frame 500 and sends the frame to the DKC, which receives the frame 500, records the parallel access discrimination information 522b-1 by allocating management information areas to each of the I/O processes from the VOL address 522a and parallel access discrimination information 522b-1, and informs the CH of the end by using the parallel access discrimination information 522b-1 to actualize parallel processes of the I/Os to the same VOL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing system and a control technique for the data processing system.
The present invention relates to a technology that is effective when applied to a data input / output control technology between a central processing unit of a mainframe system and peripheral devices such as an external storage device.

[0002]

2. Description of the Related Art A channel unit of a central processing unit in a mainframe data processing system is an industry standard channel unit for processing I / O such as a data transfer (READ / WRITE) request to a magnetic disk controller. And a frame determined by the serial channel interface of the magnetic disk controller.

In this case, even if the central processing unit issues a plurality of I / O processing requests for the same VOL, the control is controlled so that the channel unit does not simultaneously detect and simultaneously transmit and receive frames of the plurality of I / O processing. .

For this reason, a plurality of I
Of the I / O processing, the I / O processing that cannot be processed is in the processing waiting state in the channel unit, and a waiting time occurs, which is a cause of the performance degradation of the entire system.

In order to enable a plurality of I / O processes for the same VOL to be performed in parallel, US Pat. No. 5,530,897, “SYSTEM FOR DYN”
AMIC ASSOCIATION OF A VAR
ABLE NUMBEROF DEVICE ADD
LESS WITH INPUT / OUTPUTDEV
ICES TO ALLLOW INCREASED C
ONCURRENT REQUESTS FOR AC
CESS TO THE INPUT / OUTPUT
In DEVICES, a data processing system consisting of a central processing unit and a disk control unit requires
When queuing management of I / O processing is performed in the channel unit, I / O processing is normally assigned to a data structure called UCB in VOL units. If UCB is not used in VOL units but in UCB units in VOL units, A free UCB that is allocated and used as another VOL for each I / O processing unit is selected and allocated to the I / O processing, so that even if a processing request is for the same VOL, a plurality of UCBs are allocated and used. By doing so, it is proposed to realize simultaneous processing of a plurality of I / O processes.

[0006] Also, a plurality of I
In order to use another VOL number other than the actual VOL number, the binding command (BIN)
ADDRESS) is used to notify the magnetic disk controller using a special frame, and it is possible to issue I / O to an actual VOL and a virtual VOL at the same time. Has been proposed.

[0007]

The above-mentioned U.S. Pat.
In Japanese Patent No. 30,897, bindin is used to process I / O processing assigned to a plurality of UCBs to a plurality of VOLs.
The g command frame is notified to the magnetic disk controller to perform a plurality of I / O processes. If the VOL corresponding to the temporary VOL address to be duplicated is actually under the control of the magnetic disk controller, the VOL is Therefore, the temporary VOL address to be duplicated is usually the address of the unmounted VOL managed by the magnetic disk controller.

As a result, the number of VOLs mounted in a control unit (hereinafter, referred to as a CU) managed by the magnetic disk controller limits the provisional VOL address, and a plurality of I / O processes cannot always be realized. There is.

Further, since a binding command frame is required, useless access occurs. Further, the binding command frame allows the magnetic disk control device to use the original VOL and the binding command.
In order to recognize the combination of virtual VOLs that have been set, if the state is not matched with the central processing unit, data may be destroyed.

An object of the present invention is to provide a central processing unit and an external storage device without being restricted by the number of physical storage devices or peripheral devices constituting a peripheral device such as an external storage device, or by available addresses. It is an object of the present invention to provide a data processing system capable of realizing a plurality of input / output parallel operations with respect to the same logical volume, logical peripheral device, and the like, and a control technique therefor.

Another object of the present invention is to provide the same logical volume or logical peripheral between a central processing unit and a peripheral device such as an external storage device without causing useless access by issuing a special extra frame. It is an object of the present invention to provide a data processing system capable of realizing a plurality of input / output parallel operations on a device or the like and a control technique thereof.

Another object of the present invention is to eliminate the same data failure between a central processing unit and peripheral devices such as an external storage device due to inconsistency in recognition of logical volumes and logical peripheral devices. It is an object of the present invention to provide a data processing system capable of realizing a plurality of input / output parallel operations on a logical volume, a logical peripheral device, and the like, and a control technique thereof.

Another object of the present invention is to provide a data processing system capable of improving data input / output performance between a central processing unit and a peripheral device such as an external storage device, and a control technique thereof. It is in.

[0014]

SUMMARY OF THE INVENTION The present invention provides a central processing unit having an input / output channel unit for controlling the input and output of information to and from the outside, an external storage device comprising a storage control device and a storage device, The storage control device includes a channel interface that connects the input / output channel unit and the storage control device, and a frame used to transfer information between the input / output channel unit and the storage control device via the channel interface. In a data processing system that can accept access from the central processing unit in units of logical volumes or logical devices logically set for the device, a frame specifies any logical volume or logical device to be accessed First identification information to be input / output to / from the logical volume or the logical device. It is obtained by a configuration and a second identification information indicating the parallel operation of a plurality of access from the channel portion.

More specifically, as an example, an input / output channel unit for controlling data transfer (hereinafter referred to as a channel unit)
In a frame used for the serial channel interface between the central processing unit having the CPU and the magnetic disk controller, a logical device (hereinafter, referred to as VOL) managed by the central processing unit and the magnetic disk controller receives the V
In addition to the OL address, parallel access identification information (hereinafter, referred to as identification information) for managing the parallel operation of a plurality of I / Os is added, the frame is transferred from the channel unit, and the parallel operation of the plurality of I / Os for the same VOL is instructed. Things.

Further, in the data processing system,
In order to enable a parallel operation of a plurality of I / Os for the same VOL in the magnetic disk control device by the identification information, the management information area of an I / O processing unit for each VOL in the magnetic disk control device is set to the number of parallel operations. The identification information corresponding to the I / O process is added from the magnetic disk control device to the channel unit when the I / O process is completed, and the completion report is made.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing a configuration example of a mainframe computer system which is an example of a data processing system for implementing a control method of a data processing system according to an embodiment of the present invention.

The mainframe computer system according to the present embodiment includes a CPU 101 serving as a central processing unit, a disk control unit (DKC) 102, a disk drive unit (DKU) 103, and one or more units connecting the CPU 101 and the DKC 102. A plurality of cables 104 and DKC1
02 and one or a plurality of cables 105 connecting the DKU 103.

An access request from the CPU 101 to the DKU 103 via the DKC 102 is transmitted to a frame 500 illustrated in FIG.
It is executed by exchanging with the two.

The internal configuration of the CPU 101 is an arithmetic processing unit (IP) 11 that executes an operating system or the like.
1, a main storage unit (MS) 112 for storing the program, data processed by the program, etc., and an input / output unit for controlling data transfer with an external input / output device and controlling an interface with the input / output device. Output channel (CH)
113, and a system controller (SC) 114 for controlling data transfer between these units.

In the DKC 102, as an example, the CP
A channel port (PORT) 121 for controlling an interface with the input / output channel unit 113 of the U101, and a cache memory unit (CACH) for processing data at high speed.
E) 122, a control processor 123 for managing data in the DKC 102, a data transfer control unit 124 for controlling data transfer between these units, and control information for controlling I / O and managing data. Shared memory (S
M) 125. The DKU 103 includes a plurality of disk devices 131 for storing data.

The DKU 103 has a plurality of disk devices 1
A plurality of logical disk devices (logical volumes) on 31
(VOL) is logically constructed, and DK
Access to the DKU 103 via the C102 is executed by designating this logical volume (VOL).

FIG. 2 shows the CPU 101 of the mainframe computer system according to the present embodiment,
FIG. 2 is a conceptual diagram showing a configuration example of control information generated in an MS 112 to issue a plurality of I / Os to the I / O 02.

In the MS 112, UCBs (201, 202, 203, 204) for managing VOL management addresses and the like are provided.
And a free UCB that is used when executing a plurality of I / O processes and manages a free UCB that is currently unallocated.
An I / O channel 113 manages an I / O request when the I / O channel unit 113 executes I / O processing.
Q206, an IOSB 207 for passing channel program information and the like to the input / output channel unit 113, and a channel program 208 for executing I / O processing.

As the type of UCB, UCBs 203 and 204 for parallel access for realizing a plurality of I / O processes are provided for basic UCBs 201 and 202 existing for each VOL.
And free UCBs 252, 253 and 254. Basic UCBs 201 and 202, UCB 203 for concurrent access,
204 and the free UCBs 252 to 254 have the same structure. In FIG. 2, the basic UCB 201 of VOL address A and the basic UCB 202 of VOL address B
VOL address A has a UCB for concurrent access
Are connected to each other (UCBs 203 and 204 for concurrent access).

In the following, U based on the basic UCB 201
The structure of CB will be described.

VOL address 211, UC
UCB attribute flag 212 indicating the type of B (basic UCB, UCB for parallel access, free UCB), and IOQ 20 created for each input / output request in input / output channel unit 113
6, a UCB management flag 214 for managing I / O to the VOL, a next UCB address 215 connected to the concurrent access UCB 203, concurrent access identification information 216, a basic UCB 201 of the VOL
The basic UCB address 217 is returned.

The free UCB queue 205 stores the free UC
Unallocated free UCB from the start pointer 251 of B
252, 253 and 254 are connected in a queue structure. The free UCB is a state in which the concurrent access UCB is not allocated, and the concurrent UCB and the free UCB are not allocated.
The structure of the CB is, of course, the same. Free UC
The pointer for connecting B in a queue structure is UCB
Use the next UCB address in

The IOQ 206 has an IOSB address 261
The IOSB address 261 is set when a usable UCB is allocated. IOSB 207 contains channel program address 273, UCB used
UCB address 272 is stored. The channel program 208 includes a channel command word (CCW) 281 for implementing I / O processing.

FIG. 3 shows SM125 for realizing parallel processing of a plurality of I / Os at the time of I / O reception by DKC 102 of the mainframe computer system of the present embodiment.
FIG. 4 is a conceptual diagram showing an example of the configuration of control information set in the control information.

The SM 125 includes LDCBs 301 and 302 for managing VOL addresses and configuration information in VOL units.
JCB that manages the operation of I / O processing unit for each VOL
(303, 304, 305), unused JCB 362-3
There is a free JCB queue 306 that manages 64.

The LDCBs 301 and 302 include a VOL address 311, a JCB management flag 312 for managing the JCB connected to the LDCB, and basic JCBs 303 and 305.
JCB pointer address 313, and configuration information 314 for storing information on the configuration state of the VOL.

As types of JCB, LDCB 301, 3
Basic JCBs 303 and 30 that are always connected to one
5. The JCB 304 for concurrent access used to implement the parallel processing of a plurality of I / Os for each VOL, and the free JCBs 362, 363 connected to the free JCB queue 306 as the unassigned concurrent access JCB
364 are present. All types of JCB have the same structure.

In the following, based on the basic JCB 303, J
The structure of CB will be described. JCB has J for concurrent access
Next JCB pointer address 33 for connecting to CB
1. JCB attribute flag 33 for indicating the type of JCB
2. Concurrent access identification information 33 used during concurrent operation
3. An I / O processing area 334 for storing information in the frame 500 when the disk control device 102 receives the I / O, securing information necessary for the I / O processing,
Contains the pointer address to the LDCB that manages the
It consists of a B pointer address 335.

The free JCB queue 306 contains a free J
Unassigned free JCBs 362, 363, and 364 are connected in a queue structure from a JCB pointer 361 that points to the head of the CB.

FIG. 5 shows an example of a frame structure including parallel access identification information at the time of frame transfer in the serial channel interface between the input / output channel unit 113 and the disk controller 102 of the mainframe computer system of the present embodiment. It is a conceptual diagram.

The frame 500 transferred between the input / output channel unit 113 and the disk controller 102 according to the present embodiment can be largely divided into three parts, and a Link Header
(Link header 501), Information F
field (information field 502), Link Tra
iler (link trailer 503).

The Link Header 501 includes information indicating the beginning of a frame and path information used for transmission / reception, and the Link Trailer 503 includes information indicating the end of a frame and a redundancy check code. Info
operation Field 502 is device header 5
11 and a device information block 512 used for information transfer related to the CCW 281.

The device header 511 includes an information field identifier 521 (hereinafter, referred to as IFI), a device address 522, and a DHF field 523.
The device address 522 is 16-bit information. The upper 8 bits are the spare area 522b and the lower 8 bits are DK.
The VOL address 522a is a control unit (CU) unit managed by the C102.

In this embodiment, the parallel access identification information 216, 226, 236, 246 is stored when the upper 8-bit spare area 522b is transferred from the input / output channel unit 113 or the disk controller 102 to the frame. The same VO in the input / output channel unit 113 and the disk controller 102 by adding the parallel access identification information 522b-1 in the frame 500.
Implement parallel processing of multiple I / Os for L.

FIG. 4 shows an I / O sequence until the CPU 101 selects a basic UCB or a UCB for parallel access in the MS 112, generates a frame 500, and transfers the frame 500 to the DKC 102.
It is a flowchart which shows an example of O processing.

The input / output channel unit 113 includes, for example, VO
When an I / O processing request for the VOL with the L address = “A” is detected (Step 401), the IOQ 206 is obtained (Step 402), and the UCB specified in the IOSB 207 is acquired.
The UCB is specified from the address 272 (step 40).
3). The UCB determines whether the basic UCB 201 can be used (that is, there is currently no input / output processing for the target VOL) (step 404). If the basic UCB 201 is not used, the UCB management flag 214 stores the basic UC in the UCB management flag 214.
B. Put in use (step 410), basic UCB 20
1 is set (step 41).
6), an IOSB address 261 in the IOQ 206 is set (step 417), and the VOL address 211 set in the basic UCB 201 and the parallel access identification information 21 are set.
6 (step 418), the channel program 208 is obtained from the channel program address 273 stored in the IOSB 207, and the channel program 20
8 (step 419).
By specifying the OL address 211 and the parallel access identification information 216 in the frame 500 and executing the fetched CCW 281 (step 420), the frame is transmitted to the disk controller 102 by the conventional logic (step 421).

If the basic UCB 201 cannot be used (ie, if there is an input / output process currently being executed for the target VOL), the free UCB queue 205 is searched for free UCBs 252 to 254 (step 40).
5) If there are free UCBs 252 to 254, free UC
Take out UCB from B queue 205 (step 40)
6) The VOL address of the basic UCB 201 to be connected is stored in the obtained VOL address of the free UCB (step 407), and the basic UCB address 247 of the obtained UCB (for example, the concurrent access UCB 204) is stored in the basic UCB address 247.
The address of the CB 201 is set (step 408), and the UCB attribute flag 242 of the acquired UCB is set to the U
CB is set (step 409), an empty number of the parallel access identification information 216 is selected from the UCB management flag 214 in the basic UCB 201, and set as the parallel access identification information 246 of the acquired UCB (step 413).
The next UCB address 215 is traced from B201, and the obtained UCB address is set to the next UCB address 235 of the last UCB (the UCB 203 for parallel access) (step 4).
14), UCB management flag 214 in basic UCB 201
Is set to use UCB (step 415).
The IOQ address 243 in B is set (step 41).
6), the IOSB address 261 in the IOQ 206 is set (step 417), and the VOL address 24 set in the UCB (the acquired concurrent access UCB 204) is set.
1 and the concurrent access identification information 246 (step 4
18) The channel program 208 is obtained from the channel program address 273 stored in the IOSB 207, the CCW 281 is fetched from the channel program 208 (step 419), and the VOL address 241 and the parallel access identification information 246 are stored in the VOL in the frame 500.
C that is designated and taken as the parallel access identification information 522b-1 of the address 522a and the spare area 522b.
By executing CW 281 (step 420),
The frame 50 is stored in the disk controller 102 according to the conventional logic.
0 is transmitted (step 421).

If the basic UCB 201 cannot be used and there are free UCBs 252 to 254,
The queue 205 is searched (step 405), and the free U
If there are no CBs 252 to 254, the UCB management flag 21
4 is set to wait for UCB free (step 411), and IO
Q206 is released (step 412), and UC of the conventional logic is released.
Free UCBs 252 to 254
Occurs, or if the basic UCBs 201 and 202 become unused, I / O requests always remain, and
The process is restarted from the acquisition of 06 (step 402).

FIG. 6 shows a disk controller (DKC) 10 of the mainframe computer system according to the present embodiment.
7 is a flowchart of a process for realizing parallel processing of a plurality of I / Os upon receipt of a frame 500 in 2 and until reporting completion.

When the PORT 121 detects the reception of the initial frame of each I / O process (step 601), the control processor 123 performs a frame reception process (step 602), and obtains the VOL address 522a and the parallel access identification information 522b in the frame 500. 1 (step 60)
3).

Next, the VOL address (for example, VOL
From the LDCB 301 of the address = “A”), the basic JCB
The JCB management flag 312 determines whether the JCB management flag 312 is usable (step 604). If the basic JCB 303 is usable (that is, if the VOL with the VOL address = “A” is not currently accessed), the JCB management flag 312 is set to the basic JC.
B in use is set (step 605), and the basic JCB 30 is set.
3, the information acquired from the frame 500 in the parallel access identification information 333 (parallel access identification information 522b-1).
Is set (step 606), the frame 500 for performing the I / O processing is stored in the I / O processing area 334 (step 607), and the requested I / O processing is executed using the stored frame 500. (Step 608). It is determined whether the I / O processing is completed (step 609), and the reception of the related next frame (step 611) and the step 60 until there is no related succeeding frame.
7. When the step 608 is repeated and the processing is completed, the VOL address 522a and the parallel access identification information 522b-1 are designated and a completion report is sent to the input / output channel unit 113 of the CPU 101 (step 610). The process proceeds to the later conventional logic (step 619).

Also, in the judgment of step 604, the basic JCB
If 303 is unavailable (ie, there is an I / O process currently being executed for the target VOL), the free JC
It is determined whether there are free JCBs 362 to 364 in the B queue 306 (step 612). If there is a free JCB, the JCB is taken out from the free JCB queue 306 (step 6).
15), the acquired JCB (JCB30 for concurrent access)
4) (step 616), the JCB pointer address 313 of the LDCB 301, the next JCB pointer address 331 of the basic JCB 303, and the next connected JCB if any. Follow the pointer address,
Free J at the next JCB pointer address of the last JCB
The address of the JCB acquired from the CB queue 306 is set (step 617), and the JCB management flag 312 is set to use JCB for concurrent access (step 61).
8), information acquired from the frame 500 (parallel access identification information 5) is stored in the parallel access identification information 343 in the JCB.
22b-1) is set (step 606), and the frame 500 for performing I / O processing is stored in the I / O processing area 344.
(Step 607), and the I / O processing area 344
The requested I / O process is executed using the frame 500 stored in the file (step 608). It is determined whether the I / O processing is completed (step 609), and the reception of the related next frame (step 611) and the steps 607 and 60 until there is no related subsequent frame.
8 is repeated, and when the processing is completed, the VOL address 522a and the parallel access identification information 522b-1 are designated and the CPU
A completion report is sent to the input / output channel unit 113 of the PC 101 (step 610), and the process proceeds to the conventional logic after the completion report (step 619).

When the basic JCB 303 cannot be used, the free JCB 362 is added to the free JCB queue 306.
Is determined (step 612), and free J
If there are no CBs 362 to 364, the disk controller 10
2 is for the input / output channel unit 113 of the CPU 101
The VOL is reported to be in a device busy state (step 613), the parallel access identification information 522b-1 reported in the device busy is stored in the configuration information 314 of the LDCB 301 of the VOL (step 614), and the device waits in the device busy state. The process proceeds to the conventional logic (step 619).

As described above, according to the data processing system and the control method of the present embodiment, the serial communication between the central processing unit 101 having the input / output channel unit 113 for controlling data transfer and the disk control unit 102 is performed. In the frame 500 used in the channel interface, the spare area 522b of the device address 522 includes
By storing the parallel access identification information 522b-1 for managing the parallel operation of a plurality of I / Os separately from the VOL address 522a, an I / O request is instructed to the disk control device 102. A management information area such as an LDCB or JCB is allocated in the SM 125 for each I / O processing unit, and the parallel access identification information 522b-1 is stored in the management information area. Output channel unit 113
To the DK from the input / output channel unit 113 by reporting the termination with the concurrent access identification information.
A plurality of I / O processes for the same VOL (logical volume) in U103 can be realized.

Thus, for example, in order to realize parallel access to the same VOL, it is not necessary to issue an extra command (frame) for notifying the disk control device 102 that a specific VOL address is linked to a temporary VOL address. Thus, useless access due to issuance of an extra frame does not occur.

Further, only by changing the parallel access identification information 522b-1 using the same VOL address,
Since a plurality of input / output processes for a specific VOL are performed, it is not necessary to secure a temporary address or the like, and the upper limit of the VOL address managed by the disk control device 102 and the limitation of the parallel access due to the number of disk devices 131 occur. Without doing so, parallel access can be reliably realized.

Further, both the input / output channel unit 113 and the disk controller 102 have a VOL address 522a.
And the concurrent access identification information 522b-1 is used in common, so that there is no concern that the correspondence between the original VOL address and the temporary VOL address is recognized differently by the input / output channel unit 113 and the disk controller 102, for example.
It is possible to prevent occurrence of a failure such as data destruction due to access to an incorrect VOL.

As a result, the performance of data access to the disk device 131 via the input / output channel unit 113 and the disk controller 102 is improved, and the performance of the entire mainframe computer system is improved.

The invention described in the claims of the present application is expressed in another way as follows.

<1> A central processing unit having an input / output channel unit for controlling data transfer, and a logical volume managed by the central processing unit and the disk control unit in a frame used for a serial channel interface between the disk control units. At the time of I / O to the frame, parallel access identification information for managing the parallel operation of a plurality of I / Os is added to the frame separately from the logical volume address, and the frame is transferred from the input / output channel unit to the disk control device. A data processing system comprising means for instructing a parallel operation of a plurality of I / Os on a logical volume.

<2> In the data processing system according to item <1>, in order to enable a parallel operation of a plurality of I / Os to the same logical volume in the disk control device by the parallel access identification information, , The management information area of the I / O processing unit for each logical volume is allocated by the number of the parallel operations, and the corresponding parallel access identification information is stored.
A data processing system comprising means for adding the concurrent access identification information from the disk control device to the input / output channel unit at the end of the O processing and reporting the end.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is.

[0060]

According to the data processing system and the control method of the present invention, the number of physical storage devices and peripheral devices constituting a peripheral device such as an external storage device, the number of usable addresses, etc., are limited. Instead, between the central processing unit and a peripheral device such as an external storage device, it is possible to realize a plurality of input / output parallel operations for the same logical volume, logical peripheral device, and the like.

According to the data processing system and the control method thereof of the present invention, the central processing unit and peripheral devices such as an external storage device do not needlessly access by issuing a special extra frame. , A parallel operation of a plurality of inputs and outputs to a logical volume, a logical peripheral device, and the like can be realized.

According to the data processing system and its control method of the present invention, a data failure between a central processing unit and peripheral devices such as an external storage device due to inconsistency in recognition of a logical volume or a logical peripheral device or the like. , A parallel operation of a plurality of inputs and outputs to the same logical volume, logical peripheral device, and the like can be realized.

According to the data processing system and the control method of the present invention, the effect of improving the data input / output performance between the central processing unit and a peripheral device such as an external storage device can be obtained. Can be

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating a configuration example of a mainframe computer system as an example of a data processing system that executes a control method of the data processing system according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of control information generated in an MS to issue a plurality of I / Os to a subordinate DKC in a CPU of a mainframe computer system according to an embodiment of the present invention; is there.

FIG. 3 shows an example of control information set in an SM for realizing parallel processing of a plurality of I / Os at the time of I / O reception by a DKC of a mainframe computer system according to an embodiment of the present invention. FIG.

FIG. 4 is a flowchart illustrating an example of frame generation and transfer processing in an input / output channel unit of a mainframe computer system according to an embodiment of the present invention.

FIG. 5 is a conceptual diagram illustrating a configuration example of a frame in a serial channel interface between an input / output channel unit and a disk controller of a mainframe computer system according to an embodiment of the present invention.

FIG. 6 is a flowchart illustrating an example of parallel processing of frame reception and multiple I / O in a disk controller of a mainframe computer system according to an embodiment of the present invention.

[Explanation of symbols]

101: Central processing unit (CPU), 102: Disk control unit (DKC) (storage control unit), 103: Disk drive unit (DKU) (storage unit), 104: CPU-D
KC connection cable, 105 DKC-DKU connection cable, 111 arithmetic processing unit (IP), 112 main storage unit (MS), 113 input / output channel unit (CH),
114: System controller (SC), 121: Channel port (PORT), 122: Cache memory (CACHE), 123: Control processor, 124 ...
Data transfer control unit, 125: Shared memory (SM), 13
1: Disk device, 201, 202: Basic UCB (first
Input / output management information block), 211, 221... VOL
Address (first identification information), 216, 226 ... concurrent access identification information (second identification information), 203, 204 ...
UCB for parallel access (first input / output management information block), 231, 241... VOL address (first identification information), 236, 246... Parallel access identification information (second identification information), 303, 305. JCB (second input / output management information block), 304... JCB for concurrent access
(Second input / output management information block), 500 ... frame, 501 ... link header, 502 ... information field,
503: Link trailer, 511: Device header, 5
12 device information block, 521 information field identifier, 522 device address, 522a VOL
Address (first identification information), 522b ... spare area,
522b-1 ... Concurrent access identification information (second identification information), 523 ... DHF field.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Katsuhiro Kawaguchi, 2880 Kozu, Kodahara, Kanagawa Prefecture, Ltd.Storage Systems Division, Hitachi, Ltd. (72) Isamu Kurokawa 2880 Kozu, Kozu, Odawara, Kanagawa Prefecture Storage, Hitachi, Ltd. Within the System Division (72) Inventor Hiroaki Konuma 2880 Kozu, Odawara-shi, Kanagawa Prefecture F-term (Reference) 5B014 EB04 GD33 5D044 BC01 CC04 DE34 DE37 DE49 DE53 DE57 HL02 HL11

Claims (7)

[Claims] A central processing unit having an input / output channel unit for controlling input / output of information to / from the outside; an external storage device including a storage control device and a storage device; A channel interface for connecting to a control device; and a frame used for transmitting and receiving the information between the input / output channel unit and the storage control device via the channel interface. A data processing system capable of accepting access from the central processing unit in units of a logical volume or a logical device logically set for an apparatus, wherein the frame is any logical volume to be accessed. Or first identification information for specifying a logical device;
And a second identification information instructing a parallel operation of a plurality of accesses to the logical volume or the logical device from the input / output channel unit. 2. The data processing system according to claim 1, wherein the input / output channel unit is configured to share a common first identification information with each of a plurality of access requests to the same logical volume or logical device. A plurality of first input / output management information blocks including different second identification information are dynamically generated, and the first and second identification information are generated for each of the first input / output management information blocks. Executing the individual access request by generating the frame including and issuing the storage control device to the storage control device, wherein the storage control device includes the first and second frames included in the frame coming from the input / output channel unit. For each combination of two pieces of identification information, a plurality of second access points for accessing the same logical volume or logical device in parallel.
A data processing system which generates the input / output management information block of the above and uses the frame including the corresponding first and second identification information in response to the access request to the input / output channel unit. . 3. A control method for a data processing system, wherein a frame is exchanged between a central processing unit and a peripheral device to input and output data between the central processing unit and the peripheral device. The peripheral device comprises a plurality of logical peripheral devices, and the central processing unit comprises a first logical peripheral device for identifying each of the logical peripheral devices.
Characterized in that the identification information and the second identification information designating the parallel operation of a plurality of input / output requests to the logical peripheral device are set in the frame to execute input / output to / from the logical peripheral device. How to control the processing system. 4. The control method for a data processing system according to claim 3, wherein the central processing unit includes a common first identification information for each of a plurality of input / output requests to the same logical peripheral device; A plurality of first input / output management information blocks including the different second identification information are dynamically generated, and the first and second identification information blocks are individually generated for each of the first input / output management information blocks. The input / output request is executed by generating the frame including information and issuing the frame to the peripheral device, and the peripheral device performs the first and second operations included in the frame coming from the central processing unit. A plurality of second input / output management information blocks for executing a plurality of inputs / outputs to the same logical peripheral device in parallel for each combination of the identification information of Serial The response to the central processing unit, the corresponding first and second
A method for controlling a data processing system, characterized by using the frame including the identification information of (1). 5. A control method for a data processing system, wherein a frame is exchanged between a central processing unit and a peripheral device to input and output data between the central processing unit and the peripheral device. The address information set in the frame to specify the peripheral device to be input / output includes first identification information unique to each of the peripheral devices, and unused address information in the first identification information. And a second identification information set by using the first identification information and instructing a parallel operation of a plurality of input / output operations with respect to each of the peripheral devices specified by the first identification information. Control method. 6. A storage control device and a storage device,
The storage control device transmits and receives information to and from a higher-level device via a frame, and controls access from the higher-level device in units of logical volumes or logical devices logically set to the storage device. An external storage device to be received, wherein the frame includes first identification information for specifying any of the logical volumes or logical devices to be accessed;
A second command for instructing a parallel operation of a plurality of accesses from the higher-level device to the logical volume or the logical device;
The storage control device, for each combination of the first and second identification information included in the frame coming from the higher-level device, in parallel with the same logical volume or logical device A plurality of input / output management information blocks for accessing are generated, and a response to the access request to the higher-level device includes control logic using the frame including the corresponding first and second identification information. An external storage device, characterized in that: 7. A storage control device and a storage device,
The storage control device transmits and receives information to and from a higher-level device via a frame, and requests access from the higher-level device in units of logical volumes or logical devices logically set to the storage device. A method of controlling an external storage device that receives a plurality of accesses from the higher-level device to first logical device identification information that specifies an arbitrary logical volume or a logical device to be accessed. Receiving a frame in which second identification information instructing an operation is set, and the same logical volume for each combination of the first and second identification information included in the frame received from the higher-level device Or multiple I / O management information blocks for accessing a logical device in parallel. For steps, and said access request generating a step of responding to said host device by using the frame including the first and second identification information corresponding control method of an external storage device consisting of.