JP2001308745A - Signal pattern detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the signal pattern detection circuit which can detect a pattern more speedily without almost increasing circuit scales by using a matched filter and can shorten the time required for reaching a state where it is ready to call after turning on a portable telephone by shortening cell search. SOLUTION: The signal pattern detection circuit is provided with the first filter circuit 111 corresponding to a part sign line A as a factor of a spreading code line, and the second filter circuit 112 corresponding to a part sign line B. The second filter circuit 112 is provided with an 8 tap matched filter 15 and an 8 tap matched filter 16 provided according to configuration of the part sign line B, and a delay element group 17 to delay the output of 8 tap matched filter 15. An adding and subtracting circuit 113 which subtracts and adds output form the tow matched filters of the second filter circuit 112 to obtain the first outputted signal Out 1 and the second outputted signal Out 2 is arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Code Division Multiple Access) The present invention relates to a signal pattern detection circuit using a matched filter used in despreading processing in a receiver.

[0002]

2. Description of the Related Art W-CDM used in next-generation mobile phones
In the A (Wideband Code Division Multiple Access) communication system, radio waves transmitted from a base station to a mobile station include:
A common channel called the perch channel, which must be received by all mobile stations, is included.

A normal channel is spread by a short code, which is a spreading code having a period equal to the symbol length, and a long code described later. The long code is different for each base station.

[0004] On the other hand, in the perch channel, there is a place where a long code is not applied, that is, a place where only a short code is applied every several symbols. The length where this long code is not applied is 1
A symbol, called a long code mask symbol.

Here, a short code in the long code mask symbol is called a search code, and a period in which the long code mask symbol appears is called one slot.

The long code mask symbol includes 2
One search code is applied, and there is a first search code common to all base stations and a second search code that changes for each slot. The mobile station performs synchronization acquisition using the first search code. With this, the temporal start position of the short code can be found.

[0007] Further, long codes are grouped into several types, and the second search code is periodically changed in units of several slots in a specific pattern corresponding to the group. This cycle is called a frame.

As the long code, a partial code string of one frame length extracted from a spread code string called a Gold code string having a period much longer than one frame is used. That is, the cycle of the long code is one frame.
Therefore, by finding the pattern of the change of the second search code, it is possible to know which long code group the receiving base station belongs to. At this time, the second
Since the head position of the search code pattern is known, the head position of the frame is known, and the temporal start position of the long code is also known. That is, the synchronization of the long code is automatically performed.

The search code has a Hadamard code string H having a length of 256 (also called a Walsh code string) and a length of 16
Is obtained by an exclusive OR operation with a hierarchical code string Y having a length of 256 and forming a hierarchy. These symbols will be specifically described.

A Hadamard code string H is a one-row element string of a Hadamard matrix H ₈ obtained from a recurrence formula expressed by the following equation.

[0011]

(Equation 1)

Here, the upper bar in the above equation means negation in Boolean algebra.

[0013] Hadamard code sequence H of length 256 is present 256 from the number of rows Hadamard matrix H _8, search code is line 0, line 8, ..., 18 different 136 line is used. At this time, in each code string H, the same code always continues by eight.

The above-mentioned hierarchical code string Y is obtained, for example, by substituting a partial code string Z of length 16 represented by the following equation according to its element.
This is a code string in which 16 are arranged while being inverted and non-inverted.

[0015]

(Equation 2)

Here, if the element is 1, the code string is inverted (negation of the code string), and if the element is 0, the code string is non-inverted (do nothing). That is, the entire code string is represented by the following expression in the above example.

[0017]

(Equation 3)

Alternatively, the element Y (i) of the hierarchical code string Y can be expressed as follows. Here, in the following equations, mod indicates a remainder calculation, div indicates an integer division operation, and a circled positive sign indicates an exclusive OR.

[0019]

(Equation 4)

A Hadamard code string H and a hierarchical code string Y
S of search code S expressed by exclusive OR with
_{y, x} (i) is represented by the following equation (1). here,
0 ≦ y ≦ 1, 0 ≦ x ≦ 8.

[0021]

(Equation 5)

Here, the elements of the partial code strings s ₀ and s ₁ and the partial code strings z _{0 to} z ₈ of the search code S are represented by the following equations, respectively.

[0023]

(Equation 6)

[0024]

(Equation 7)

That is, in each of the search codes S, two code strings s ₀ and s ₁ having a length of 16 are inverted and non-inverted according to the elements of nine code strings z _{0 to} z ₈ having a length of 16. Thus, a code string in which 16 are arranged is obtained.

As a result, the search code S represented by the exclusive OR of the Hadamard code string H and the hierarchical code string Y is 18
It can be seen that there are kinds.

An advantage of using such a code string is that when a matched filter is used for synchronization acquisition or the like, the configuration of the matched filter can be simplified. In other words, instead of using a signal pattern detection circuit using a 256-tap matched filter as before, two 16-tap matched filters may be used, so that the circuit scale of the entire signal pattern detection circuit can be considerably reduced.

Here, an example of a signal pattern detection circuit using two matched filters will be described with reference to FIG. These two matched filters use different types.

As shown in FIG. 6, a matched filter 6 included in a first filter circuit 201 at a stage prior to signal input is provided.
Reference numeral 4 denotes a matched filter having 16 stages of delay elements 61 between internal taps.
The matched filter 65 included in the second filter circuit 202 at the subsequent stage is an ordinary matched filter in which the internal delay element 61 is one stage.

It is assumed that the input signal is sampled at the same time interval Tc as the delay time of the delay element 61 in the matched filter 64. Hereinafter, the sampled input signal is referred to as input data.

The matched filter 64 is composed of 240 delay elements 61 for sequentially delaying input data, each delayed output of input data and input data by every 16th delay element 61 and each code of a code string to be detected. Find the product of 1
This is a transversal filter including six multipliers 62 and an adder 63 for obtaining the sum of outputs from the multipliers 62.

On the other hand, the matched filter 65 is composed of fifteen delay elements 61 for sequentially delaying the input data, the input data, each delay output of the input data by the delay element 61, and each code of the code string to be detected. This is a transversal filter comprising 16 multipliers 62 for obtaining a product and an adder 63 for obtaining the sum of outputs of the multipliers 62.

In FIG. 6, the matched filter 64 is placed at the front stage, and the matched filter 65 is placed at the rear stage. In this configuration, the matched filter 64 is provided with a code string z _{x to} be detected among the code strings z _{0 to} z ₈ as a coefficient. On the other hand, the matched filter 65 includes the code strings s ₀ and s ₁ ,
Code sequence s _y to be detected is given as a coefficient. In addition,
Elements 0 and 1 of the code string given as coefficients mean +1 and −1 in an actual matched filter, respectively.

The matched filter 64 calculates a cross-correlation value between every 16th input data and the code string z _x for each Tc. As a result, if the input data includes the same code sequence as the code sequence z _x to be detected, the absolute value of the cross-correlation value becomes 16 consecutively large values somewhere in 256.

Since the 16 consecutive cross-correlation values correspond to _one of the code strings s ₀ and s ₁ , the cross-correlation values are output to the matched filter 65.

The matched filter 65 is obtained by calculating the cross-correlation value between the correlation value and the code sequence s _y every time Tc. As a result, the code string z _x to be detected in the input data,
If s _y is included, the absolute value of the cross-correlation value is 25
Only one of the six has a large value. Note that the code string z _x to be detected in the input data, if s _y is not included in one the absolute value of the cross-correlation value is not a large value.

[0037] Thus, it is possible to detect the code sequence z _x included in the input data, s _y and its timing. FIG.
Then, after the matched filter 64, the matched filter 65
Are connected in series. Conversely, a similar result can be obtained by a configuration in which the matched filter 64 is connected in series after the matched filter 65.

[0038]

By the way, generally, C
A problem with the mobile phone of the DMA system is that it takes time to specify a base station called a cell search. In particular, W-CDMA used in the next-generation mobile phones described above
For perpetual phones, the perch channel code,
That is, due to the complexity of the configuration of the short code and the long code, there is a problem that the time of the cell search including synchronization acquisition, long code group identification, and long code identification becomes long.

As described above, a long cell search time means that, for example, the time from when the power of the portable telephone is turned on until the state in which the telephone can be actually called becomes long.

Therefore, the speed of the synchronous acquisition in the cell search can be increased by using a matched filter.

Since the long code is synchronized by the time the synchronization is acquired, the long code is specified using, for example, one symbol at a time using the same matched filter as the synchronization acquisition. If long codes are detected, less time is required.

Further, in order to specify the long code group, it is necessary to detect a change pattern of each slot of the second search code. For this reason, the easiest and fastest way to detect long code groups is
There is a method of arranging the same number of correlators as the type of the second search code and viewing the output pattern of the correlators.

However, since a plurality of correlators are separately required, there is a problem that the circuit scale becomes large. Such an increase in circuit scale is not preferable in a mobile phone aiming at miniaturization.

In order to minimize the circuit size in order to detect a pattern of a group of long codes, it is conceivable to use a matched filter used for synchronization acquisition as shown in FIG.

However, when the matched filter used for synchronization acquisition is used, as described above, only one second search code corresponding to the pattern of the long code group can be detected at a time. This takes time, and as a result, the cell search becomes longer, which causes a problem that the time from when the mobile phone is turned on to when the mobile phone is actually ready to make a call becomes longer.

The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to use a matched filter to specify a long code group, and to increase the pattern speed without increasing the circuit scale. It is an object of the present invention to provide a signal pattern detection circuit capable of performing detection, shortening a cell search, and shortening the time from when the mobile phone is turned on to when a call can be actually made.

[0047]

In order to solve the above-mentioned problems, a signal pattern detection circuit according to the present invention comprises a signal pattern detecting circuit for detecting a signal pattern of an input signal from a spread code string in which a plurality of partial code strings are spread. In the detection circuit, a plurality of matched filters for obtaining and outputting a cross-correlation value between the spread code sequence and the input signal are provided in correspondence with the partial code sequences of the spread code sequence, and the output of each matched filter is provided. And an addition / subtraction circuit for simultaneously outputting a plurality of signals by adding / subtracting the signals.

According to the above configuration, the cross-correlation value between the partial code sequence of the spread code sequence and the input signal is obtained by the matched filter corresponding thereto, and each cross-correlation value is input to the addition / subtraction circuit to perform addition / subtraction. By simultaneously outputting a plurality of signals, it is possible to simultaneously detect signal patterns corresponding to the respective partial code strings.

Thus, for example, in the W-CDMA system, which is a communication system for a cellular phone or the like, a second search code, which is one of search codes for specifying a group of mobile stations, is spread by a plurality of partial code strings. In this case, since a plurality of partial code strings can be detected at the same time, the time required for detecting the second search code can be significantly reduced.

Therefore, the signal pattern can be detected at a higher speed, the cell search in the W-CDMA system can be shortened, and the time from when the portable telephone is turned on until the telephone can be actually called can be shortened. be able to.

Another signal pattern detection circuit according to the present invention is a signal pattern detection circuit for detecting a signal pattern of an input signal from a spread code sequence in which a partial code sequence A and a partial code sequence B are spread. The elements of the column A are inverted and non-inverted according to the elements of the other partial code strings B, and the first filter circuit for detecting the partial code string A and the second filter circuit for detecting the partial code string B At least one of the filter circuits is provided with a plurality of matched filters for obtaining and outputting a cross-correlation value between the spread code string and the input signal in correspondence with a partial code string to be detected. A delay circuit for adjusting the delay time of each of the matched filters, and an addition / subtraction circuit for adding and subtracting the outputs of the matched filters and outputting a plurality of signals simultaneously. It is set to.

According to the above configuration, at least one of the first filter circuit and the second filter circuit is provided with a plurality of matched filters and a plurality of matched filters according to the configuration of the applied partial code string. By including a delay circuit for adjusting the delay time, a plurality of matched filter outputs can be obtained. By inputting the outputs of the matched filters to the adding / subtracting circuit and performing addition / subtraction, a plurality of partial code strings can be simultaneously detected by a filter circuit having a plurality of matched filters.

As a result, it is possible to reduce the time required for detecting a spread code string in which the partial code strings A and B are spread. For example, W-CDMA, which is a communication method for mobile phones
In the method, when a signal pattern of a second search code, which is one of search codes for specifying a group of mobile stations, is spread by a plurality of partial code strings, a plurality of partial code strings are detected at the same time. Therefore, the time required to detect the signal pattern, that is, the time required to detect the second search code can be significantly reduced.

The circuit scale of a filter circuit comprising a plurality of matched filters is substantially the same as that of a filter circuit having a matched filter when there are not a plurality of matched filters.

Therefore, pattern matching can be performed at a higher speed without using a matched filter to specify a long code group in the W-CDMA system or the like, and the cell search can be shortened. In addition, it is possible to reduce the time from when the power of the mobile phone is turned on to when the mobile phone can be actually called.

One of the first and second filter circuits having the plurality of matched filters therein is located downstream of the other filter circuit not having the plurality of matched filters therein. The number of output signals may be equal to the number of the respective addition / subtraction circuits connected in series.

In this case, by disposing a filter circuit having a plurality of matched filters at the subsequent stage, a plurality of output signals corresponding to a plurality of code strings (search codes) can be simultaneously obtained in the entire signal pattern detection circuit.

Thus, in the W-CDMA system, which is a communication system for mobile phones, for example, the signal pattern of the second search code, which is one of the search codes for specifying a group of mobile stations, is divided into a plurality of partial code strings. , It is possible to detect a plurality of partial code strings at the same time, so that the time required for signal pattern detection, that is, detection of the second search code can be significantly reduced.

Further, the filter circuit arranged at the subsequent stage may be a first filter circuit for detecting the partial code string A.

In this case, since a plurality of partial code strings A can be detected at the same time, the partial code string A can be specified quickly. Therefore, the time required for detecting the search code corresponding to the spread code string obtained by spreading the partial code string A and the partial code string B can be significantly reduced.

Further, the filter circuit arranged at the subsequent stage may be a second filter circuit for detecting the partial code string B.

In this case, since a plurality of partial code strings B can be detected simultaneously, the partial code string B can be specified quickly. Therefore, the time required for detecting the search code corresponding to the spread code string obtained by spreading the partial code string B and the partial code string A can be significantly reduced.

Further, the number of the plurality of matched filters may be equal to the number of code strings constituting the applied partial code string.

In this case, since each matched filter can be used for detecting each code string, pattern detection of a partial code string can be performed efficiently.

A part of the delay circuit may be shared with a delay circuit inside a plurality of matched filters.

In this case, the delay circuit in the filter circuit is
Since the size can be reduced by the amount that can be shared, the rate of increase in the size of the circuit due to the increase in the number of matched filters in the signal pattern detection circuit can be reduced.

Another signal pattern detection circuit of the present invention is:
The first filter circuit for detecting the partial code string A includes a plurality of matched filters Ma according to the configuration of the partial code string A.
i, and a second filter circuit for detecting the partial code string B comprises a plurality of matched filters Mbj in accordance with the configuration of the partial code string B.
ai, a delay circuit for adjusting the delay time of Mbj, and a plurality of addition / subtraction circuits for adding / subtracting the outputs of the matched filters Mai, Mbj, respectively. One of the first filter circuit and the second filter circuit is provided in the preceding stage. Become
The other is a latter stage, and a matched filter constituting a latter stage filter circuit is connected in series to each of a plurality of outputs of a matched filter constituting a former stage filter circuit.

According to the above configuration, since a plurality of outputs of each matched filter are obtained in the subsequent filter circuit, more output signals can be obtained as a whole. Therefore, since more search codes can be detected simultaneously, the time required for detecting the second search code can be further reduced.

The number of the matched filters Mai or Mbj may be equal to the number of code strings in the partial code string to be applied.

In this case, since each matched filter can be used for detecting each code string, pattern detection of a partial code string can be performed efficiently.

Further, a part of the delay circuit may be shared with a delay circuit in each of the plurality of matched filters Mai or Mbj.

In this case, the delay circuit in the filter circuit is
Since the size can be reduced by the amount that can be shared, the rate of increase in the size of the circuit due to the increase in the number of matched filters in the signal pattern detection circuit can be reduced.

[0073]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] An embodiment of the present invention will be described with reference to FIGS.
It is as follows.

The signal pattern detection circuit according to the present embodiment is a W-CDMA (Wideba
nd Code Division Multiple Access) In a communication system, radio waves transmitted from a base station to a mobile station use a base station that the mobile station receives from a common channel called a perch channel, which must be received by all mobile stations. A circuit used to identify a station.

The perch channel has a first search code common to all base stations and a second search code that changes for each slot, as described in the section of the related art. By performing synchronization acquisition using the first search code and detecting a change pattern of the second search code, it is specified which long code group the receiving base station belongs to.

The second search code is obtained by the exclusive OR of a 256-length Hadamard code string H and a 256-length hierarchical code string Y composed of 16-length code strings. Can be The details of the Hadamard code string H and the hierarchical code string Y have been described in the section of the prior art, and will not be described.

The second search code S is represented by an exclusive OR of the Hadamard code string H and the hierarchical code string Y, and its element is represented by the following equation (1). Here, 0 ≦ y ≦
1, 0 ≦ x ≦ 8.

[0078]

(Equation 8)

The partial code of the second search code S
Column s₀, S₁And the partial code string z₀~ Z₈ And the elements are
It looks like this:

[0080]

(Equation 9)

[0081]

(Equation 10)

As a result, it can be seen that there are 18 types of second search codes S.

Therefore, the signal pattern detection circuit according to the present embodiment is designed to detect a spread code string (signal pattern) of the second search code S used to specify the long code group. As shown in FIG. 1, a first filter circuit 111, a second filter circuit 112, and an addition / subtraction circuit 113 are arranged in this order from the signal input side.

The first filter circuit 111 comprises a 16-tap matched filter 14 having 16 taps and 16 stages of delay elements 11 between internal taps. In the first filter circuit 111, the input signal In to be input is sampled at the same time interval Tc as the delay time of the delay element 11.
Hereinafter, the sampled input signal will be described as input data.

The 16-tap matched filter 14
The product of 240 (16 × 15) delay elements 11 for sequentially delaying the input data, and the product of each delayed output of the input data and the input data of every 16th delay element 11 and each code of the code string to be detected is obtained. This is a transversal filter including a number of multipliers 12 and an adder 13 for calculating the sum of outputs from the respective multipliers 12.

Here, the 16-tap matched filter 14 selects a code sequence z _x (z, z _x (z) of a partial code sequence z _{0 to} z ₈ which is one of the partial code sequences of the second search code.
_x 0 to z _x 15, x = 0 to 8) are given as the coefficients of the multiplier 12.

That is, the first filter circuit 111
Has a circuit for detecting a partial code sequence z ₀ to z ₈ is one of the partial code string of the second search codes.

The second filter circuit 112 includes two 8-tap matched filters 15 and 16 having eight taps and eight delay elements 1.
1 comprises a delay element group 17 connected in series.

The 8-tap matched filters 15 and 16 are matched filters having eight taps and one stage of delay element 11 between internal taps. That is, the 8-tap matched filter 15 is composed of seven delay elements 11 for sequentially delaying input data, a product of the input data, each delayed output of the input data by the delay element 11, and each code of the code string to be detected. And an adder 13 for calculating the sum of the outputs of the multipliers 12
And a transversal filter.

When the data output from the first filter circuit 111 is used as input data, the 8-tap matched filter 16 directly delays the input data without delay in the first-stage delay element 11 and The data is input to the multiplier 12. On the other hand, in the 8-tap matched filter 15, the input data delayed by the delay element group 17 is input to the first-stage delay element 11 and the multiplier 12.
To be entered.

Here, the 8-tap matched filter 1
5 and 16 use the first eight elements of the code strings s ₀ and s ₁ , which are one of the partial code strings of the second search code, as coefficients (s ₀ to s 7) of the multiplier 12. In FIG. 1, the coefficients are simply described as a partial code string s.

That is, the second filter circuit 112
This is a circuit for detecting code strings s ₀ and s ₁ which are one of partial code strings of the second search code.

Note that the latter eight elements are the same as the former eight elements in the code string s ₀ , and the code string s ₁
Has a negative relationship with the code string s ₀ . That is, the code strings s ₀ and s ₁ are represented by the following equations (2) and (3).

S ₀ = {s, s} (2) s ₁ = {s, / s} (3) In the above equation (3), The element “/ s” (partial code sequence) indicates that the polarity of the former element “s” (partial code sequence) is inverted.

In the 8-tap matched filters 15 and 16, the outputs of the multipliers 12 are added by the adder 13 and output to the addition / subtraction circuit 113.

The adding / subtracting circuit 113 includes an adder 18 and a subtractor 19.

The adder 18 adds the outputs of the 8-tap matched filter 15 and the 8-tap matched filter 16 and outputs a first output signal Out1.

The subtractor 19 subtracts the outputs of the 8-tap matched filter 15 and the 8-tap matched filter 16 and outputs a second output signal Out2.

The input timing of the 8-tap matched filter 15 is delayed by 8Tc from the input timing of the 8-tap matched filter 16 by the delay element group 17, and the first and second half partial code strings of the code string s ₀ are s, the 8-tap matched filter 15 is the 16-tap matched filter 6 shown in FIG.
5. The 8-tap matched filter 16 has a function of 8 taps on the left side of the 16-tap matched filter 65 shown in FIG. By adding the 16 outputs by the adder 18, the function becomes exactly the same as that of the 16-tap matched filter 65.

[0100] Thus, the first output signal Out1 is just for the code sequence s _0, it can be seen that obtained by performing the same calculation and 16-tap matched filter 65 in FIG. 6.

Also, as can be seen from the above equation (3), the outputs of the 8-tap matched filters 15 and 16 are subtracted because the _first and second eight partial code strings of the code string s ₁ are in an inverted relationship. it is given a negative partial code sequence s as a coefficient of each tap of the 8-tap matched filter 16, as in the case of the bit stream s _0, adds the outputs of the 8-tap matched filter 15 and 16 FIG.
The same function as the 16-tap matched filter 65 shown in FIG.

[0102] Thus, the second output signal Out2 is just for the code sequence s _1, is can be seen that obtained by performing the same calculation and 16-tap matched filter 65 in FIG. 6.

As described above, in the signal pattern detection circuit having the above configuration, the two 8-tap matched filters 15 and 16 and the delay element group 17 in the second filter circuit 112, and the adder 18 and the subtractor By using 19, the code strings s ₀ and s ₁ , which are one of the partial code strings of the second search code, can be simultaneously detected.

Naturally, the 16-tap matched filter 65 shown in FIG. 6 described in the section of the prior art can handle only one code string, so the signal pattern detection circuit shown in FIG. It has the function of two filters 65.

However, the configuration of the matched filter,
In particular, although it cannot be said unconditionally depending on the addition method of each tap output, two 8-tap matched filters and one adder have substantially the same circuit scale as the 16-tap matched filter shown in FIG. Since it can be considered, the delay element group 17
Although only the subtractor 19 and the subtracter 19 have a larger circuit scale than the 16-tap matched filter 65 shown in FIG. 16, the circuit size is sufficiently smaller than two 16-tap matched filters 65.

If the signal pattern detection circuit having the above configuration is used, two partial code strings s ₀ and s ₁ can be detected at the same time. Therefore, if only another nine code strings z _x are detected, the second search code , A total of 18 code strings (18 types of signal patterns) can be detected. As a result, the time required for detecting the partial code string of the second search code (detection time) can be reduced by half, and as a result,
The speed of detecting the signal pattern of the second search code can be increased.

The 16-tap matched filter 14,
The 8-tap matched filters 15 and 16 may have any configuration other than the configuration shown in FIG.

For example, the 8-tap matched filter 1
If the configuration 6 stores each delay input signal such as the configuration shown in FIG. 1, a part of the function of the delay element group 17 (that is, a seven-stage delay) is added to the delay element 1 in the 8-tap matched filter 16.
1 may be realized. Specifically, instead of the second filter circuit 112 shown in FIG. 1, the second filter circuit 1 shown in FIG.
Use 22. The second filter circuit 1 shown in FIG.
Members having the same functions as 12 are given the same numbers,
The description is omitted.

In the second filter circuit 122, as shown in FIG. 2, the seven delay elements 11 of the 8-tap matched filter 16 are used for delay of seven stages in the delay element group 17 shown in FIG. By adding a delay element 21 having the same function as that of the delay element 11 to the output side of the rightmost delay element 11 of the 8-tap matched filter 16, the signal from the first filter circuit 111 is delayed by eight stages. Of the 8-tap matched filter 15.

According to the above configuration, the second filter circuit 1
22 is different from the second filter circuit 112 shown in FIG. 1 in that a delay element group 17 including eight delay elements 11
Instead of using only one delay element 21, the number of delay stages can be significantly reduced by the amount of the seven delay elements 11 used in the delay element group 17.

That is, the second filter circuit 12 including the 8-tap matched filters 15 and 16 and the delay element 21
2 and the addition / subtraction circuit 113 including the adder 18 and the subtractor 19 can have the same circuit scale as the 16-tap matched filter 65 shown in FIG.

The signal pattern detection circuit according to the present invention provides that if the search code S satisfies the above equation (1) and the partial code strings s ₀ and s ₁ satisfy the above equations (2) and (3),
Any code sequence is applicable.

Further, instead of the above equations (2) and (3), s ₀ = {s, s ′} (2 ′) s ₁ = {s, / s ′}. ... (3 ′) where s ≠ s ′, and in the above equation (3 ′),
The latter half element “/ s ′” (partial code sequence) indicates that the polarity of the latter half element “s ′” (partial code sequence) of the code sequence s ₀ is inverted.

In this case, the second filter circuit 1 shown in FIG.
In 12, the coefficients of the 8-tap matched filter 16 may be replaced with elements of the code string s' instead of the code string s. In addition, if the partial code sequences forming the two partial code sequences are common or negated in the first half and in the second half, even if the lengths of the first and second code sequences are not the same, the length depends on the length. To change the number of taps, adder 18, subtractor 1
If 9 is changed in accordance with the relationship between the partial code strings, the signal pattern detection circuit of the present invention can be applied.

Further, in this embodiment, the length of the hierarchical code string Y is 256, but any value of this length can be obtained by using the above formulas (1) to (3) or (1). ,
If the relationship of (2 ′) and (3 ′) is satisfied, it is possible to realize the signal pattern detection circuit of the present invention.

[Second Embodiment] The following will describe another embodiment of the present invention with reference to FIG.

In the signal pattern detection circuit according to the present embodiment, the partial code strings s ₀ and s ₁ are calculated by the following equation (2 ″).
Applicable when (3 '') is satisfied.

S ₀ = {t, t ′, / t ″} (2 ″) s ₁ = {t, / t ′, t ″}. (3 ″) As described above, when each code string is composed of three or more partial code strings, a function for preparing matched filters and adding / subtracting the output of each matched filter is provided. The signal pattern detection circuit of the present invention can be realized only by preparing a group of delay elements for adjusting the input timing.

A specific signal pattern detection circuit that satisfies the above equations (2 ″) and (3 ″) includes, for example, a first filter circuit 131, a second filter circuit 132, The circuit 133 is provided. Here, the number of elements of each of the partial code strings t, t ′, and t ″ is 5,
5 and 6.

The first filter circuit 131 is a 16-tap matched filter 31 for giving a code sequence z _x as a coefficient.
have. This 16 tap matched filter 31
Has the same function as the 16-tap matched filter 14 shown in FIG.

The second filter circuit 132 has two
5-tap matched filters 32 and 34, one 6-tap matched filter 36, 5-stage delay element group 3
3 and 35.

The 5-tap matched filters 32 and 34 are obtained by converting the 8-tap matched filter 15 and the like shown in FIG. 1 into 5-tap. Elements are given,
The element of the code string t ′ is given to the 5-tap matched filter 34.

The 6-tap matched filter 36 is obtained by converting the 8-tap matched filter 15 shown in FIG. 1 and the like into 6 taps, and is provided with an element of a code string t ″ as a coefficient.

The five-stage delay element groups 33 and 35
Is obtained by connecting the delay elements 11 shown in FIG. 1 in five stages in series. The five-stage delay element group 33 delays the input of the five-tap matched filter 34 by five stages, and the five-stage delay element group The reference numeral 35 further delays the input of the 6-tap matched filter 36 by five stages (a total of ten stages).

The five-stage delay element groups 33 and 35
Is 5 as in the case shown in FIG.
By using the delay elements constituting the tap matched filters 32 and 34, the number of stages in each of the five-stage delay element groups 35 and 36 can be reduced.

The adder / subtractor 133 is composed of two adder / subtracters 37 and 38, and outputs the outputs of the 5-tap matched filters 32 and 34 and the 6-tap matched filter 36 according to the above equation (2 ″) (3 '') To calculate the first output signal Out1 and the second output signal Out2.
Is output.

[0127] According to the signal pattern detection circuit having the above configuration, similarly to the first embodiment, since the two partial code sequence s _0, s ₁ to be detected simultaneously, only nine another code sequence z _x Is detected, a total of 18 code strings (18 types of signal patterns) of the second search code can be detected. As a result, the time required for detecting the partial code string of the second search code (detection time) can be reduced to half, and as a result, the speed of detecting the signal pattern of the second search code can be increased.

Further, in this embodiment, the partial code strings s ₀ and s ₁ are further composed of three types of code strings t, t ′, and t ″, and three matched strings corresponding to the number of these code strings. Filters 32, 34, 36 are provided. in this way,
If the number of matched filters is made equal to the number of code strings constituting the applied partial code string, each matched filter can be used for detecting each code string, so that the efficiency of the partial code string Pattern detection can be performed.

For example, if the number of matched filters is smaller than the number of code strings constituting a partial code string, a plurality of code strings must be detected by one matched filter. A problem arises when the time required for the operation becomes longer.

On the other hand, if the number of matched filters is larger than the number of code strings constituting the partial code string, the same code string is detected simultaneously by a plurality of matched filters, so that the circuit scale is increased. Therefore, it cannot contribute to the reduction of the time required to detect the pattern of the partial code string.

However, if the number of matched filters and the number of code strings forming a partial code string are the same as in the present embodiment, the above-described problem does not occur.

[0132] In the first and second above embodiment, although the partial code sequence s _y described two types of s _0, s _1, in the present invention, the type of the partial code sequence s _y is greater than two even if, if they meet the portion two or more sets constituting a code string s _y are the aforementioned formula (2) (3) or the like, can of course be applied.

[0133] Thus, the portion as the type of the code sequence s _y is larger than in the case of the 16-tap matched filter 65 shown in FIG. 6 of the prior art, the second search code required for a particular group of long code The detection time of the code string pattern (signal pattern) can be shortened.

In addition to the above equations (2 ″) and (3 ″), the following equation (4 ″) s ₂ = {t, / t ′, / t ″}... ... (4 '') If there is a relational expression,
The result obtained by adding another adder / subtractor to the signal pattern detection circuit shown in FIG. 3 and subtracting the output of the 5-tap matched filter 34 and the output of the 6-tap matched filter 36 from the output of the 5-tap matched filter 32. To the third output signal Ou
If the signal is output as t3, the time required to detect the signal pattern of the second search code can be further reduced.

[0135] The signal pattern according to the first case, for example, carried out to detect the partial code sequence s _y does not satisfy the above equation (2) (3) or the like in the signal pattern detection circuit according to the above embodiments for detection circuit, the signal pattern detection circuit shown in FIG. 1, the coefficient of 8-tap matched filter 15, the eight elements the first half of the partial code sequence s _y, the coefficient of 8-tap matched filter 16, give the elements of the partial code sequence s _y. Then, only the first output signal Out1 is used, and the second output signal Out2 is not used.

When the partial code string z _x of the above equation (1) has the relationship of the above equations (2) and (3), for example, z _x1 = {z, z}... _{········ (5) z x2 = {} z, / z} partial code sequence z _x1 satisfying ........... (6), the case where z _x2 is present also The signal pattern detection circuit according to the present invention can be applied. Here, 0 ≦ x1 ≦ 8 and x1 ≠ x2. Further, the partial code sequence z is a code sequence having the first eight elements of the partial code sequence z _x1 .

[0137] Here, the partial code sequence z _x in the example shown in the column of Prior Art _{(z 0, z 5),} (z 1, z 6), (z
₂ , z ₇ ) and (z ₃ , z ₈ ) are calculated by the above equations (5) and (6).
Meets. An optimal signal pattern detection circuit in this case will be described in a third embodiment below.

[Embodiment 3] The following will describe still another embodiment of the present invention with reference to FIG. For convenience of explanation, members having the same functions as those in the above-described embodiments are given the same reference numerals, and descriptions thereof are omitted.

As shown in FIG. 4, the signal pattern detection circuit according to this embodiment includes a first filter circuit 141 and a second filter circuit 141.
A filter circuit 142 and an addition / subtraction circuit 143 are provided.

The first filter circuit 141 includes a 16-tap matched filter 41 having one delay element 11 between internal taps and 16 taps. The 16-tap matched filter 41 obtains a product of 15 delay elements 11 for sequentially delaying input data, a product of the input data, each delay output of the input data by the delay element 11, and each code of a code string to be detected. This is a transversal filter including 16 multipliers 12 and an adder 13 for obtaining a sum of outputs from the multipliers 12.

[0141] Here, the above-mentioned multiplier 12, a coefficient, partial code by providing a column s _y, in the first filter circuit 141, the partial code sequence from the input signal In by the 16-tap matched filter 41 _sy is detected.

The second filter circuit 142 has one
Delay element group 42 in which 28 delay elements 11 are connected in series
And 8-tap matched filters 43 and 44.

Each of the 8-tap matched filters 43 and 44 has 16 delay elements 11 between internal taps, and has eight taps. That is, the 8-tap matched filters 43 and 44 are composed of 112 delay elements 11 for sequentially delaying input data, input data and delayed outputs of input data by every 16th delay element 11, and a code string to be detected. This is a transversal filter including eight multipliers 12 for obtaining a product of each code and an adder 13 for obtaining a sum of outputs of the multipliers 12.

Here, the 8-tap matched filter 4
Elements of the partial code sequence z are given to 3 and 44 as coefficients. Therefore, the second filter circuit 142
Then, the partial code string z is detected from the signal from the first filter circuit 141 by the 8-tap matched filters 43 and 44.

In the 8-tap matched filters 43 and 44, the outputs of the multipliers 12 are added by the adder 13 and output to the addition / subtraction circuit 143.

The addition / subtraction circuit 143 has the same configuration as the addition / subtraction circuit 113 of the first embodiment shown in FIG.
It comprises an adder 45 and a subtractor 46.

The adder 45 adds the outputs of the 8-tap matched filters 43 and 44 to generate a first output signal Ou.
t1 is output.

The subtractor 46 subtracts the outputs of the 8-tap matched filters 43 and 44 and outputs a second output signal Out2.

The 8-tap matched filter 43 receives the signal from the first filter circuit 141 via the delay element group 42, while the 8-tap matched filter 44 The signal from the filter circuit 141 is directly input without delay.

Thus, the 8-tap matched filter 4
The input of No. 3 lags behind the 8-tap matched filter 44 by the number of delays between taps (16 stages × 8 taps = 128 stages). Therefore, in the second filter circuit 142, the 8-tap matched filters 43 and 44
The partial code strings z _x1 and z _x2 can be simultaneously detected.

As described above, since two partial code strings z _x1 and z _x2 can be detected at the same time, the detection of the signal pattern of the second search code as a whole can be speeded up. However,
Since the number of stages of the delay element group 42 is increased to 128, the circuit scale of the entire signal pattern detection circuit is increased.

Therefore, similarly to the case shown in FIG. 2 of the first embodiment, the configuration of 8-tap matched filters 43 and 44 for detecting partial code strings z _x1 and z _x2 is changed to a configuration capable of storing the input signal itself. , 112 stages of the delay element group 42 are shared with the delay elements 11 of the 8-tap matched filter 44, and the remaining 16 stages are shared by the 8-tap matched filter 44.
If it is arranged between the output of the delay element 11 of the last stage and the input of the 8-tap matched filter 43, the circuit scale of the entire signal pattern detection circuit does not need to be made too large.

Further, when the partial code strings z _x1 and z _x2 have the relations as in the above equations (2 ′) (3 ′) (2 ″) (3 ″) (4 ″) (each equation) In the signal pattern detection circuit shown in FIG. 4, the second filter circuit 142 and the addition / subtraction circuit 1 are used similarly to the signal pattern detection circuit shown in FIG. 3 of the second embodiment.
What is necessary is just to make the configuration with 43 conform to the above-mentioned relational expressions.

It is also possible to arrange a filter circuit having a plurality of matched filters before the signal pattern detection circuit. However, in this case, for each of the two outputs of the former stage, it is necessary to connect in series to the matched filter forming the filter circuit of the latter stage, and the signal pattern in which the filter circuit having a plurality of matched filters is arranged in the latter stage An additional matched filter is required compared to the detection circuit.

Here, the partial code strings s _y and z _{x satisfy the} equations (2) and (3) and the equations (5) and (6), respectively.
If it is desired to make the detection of the second search code faster even at the expense of the circuit scale, the respective partial code strings _sy ,
A plurality of matched filters corresponding to z _x may be provided. In this case, as described above, two matched filters are connected to the respective outputs from the two matched filters of the preceding-stage filter circuit in the subsequent-stage filter circuit. The total is four, and it is possible to simultaneously detect four partial code strings. This example will be described in a fourth embodiment below.

[Embodiment 4] Still another embodiment of the present invention is described below with reference to FIG.

As shown in FIG. 5, the signal pattern detection circuit according to the present embodiment is configured such that the first signal from the input side of the input signal In
The filter circuit 151 and the second filter circuit 152 are arranged in this order.

The first filter circuit 151 includes a 128-stage delay element group 511 and an 8-tap matched filter 512.
And 513, an adder 514, and a subtractor 515.

That is, the first filter circuit 151
Is the second filter circuit 1 of the third embodiment shown in FIG.
The configuration is the same as that of the combination of the C.42 and the addition / subtraction circuit 143.

Here, the 8-tap matched filter 512
And 513, the element of the partial code sequence z _x (code sequence z) is given as a coefficient. Therefore, the input of the 8-tap matched filter 512 is delayed by 128 stages by the 128-stage delay element group 511 from the 8-tap matched filter 513, so that the matched filter 5
1 can simultaneously detect the partial code strings z _x1 and z _x2 .

The second filter circuit 152 includes a first matched filter 52 to which a signal from the adder 514 in the matched filter 51 of the first filter circuit 151 is input, and a subtraction in the matched filter 51. And a second matched filter 53 to which a signal from the device 515 is input.

The first matched filter 52 and the second matched filter 52
The matched filter 53 is the same as the combination of the second filter circuit 112 and the addition / subtraction circuit 113 shown in FIG. 1 of the first embodiment. Therefore, the operation of detecting the code string in the first matched filter 52 and the second matched filter 53 is the same as that of the second filter circuit 112 and the addition / subtraction circuit 113 of the first embodiment shown in FIG.

When the data output from the first filter circuit 151 is input data, the 8-tap matched filter 523 of the first matched filter 52 receives the input data without delay. It has become so. On the other hand, the 8-tap matched filter 522 of the first matched filter 52 receives the input data delayed by the eight-stage delay element group 521.

Here, the 8-tap matched filter 5
In 22 and 523, the first eight elements (code strings s) of the code strings s ₀ and s ₁ , which are one of the partial code strings of the second search code, are given as coefficients.

Then, the 8-tap matched filter 522
And 523 are added by an adder 524 to form a first
The output is output as an output signal Out1, and the outputs of the 8-tap matched filters 522 and 523 are subtracted by a subtractor 525 and output as a second output signal Out2.

Similarly, when the data output from the first filter circuit 151 is input data, the 8-tap matched filter 533 of the second matched filter 53 is used.
, The input data is input without delay. On the other hand, the second matched filter 53
In the 8-tap matched filter 532, input data delayed by the 8-stage delay element group 531 is input.

Here, the 8-tap matched filter 5
In 32 and 533, the first eight elements (code sequence s) of the code sequences s ₀ and s ₁ , which are one of the partial code sequences of the second search code, are given as coefficients.

Then, the 8-tap matched filter 532
And 533 are added by an adder 534 to form a third
The output is output as an output signal Out3, and the outputs of the 8-tap matched filters 532 and 533 are subtracted by a subtractor 535 and output as a fourth output signal Out4.

As a result, the first output signal Out1 becomes
The second output signal Out2 is used to detect the partial code sequence z _x1 , s _1, and is used to detect the partial code sequence z _x1 , s ₀ . Further, the third output signal Out3
Is used to detect the partial code sequence z _x2 , s _0, and the fourth output signal Out4 is used to detect the partial code sequence z _x2 , s ₁ .

Therefore, according to the signal pattern detection circuit having the above configuration, four types of partial code strings can be detected simultaneously. As a result, the time required to detect the signal pattern of the second search code can be significantly reduced as compared with the signal pattern detection circuits shown in FIGS.

The signal pattern detection circuit shown in FIG.
Is a partial code string z_x1, Z_x21st fill for detection of
Data circuit 151 is arranged, but the partial code string
s₀, S ₁A second filter circuit 152 for detecting
It is also possible. In this case, the partial code
Column z_x1, Z_x2Need two filter circuits to detect
Becomes

In other words, the signal pattern detection circuit according to the present embodiment uses the partial code strings z _x1 , z _x
The first filter circuit 151 (matched filter 51) that detects _x2 is an 8-tap matched filter 5 that is a plurality of matched filters Mai according to the configuration of the partial code string A.
12 and 513, a second filter circuit 152 for detecting partial code strings s ₀ and s ₁ as a partial code string B
(First matched filter 52, second matched filter 5
3) is an 8-tap matched filter 522 that is a plurality of matched filters Mbj according to the configuration of the partial code string B.
And 523, 8-tap matched filters 532 and 533, and these matched filters Mai, M
delay circuits (8-stage delay element groups 521 and 531) for adjusting the delay times of the respective bj and matched filters Ma
It comprises a plurality of addition / subtraction circuits (adder 524, subtractor 525, adder 534, and subtractor 535) for adding / subtracting the outputs of i and Mbj, respectively, and one of the first filter circuit and the second filter circuit is provided in the preceding stage. That is, the other is a latter stage, and a matched filter constituting a latter stage filter circuit is connected in series to each of a plurality of outputs of a matched filter constituting a former stage filter circuit.

According to the above configuration, a plurality of outputs of each matched filter are obtained in the subsequent filter circuit, so that more output signals can be obtained as a whole. Therefore, since more search codes can be detected simultaneously, the time required for detecting the second search code can be further reduced.

The partial code strings s ₀ , s ₁ and z _x1 , z _x2
Is the above equation (2 ′) (3 ′) (2 ″) (3 ″)
Also in the case of the relationship (4 ″), the first filter circuit 151 in the signal pattern detection circuit shown in FIG. 5 is similar to the case of the signal pattern detection circuit shown in FIG. And addition and subtraction circuits 514 and 51 therein.
5 and the configuration of the second filter circuit 152 and the addition / subtraction circuits 524, 525, 534, and 535 inside the second filter circuit 152 may be adapted to the above-described relational expressions.

As in the present embodiment, if the number of the matched filters Mai or Mbj is made equal to the number of code strings in the partial code string to be applied, each matched filter is Since it can be used for detecting a code string, it is possible to efficiently detect a pattern of a partial code string.

Also, in the present embodiment,
As described in Embodiment 3, the partial code string z_x1, Z_x2Detect
Of 8-tap matched filters 512 and 513
The delay element group has a configuration that can store the input signal itself.
8-stage matched filter 513 for 112 stages of 511
, And the remaining 16 stages are 8 taps
Output of delay element 11 at last stage of matched filter 513
And between the input of the 8-tap matched filter 512
In addition, as shown in FIG. ₀, S₁
8 tap matched filters 522, 523 and
532, 533 can save the input signal itself
As a result, seven stages of the delay element groups 521 and 531 are divided into eight
Delay elements of top matched filters 523 and 533
Shared with 11 and the remaining one stage is the 8-tap matched fill
Outputs of the delay element 11 at the last stage of the
The inputs of the 8-tap matched filters 522 and 532
Between them, the entire signal pattern detection circuit
Need not be so large.

As described above, according to the signal pattern detection circuit disclosed in each of the above-described embodiments, the speed of detecting the partial code string can be increased as compared with the signal pattern detection circuit shown in FIG. Therefore, such a signal pattern detection circuit is used in a W-CDMA (Wideband) used in a next-generation mobile phone.
Adopting the Code Division Multiple Access (CC) communication method can greatly reduce the time from when the mobile phone is turned on to when it is possible to actually make a call.

[0178]

As described above, the signal pattern detection circuit according to the present invention is a signal pattern detection circuit for detecting a signal pattern of an input signal from a spread code string in which a plurality of partial code strings are spread. A plurality of matched filters for calculating and outputting a cross-correlation value between the input signal and the input signal are provided in correspondence with the partial code strings of the spread code string,
In this configuration, an addition / subtraction circuit is provided for adding / subtracting the output of each matched filter and outputting a plurality of signals simultaneously.

Therefore, a cross-correlation value between the partial code sequence of the spread code sequence and the input signal is obtained by a matched filter corresponding thereto, and each cross-correlation value is input to an addition / subtraction circuit to perform addition / subtraction. , The signal patterns corresponding to the respective partial code strings can be simultaneously detected.

Thus, for example, in the W-CDMA system, which is a communication system for a cellular phone or the like, the second search code, which is one of the search codes for specifying a group of mobile stations, is spread by a plurality of partial code strings. In this case, since a plurality of partial code strings can be detected at the same time, the time required for detecting the second search code can be significantly reduced.

Therefore, the signal pattern can be detected at a higher speed, the cell search in the W-CDMA system can be shortened, and the time from when the portable telephone is turned on until the telephone can be actually called can be shortened. It has the effect of being able to do so.

Another signal pattern detection circuit according to the present invention is a signal pattern detection circuit for detecting a signal pattern of an input signal from a spread code sequence in which a partial code sequence A and a partial code sequence B are spread. The elements of the column A are inverted and non-inverted according to the elements of the other partial code strings B, and the first filter circuit for detecting the partial code string A and the second filter circuit for detecting the partial code string B At least one of the filter circuits is provided with a plurality of matched filters for obtaining and outputting a cross-correlation value between the spread code sequence and the input signal in correspondence with the partial code sequence to be detected. A delay circuit for adjusting the delay time of each of the matched filters, and an addition / subtraction circuit for adding and subtracting the outputs of the respective matched filters and simultaneously outputting a plurality of signals. .

Therefore, the first filter circuit or the second filter circuit
At least one of the filter circuits includes a plurality of matched filters and a delay circuit for adjusting the delay time of each of the matched filters according to the configuration of the applied partial code string, thereby providing a plurality of matched filters. Filter output can be obtained. Then, by inputting the outputs of the matched filters to the addition / subtraction circuit and performing addition / subtraction, a plurality of partial code strings can be simultaneously detected by a filter circuit having a plurality of matched filters.

As a result, it is possible to reduce the time required for detecting a spread code string in which partial code strings A and B are spread. For example, W-CDMA, which is a communication method for mobile phones
In the method, when a signal pattern of a second search code, which is one of search codes for specifying a group of mobile stations, is spread by a plurality of partial code strings, a plurality of partial code strings are detected at the same time. Therefore, the time required to detect the signal pattern, that is, the time required to detect the second search code can be significantly reduced.

Further, the circuit scale of a filter circuit including a plurality of matched filters is substantially the same as that of a filter circuit having a matched filter when there are not a plurality of matched filters, and only needs to be increased by a delay circuit.

Therefore, pattern matching can be performed at a higher speed without using a matched filter for specifying a long code group in the W-CDMA system or the like, with almost no increase in circuit size, and the cell search can be shortened. In addition, it is possible to shorten the time from when the power of the mobile phone is turned on to when the mobile phone can be actually called.

Either the first or second filter circuit having the plurality of matched filters therein is connected in series with the other filter circuit having no matched filters therein. The number of output signals may be equal to the number of the respective addition / subtraction circuits.

In this case, by arranging a filter circuit having a plurality of matched filters at the subsequent stage, a plurality of output signals corresponding to a plurality of code strings (search codes) can be simultaneously obtained in the entire signal pattern detection circuit.

Thus, in the W-CDMA system, which is a communication system for mobile phones, for example, the signal pattern of the second search code, which is one of the search codes for specifying a group of mobile stations, is divided into a plurality of partial code strings. In this case, since a plurality of partial code strings can be detected at the same time, the time required for signal pattern detection, that is, detection of the second search code can be significantly reduced. .

Further, the filter circuit arranged at the subsequent stage may be a first filter circuit for detecting the partial code string A.

In this case, since a plurality of partial code strings A can be simultaneously detected, the partial code string A can be specified quickly. Therefore, there is an effect that the time required for detecting the search code corresponding to the spread code string obtained by spreading the partial code string A and the partial code string B can be significantly reduced.

Further, the filter circuit arranged at the subsequent stage may be a second filter circuit for detecting the partial code string B.

In this case, since a plurality of partial code strings B can be detected at the same time, the partial code string B can be specified quickly. Therefore, there is an effect that the time required for detecting the search code corresponding to the spread code string obtained by spreading the partial code string B and the partial code string A can be greatly reduced.

Further, the number of the plurality of matched filters may be equal to the number of code strings constituting the applied partial code string.

In this case, since each matched filter can be used for detecting each code string, there is an effect that pattern detection of a partial code string can be performed efficiently.

Further, a part of the delay circuit may be shared with a delay circuit inside a plurality of matched filters.

In this case, the delay circuit in the filter circuit is
Since the size can be reduced by the amount that can be shared, the effect of increasing the size of the circuit due to the increase in the number of matched filters of the signal pattern detection circuit can be reduced.

Another signal pattern detection circuit of the present invention is as follows.
The first filter circuit for detecting the partial code string A includes a plurality of matched filters Ma according to the configuration of the partial code string A.
i, and a second filter circuit for detecting the partial code string B comprises a plurality of matched filters Mbj in accordance with the configuration of the partial code string B.
ai, a delay circuit for adjusting the delay time of Mbj, and a plurality of addition / subtraction circuits for adding / subtracting the outputs of the matched filters Mai, Mbj, respectively. One of the first filter circuit and the second filter circuit is provided in the preceding stage. Become
The other is a latter stage, and a matched filter constituting a latter stage filter circuit is connected in series to each of a plurality of outputs of a matched filter constituting a former stage filter circuit.

Therefore, in the subsequent filter circuit,
Since a plurality of outputs of each matched filter are obtained, more output signals are obtained as a whole. Therefore, since more search codes can be detected simultaneously, the time required for detecting the second search code can be further reduced.

Further, the number of the matched filters Mai or Mbj may be equal to the number of code strings in the applied partial code string.

In this case, since each matched filter can be used for detecting each code string, there is an effect that pattern detection of a partial code string can be performed efficiently.

Further, a part of the delay circuit may be shared with a delay circuit in each of the plurality of matched filters Mai or Mbj.

In this case, the delay circuit in the filter circuit is
Since the size can be reduced by the amount that can be shared, the effect of increasing the size of the circuit due to the increase in the number of matched filters of the signal pattern detection circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a signal pattern detection circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a state where a delay element group is omitted in the second filter circuit shown in FIG. 1;

FIG. 3 is a block diagram showing a signal pattern detection circuit according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a signal pattern detection circuit according to still another embodiment of the present invention.

FIG. 5 is a block diagram showing a signal pattern detection circuit according to still another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional signal pattern detection circuit.

[Explanation of symbols]

Reference Signs List 11 delay element 12 multiplier 13 adder 14 16 tap matched filter (matched filter) 15 8-tap matched filter (matched filter) 16 8-tap matched filter (matched filter) 17 delay element group (delay circuit) Reference Signs List 21 delay element 31 16-tap matched filter (matched filter) 32 5-tap matched filter (matched filter) 33 5-stage delay element group (delay circuit) 34 5-tap matched filter (matched filter) 35 5-stage delay Element group (delay circuit) 36 6 tap matched filter (matched filter) 41 16 tap matched filter (matched filter) 42 delay element group (delay circuit) 43 8 tap matched filter (matched filter) 44 8 tap Matched filter (matched filter) 11 first filter circuit 112 second filter circuit 113 addition / subtraction circuit 122 second filter circuit 131 first filter circuit 132 second filter circuit 133 addition / subtraction circuit 141 first filter circuit 142 second filter circuit 143 addition / subtraction circuit 151 first filter circuit 152 Second filter circuit 511 128-stage delay element group (delay circuit) 512 8-tap matched filter (matched filter) 513 8-tap matched filter (matched filter) 521 8-stage delay element group (delay circuit) 522 8-tap match Filter (matched filter) 523 8-tap matched filter (matched filter) 531 8-stage delay element group (delay circuit) 532 8-tap matched filter (matched filter) 533 8-tap matched filter (matched filter) Ruta)

Claims (10)

[Claims] 1. A signal pattern detection circuit for detecting a signal pattern of an input signal from a spread code sequence in which a plurality of partial code sequences are spread, wherein a match for obtaining and outputting a cross-correlation value between the spread code sequence and the input signal is provided. A plurality of filters corresponding to the partial code strings of the spread code string, and an addition / subtraction circuit for adding and subtracting the output of each matched filter and outputting a plurality of signals simultaneously. Signal pattern detection circuit. 2. A signal pattern detecting circuit for detecting a signal pattern of an input signal from a spread code string obtained by spreading a partial code string A and a partial code string B, wherein an element of the partial code string A is another partial code string. B. Inverting and non-inverting according to the element of B. At least one of a first filter circuit for detecting the partial code string A and a second filter circuit for detecting the partial code string B is the spread code string. A plurality of matched filters for obtaining and outputting a cross-correlation value between the input signal and the input signal are provided in correspondence with the partial code strings to be detected, and a delay circuit for adjusting a delay time of each of the matched filters is provided. A signal pattern detection circuit provided with an addition / subtraction circuit for adding and subtracting the outputs of the matched filters and outputting a plurality of signals simultaneously. 3. When one of the first and second filter circuits has a plurality of matched filters, the other filter circuit does not have a matched filter therein. 3. The signal pattern detection circuit according to claim 2, wherein the signal pattern detection circuit is connected in series at a subsequent stage of the circuit. 4. The signal pattern detection circuit according to claim 3, wherein the filter circuit arranged at the subsequent stage is a first filter circuit for detecting a partial code string A. 5. The signal pattern detection circuit according to claim 3, wherein the filter circuit disposed at the subsequent stage is a second filter circuit for detecting a partial code string B. 6. The signal pattern detection circuit according to claim 2, wherein the number of said plurality of matched filters is equal to the number of code strings constituting a partial code string to be applied. 7. The signal pattern detection circuit according to claim 2, wherein a part of said delay circuit is shared with a delay circuit inside a plurality of matched filters. 8. The first filter circuit for detecting the partial code string A includes a plurality of matched filters Mai according to the configuration of the partial code string A. The second filter circuit for detecting the partial code string B includes: According to the configuration of the partial code string B, a plurality of matched filters Mb
j, and a delay circuit for adjusting the delay time of each of the matched filters Mai and Mbj and each matched filter Ma
a plurality of addition / subtraction circuits for adding / subtracting the outputs of i and Mbj, respectively, one of the first filter circuit and the second filter circuit being a front stage, the other being a rear stage, and a matching circuit forming a front stage filter circuit. 3. The signal pattern detection circuit according to claim 2, wherein a matched filter constituting a subsequent filter circuit is connected in series to each of the plurality of outputs of the filter. 9. The matched filter Mai or Mb described above.
9. The signal pattern detection circuit according to claim 8, wherein the number of j is equal to the number of code strings in the partial code string to be detected. 10. The signal pattern detection according to claim 8, wherein a part of said delay circuit is shared with a delay circuit in each of a plurality of matched filters Mai or Mbj. circuit.